ST L9954 L9954XP handbook
Contents
1. Figure 3 SPI transfer timing diagram CSN high to low DO enabled CSN gt 7 DI data will be accepted on the rising edge of CLK signal time DI MWISOQOAGOO xXx CoC C O DO data will change on the falling edge of CLK signal time DO 20000006 2D CO CO C AE OK time CSN low to high actual data is fauto transfered to output power TA Input old data X new data Data Register time Figure 4 SPI input timing CSN t set CSN CLK DI Doc ID 14279 Rev 3 L9954 L9954XP Electrical specifications Figure 5 SPI DO valid data delay time and valid time t t fin rin CLK DO 0 8 VCC high to low Figure 6 SPI DO enable and disable time t in CSN DO pull up load to VCC C 100 pF ten DO til Lais DOL tri i a DO 50 pull down load to GND C 100 pF ten DO triH tais DO H tri ky Doc ID 14279 Rev 3 17 37 Electrical specifications L9954 L9954XP 18 37 Figure 7 SPI driver turn on off timing minimum CSN HI time CSN low to high data from shift register is transferred to output power switches t in t t in i M a CSN_HI min CSN en Coe ee os output current of a driver output current of a driver Figure 8 SPI timing of status bit 0 fault condition CSN CLK DI CSN high to low and CLK stays low status information o2. dhe DETAIL A M d i BOTTOM VIEW o3 N slug DETAIL B o D1 E1 f 3 EE slug tail width c NE 1 li L SEATING 1 18 eec c COPLANARITY hx45 0 12 A 8 a Doc ID 14279 Rev 3 ky L9954 L9954XP Package and packing information Table 20 PowerSO 36 mechanical data Millimeters Symbol Min Typ Max A 3 60 al 0 10 0 30 a2 3 30 a3 0 0 10 b 0 22 0 38 C 0 23 0 32 D 15 80 16 00 D1 9 40 9 80 E 13 90 14 5 E1 10 90 11 10 E2 2 90 E3 5 80 6 20 e 0 65 e3 11 05 G 0 0 10 15 50 15 90 h 1 10 L 0 8 1 10 M N 10 deg R S 8 deg Doc ID 14279 Rev 3 31 37 Package and packing information L9954 L9954XP 6 3 PowerSSO 36 package information Figure 12 PowerSSO 36 package dimensions Table 24 PowerSSO 36 mechanical data Millimeters Symbol Min Typ Max A pe LP 245 A2 2 15 2 35 al 0 0 1 b 0 18 0 36 c 0 23 0 32 D 10 10 10 50 E 7 4 7 6 e 0 5 e3
3. If bit 23 is zero the device will go into the standby mode The bits 18 and 19 are used to control the current monitor multiplexer Bit 22 is used to reset all status bits in both status registers The bits in the status registers will be cleared after the current communication frame rising edge of CSN Status register This devices uses two status registers to store and to monitor the state of the device No error bit bit 0 is used as a fault bit and is a logical NOR combination of bits 1 22 in both status registers The state of this bit can be polled by the microcontroller without the need of a full SPl communication cycle If one of the over current bits is set the corresponding driver will be disabled If the over current recovery bit of the output is not set the microcontroller has to clear the over current bit to enable the driver If the thermal shutdown bit is set all drivers will go into a high impedance state Again the microcontroller has to clear the bit to enable the drivers Doc ID 14279 Rev 3 ky L9954 L9954XP Functional description of the SPI 4 8 4 SPI Input data and status registers Table 18 SPI input data and status registers 0 Input register 0 write Status register 0 read Bit Name Comment Name Comment If Enable Bit is set the device switches in active A broken VCC or SPI mode If Enable Bit is connection of the L9954 can cleared the device goes be detected by the 23 Enabla
4. Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Block diagrams iv tiara meer mde er er rr ANFERTH AN NF HNNAN 6 Configuration diagram top view LYL FF eee 8 SPI transfer timing diagram FF EF FF FFF Y uad 16 SPl inputtiming Y FF FF FF RR rr 16 SPI DO valid data delay time and valid time FF a 17 SPI DO enable and disable time YYY Y Y FF FF FA Rad 17 SPI driver turn on off timing minimum CSN Hltime Y ug 18 SPI timing of status bit O fault condition Y YY YY A Ra 18 Example of programmable softstart function for inductive loads 22 Packages thermal data llli 29 PowerSO 36 package dimensions FF Fu uu 30 PowerSSO 36 package dimensions leeren 32 PowerSO 36 tube shipment no suffiX esee 33 PowerSO 36 M tape and reel shipment suffix TR Y YY La 34 PowerSSO 36 tube shipment no suffiX VYIY YY YY Y esses 35 PowerSSO 36 M tape and reel shipment suffix TR Y Y Y Yu 35 Doc ID 14279 Rev 3 5 37 Block diagram and pin description L9954 L9954XP 6 37 Block diagram and pin description Figure 1 Block diagram V BAT Reverse Polarity Protection vcc Note Value of capacitor has to be choosen carefully to limit the V
5. ky L9954 L9954XP Door actuator driver Features Three half bridges for 1 5A load R5 800mQ One highside driver for 6A load R 100mO Two highside drivers for 1 5A load Ry42800mO Programmable softstart function to drive loads with higher inrush currents i e current 26A gt 1 5A m Very low current consumption in standby mode Is lt 6HA typ T lt 85 C m All outputs short circuit protected m Current monitor output for highside OUT1 OUT4 OUT5 and OUT6 All outputs over temperature protected Open load diagnostic for all outputs Overload diagnostic for all outputs PWM control of all outputs Charge pump output for reverse polarity protection PowerSSO 36 PowerSO 36 Applications m Door actuator driver with bridges for mirror axis control and highside driver for mirror defroster and two 10W light bulbs Description The L9954 and L9954XP are microcontroller driven multifunctional door actuator drivers for automotive applications Up to two DC motors and three grounded resistive loads can be driven with three half bridges and three highside drivers The integrated standard serial peripheral interface SPI controls all operation modes forward reverse brake and high impedance All diagnostic information is available via the SPI Table 1 Device summary Order codes Package Tape and reel PowerSO 36 L9954 L9954TR PowerSSO 36 L9954XP L9954XPTR May 2010
6. PWM1 2 input is low OUTS is controlled by PWM input All open load don t other outputs are controlled by OUT2 HS 3 OUT3 PWM1 OUT2 LS Enable open load gt OUT2 PWM1 OUT HS Enable open load 1 OUT1 PWM1 OUT1 LS Enable open load A logical NOR combination of all bits 1 0 1 No Error bit 4552 in both status registers Doc ID 14279 Rev 3 4 L9954 L9954XP Packages thermal data 5 Packages thermal data Figure 10 Packages thermal data Pad soldered PowerSSO 36 double side 2 GND layers PowerSSO 36 double side 2 GND layers Via s PSO 36 double side 2 GND layers PSO 36 double side 2 GND layers Via s 1 E 04 1 E 03 1 E 02 1 E 01 1 E 00 1 E 01 1 E 02 1 E 03 Time s Doc ID 14279 Rev 3 29 37 Package and packing information L9954 L9954XP 6 6 1 6 2 30 37 Package and packing information ECOPACK packages In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark PowerSO 36 package information Figure 11 PowerSO 36 package dimensions 1 ILL CT LD JN DETAIL B E g H N lead u
7. SPI 23 4 1 Serial Peripheral Interface SPI VVV ug 23 4 2 Chip Select Not CSN YI FYR eee 23 43 Serial Data In DI iwaseskoestetkme RG ce ekXeR Shea eee see ds 23 44 Serial Data Out DO FFI II RW Y Ya 23 45 S ral clock CLK visis debate Y RE GY DE y 24 4 6 Input data register sere yes RR EY EUR EA REOR KR ERE 24 47 Status register a da een ens ce wee GO REOR EG DRO ERRARE Ges 24 2 37 Doc ID 14279 Rev 3 ky L9954 L9954XP Contents 48 SPI Input data and status registers V Yu 25 5 Packages thermal data eee 29 6 Package and packing information 30 6 1 ECOPACK packages ssss e 30 6 2 PowerSO 36 package information suana nanana 30 6 3 PowerSSO 36 package information Fu 32 6 4 PowerSO 36 packing information VY Y uu 33 6 5 PowerSSO 36 M packing information VV eee 35 7 Revision history 2255222 RCH GAREG RR Ee E Re RSS 36 ky Doc ID 14279 Rev 3 3 37 List of tables L9954 L9954XP List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 4 37 Device SUMMA we cis edm dense Sa Paced ma E Rd dra
8. Trest 40 C 25 C Tiest 85 C 0 6 25 uA Vg 16V Vcc 5 3V Vcc DC t 1 A ue ED CSN Vcc active mode m lcc y i Vs 16V Vcc 5 3V oe Supp y CSN Vcc standby mode 25 50 pA OUT1 OUT6 floating Vs 16V Vcc 5 3V S CSN Vec ls loc Re E Supp y standby mode 50 100 pA OUT1 OUT6 floating Trest 130 C 1 Guaranteed by design 10 37 Doc ID 14279 Rev 3 ky L9954 L9954XP Electrical specifications 4 Table 8 Overvoltage and undervoltage detection Symbol Parameter Test condition Min Typ Max Unit Vsuv on VS UV threshold voltage Vs increasing 5 7 7 2 V Vsuv orr V8 UV threshold voltage Vs decreasing 5 5 6 9 V Vsuv hyst VS UV hysteresis Vsuv ON Vsyv OFF 0 5 V Vsov orr VS OV threshold voltage Vs increasing 18 24 5 V Vsov on VS OV threshold voltage Vs decreasing 17 5 235 V Vsov nyst VS OV hysteresis Vsov orr Vsov ON 1 V Vpon orr Power On reset threshold Vcc increasing 4 4 V Vpon on Power On reset threshold Vcc decreasing 3 1 V Vpon hyst Power On reset hysteresis Vpor ofr VPoR ON 0 3 V Table 9 Current monitor output Symbol Parameter Test condition Min Typ Max Unit VcM Functional voltage range Vcc 5V 0 4 V Current monitor output A tio lt lt a lcu ratio OV lt Vem lt 4V VCC 5V 10 000 lom lOUT1 4 5 6 0 V lt Vem
9. a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended Serial Data Out DO The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit O fault condition The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the Doc ID 14279 Rev 3 23 37 Functional description of the SPI L9954 L9954XP 4 5 4 6 4 7 24 37 content of the selected status register into the data out shift register Each subsequent falling edge of the CLK will shift the next bit out Serial clock CLK The CLK input is used to synchronize the input and output serial bit streams The data input DI is sampled at the rising edge of the CLK and the data output DO will change with the falling edge of the CLK signal Input data register The device has two input registers The first bit bit O at the DI input is used to select one of the two Input Registers All bits are first shifted into an input shift register After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 24 data bits are detected Depending on bit 0 the contents of the selected status register will be transferred to DO during the current communication frame Bit 1 17 controls the behavior of the corresponding driver
10. la ON H highside driver On corresponding lowside 20 40 80 us driver is not active Output delay time _ td OFF H highside driver Off Vs 1 3 5 V 50 150 300 us Vg 13 5 V Output delay time ONL owside driver On corresponding highside 15 30 70 us driver is not active t Output delay ume Vs 13 5 V 80 150 300 us dOFFL owside driver Off a Cross current protection MHL time source A toc ONLS_OFFHS ta orr H 200 400 us Cross current protection LH time sink to Rand toc ONHS_OFFLS ta orr LU 200 400 us Switched off output Vour1 e7 OV standby 0 2 5 UA lou current highside drivers of mode OUT1 6 Vour1 e7 OV active mode 40 15 0 pA 12 37 Doc ID 14279 Rev 3 4 L9954 L9954XP Electrical specifications Table 11 OUT1 OUT6 continued Symbol Parameter Test condition Min Typ Max Unit Switched off output Vour1 37 Vs Standby 0 80 120 UA low current lowside drivers of mode OUT1 3 Vour1 37 Vs active mode 40 15 0 pA Open load detection loLp123 current of OUT1 OUT2 Source and sink 15 40 60 mA and OUT3 Open load detection loip4s current of OUT4 and Source and sink 15 40 60 mA OUT5 Open load detection loLD6 current of OUT6 Source 30 150 300 mA Minimum duration of tao openload condition to set 500 3000 us the status bit Minimum duration of tisc over current condition to 10 100 us switch off the driver Rec
11. ui into standby mode and all Always 1 microcontroller because all 24 bits are cleared After bits low or high is not a valid power on reset device frame starts in standby mode If Reset Bit is set both i i i n case of an overvoltage or 22 Reset bit status registers will be Vs overvoltage cleared after rising edge of CSN input OC recovery This bit defines in undervoltage event the corresponding bit is set and the outputs are deactivated If VS voltage recovers to normal duty cycle combination with the over operating conditions outputs 21 Hanse de du Dd Vs undervoltage vid s automatically 0 12 1 25 in over current condition of 3 s LE E an activated driver If this bit is set the In case of a thermal shutdown Overvoltage microcontroller has to all outputs are switched off oo Undervoltage clear the status register Thermal The microcontroller has to recovery a ter undervoltage shutdown clear the TSD bit by setting the disable overvoltage event to Reset Bit to reactivate the enable the outputs outputs Depending on The TW bit can be used for combination of bit 18 and 19 the current image thermal management 19 1 10 000 of the selected Temperature by the microcontroller to avoid HS output will be warning a thermal shutdown The multiplexed to the CM microcontroller has to clear the output Terbi Bit Bit Output After switching the device from Currentmon
12. 3 8V Vec 5V loutmin 500mA 496 896 Icmacc Current monitor accuracy Si m 1 FS 294FS FS full scale 600A Table 10 Charge pump output Symbol Parameter Test condition Min Typ Max Unit Vs 8V lcp 60uA Vs 6 Vs 1 3 V Charge pump output Vcp voltage Vs 10V lop 80UA Vot8 Vst1 3 V Vs 2 12V lgp 2 1004A Vgt10 Vs 13 V Charge pump output _ lcp ret Vcp Vs 10V Va 13 5V 95 150 300 HA Doc ID 14279 Rev 3 11 37 Electrical specifications L9954 L9954XP Table 11 OUT1 OUT6 Symbol Parameter Test condition Min Typ Max Unit Vs 18 5 V T 25 C jaca 3 j 800 1100 mo bs OUT On resistance to supply out1 2 3 0 8A ON OUT or GND Vg 13 5 V T 125 C ON OUT3 on i 1250 1700 mo lout1 2 3 0 8A 13 5 V T 25 bu ca 500 700 mo TON OUT4 lour s 08 A On resistance to supply ON OUT5 Vs 13 5 V Tj 125 C 700 950 me lour457 0 8 A VS 13 5 V T 25 C 163 sd omg r On resistance to supply DUC ON OUT6 13 5 V Tj 125 c eens 150 200 mQ loure 3 A lout Output current limitation 7 loure to GND Source Vg 13 5 V 3 0 1 5 A louts lout Output current limitation _ lour to supply Sink Vg 13 5 V 1 5 3 0 A loura lour4 Output current limitation Source Vg 13 5 V 30 45 A lours to GND Output current limitation i s loure to GND Source Vg 13 5 V 10 5 6 A Vg 13 5 V Output delay time
13. 8 5 F 2 3 G 0 1 G1 0 06 H 10 1 10 5 h 0 4 k 0 8 L 0 55 0 85 N 10 deg 32 37 Doc ID 14279 Rev 3 ky L9954 L9954XP Package and packing information Table 24 PowerSSO 36 mechanical data continued Millimeters Symbol Min Typ Max 4 3 5 2 Y 6 9 7 5 6 4 PowerSO 36 packing information Figure 13 PowerSO 36 tube shipment no suffix 45 02 MU 17 2 08 188 REF ky Doc ID 14279 Rev 3 33 37 Package and packing information L9954 L9954XP Figure 14 PowerSO 36 M tape and reel shipment suffix TR T 0 30 D 05 TAPE DIMENSIONS P2 Po Do 2 04 1 I 4 0 0 1 Il 1 59 Y BE E p ole 8 o o x 5 w H REEL DIMENSIONS A0 15 20 0 1 Base Qty 600 Bo 16 60 0 1 Bulk Qty 600 KO 3 90 0 1 A max 330 K1 3 50 0 1 B min 1 5 F 11 50 2 0 1 C 0 2 13 P1 24 00 x 0 1 D min 20 2 SECTION X w 24 00 0 3 G 2 0 24 4 N min 60 All dimensions are in mm T max 30 4 T eje 40mm min Access hole at slot location G measured Full radius Tape slot in core for tape start 2 5mm min width 34 37 Doc ID 14279 Rev 3 4 L9954 L9954XP Package and packing information 6 5 PowerSSO 36 packing information Figure 15 PowerSSO 36 V
14. A Pull down current at input lowe in pwm P VpwM 1 5V 10 25 50 pA _ 1 Input capacitance at input Ci CSN CLK DI and PWM1 2 Preces nav e ssp 14 37 1 Value of input capacity is not measured in production test Parameter guaranteed by design Table 14 DI timing Symbol Parameter Test condition Min Typ Max Unit tc Clock period Voc 5V 1000 ns tcLKH Clock high time Vcc 5V 400 ns teLKL Clock low time Voc 5V 400 ns CSN setup time CSN low setCSN before rising edge of CLK Vcc 5V 400 da CLK setup time CLK high _ setCLK before rising edge of CSN Voc 5V 400 is tsetpi DI setup time Voc 5V 200 ns thold DI DI hold time Vcc 5V 200 ns Rise time of input signal DI _ tr in CLK CSN Vcc 5V 100 ns Fall time of input signal DI E t in CLK CSN Vcc 5V 100 ns 1 DI timing parameters tested in production by a passed failed test Tj 40 C 25 C SPI communication 9 2MHz Tj 125 C SPI communication 1 25 MHz Table 15 DO Symbol Parameter Test condition Min Typ Max Unit VpoL Output low level VCC 5 V Ip 2mA 0 2 0 4 V VpoH Output high level VCC 5 V lp 2 mA Voc 0 4 Vcc 0 2 V Doc ID 14279 Rev 3 4 L9954 L9954XP Electrical specifications Table 15 DO contin
15. D 14279 Rev 3 19 37 Application information L9954 L9954XP 3 5 3 6 3 7 3 8 3 9 20 37 Overvoltage and undervoltage detection If the power supply voltage Vs rises above the overvoltage threshold Vsoy orr typical 21 V the outputs OUT1 to OUT6 are switched to high impedance state to protect the load When the voltage Vs drops below the undervoltage threshold Vsyy ofr UV switch OFF voltage the output stages are switched to the high impedance to avoid the operation of the power devices without sufficient gate driving voltage increased power dissipation If the supply voltage Vs recovers register 0 bit 2020 to normal operating voltage the outputs stages return to the programmed state after at least 32 us If the undervoltage overvoltage recovery disable bit is set the automatic turn on of the drivers is deactivated The microcontroller needs to clear the status bits to reactivate the drivers It is strongly recommended to set bit 20 to avoid a possible high current oscillation in case of a shorted output to GND and low battery voltage Charge pump The charge pump runs under all conditions in normal mode In standby the charge pump is out of action Temperature warning and thermal shutdown If junction temperature rises above Tj rw a temperature warning flag is set after at least 32 us and is detectable via the SPI If junction temperature increases above the second threshold T sp the thermal shutdown bit will
16. Doc ID 14279 Rev 3 1 37 www st com Contents L9954 L9954XP Contents 1 Block diagram and pin description 6 2 Electrical specifications ug 9 2 1 Absolute maximum ratings lt es 9 2 2 ESD protection GEEDND _ Oe O Oe 2 aces Rees eerekeea cone 9 2 3 Thermal data C lt nat teens ete wens omens ated 9 2 4 Electrical Characteristics ix ik kA Rr UR RR REOR DUR RE CR OR UL 10 2 5 SPI electrical characteristics V V eee 13 3 Application information elelllseeeeen 19 3 1 Dual power supply VS and VCC FFI IR Ru ug 19 3 2 Standby Mode unisce sre SER eta ie P ey Ra SS pios 19 3 3 Inductive OBtls cocer Rm iD YN NF 19 3 4 Diagnostic functions SP c r 19 3 5 Overvoltage and undervoltage detection 20 36 Charge PUMP DD edia na SUP SERRE Ree io es 20 3 7 Temperature warning and thermal shutdown 20 3 8 Open load detection ides pera px rm Red ador RR ER RR ER 20 3 9 Overload detection FY YY A Y ug 20 3 10 Current monitor a wesw Ses Bes bob eed eS Ree Me wR Yaw X EXER 21 al PWM INPUTS ee Ru a e a Ed GYDD YR EDD YR 21 3 12 Cross current protection Y ees 21 3 13 Programmable softstart function to drive loads with higher inrush current 22 4 Functional description of the
17. OUT6 OC In case of an overvoltage 22 Recovery VS overvoltage or undervoltage event Enable the corresponding bit is set and the outputs are deactivated If Vs voltage recovers to normal 21 x don t care VS undervoltage 20 OUT5 OC Recovery Enable 19 OUT4 OC Recovery Enable 18 x don t care In case of an over current event the over current status bit Status Register O is set and the output is switched off If the over current Recovery Enable bit is set the output will be automatically reactivated after a delay time resulting in a PWM modulated current with a programmable duty cycle Bit 21 of Input Data Register 0 Depending on occurrence of Overcurrent Event and internal clock phase it is possible that one recovery cycle is executed even if this bit is set to zero operating conditions outputs are reactivated automatically Thermal shutdown In case of a thermal shutdown all outputs are switched off The microcontroller has to clear the TSD bit by setting the Reset Bit to reactivate the outputs Temperature warning The TW bit can be used for thermal management by the microcontroller to avoid a thermal shutdown The microcontroller has to clear the TW bit Not ready bit After switching the device from standby mode to active mode an internal timer is started to allow chargepump to settle before the outputs can be activated This bit is only present dur
18. S voltage below absolute maximum ratings in case of an unexpected freewheeling condition e g TSD POR Mirror Common Mirror Vertical Mirror Horizontal Lock Folder Programmable Note Resistors between uC and L9954LXP are recommended to limit currents for negative voltage transients at VBAT e g ISO type 1 pulse Table 2 Pin definitions and functions Bulb 10W or LED Mode Driver Interface amp Diagnostic Defroster Pin Symbol 1 18 19 36 GND Function Ground Reference potential Important for the capability of driving the full current at the outputs all pins of GND must be externally connected 2 35 OUT6 Highside driver output 6 The output is built by a highside switch and is intended for resistive loads hence the internal reverse diode from GND to the output is missing For ESD reason a diode to GND is present but the energy which can be dissipated is limited The highside driver is a power DMOS transistor with an internal parasitic reverse diode from the output to VS bulk drain diode The output is over current and open load protected Important for the capability of driving the full current at the outputs both pins of OUT6 must be externally connected 4 Doc ID 14279 Rev 3 L9954 L9954XP Block diagram and pin description Table 2 Pin definitions and functions continued Pin Symbol Function Half bridge output 1 2 3 OUT1 The ou
19. T1 2 3 4 5 Output current 5 A loute Output current 10 A ESD protection Table 4 ESD protection Parameter Value Unit All pins 2 1 kV Output pins OUT1 OUT6 8 2 kV 1 HBM according to MIL 883C Method 3015 7 or EIA JESD22 A1 14 A 2 HBM with all unzapped pins grounded Thermal data Table 5 Operating junction temperature Symbol Parameter Value Unit T Operating junction temperature 40 to 150 C Doc ID 14279 Rev 3 9 37 Electrical specifications L9954 L9954XP Table 6 Temperature warning and thermal shutdown Symbol Parameter Min Typ Max Unit Temperature warning threshold junction Tirw on temperature Tj 139 Maa EE TD 6N Thermal shutdown threshold junction Tj l 170 c temperature increasing 1 Thermal shutdown threshold junction Tj 150 C jSD OFF temperature decreasing Tjsp Hys Thermal shutdown hysteresis 5 K 2 4 Electrical characteristics Vs 8 to 16V Voc 4 5 to 5 3V T 40 to 150 C unless otherwise specified The voltages are referred to GND and currents are assumed positive when the current flows into the pin Table 7 Supply Symbol Parameter Test condition Min Typ Max Unit Vs Operating supply voltage 7 28 V range Vs 16V Voc 5 3V Vs DC supply current active mode 7 20 mA OUT1 OUT6 floating Vs 16V Vcc OV 3 standby mode 12 UA Vs quiescent supply current OUT1 OUT6 floating
20. al delay time If one driver LS or HS is turned off the activation of the other driver of the same half bridge will be automatically delayed by the cross current protection time After the cross current protection time is expired the slew rate limited switch off phase of the driver will be changed to a fast turn off phase and the opposite driver is turned on with slew rate limitation Due to this behavior it is always guaranteed that the previously activated driver is totally turned off before the opposite driver will start to conduct Doc ID 14279 Rev 3 21 37 Application information L9954 L9954XP 3 13 22 37 Programmable softstart function to drive loads with higher inrush current Loads with start up currents higher than the over current limits e g inrush current of lamps start current of motors and cold resistance of heaters can be driven by using the programmable softstart function i e overcurrent recovery mode Each driver has a corresponding over current recovery bit If this bit is set the device will automatically switch on the outputs again after a programmable recovery time The duty cycle in over current condition can be programmed by the SPI interface to be about 1596 25 The PWM modulated current will provide sufficient average current to power up the load e g heat up the bulb until the load reaches operating condition The PWM frequency settles at 1 5 kHz or 3 kHz The device itself cannot distinguish betw
21. anner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a re
22. ax value from 2 47 to 2 45 Changed A2 max value from 2 40 to 2 35 Changed a1 max value from 0 075 to 0 1 Added F and k rows 17 May 2010 Table 21 PowerSSO 36 mechanical data Changed X minimum value from 4 1 to 4 3 and maximum value from 4 7 to 5 2 Changed Y minimum value from 6 5 to 6 9 and maximum value from 7 1 to 7 5 Doc ID 14279 Rev 3 L9954 L9954XP Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any m
23. be set and power DMOS transistors of all output stages are switched off to protect the device after at least 32 us Temperature warning flag and thermal shutdown bit are latched and must be cleared by the microcontroller The related bit is only cleared if the temperature decreases below the trigger temperature If the thermal shutdown bit has been cleared the output stages are reactivated Open load detection The open load detection monitors the load current in each activated output stage If the load current is below the open load detection threshold for at least 1 ms tgor the corresponding open load bit is set in the status register Due to mechanical electrical inertia of typical loads a short activation of the outputs e g 3ms can be used to test the open load status without changing the mechanical electrical state of the loads Over load detection In case of an over current condition a flag is set in the status register in the same way as open load detection If the over current signal is valid for at least tjsgc 32 us the over current flag is set and the corresponding driver is switched off to reduce the power dissipation and to protect the integrated circuit If the over current recovery bit of the output is zero the microcontroller has to clear the status bits to reactivate the corresponding driver Doc ID 14279 Rev 3 ky L9954 L9954XP Application information 3 10 3 11 3 12 Current monitor The current monit
24. een a real overload and a non linear load like a light bulb A real overload condition can only be qualified by time As an example the microcontroller can switch on light bulbs by setting the over current recovery bit for the first 50ms After clearing the recovery bit the output will be automatically disabled if the overload condition still exits Figure 9 Example of programmable softstart function for inductive loads Load Current Unlimited Inrush Current di Limited Inrush Current in programmable Recovery Mode Doc ID 14279 Rev 3 ky L9954 L9954XP Functional description of the SPI 4 4 1 Note 4 2 4 3 Note 4 4 Functional description of the SPI Serial Peripheral Interface SPI This device uses a standard SPI to communicate with a microcontroller The SPI can be driven by a microcontroller with its SPI peripheral running in following mode CPOL 0 and CPHA 0 For this mode input data is sampled by the low to high transition of the clock CLK and output data is changed from the high to low transition of CLK This device is not limited to microcontroller with a build in SPI Only three CMOS compatible output pins and one input pin will be needed to communicate with the device A fault condition can be detected by setting CSN to low If CSN 0 the DO pin will reflect the status bit 0 fault condition of the device which is a logical or of all bits in the status registers 0 and 1 T
25. en dod NN E FN FEDR YN e des 1 Pin definitions and functions 6 00 ce eh 6 AbsolutemaximumratingS YYF FF eh 9 ESD protection us re RR at e soi Rcx A ON RUG ID whe ee Fly RC o 9 Operating junction temperature YF FL a 9 Temperature warning and thermal shutdown LI FFF Y ug 10 SUpDly ssi UR FON ON ew Bo aie Rok ane ea Ro ed E e ER RO a ed dea a CR OU NF HR C 10 Overvoltage and undervoltage detection llli 11 Current monitor output lille hr 11 Chargepumpoutput LL YY I hrs 11 OUTI OUT6G dete e roter be es ete Ris ped YR y ae SERE Ree 12 Delay time from standby to activemode YYFY FER eee 13 Inputs CSN CLK PWM1 2 and DI FFF FF FF n 14 anl _ A OK TH A HNN NN UEF T 14 DOs sts EDD 14 DO TIMING sre air ts oats peat wu A dt dace e astu te WA o FEED GN Doe wn EGO eats 15 CSN timing s odere RR tet Sig bed Gowan bebe deir heed edad s 15 SPI input data and status registers 0 eens 25 SPI input data and status registers 1 uuna 000 ccc ee 27 PowerSO 36 mechanical data V Y FFF eee 31 PowerSSO 36 mechanical data Y FY FFI FF res 32 Document revision history YY FF REF rn 36 Doc ID 14279 Rev 3 ky L9954 L9954XP List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9
26. f data bit O fault condition is transfered to DO j DO DO status information of data bit O fault condition will stay as long as CSN is low Doc ID 14279 Rev 3 ky L9954 L9954XP Application information 3 3 1 3 2 3 3 3 4 Application information Dual power supply Vs and Vcc The power supply voltage Vs supplies the half bridges and the highside drivers An internal charge pump is used to drive the highside switches The logic supply voltage Vcc stabilized 5 V is used for the logic part and the SPI of the device Due to the independent logic supply voltage the control and status information will not be lost if there are temporary spikes or glitches on the power supply voltage In case of power on Vcc increases from undervoltage to Vpon ofr 4 2 V the circuit is initialized by an internally generated power on reset POR If the voltage Vcc decreases under the minimum threshold Vpon on 3 4 V the outputs are switched to tristate high impedance and the status registers are cleared Standby mode The standby mode of the L9954 is activated by clearing the bit 23 of the Input Data Register O All latched data will be cleared and the inputs and outputs are switched to high impedance In the standby mode the current at Vs Vcc is less than 6 pA 50pA for CSN high DO in tristate By switching the Vcc voltage a very low quiescent current can be achieved If bit 23 is set the device
27. gistered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 14279 Rev 3 37 37
28. he microcontroller can poll the status of the device without the need of a full SPI communication cycle In contrast to the SPI standard the least significant bit LSB will be transferred first see Figure 3 Chip Select Not CSN The input pin is used to select the serial interface of this device When CSN is high the output pin DO will be in high impedance state A low signal will activate the output driver and a serial communication can be started The state when CSN is going low until the rising edge of CSN will be called a communication frame If the CSN input pin is driven above 7 5V the L9954 will go into a test mode In the test mode the DO will go from tri state to active mode Serial Data In DI The input pin is used to transfer data serial into the device The data applied to the DI will be sampled at the rising edge of the CLK signal and shifted into an internal 24 bit shift register At the rising edge of the CSN signal the contents of the shift register will be transferred to Data Input Register The writing to the selected Data Input Register is only enabled if exactly 24 bits are transmitted within one communication frame i e CSN low If more or less clock pulses are counted within one frame the complete frame will be ignored This safety function is implemented to avoid an activation of the output stages by a wrong communication frame Due to this safety functionality a daisy chaining of SPI is not possible Instead
29. iguration diagram top view GND 1 OUT6 2 OUT1 3 OUT2 4 OUT3 5 Vs 6 Vs 7 DI 8 CM PWM2 9 CSN 10 DO 11 Vcc 12 CLK13 Vs 14 NC 15 NC 16 NC 17 GND 18 PowerSO 36 PowerSSO 36 Doc ID 14279 Rev 3 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 GND OUT6 NC OUT5 Vs OUT4 NC NC Vs PWM1 CP Vs NC NC NC NC NC GND L9954 L9954XP Electrical specifications 2 2 1 2 2 2 3 Electrical specifications Absolute maximum ratings Stressing the device above the rating listed in the Absolute maximum ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality document Table 3 Absolute maximum ratings Symbol Parameter Value Unit DC supply voltage 0 3 to28 V i Single pulse tmax lt 400ms 40 V Vcc Stabilized supply voltage logic supply 0 3 to 5 5 V Vpn Vpo Voi M DI DO SCL Digital input output voltage 0 3 to Voc 0 3 V VCSN Vpwmt VcM Current monitor output 0 3 to Voc 0 3 V Vcp Charge pump output 25 to Vs 11 V lou
30. ing start up time Since this bit is controlled by internal clock it can be used for synchronizing testing events e g measuring filter times Doc ID 14279 Rev 3 27 37 Functional description of the SPI L9954 L9954XP 28 37 Table 19 SPI input data and status registers 1 continued Input register 1 write Status register 1 read Bit Name Comment Name Comment OUT6 HS 17 x don t care open load 16 x don t care 0 OUT5 HS 15 x don t care open load After 50ms the bit can be OUT3 OC 14 Recovery _ cleared If over current OUT4 HS Enable condition still exists a wrong open load load can be assumed OUT2 OC 13 Recovery 0 Enable The open load detection monitors the load current 12 Pdl in 0 in each activated output E stage If the load current nane is below the open load OUT6 PWM1 detection threshold for at 11 0 Enable least 1 ms tgo the 10 x don t care 0 corresponding open load LLL bit is set Due to 9 OUT5 PWM2 0 mechanical electrical Enable inertia of typical loads a 8 OUT4 PWM1 0 short activation of the Enable outputs e g 3ms can 7 x don i care If the PWM1 2 Enable Bit is set 0 be used to test the open and the output is enabled load status without Input Register 0 the output is OUT3 HS changing the high and switched off if OUT3 LS state of the loads 5 x don tcare
31. itor 19 18 p standby mode to active mode select bits 0 0 OUT6 an internal timer is started to allow chargepump to settle 1 0 OUT1 before the outputs can be activated This bit is cleared Uu 0 1 OUT4 Not ready DIE automatically after start up 1 1 OUT5 time has finished Since this bit is controlled by internal clock it can be used for synchronizing testing events e g measuring filter times Doc ID 14279 Rev 3 25 37 Functional description of the SPI L9954 L9954XP 26 37 Table 18 SPI input data and status registers 0 continued Input register 0 write Status register 0 read Bit Name Comment Name Comment OUT6 HS OUT6 HS 17 on off over current 16 x don t care 0 OUT5 HS OUT5 HS 15 on off over current OUT4 HS OUT4 HS 14 on off Odd over current a bit is set the selecte 5 In case of an over current 13 x don t care iver i i 0 bus dd d event the corresponding status 12 x don t care UM ELLE 0 bit is set and the output driver f is disabled If the over current ME EFE n dicc ns if 0 Recovery Enable bit is set 10 x don t care el le OR HENRI 0 Input Register 1 the output PWM1 PWM2 input will b t ticall don t care signal is high The outputs 0 idisse ned ad f OUTI OUT3 half reactivated after a delay time 8 x don t care s id if ih Ur iis 0 resulting in a PWM m
32. odulated dar Ped o current with a programmable 7 x dontcare and LS driver of the same 0 duty cycle Bit 21 half bridge are set the 6 OUT3 HS internal logic prevents that OUTS HS on off both drivers of this output over current l the over current recovery bit OUT3 LS stage can be switched on OUT3 LS is not set the microcontroller 5 has to clear the over current on off simultaneously in order to over current pit R Bi h avoid a high internal it eset it to reactivate the 4 OUT2 HS current from VS to GND OUT2 HS output driver on off over current OUT2 LS OUT2 LS 3 on off over current OUT1 HS OUT1 HS 2 on off over current 1 OUT1 LS OUT1 LS on off over current A logical NOR combination of 0 0 No error bit all bits 1 to 22 in both status registers Doc ID 14279 Rev 3 4 L9954 L9954XP Functional description of the SPI 4 Table 19 SPI input data and status registers 1 Input register 1 write Status register 1 read Bit Name Comment Name Comment If Enable bit is set the device A broken VCC or SPI will be switched in active mode ee connection of the L9954 If Enable Bit is cleared device can be detectad by the 23 Enable bit goes into standby mode and all Always 1 y microcontroller because bits are cleared After power nee all 24 bits low or high is on reset device starts in not a valid frame standby mode
33. or output sources a current image at the current monitor output which has a fixed ratio 1 10000 of the instantaneous current of the selected highside driver Signal at output CM is blanked after switching on of driver until correct settlement of circuitry at least for 32 us The bits 18 and 19 of the Input Data Register O control which of the outputs OUT1 OUTA OUT5 and OUT6 will be multiplexed to the current monitor output The current monitor output allows a more precise analysis of the actual state of the load rather than the detection of an open or overload condition For example this can be used to detect the motor state starting free running stalled Moreover it is possible to regulate the power of the defroster more precise by measuring the load current The current monitor output is bidirectional c f PWM inputs PWM inputs Each driver has a corresponding PWM enable bit which can be programmed by the SPI interface If the PWM enable bit in Input Data Register 1 is set the output is controlled by the logically AND combination of the PWM signal and the output control bit in Input Data Register 0 The outputs OUT1 OUT4 and OUT6 are controlled by the PWM1 input and the output OUTS is controlled by the bidirectional input CM PMW2 For example the two PWM inputs can be used to dim two lamps independently by external PWM signals Cross current protection The three half bridges of the device are cross current protected by an intern
34. output 11 DO The diagnosis data is available via the SPI and this tristate output The output will remain in tristate if the chip is not selected by the input CSN CSN high Logic supply voltage 12 Voc For this input a ceramic capacitor as close as possible to GND is recommended Serial clock input 13 CLK This input controls the internal shift register of the SPI and requires CMOS logic levels Charge pump output 26 CP This output is provided to drive the gate of an external n channel power MOS used for reverse polarity protection PWM1 input 27 PWM1 _ This input signal can be used to control the drivers OUT1 OUT4 and OUT6 by an external PWM signal 4 Doc ID 14279 Rev 3 7 37 Block diagram and pin description L9954 L9954XP 8 37 Table 2 Pin definitions and functions continued Pin Symbol Function Highside driver output 4 and 5 Each output is built by a highside switch and is intended for resistive loads hence the internal reverse diode from GND to the output is 31 OUT4 missing For ESD reason a diode to GND is present but the energy 33 OUT5 which can be dissipated is limited Each highside driver is a power DMOS transistor with an internal parasitic reverse diode from each output to VS bulk drain diode Each output is over current and open load protected 15 16 17 20 21 22 23 24 NC Not connected pins 29 30 34 Figure 2 Conf
35. overy freguency for freco OC recovery duty cycle 1 4 kHz bit 0 Recovery frequency for frect OC recovery duty cycle 2 6 kHz bit 1 dVoyr423 dt Slew rate of OUT425 and Vs 13 5 V 0 08 0 2 0 4 V us dVourag dt OUT 45 Roag 16 8 Q H Vs 13 5 V dVoure dt Slew rate of OUT 8 0 08 0 2 0 4 V us Rioad 4 5 Q 1 tcc on is the switch on delay time tg on if complement in half bridge has to switch Off 2 5 SPI electrical characteristics Vs 8 to 16V Vcc 4 5 to 5 3V Tj 40 to 150 C unless otherwise specified The voltages are referred to GND and currents are assumed positive when the current flows into the pin Table 12 Delay time from standby to active mode Symbol Parameter Test condition Min Typ Max Unit Switching from standby to active mode tset Delay time Time until output drivers are enabled 160 300 Hs after CSN going to high ky Doc ID 14279 Rev 3 13 37 Electrical specifications L9954 L9954XP Table 13 Inputs CSN CLK PWM1 2 and DI Symbol Parameter Test condition Min Typ Max Unit Vint Input low level Voc 5V 1 5 2 0 V VinH Input high level Voc 5V 3 0 3 5 V VinHyst Input hysteresis Voc 5V 0 5 V lcsNin Pull up current at input CSN VcsN 3 5V Voc 5V 40 20 5 pA lcLKin Pull down current at input CLK Voix 1 5V 10 25 50 pA lpiin Pull down current at input DI Vp 1 5V 10 25 50 y
36. tput is built by a highside and a lowside switch which are OUT2 _ internally connected The output stage of both switches is a power 5 OUT3 DMOS transistor Each driver has an internal parasitic reverse diode bulk drain diode highside driver from output to VS lowside driver from GND to output This output is over current and open load protected ABO Power supply voltage external reverse protection required For this input a ceramic capacitor as close as possible to GND is Vs recommended Important for the capability of driving the full current at the outputs all pins of VS must be externally connected 6 7 14 25 28 32 Serial data input 8 DI The input requires CMOS logic levels and receives serial data from the microcontroller The data is an 24bit control word and the least significant bit LSB bit 0 is transferred first Current monitor output PWM2 input Depending on the selected multiplexer bits of Input Data Register this 9 CM PWM2 output sources an image of the instant current through the corresponding highside driver with a ratio of 1 10 000 This pin is bidirectional The microcontroller can overdrive the current monitor signal to provide a second PWM input for the output OUT5 Chip select not input testmode 10 CSN This input is low active and requires CMOS logic levels The serial data transfer between L9954 and micro controller is enabled by pulling the input CSN to low level Serial data
37. tube shipment no suffix Base Qty 49 Bulk Qty 1225 Tube length 0 5 532 A 3 5 B 13 8 C 0 1 0 6 All dimensions are in mm Reel dimensions 40mm min Access hole at slot location Base Qty 1000 Bulk Qty 1000 c A max 330 RE ERES Ss NI B min 1 5 i m Di C 0 2 13 F 20 2 H G measured a H a in core for v tape start T max 30 4 2 5mm min width Tape dimensions According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width Ww 24 Tape Hole Spacing PO 0 1 4 Component Spacing P 12 Hole Diameter D 0 05 1 55 Hole Diameter D1 min 1 5 Hole Position F 0 1 11 5 Compartment Depth K max 2 85 Hole Spacing P1 0 1 2 Top No components Components No components cover le ala AR tape 500mm min 500mm min um Empty components pockets sealed with cover tape Pd User Direction of Feed User direction of feed Doc ID 14279 Rev 3 35 37 4 Revision history L9954 L9954XP 7 36 37 Revision history Table 22 Document revision history Date 23 Jan 2008 Revision 1 Description of changes Initial release 24 Jun 2009 Table 21 PowerSSO 36 mechanical data Deleted A min value Changed A m
38. ued Symbol Parameter Test condition Min Typ Max Unit IDoLK Tristate leakage current Vesn Vcc 10 10 pA OV lt Vpo Vcc a Tristate input VcsN Voc 1 1 F Coo capacitance OV lt Vcc lt 5 3V Re 1 Value of input capacity is not measured in production test Parameter guaranteed by design Table 16 DO timing Symbol Parameter Test condition Min Typ Max Unit tr DO DO rise time C 100 pF ligag 1mA 80 140 ns tt po DO fall time C 100 pF lioag 1mA 50 100 ns DO enable time C 100 pF I 1mA ten DO tri L p P load 100 250 ns from tristate to low level pull up load to Vec DO disable time C 100 pF I 4mA ldis DO L tri p P load 380 450 ns from low level to tristate pull up load to Vec DO enable time C 2100 pF lioag 1mA t i p 100 250 ns en DO H from tristate to high level pull down load to GND DO disable time C 100 pF ligag 4mA tai i S 380 450 ns dis DO H tri from high level to tristate pull down load to GND V 0 3 Voc V 0 7Vcc tioo DO delay time Hg e MP T DO TACE 50 250 ns C 100pF Table 17 CSN timing Symbol Parameter Test condition Min Typ Max Unit t CSN HI time switching from Transfer of SPl command 20 CSN_HI stb standby mode to Input Register H F Transfer of SPl command lcsN Hi min CSN HI time active mode to input register 4 us ky Doc ID 14279 Rev 3 15 37 Electrical specifications L9954 L9954XP 16 37
39. will be switched to active mode Inductive loads Each half bridge is built by an internally connected highside and a lowside power DMOS transistor Due to the built in reverse diodes of the output transistors inductive loads can be driven at the outputs OUT1 to OUT3 without external free wheeling diodes The highside drivers OUT4 to OUT6 are intended to drive resistive loads Hence only a limited energy E 1mdJ can be dissipated by the internal ESD diodes in freewheeling condition For inductive loads L gt 1001H an external free wheeling diode connected to GND and the corresponding output is needed Diagnostic functions All diagnostic functions over open load power supply over undervoltage temperature warning and thermal shutdown are internally filtered and the condition has to be valid for at least 32 us open load 1ms respectively before the corresponding status bit in the status registers will be set The filters are used to improve the noise immunity of the device Open load and temperature warning function are intended for information purpose and will not change the state of the output drivers On contrary the overload condition will disable the corresponding driver over current and overtemperature will switch off all drivers thermal shutdown Without setting the over current recovery bits in the Input Data register the microcontroller has to clear the over current status bits to reactivate the corresponding drivers Doc I
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