ST L9733 handbook
Contents
1. ke De 8 HIGH LOW SIDE DRIVER 5 a VBAT RES ore SCLK E DI D i r3 20 S o i DANY i 9 2 b High Side Driver Be 5 2 Configuration i pli O H e LH l a tf SRO eee L2 vDo e e ep cu E epo X i ING Todriver6 LOW Side Driver i IN7 das Configuration e IN8 gt To driver 8 GND e Figure 8 L9733 HVAC applicative examples Stall sense Four flap motors become sequentially driven Unipolar stepper motor are selected by 4 high side configured switches If the decoupling diodes are inside the motor housing only 8 wires are needed to drive this arrangement 4 channels configured to low and 4 channels configured to high side build a quad half bridge This can drive 3 DC motors sequantially Doc ID 11319 Rev 10 29 34 Fault operation L9733 Figure 9 L9733 powertrain applicative examples Vbatt Vbatt Key On Relay Power Latch Relay Canister Purge Relay opt PWM MIL Lamp Main Relays and Lamps Driving Idle speed stepper motor driving and auxiliary loads x 30 34 Doc ID 11319 Rev 10 L9733 Application circuit 8 Application circuit Figure 10 Optimized circuit layout to achieve proper EMI ESD capability Voltage Reg R1 10 22 EMI improv2. E 4 zm N i DO Lao CS2SCLK DO B hm a A tah DOa FAULTLSB X X Fa MSB x DI MR bi XM Ma DILSB y x DI MSB X Dlsus d V v k Dis ky Doc ID 11319 Rev 10 17 34 Functional description L9733 A 4 1 4 2 18 34 Functional description L9733 integrates 8 self configuring outputs OUT 1 8 which are able to drive either incandescent lamps inductive loads non pwm d in pwm is necessary an external diode to reduce flyback power dissipation or resistive loads biased to Vbat low side configuration or to GND high side configuration These outputs can be enabled and disabled via the SPI bus Each of these outputs has a short circuit protection with 0 8 2 4 Amps threshold selectable via SPI bus between a filtered switching OFF overcurrent protection or a linear current limitation default condition after power ON is switching OFF protection enabled An over temperature protection as described in Section 2 1 is available for each outputs When a high side configured output is commanded OFF after having been commanded ON the source voltage will go to VGND 15 V This is due to the design of the circuitry and the transconductance of the MOSFET When a low side configured output is commanded OFF after having been commanded ON the output voltage will rise to the internal zener clamp voltage 50 VDC minimum due to the flyback of the inductive load Outputs 1 8 are able to drive any comb
3. Symbol Parameter Value Unit Vda Supply voltage 4 5 to 5 5 V Vpa operative 4 5N to 18 range Vra JSC 18 to 27 Vra low Battery supply voltage V battery Vbat load 27 to 40 dump Tj Thermal junction temperature range 40 to 150 C Snubbing voltage of DRN1 8 min 50 VDC lox Output current 1 8 max 800 mA Eso Maximum clamping energy at switch off 20 mJ Functional operative range 4 5 V lt Vpat lt 18 V 40 C lt T lt 150 C All the electrical capabilities are guaranteed by characterization as reported in Section 3 Electrical performance characteristics Jump start conditions 18 V Vhat lt 27 V 40 C lt T lt 150 C Operation at Jump start condition for a maximum duration of 1 minute All ouputs are switched according to the commands on the SPI bus or the PWM inputs The SPI bus and the inputs are functional during the Jump Start condition The over temperature shutdown and over current protection of the device is not guaranteed to stay functional for Vbat between 18 V and 27 V The reliability and the functionality of the L9733XP are not compromised when the Jump Start condition is not repeated for more than five times Doc ID 11319 Rev 10 ky L9733 Operating conditions 2 1 3 Operation at low battery condition 3 5 V lt Vhat lt 4 5 V 40 C lt Tj lt 150 C All outputs are able to keep the status in according to the commands on the SPI bus or the
4. 0 7vdo V IN6 input voltage IN6vii 0 3vdo V linei In6 0 VDC 1101 A D IN6 input current liN6ih In6 VDO 10 E 100 HA IN7Vin 0 7vdo V IN7 input voltage IN7vi 0 3vdo V liNil In7 0 VDC E 1101 HA INZ input current liN7ih In7 VDO 10 100 HA IN8vjn x zi 0 7vdo IN8 input voltage IN8vii 0 3vdo V liNai In8 0 VDC 110 A gi IN8 input current a liN8ih In8 VDO 10 100 HA CSin 0 7vdo V CS input voltage CS 0 3vdo Ei V Icsi CS VDO 110 pA 2r CS input current Icsil CS 0 VDC 10 100 HA SCLKi E 0 7vdo V SCLK input voltage SCLKj 0 3vdo i V l i SCLK VDO 1101 pA Se SCLK input current ISCLKil SCLK 0 VDC 10 100 uA Dlin E 0 7vdo DI input voltage Dli 0 3vdo Ipiih DI VDO T 7 1101 HA DI input current Ipiii DI 20 VDC 10 100 HA DO Ipo 2 5mA 0 4 V DO output voltages DOon Ibo 2 5mA vdo 0 6 gt y Doc ID 11319 Rev 10 11 34 Electrical performance characteristics L9733 Table 6 DC characteristics continued Symbol Parameter Conditions Min Typ Max Units DO 0 VDC 1101 pA pila DO Tri state currents IDOzoh DO VDO gt 1101 HA RESi 0 7vdo V RES input voltage RES 0 3vdo V InESi RES 0 VDC 10 100 pA RES input current InESih RES VDO 1101 HA 40 C 2 8 4 2 POR Power on reset threshold 25 C 2 8 3 7 V 125 C 2 3 4 VDD SRC1 8 OVDC V
5. ky L9733 Octal self configuring low high side driver Features m Eight independently self configuring low high drivers m Supply voltage from 4 5 V to 5 5 V RoN max 0 70 Tj 25 C RoN max 1 2 Q QT 125 C m Minimum current limit of each output 1 A m Output voltage clamping min 40 V in low side configuration m Output voltage clamping max 14 V in high side configuration m SPlinterface for outputs control and for diagnosis data communication m Additional PWM inputs for 3 outputs m Independent thermal shutdown for all outputs open load short to GND short to Vb overcurrent diagnostics in latched or unlatched mode for each channel m Internal charge pump without need of external capacitor m Controlled SR for reduced EMC Description The L9733 is a highly flexible monolithic medium current output driver that incorporates 8 outputs that can be used as either internal low or high side drives in any combination PowerSSO 28 Outputs 1 8 are self configuring as high or low side drives Self configuration allows a user to connect a high or low side load to any of these outputs and the L9733 will drive them correctly as well as provide proper fault mode operation with no other needed inputs In addition outputs 6 7 and 8 can be PWM controlled via a external pins IN6 8 This device is capable of switching variable load currents over the ambient range of 40 C to 125 C Th
6. PWM inputs Switching commands entered via the SPI bus might not be executed by the L9733 at low battery condition The SPI bus and the inputs are functional during the Low Battery condition 2 1 4 Operation at load dump condition 27 V lt Vhat lt 40 V 40 C lt Tj lt 150 C There is not an internal circuit that switches OFF the drivers during load dump condition The over temperature shutdown and over current protection of the device is not guaranteed to stay functional during load dump condition 2 1 5 Loss of protection against short to battery When the battery supply voltage Vpat pin 14 is switched off during a short to battery condition at a output in high side configuration the protection circuits are no longer functional and the L9733 may fail with EOS 2 2 Absolute maximum ratings This part may be irreparably damaged if taken outside the specified absolute maximum ratings Operation outside the absolute maximum ratings may also cause a decrease in reliability Table 4 Absolute maximum ratings Symbol Parameter Value Unit Vpp Supply voltage 0 3 to 7 V Vbat Supply voltage 0 3 to 40 V CS DI DO SCLK EN IN6 IN7 IN8 VDO 0 3 to 7 0 V SRCx pin min 24 VDC Max value of Vancy Minimum of Vpat 1V IIl Vpryx 0 3 V III 40 V DRN1 8 0 3 to 60 VDC lo Current limit of output 1 8 40 C 2 5 A lop Over current protection at output 1 8 40 C 3 A Maximum clamping energy 20 m
7. Bopen Voltage High side SCR1 8 2 0 2 8 V DRN1 DRNS FE open DI ACFFh DI AAFFh i B DRN1 DRN8 SRC1 SRC8 0 VDC DRNImIU current limits DRN1 DRN8 4 5 16 VDC DRN alimit low side Tamb gt 0 C 1 2 2 A Tamb 40 C 1 2 5 A DI ACOOh DI AA00h SRC1 l DRN1 DRN8 SRC8 0 VDC de overcurrent threshold DRN1 DRN8 4 5 16 VDC DRNBOVC low side Tamb gt 0 C 1 2 7 A Tamb 40 C 1 3 A DI ACFFh DI AAFFh SRC1 SRC8 DRN1 DRN8 Vb E current limits SRC1 SRC8 GND SRC8limit high side Tamb gt 0 C 1 29 A Tamp 40 C 1 2 5 A DRN1 DRN8 Vbat lenciovc Overcurrent threshold SRC1 SRC8 GND lenceovc _ high side Tamb gt 0 C 1 2 7 A Tamp 40 C 1 3 A DRNig DRN1 DRN8 DI ACOOh m d Y DRN8c Clamp voltages low side SRC1 8 GND IDRN1 8 350 mA SRC1ig SRC1 SRC8 i DI ACOOh D g 44 V SRC8ci Clamp voltages High side DRN1 8 Vbat lagc4 g 350 mA Vprn1 8open Short to GND threshold SRC1 SRC8 GND DRN1 distance from open load Decrease Drn1 Drn8 until Faults 0 3 0 7 V 8vinenp Voltage low side are Set DRN1 DRN1 DRN8 DI ACOOh 8 _ Short to Vbat threshold SRC1 SRC8 GND Increase 03 7 0 7 V VinVbat distance from open load Drn1 Drn8 until Faults are Not i l Drn1 8open_ voltage low side Set SRC1 SRC8 Vornt 8open Short to GND threshold DEP SRC1 distance from open load Drn1 Drn8 Vb
8. Decrease SRC1 0 2 0 6 V BVNGND voltage High side SRC8 until Faults are Not Set SRC1 SRC1 SRC8 DI ACOOh 8 Short to Vbat threshold Drn1 Drn8 Vbat Increase 0 2 0 6 V VihVbat distance from open load SCR1 SCR8 until Faults are f VDrn1 8open i d P voltage High side Set ky Doc ID 11319 Rev 10 13 34 Electrical performance characteristics L9733 Table 6 DC characteristics continued Symbol Parameter Conditions Min Typ Max Units 125 C IDRN 350 mA x 1 2 Q 1 On resistance E Rdsonprmn1 8 Drn to SRC1 8 25 C IDRN 350 mA 0 7 Q 40 C IDRN 350 mA 0 5 Q DI ACFFh Ipmia 1 MA 2 Thermal shutdown SRC1 SRC8 GND Increase Drn1 8ther temperature temperature until Drn1 Drn8 gt 2 we od P VDC Verify DO Bits 0 15 are Set Drni 8ya Hysteresis Drn1 Drn8 lt 2 VDC 5 15 C 1 RasonDmi a lt 1 2 Q at Vbat between 3 5 V and 27 V and T between 40 C and 150 C 2 Design Information not tested 3 2 AC characteristics Tamb 40 to 125 C Vag 4 5 to 5 5 Vdc Vhat 4 5 to 18 Vdc unless otherwise specified Table 7 AC characteristics Symbol Parameter Conditions Min Typ Max Units DRN1 DRN8 Open load amp short to DI ACOOh DI A3FFh ThitORN1 8 GND filter time low side SRC1 SRC8 GND N 900 pe Latch mode SRC1 SRC8 Open loa
9. IN7 Discrete input used to PWM output driver 7 14 Vbat Battery supply voltage 15 GND _ Analog ground 16 IN8 Discrete input used to PWM output driver 8 17 RES Reset input active low 18 SRC5 Source pin of configurable driver 5 0 7 Q Rdso 25 C 4 Doc ID 11319 Rev 10 L9733 Pin description Table 2 Pin description continued N Pin Function 19 DRN5 Drain pin of configurable driver 5 0 7 Q Rdso 25 C 20 DRN6 Drain pin of configurable driver 6 0 7 Q Rdso 25 C 21 SRC6 Source pin of configurable driver 6 0 7 Q Rdso 25 C 22 SRC7 Source pin of configurable driver 7 0 7 Q Rds 25 C 23 DRN7 Drain pin of low side driver 7 0 7 Rds 25 C 24 DRN8 Drain pin of low side driver 8 0 7 Q Rds 25 C 25 SRC8 Source pin of configurable driver 8 0 7 Q Rdso 25 C 26 DI SPI data in 27 DO SPI data out 28 VDO Microcontroller logic interface voltage Note The exposed slug must be soldered on the PCB and connected to GND Doc ID 11319 Rev 10 7 34 Operating conditions L9733 2 2 1 8 34 Operating conditions Operating range This part may not operate if taken outside the operating range Once the condition is returned to within the specified maximum rating or the power is recycled the part will recover with no damage or degradation Table 3 Operating range
10. and then open load or short circuit to Vb this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to Vbat faults that happen before that the register is cleared will be ignored 7 2 1 No latch mode This diagnostic operating mode doesn t latch open load and short to Vbat faults 1 Open load The diagnostic of open load is detected only in OFF condition sensing the Src1 8 output voltage This fault is detected on the falling edge of the CS input if the power drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth GND An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected 2 Short Circuit to Vb The diagnostic of short circuit to Vbat is detected only in OFF condition sensing the Src1 8 output voltage This fault is detected on the falling edge of the CS input if the power drain voltage is higher than the Vth Vbat threshold 3 Overcurrent The diagnostic of overcurrent is detected only in ON condition if the switching OFF protection of the channel is enabled default sensing the current level of the output power transistor If the output current has been above the short threshold lovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register There are three possibilities to restart one output after the fau
11. 025 e3 8 45 0 033 F 2 3 0 090 G 0 10 0 004 G1 0 06 0 002 H 10 10 10 50 0 398 0 413 h 0 40 0 016 k 5 typ L 0 60 1 0 0 023 0 039 M 4 3 0 169 N 10 max Oo 1 2 0 047 Q 0 8 0 031 S 2 9 0 114 T 3 65 0 144 U 1 0 0 039 X 4 2 48 0 165 0 189 PowerSSO 28 Y 6 6 7 2 0 259 0 283 1 D and E do not include mold flash or protrusions Mold flash Exposed pad or protrusions shall not exceed 0 15 mm per side 0 006 lt 2 f Ee HH tf i LAAT L te j ep d i ub A TT 23 lag q ua lt Mk 1 ES pe mmm z i mn 7633868 C 4 Doc ID 11319 Rev 10 L9733 Revision history 10 Revision history Table 13 Document revision history Date Revision Changes 13 Apr 2005 1 Initial release 15 Jun 2006 2 Changed only look and feel 08 Aug 2006 3 Modified Table 9 Bit command register definition on page 22 28 May 2007 4 Changed the min value of the CSlead parameter on the Table 8 en dr OT cina sus tom Tien dea to ese 03 Aug 2007 6 Updated in Table 4the ESD parameter Added order codes in Table 1 Device summary 12 Jun 2008 7 Added CS2SCLK p
12. alidate the thermal fault 5 us to 20 us There is a 5 to 15 C hysteresis between the enable and disable temperature levels The faulted channel will periodically turn off and on until the fault condition is cleared the ambient temperature is decreased sufficiently or the output is commanded off If a thermal shutdown of one or more output drivers is active during the falling edge of the chip select CS signal all the bits of the Fault Register are setted to 1 thermal shutdown is not latched and could be read only in the moment it is present The thermal fault is cleared on the rising edge of Chip Select if a valid DI byte was received Due to the design of the L9733 each output s thermal limit may not be truly independent to the extent that if one output is shorted it may impact the operation of other outputs due to lateral heating in the die Doc ID 11319 Rev 10 ky L9733 Fault operation 7 Fault operation The fault diagnostic capability consists of one internal 16 bits shift register and 2 bits are used for each output The diagnostic information are no fault present overcurrent open load and short circuit For L9733XP all of the faults will be cleared on the rising edge of chip select if a valid DI byte was received For L9733CN The OVC register will be cleared after the end of the diagnosis restart time Tres or by the in
13. arameter in Table 8 SPI characteristics and timings Updated Figure 6 SPI timing diagram Updated Table 1 Device summary on page 1 Removed all references to the SO 28 package Updated Section 2 1 Operating range and Section 2 2 Absolute maximum ratings 02 Dec 2008 8 Added Section 2 1 1 Functional operative range Section 2 1 2 Jump start conditions Section 2 1 3 Operation at low battery condition and Section 2 1 4 Operation at load dump condition Added Section 8 Application circuit Added POR parameter in Table 6 DC characteristics Updated Table 1 Device summary on page 1 13 May 2009 9 Updated Figure 11 PowerSSO28 mechanical data and package dimensions Updated Table 1 Device summary on page 1 27 Jul 2010 10 Updated Section 7 Fault operation on page 25 4 Doc ID 11319 Rev 10 33 34 L9733 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice sel
14. bai sleep c trent DRN1 DRN8 18VDC Vb Sum g sip p currents Tamb gt 0 C 10 uA Tamp 40 C 3 HA Vbat current ed 15 mA vba All Outputs Commanded On lypp Max VDD current All Outputs Commanded On 8 5 mA lypp Min VDD current All Outputs Commanded Off 0 5 mA DRN1 DRN8 VDD 0 VDC SRC1 8 0 VDC DENA leakage currents DRN1 DRN8 16 VDC 5 uA DANS ow side DRN1 DRN8 40 VDC 10 uA i SRC1 SRC8 VDD 0 VDC SRC1 8 0 VDC a Leakage currents DRN1 8 16 V 5 HA SROB high side DRN1 8 40 VDC 40 pA BENDER ER a SRC1 8 GND DI ACOOh sink curren IDrn1 8sink low side Rioad lt 11 KQ 10 H 100 pA Rigag lt 200 KQ 120 280 uA Bas perdon saison VBAT gt 9V 11 200 Ko resistance IDrni 8source Source current DRN1 DRN8 GND 10 100 HA DRN1 8 Vb DI ACOOh lsrc1 8sink EH eeu E sink source current SCR1 8 Vb 10 100 HA lsre1 8source high side SCR1 8 GND 18 100 uA SRC1 8 GND DI ACOOh DRN1 DRN8 Open 2 7 3 1 V id K me VDD 4 9 to 5 1 VDC Drn1 8 open load voltage SP M dw aide SRC1 8 GND DI ACOOh DRN1 DRN8 Open 2 5 3 5 V VDD 4 5 to 5 5 V 12 34 Doc ID 11319 Rev 10 q L9733 Electrical performance characteristics Table 6 DC characteristics continued Symbol Parameter Conditions Min Typ Max Units SRC1 SRC8 open load DRN1 8 Vb DI ACOOh Vsrct
15. ble 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 4 34 Device sumtmary iue ee eed ete eee Pare bea ea Pee ded oe era 1 PIN description us Pubs eae oca ined unes tede onde See eae eaa 6 Operating range is ER pau e ur ku eee oa ee ee a et wee ee ee ert 8 Absolute maximum ratings 0 6 0 eee ee 9 Thermal data EE ete ae uk s Re eae ee aba CR Fr bate Soh war ad Gee 10 DC characteristics 0 0 0 11 AC characteristics secs sea sud Ok Ra vad Ead pr EORR RICE Peay eee we 14 SPI characteristics and timings liliis 16 Bit command register definition lier 22 Command register logic definition llle 23 Fault register definition EE EE Ee Ek ee Ee ee Ge mh 25 Fault logic definition EE EE EE Ee EE Ee SE Ee ee Ek ee RI III 25 Document revision history lt ie EE EE Ee eee 33 Doc ID 11319 Rev 10 ky L9733 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Pin connection top VIEW EE EE EE EE eee 6 Output turn on off delays and slew rates is SE eee eee 15 DO loading for disable time measurement EE EE EG EE eens 17 Output loading for slew rate measurements se EE SE eee eee 17 SPI input output timings ei EE RE Ee ee ER ee Se ee ee ee de ed dee ee 17 SPI timing diagram 2 EE Ee ER Ee ee hr 17 L9733 applicat
16. bsolute maximum ratings esse EE EE Re ee EE ee 9 2 3 Thermal data sis ete Re arin aa GER Ee de de Re wl N 10 3 Electrical performance characteristics 11 3 1 DE characteristics auc pigs BERE ca ACA Coe aC Rb do dC Be od RAS E 11 3 2 AC characteristics sos TRAP ROTER UT dob Dua did OE dom DA 14 3 3 SPI characteristics and timings 0 cece eee eee 16 4 Functional description 0 0 cee eee ee 18 4 1 Configurations for outputs 1 8 2 EE EE EE ee ek ed ek ee 18 4 1 1 Low side drivers ses SE ER ee eee 18 4 1 2 High side drivers 0 cee eee 18 4 2 Outp ts MEE EE EE 9t Ac OE OE eed ac doe dvo taper d 18 43 QUIDIIS DD 5 241 EEN RUE T EAS E HORE Pod ESE TER 19 4 4 Drn1 8 susceptibility to negative voltage transients 19 4 5 Supply PINS uia d isse de Ex aU end a DE EA ERR E d RR REPE 19 4 5 1 Main power input Vdd EE ES EE ee Ge Ee eres 19 4 5 2 Battery supply Vbat EE EE ee 19 4 5 3 Discrete inputs voltage supply VDO ee se eee eee 19 4 6 Discrete inputs suere 045504463 E PRAGA ACRI Re Pane e Reg di 20 4 6 1 Output 6 8 enable input In6 In7 InB liliis 20 4 6 2 Reset input RES ixi si dad eg ex v aco re ie OG dade A 20 5 Serial peripheral interface SPI Llles sse 21 2 34 Doc ID 11319 Rev 10 ky L9733 Contents 5 1 Serial data output DO sesse PERE DORRE RES EERS e heat duane 21 5 2 Serial
17. d amp short to DI ACOOh DI A3FFh TitsRC1 8 Vbat filter time DRN1 DRN8 Vb 300 z 900 us high side Latch mode DRN1 DRN8 T Overcurrent switch off DI ACFFh DI AA00h 10 75 delDRN1 8 delay SRC1 SRC8 GND P low side SRC1 SRC8 Overcurrent switch off DI ACFFh DI AAOOh TdelsRC1 8 delay DRN1 DRN8 Vb n s m high side Restart time after Tres overcurrent switch off DI ACFFh DI AAOOh 120 450 ms time Int Slew rate Outputs loaded as Figure 4 Drn1 Bhtol 7 turn on See Figure 2 0 65 1 95 V us Drni 8gg Turn off low side See Figure 2 0 5 1 5 V us 14 34 Doc ID 11319 Rev 10 ky L9733 Electrical performance characteristics Table 7 AC characteristics continued Symbol Parameter Conditions Min Typ Max Units Slew rate Outputs loaded as Figure 4 SRC1 8hto1 turn on See Figure 2 0 65 1 95 V us SRC1 8io Turn off High side See Figure 2 0 5 1 5 V us Drn1 8 Delay time Outputs loaded as Figure 4 i tondly Turn on See Figure 2 2 20 us Drn1 8toffay Turn off low side See Figure 2 10 100 us SRC1 8 Delay time Outputs loaded as Figure 4 tondly Turn on See Figure 2 2 20 us SRC1 8toftaly Turn off high side See Figure 2 10 100 US Drn1 Bofon Delay delta Drn1 8toffaly DrNT Btondiy 10 60 US SRC1 Boon Delay delta SRC1 Broffdiy SRC1 Brondly 10 60 US Figure 2 Output turn on of
18. data input DI ss kes WERE BAD ES RR NR DE dE AN RE we x 21 53 Chip select CS coss KERKE EE KEER eben EE DRS be KS ee OE DR RS 21 54 Serial clock SCLK RE deve ee BEES BE WERNER EERS DEE RE 22 5 5 Initial input command register and fault register SPI cycle 22 5 6 Input command register used ERENS ROES Re ESE RR ES Leet oe RR HE 22 6 Other L9733 features ie EE EE ER ER EER EE N WETE N EEN EE RENEE RE 24 6 1 Charge pump usage is seges hence EE ORAEE RES ORR SERE R GE DE N 24 6 2 Waveshaping ss beets edes aea p bo Races Doe RR we Genesee pes 24 6 3 POR register initialization llle 24 6 4 Thermal shutdown selle 24 7 Fault operation adi sace one knee RC OR QR a ER d eee Roe S m 25 7 1 Low side configured output fault operation EE EE Ee ee 25 7 1 1 No latch mode 0 000 cee ens 25 7 1 2 Lateh mode vss e eR hehe ONG se Ra a hee eee aha 26 7 2 High side configured output fault operation ie EE ke ee 27 7 2 1 Noilatch mode i se sese RE RR RE eaa ER E eee te 4E ed 27 7 2 2 Latch mode e ER HR RE BE RE RE DE SG Re RR EE RE ae DR 28 8 Application circuit 23 seis sieke ss n ER EER ER EE EERS ESE DR EER ER EE 31 9 Package information LLlleeeeeeeeeee 32 10 Revision hiSTOI V sesse se bie dee exa ca X ROCK UR CR RON OR Ee C yd ee 33 y Doc ID 11319 Rev 10 3 34 List of tables L9733 List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Ta
19. detected only in OFF condition sensing the Src1 8 output voltage This fault is detected if the power drain voltage is higher than the Vth Vbat threshold for the filtering time Tfilt Overcurrent The diagnostic of overcurrent is detected only in ON condition if the switching OFF protection of the channel is enabled default sensing the current level of the output power transistor If the output current has been above the short threshold lovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register There are three possibilities to restart one output after the fault has occurred Automatically after a time Tres Ontherising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic 0 and then with a logic 1 in the following SPI cycle Onthe rising edge low to high transition at the corresponding parallel input pin only for Outputs 6 8 If the switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available If the power MOS transient after a switching off command is longer than Tdel filtering time a bad diagnostic behavior happens and software filtering may be needed Doc ID 11319 Rev 10 ky L9733 Fault operation Figure 7 L9733 application schematic
20. e outputs are MOSFET drivers to minimize Vdd current requirements For low side configured outputs an internal zener clamp from the drain to gate with a breakdown of 50 V minimum will provide fast turn off of inductive loads When a high side configured output is commanded Off after having been commanded On the source voltage will go to VGND 15 V An 16 bit SPI input is used to command the 8 output drivers either On or Off reducing the VO port requirement of the microcontroller Multiple L9733 can be daisy chained In addition the SPI output indicates latched fault conditions that may have occurred Table 1 Device summary Order code Package Packing L9733XP PowerSSO 28 Exposed pad Tube L9733XPTR PowerSSO 28 Exposed pad Tape and reel L9733CN PowerSSO 28 Exposed pad Tube L9733CNTR PowerSSO 28 Exposed pad Tape and reel July 2010 Doc ID 11319 Rev 10 1 34 www st com Contents L9733 Contents 1 PIN GESCIIDUON sos e Ee E x63 DR BR a t don GER ER ME SERE 6 2 Operating conditions sa ss sn n ER N no ec e e RR RC RR N 8 2 1 Operating range uode bc ER anes BeBe OS EE OR we 8 2 1 1 Functional operative range 2 cc tee 8 2 1 2 Jump start conditions auauua EE SE EE ne 8 2 1 3 Operation at low battery condition EE EE EE EE ee eee 9 2 1 4 Operation at load dump condition EE EE EE EE ER ee eee 9 2 1 5 Loss of protection against short to battery EE EE EE ee 9 2 2 A
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22. ement pum 47 100nF Positive ISO pulse Ceramic protection Reverse polarity amp neg ISO pulse protection Battery 47 100nF Ceramic Bes 1 DRNX All output C 47nF ceramic T VDD on off for low quiescent current Capacitor impedance Frequency VBAT supplies the floating charge pump Filtering capacitor C1 is important to achieve a proper EMI performance Impedance minimum should fit to the critical frequency range A series resistor to VBAT can improve furthermore EMI performance Central ground plane blue coloured Module Connector 4 Doc ID 11319 Rev 10 31 34 Package information L9733 9 32 34 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Figure 11 PowerSSO28 mechanical data and package dimensions DIM mm inch MIN TYP MAX MIN TYP MAX OUTLINE AND A 2 15 2 45 0 084 0 0965 A2 2 15 2 35 0 084 0 0925 MECHANICAL DATA al 0 0 10 0 0 004 b 0 18 0 36 0 007 0 014 c 0 23 0 32 0 009 0 012 D 1 10 10 10 50 0 398 0 413 E 1 7 4 7 6 0 291 0 299 e 0 65 0
23. f delays and slew rates DRN1 8htol DRN1 8ltoh ie DRN1 8tondiy DRN1 Btoffdiy 80 80 HSD SRC1 8 10994 SRC1 8 N 1 SRC1 8ltoh Fm SRCtSht SRC1 8tondly SRCI 8toffdly gt IN1 5 are available on wafer oly ky Doc ID 11319 Rev 10 15 34 Electrical performance characteristics L9733 3 3 SPI characteristics and timings Tamb 40 to 125 C Vag 4 5 to 5 5 Vdc Vpat 4 5 to 18 Vdc unless otherwise specified Table 8 SPI characteristics and timings Symbol Parameter Conditions Min Typ Max Units DINGin 20 pF Input capacitance SCLKcin 20 pF Output data do 50 pF from DO to Ground i DOrse rise time See Figure 5 N d Output data do I DO fall time See Figure 5 70 ns DO Access time See Figure 6 350 ns DOgum Set up time See Figure 6 20 ns DOrm Hold time See Figure 6 10 ns Output data DO F g DOgis disable time No Capacitor on DO See Figure 5 400 ns ttheitt Filter time All Fault bits are Set 5 20 us SCLKwid SCLK width See Figure 5 fsck 5 4MHz 185 ns SCLKIm SCLK low time See Figure 5 fsck 5 4MHz 58 ns SCLKhm SCLK high time See Figure 5 fsck 5 4MHz 58 ns SCLKrise SCLK rise time See Figure 5 fac 5 4MHz 21 ns SCLKfal SCLK fall time See Figure 5 fgg 5 AMHz 21 ns CSrise Channel select CS See Figure 5 100 ns rise ti
24. face consisting of Serial Clock SCLK Data Out DO Data In DI and Chip Select CS All outputs will be controlled via the SPI The input pins CS SCLK and DI thanks to VDO pin have level input voltages allowing proper operation from microcontrollers that are using 5 0 or 3 3 volts for their Vdd supply The design of the L9733 allows a daisy chaining of multiple L9733 s to further reduce the need for controller pins Serial data output DO This output pin is in a tri state condition when CS is a logic 1 When CS is a logic 0 this pin transmits 16 bits of data from the fault register to the digital controller After the first 16 bits of DO fault data are transmitted after a CS transition from a logic 1 to a logic 0 then the DO output sequentially transmits the digital data that was just received 16 SCLK cycles earlier on the DI pin The DO output continues to transmit the 16 SCLK delayed bit data from the DI input until CS eventually transitions from a logic 0 to a logic 1 DO data changes state 10 nsec or later after the falling edge of SCLK The LSB is the first bit of the byte transmitted on DO and the MSB is the last bit of the byte transmitted on DO once CS transitions from a logic 1 to a logic 0 Serial data input Dl This input takes data from the digital controller while CS is low The L9733 accepts an 16 bit byte to command the outputs on or off The L9733 also serially wraps around the DI input bits to t
25. figured output is commanded OFF Drain pins of Outputs 6 8 Drn6 8 are connected to the drains of the N channel MOSFET transistors Source pins of Outputs 6 8 Src6 8 are connected to the sources of the N channel MOSFET transistors Drn1 8 susceptibility to negative voltage transients All outputs connected in the low side configuration must have a ceramic chip capacitor of O O1uF to 0 1 pF connected from drain to ground This is needed to prevent potential problems with the device operation due to the presence of fast negative transient s on the drain s of the device Adequate de coupling capacitors from the Drain VBAT to ground shall be provided for high side configured outputs Supply pins Main power input Vdd An external 15 0 0 5 VDC supply provided from an external source is the primary power source to the L9733 This supply is used as the power source for all of its internal logic circuitry and other miscellaneous functions Battery supply Vbat This input is the supply for the on board charge pump This input shall be connected directly to battery If this input is not connected to the same supply without additional voltage drops of the drains of any high side connected outputs then the Rdson of that given output will be higher than the specified maximum Discrete inputs voltage supply VDO This pin is used to supply the discrete input stages of L9733 and must be connected to the same voltage used to supply the per
26. g 7 Diag 6 Diag 5 Diag 4 Diag 3 Diag 2 Diag 1 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 DO Key word Writing mode protect Driver overcurrent protection LSB 1 0 1 0 1 O Ilim 8 llim 7 Ilim 6 Ilim 5 Ilim 4 Ilim 3 Ilim 2 Ilim 1 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 DO 22 34 Doc ID 11319 Rev 10 ky L9733 Serial peripheral interface SPI Table 10 Command register logic definition Bit State Status Writing mode bO b7 0 OUT1 OUT8 are commanded off Output bO b7 1 OUT1 OUT8 are commanded on Output bO b7 0 OUT1 OUT8 diagnostic is No Latch Mode Diag bO b7 1 OUT1 OUT8 diagnostic is Latch Mode Diag bO b7 0 OUT1 OUT8 switching OFF overcurrent protection Protection bO b7 1 OUT1 OUT8 linear overcurrent protection Protection Doc ID 11319 Rev 10 23 34 Other L9733 features L9733 6 6 1 6 2 6 3 6 4 Note 24 34 Other L9733 features Charge pump usage In order to provide low Rdson values when connected in a high side configuration a charge pump to drive the internal gate voltage s above Vbat is implemented The charge pump used on the L9733 doesn t need external capacitor The L9733 uses a common charge pump and oscillator for all the 8 configurable output channels The charge pump uses the Vbat
27. he DO output after the DO output transmits its 16 fault flag bits The LSB is the first bit of each byte received on DI and the MSB is the last bit of each byte received on DI once CS transitions from a logic 1 to a logic 0 The last 4 bits b15 b12 of the first 16 bit byte are used as key word The 4 bits b11 b8 of the first 16 bits byte are used to select writing mode between OUT8 1 status and diagnosis operating mode The DI input has a nominal 100 KO resistor connected from this pin to the VDO pin which pulls this pin to VDO if an open circuit condition occurs Chip select CS This is the chip select input pin On the falling edge of CS the DO pin is released from tri state mode While CS is low register data are shifted in and shifted out the DI pin and DO pin respectively on each subsequent SCLK On the rising edge of CS the DO pin is tri stated and the fault register is Cleared if a valid DI byte has been received A valid DI byte is defined as such a multiple of 16 bits was received a valid key word was received The fault data is not cleared unless all of the 2 previous conditions have been met The CS input has a nominal 100 kO resistor connected from this pin to the VDO pin which pulls this pin to VDO if an open circuit condition occurs Doc ID 11319 Rev 10 21 34 Serial peripheral interface SPI L9733 5 4 5 5 5 6 Table 9 Serial clock SCLK This is the clock signal input for sync
28. hronization of serial data transfer DI data is shifted into the DI input on the rising edge of SCLK and DO data changes on the falling edge of SCLK The SCLK input has a nominal 100kQ resistor connected from this pin to the VDO pin which pulls this pin to VDO if an open circuit condition occurs Initial input command register and fault register SPI cycle After initial application of Vdd to the L9733 the input command register and the fault register are Cleared by the POR circuitry and that means that the default condition for the output status is Off the default diagnostic mode is No Latch and the switching OFF overcurrent protection is enable During the initial SPI cycle and all subsequent cycles valid fault data will be clocked out of DO fault bits Input command register An input byte 16 bits is routed to the Command Register The content of this Command Register is given in table 9 Additional DI data will continue to be wrapped around to the DO pin If CS should happen to go high before complete reception of the current byte this just transmitted byte shall be ignored invalid Bit command register definition Key word Writing mode output Output status 0 LSB 1 0 1 1 0 O JOUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 DO Key word Writing mode diag Driver diag mode 0 LSB 1 0 0 0 1 1 Diag 8 Dia
29. iagnostic of open load is detected only in OFF condition sensing the Drn1 8 output voltage This fault is detected on the falling edge of the CS input if the power Doc ID 11319 Rev 10 25 34 Fault operation L9733 26 34 drain voltage is inside the voltage range limited by the two thresholds Vth_Vbat and Vth_GND An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected Short circuit to GND The diagnostic of short circuit to GND is detected only in OFF condition sensing the Drn1 8 output voltage This fault is detected on the falling edge of the CS input if the power drain voltage is lower than the Vth_GND threshold Overcurrent The diagnostic of overcurrent is detected only in ON condition if the switching OFF protection of the channel is enabled default sensing the current level of the output power transistor If the output current has been above the short threshold love for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register There are three possibilities to restart one output after the fault has occurred Automatically after a time Tres Onthe rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic 0 and then with a logic 1 in the following SPI cycle Onthe rising edge low to high
30. ination of inductive loads or lamps at one time Inductive loads for the L9733 can range from 35mH to a maximum of 325 mH The recommended worst case solenoid loads at 40 C are calculated using a minimum resistance of 40Q for each output The maximum single pulse inductive load energy the L9733 outputs is able to be safely handle is 20 mJ at 40 C to 125 C Worst case load of 325 mH and 40 Configurations for outputs 1 8 The drain and source pins for each output must be connected in one of the two following configurations see Figure 7 Low side drivers When any combination of outputs 1 8 are connected in a low side drive configuration the source of the applicable output Src1 8 shall be connected to ground The drain of the applicable output Drn1 8 shall be connected to the low side of the load High side drivers When any combination of outputs 1 8 are connected in a high side drive configuration the Drain of the applicable output Drn1 8 shall be connected to Vbat The source of the applicable output Src1 8 shall be connected to the high side of the load Outputs 1 5 These five outputs can be used as either high or low side drives The room temperature Rdson of these outputs is 0 7 Q A current limited 100 pA max voltage generator is connected to Src 1 5 for open load and short to GND detection when a low side configured output is commanded OFF Another current limited 100 pA max if VDrn 1 5 gt 60 Vbat 280 pA
31. ion schematic EE EE Ee tenes 29 L9733 HVAC applicative examples ses Ee Se ee ee ee ee Re ek ee ke de 29 L9733 powertrain applicative examples EE EE EE EE EE RR ee 30 Optimized circuit layout to achieve proper EMI ESD capability 31 PowerSSO28 mechanical data and package dimensions sulss 32 Doc ID 11319 Rev 10 5 34 Pin description L9733 1 6 34 Pin description Figure 1 Pin connection top view VDD 1 VDO SCLK 2 DO CS 3 D1 SRC1 4 SRC8 DRN1 5 DRNS DRN2 6 DRN7 SRC2 7 SRC7 SRC3 8 SRC6 DRNS 9 DRN6 DRN4 10 DRN5 SRC4 11 SRC5 IN6 12 RES IN7 13 IN8 Vbat 14 GND D06AT544 Table 2 Pin description N Pin Function 1 VDD 5 Volt supply input 2 SCLK SPI serial clock input 3 CS SPI chip select active low 4 SRC1 Source pin of configurable driver 1 0 7 Q Rds 25 C 5 DRN1 Drain pin of configurable driver 1 0 7 Q Rds 25 C 6 DRN2 Drain pin of configurable driver 2 0 7 Q Rdso 25 C 7 SRC2 Source pin of configurable driver 2 0 7 Q Rdso 25 C 8 SRC3 Source pin of configurable driver 3 0 7 Q Rdso 25 C 9 DRNS Drain pin of configurable driver 3 0 7 Rds 25 C 10 DRN4 Drain pin of configurable driver 4 0 7 Rds 25 C 11 SRC4 Source pin of configurable driver 4 0 7 Q Rdso 25 C 12 ING Discrete input used to PWM output driver 6 13
32. ipherals of the processor interfaced to L9733 Doc ID 11319 Rev 10 19 34 Functional description L9733 4 6 4 6 1 4 6 2 20 34 Discrete inputs Output 6 8 enable input In6 In7 In8 This input allows Output 6 or Output 7 or Output 8 to be enabled via this external pin without the use of the SPI The SPI command and the In6 7 input are logically or d together A logic 1 on this input In6 In7 or In8 will enable this output no matter what the status of the SPI command register A logic O on this input will disable this output if the SPI command register is not commanding this output on This pins In6 In7 or In8 can be left open if the internal output device is being controlled only via the SPI This input has a nominal 100kQ resistor connected from this pin to ground which will pull this pin to ground if an open circuit condition occur This input is ideally suited for non inductive loads that are pulse width modulated PWM d This allows PWM control without the use of the SPI inputs Reset input RES When this input goes low it resets all the internal registers and switches off all the output stages This input has a nominal 100 kO resistor connected from this pin to VDD which will pull this pin to VDD if an open circuit condition occur Doc ID 11319 Rev 10 ky L9733 Serial peripheral interface SPI 5 1 5 2 5 3 Serial peripheral interface SPI The L9733 has a serial peripheral inter
33. j Human body model All pins 2 2 kV ED Human body model Driver outputs 4 2 kV 1 For the DRNx the MAX ASB value is the Max Clamp Voltage see Table 6 on page 13 DRNx Clamp voltage 2 Device is only protected vs GND Doc ID 11319 Rev 10 9 34 Operating conditions L9733 2 3 10 34 Thermal data Table 5 Thermal data Symbol Parameter Min Typ Max Unit Tamb Operating ambient temperature 40 125 C Tsy Storage temperature 50 150 C Tj Maximum operating junction temperature 150 C Rih Thermal shutdown temperature 151 175 200 C Rth hys Thermal shutdown temperature hysteresis 7 10 25 C Rthj amb Thermal resistance junction to ambient 1 24 C W RTh j case Thermal resistance junction to case 3 C W 1 With 2s2p PCB thermally enhanced Doc ID 11319 Rev 10 4 L9733 Electrical performance characteristics 3 Electrical performance characteristics These are the electrical capabilities this part was designed to meet It is required that every part meet these characteristics 3 1 DC characteristics Tamb 40 to 125 C Vaq 4 5 to 5 5 Vdc Vpat 4 5 to 18 Vdc high side configuration unless otherwise specified Table 6 DC characteristics Symbol Parameter Conditions Min Typ Max Units INGVin
34. lt has occurred Automatically after a time Tres Ontherising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic 0 and then with a logic 1 in the following SPI cycle ky Doc ID 11319 Rev 10 27 34 Fault operation L9733 7 2 2 28 34 On the rising edge low to high transition at the corresponding parallel input pin only for Outputs 6 8 Ifthe switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available The use of the IN6 8 pins for PWM control on the outputs 6 8 could generates bad diagnostic behavior when the falling edge of CS happens a short time after the falling edge of IN6 8 during the power MOS transient Software filtering may be needed to ignore fault signals during Drn6 8 transient after falling edge of IN6 8 Latch mode This diagnostic operating mode latches all faults when they happen 1 Open load The diagnostic of open load is detected only in OFF condition sensing the Src1 8 output voltage This fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds Vth Vbat and Vth GND for the filtering time Tfilt An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected Short Circuit to Vb The diagnostic of short circuit to Vbat is
35. max if VDrn 1 5 lt 60 Vbat voltage generator is connected to Drn 1 5 for open load and short to V bat detection when a high side configured output is commanded OFF Drain pins of outputs 1 5 Drn1 5 are connected to the drains of the N channel MOSFET Doc ID 11319 Rev 10 ky L9733 Functional description 4 3 4 4 4 5 4 5 1 4 5 2 4 5 3 transistors Source pins of outputs 1 5 Src1 5 are connected to the sources of the N channel MOSFET transistors Outputs 6 8 These three self configuring outputs can be used to drive either high or low side loads In addition to being controlled by the SPI BUS these outputs can also be enabled and disabled via the ING amp IN7 amp IN8 inputs The ING IN7 and IN8 inputs are logically ord with the SPI commands to allow either the IN6 amp IN7 amp IN8 inputs or the SPI commands to activate these outputs The use of the ING amp IN7 amp IN8 pins for PWM control on these outputs should only be done with non inductive loads if an external flyback diode is not present The room temperature Rdson of these four outputs is 0 7 A current limited 100A max voltage generator is connected to Src 6 8 for open load and short to GND detection when a low side configured output is commanded OFF Another current limited 100A max if VDrn 6 8 gt 60 Vbat 280 pA max if VDrn 6 8 60 Vbat voltage generator is connected to Drn 6 8 for open load and short to Vbat detection when a high side con
36. me CSfall Channel select CS See Figure 5 100 ns fall time CSlead Channeliselect Cs See Figure 6 1 455 ns lead time CSlag Channel select CS See Figure 6 50 ns lag time Input data DI j 3 1 E Dlrise rise time See Figure 5 fsck 5 4MHz 30 ns Input data DI 1 i Difall fall time See Figure 5 fsck 5 4MHz 30 ns Input data DI E 1 i Disus set up time See Figure 6 fsck 5 4MHz 15 ns Input data Dl _ 1 i Dihs hold time See Figure 6 fac 2 5 4MHz 10 ns CS2SCLK CS rise to SCLK rise See Figure 6 fs 5 4MHz 40 300 ns 1 Guaranteed by design 16 34 Doc ID 11319 Rev 10 L9733 Electrical performance characteristics Figure 3 DO loading for disable time measurement 5 V5 Vcc 4 0 V 1kQ x DOdis DO 10V ov 1kQ cs Figure 4 Output loading for slew rate measurements All Low Side Outputs must meet the slew rate requirements of this load condition I LI Vbat I All High Side Outputs must 1 meetthe slew rate requirements H of this load condition LI 1800 Outputs 18 i Outputs 1 8 i LI LI 1800 i i LI LI LI 1 I Figure 5 SPI input output timings bamm S C K y erf Pa SCLKIM ad ja SCLKhm mpg SCLK N SCLKfall 90 DOrise e7 DO 2 i DOfall 10 F Figure 6 SPI timing diagram CS
37. nsistor If the output current has been above the short threshold lovc for the filtering time Tdel the output power is switched off and at the same time an overcurrent fault is written in the fault register If the switching OFF protection is not active the On Doc ID 11319 Rev 10 ky L9733 Fault operation phase overcurrent protection is a linear current limitation and no diagnosis is available There are three possibilities to restart one output after the fault has occurred Automatically after a time Tres On the rising edge of CS if two valid DI byte has been received and first the Output Status in the command register is written with logic 0 and then with a logic 1 in the following SPI cycle On the rising edge low to high transition at the corresponding parallel input pin only for Outputs 6 8 If the power MOS transient after a switching off command is longer than Tdel filtering time a bad diagnostic behavior happens and software filtering may be needed 7 2 High side configured output fault operation The diagnostic circuitry verifies for the high side configured output the following condition Normal operation open load short circuit to Vbat and overcurrent only if the switching OFF protection selectable for each channel via SPI bus is active The diagnostic circuitry operates in two different modes selected for each channel by SPI no latch mode and latch mode The fault priority is overcurrent
38. put signal IN in low state The other faults will be cleared on the rising edge of chip select if a valid DI byte was received Table 11 Fault register definition OUT 8 OUT 7 OUT6 OUT5 OUT4 OUT3 OUT2 OUT1 MSB LSB D1 DO D1 DO D1 DO D1 DO D1 DO D1 DO D1 DO D1 DO b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO Table 12 Fault logic definition D1 DO Fault status 0 0 No fault is present 0 1 Open load 1 0 Short circuit to GND low side or short circuit to Vbat high side 1 1 Overcurrent If all the bits bO b15 of the fault register have value 1 it means that a thermal fault at least on one of the eight independent Outputs occurred 7 1 Low side configured output fault operation The diagnostic circuitry verifies for the low side configured output the following condition Normal operation open load short circuit to GND and overcurrent only if the switching OFF protection selectable for each channel via SPI bus is active The diagnostic circuitry operates in two different modes selected for each channel by SPI no latch mode and latch mode The fault priority is overcurrent and then open load or short circuit to GND this means that if an overcurrent occurs the fault register is always overwritten and following open load or short to GND faults that happen before that the register is cleared will be ignored 7 1 1 No latch mode This diagnostic operating mode doesn t latch open load and short to GND faults 1 Open load The d
39. rovisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 34 34 Doc ID 11319 Rev 10 ky
40. supply connected directly to the Vb pin The normal range of the Vbat voltage is 10 to 18V18V However the L9733 is functional with Vbat voltages as low as 4 5V DC with eventually a degradation of Rdson The frequency range of this charge pump is from 3 6 to 7 6 MHz The frequency is above 1 8 MHz in order to be above the AM radio band and below 8 0 MHz so that harmonics do not get within the FM radio band Waveshaping Both the turn on and the turn off slew rates on all outputs OUT1 8 are limited to between 10 us and 100 us for both rise and fall times 10 to 90 and vice versa to reduce conducted EMC energy in the vehicle s wiring harness The characteristics of the turn on and turn off voltage is linear with no discontinuities during the output driver state transition POR register initialization When the L9733 wakes up the Vdd supply to the L9733 is allowed from 0 to 5 VDC in 0 3 to 3ms The L9733 has a POR circuit which monitors the Vdd voltage When the Vdd voltage reaches an internal threshold and remains above this trip level for at least 5 to 20 us the Command and Fault registers are cleared Before Vdd reaches this trip level none of the eight outputs are allowed to momentarily glitch on Thermal shutdown Each of the eight outputs has independent thermal protection circuitry that disables each output driver once the local N Channel MOSFET s device temperature reaches between 151 and 200 C A filter is present to v
41. transition at the corresponding parallel input pin only for Outputs 6 8 Ifthe switching OFF protection is not active the On phase overcurrent protection is a linear current limitation and no diagnosis is available The use of the IN6 8 pins for PWM control on the outputs 6 8 could generates bad diagnostic behavior when the falling edge of CS happens a short time after the falling edge of IN6 8 during the power MOS transient Software filtering may be needed to ignore fault signals during Drn6 8 transient after falling edge of IN6 8 Latch mode This diagnostic operating mode latches all faults when they happen 1 Open load The diagnostic of open load is detected only in OFF condition sensing the Drn1 8 output voltage This fault is detected if the power drain voltage is inside the voltage range limited by the two thresholds Vth Vbat and Vth_GND for the filtering time Tfilt An internal current limited voltage regulator fixes the drain voltage inside the described range when no load is connected Short circuit to GND The diagnostic of short circuit to GND is detected only in OFF condition sensing the Drn1 8 output voltage This fault is detected if the power drain voltage is lower than the Vth_GND threshold for the filtering time Tfilt Overcurrent The diagnostic of overcurrent is detected only in ON condition if the switching OFF protection of the channel is enabled default sensing the current level of the output power tra
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