ST VNN7NV04 VNS7NV04 VND7NV04 VND7NV04-1 handbook
Contents
1. 0 0 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 0 05 1 15 2 25 3 35 4 45 5 55 6 Vin V Id A Figure 19 Input voltage vs input charge Figure 20 Turn off drain source voltage slope part 1 2 Vin V av au v us 300 8 T 250 Vds 12V Id 3 5A 6 200 5 150 4 3 100 2 50 0 0 100 200 300 400 500 600 700 800 900 1000 1100 0 5 10 15 20 25 Qa nC Rg ohm 14 37 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Protection features Figure 21 Turn off drain source voltage slope Figure 22 Capacitance variations part 2 2 dv dt v us C pF 300 600 250 500 Vin 3 5V 200 Vdd 15V Id 3 5A 400 150 300 100 50 200 9 100 100 200 300 400 500 600 700 800 900 1000 1100 0 5 10 15 20 25 30 35 Vds V Rg ohm Figure 23 Output characteristics Figure 24 Normalized on resistance vs temperature ID A 12 11 10 9 Vinz5V Vin 4 5V 8 Vin 4V T 6 Vinz3V 5 4 3 Vinz2 5V 2 1 Vin 2V 5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 VDS V 1 75 1 25 Vin 5V Id 3 5A 25 0 25 50 75 100 125 150 175 TPC Figure 25 Switching time resistive load part Figure 26 Switching time resistive load part Rg ohm t us t ns 5 5 1600 tr 5 Vdd 15V tr 1400 4 5 Id 3 5A td off Vdd 15V 4 Vin 5V 1200 1d 3 5A tf Rg 150ohm 3 9 1000 3 25 800 2 600 1 5 1 400 tf2. 4 2 Note 22 37 Table 5 SO 8 thermal parameter continued Area island cm Footprint C2 W s C 9 00E 04 C3 W s C 7 50E 03 C4 W s C 0 045 C5 W s C 0 35 C6 W s C 1 05 SOT 223 thermal data Figure 40 SOT 223 PC board Layout condition of Ry and Zy measurements PCB FR4 area 58 mm x 58 mm PCB thickness 2 mm Cu thickness 35 um Copper areas 0 11 cm 1 cm 2 cm Figure 41 Rthj amb vs PCB copper area in open box free air condition 140 130 120 110 100 90 80 70 60 RTH j amb C W Doc ID 7383 Rev 3 1 1 5 2 2 5 Cu area cm 2 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and PCB thermal data Figure 42 SOT 223 thermal impedance junction ambient single pulse ZTH C W 1000 100 10 0 1 0 0001 0 001 0 01 0 1 1 10 100 1000 Time s Figure 43 Thermal fitting model of an OMNIFET Il in SOT 223 TJ c C2 C3 C4 C5 C6 JL L J J I i j if i A mo gm FP 9m T4 omm TM og E R6 a AWW AWW AW AWW AW AWV Pd T amb Equation 2 Pulse calculation formula ZrQ8 Bru Zggap 1 7 9 where tp T Table 6 SOT 223 thermal parameter Area island cm Footprint 2 R1 C W 0 2 R2 C W 1 1 R3 C W 4 5 R4 C W 24 R5 C W 0 1 R6 C W 100 45 C1 W s
3. 17 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 OMNIFET II fully autoprotected Power MOSFET Features VNN7NV04 VNS7NV04 VND7NV04 VND7NVO4 1 Type Rps on liim Velamp 60 mQ 6A 40V Linear current limitation Thermal shutdown Short circuit protection Integrated clamp Low current drawn from input pin Diagnostic feedback through input pin ESD protection Direct access to the gate of the Power MOSFET analog driving TO252 DPAK TO251 IPAK Description The VNN7NV04 VNS7NV04 VND7NV04 VND7NVOZ4 1 are monolithic devices designed in STMicroelectronics VIPower MO 3 Technology e ba sek OEC pads n intended for replacement of standard Power Dir ds P MOSFETSs from DC up to 50 kHz applications PS Built in thermal shutdown linear current limitation and overvoltage clamp protect the chip in harsh environments Fault feedback can be detected by monitoring the voltage at the input pin Table 1 Device summary Order codes Package Tube Tube lead free Tape and reel Tape and reel lead free SOT 223 VNN7NV04 VNN7NV0413TR SO 8 VNS7NV04 VNS7NV0413TR TO 252 VND7NV04 VND7NV04 E VND7NV0413TR VND7NVO4TR E TO 251 VND7NVO4 1 VND7NVO04 1 E September 2010 Doc ID 7383 Rev 3 1 37 www st com Contents VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Contents 1 Block diagram and pin description ssssss 6
4. 0 60 C2 0 48 0 60 D 6 00 6 20 D1 5 1 E 6 40 6 60 E1 4 7 e 2 28 4 40 4 60 H 9 35 10 10 28 37 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and packing information 5 3 Table 9 TO 252 DPAK mechanical data continued millimeters Symbol Min Typ Max L2 0 8 L4 0 60 1 00 R 0 2 V2 0 8 Package Weight Gr 0 29 Figure 49 TO 252 DPAK package dimensions P032P SOT 223 mechanical data Table 10 SOT 223 mechanical data millimeters Symbol Min Typ Max A 1 8 B 0 6 0 7 0 85 B1 2 9 3 3 15 C 0 24 0 26 0 35 D 6 3 6 5 6 7 e 2 3 Doc ID 7383 Rev 3 29 37 Package and packing information VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 5 4 30 37 Table 10 SOT 223 mechanical data continued millimeters Symbol Min Typ Max e1 4 6 3 3 3 5 3 7 6 7 7 7 3 10 max Al 0 02 0 1 Figure 50 SOT 223 package dimensions j 0046067 SO 8 mechanical data Table 11 SO 8 mechanical data millimeters Symbol Min Typ Max A 1 75 al 0 1 0 25 a2 1 65 a3 0 65 0 85 b 0 35 0 48 A 1 75 Al 0 10 0 25 Doc ID 7383 Rev 3 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and packing information 4 Table 11 SO 8 mechanical data continued mi
5. 1 Note 20 37 Package and PCB thermal data SO 8 thermal data Figure 36 SO 8 PC board SS OSS US D 14cm 2 D 8cm 2 2cm 2 Layout condition of Ri and Zm measurements PCB FR4 area 58 mm x 58 mm PCB thickness 2 mm Cu thickness 35 um Copper areas 0 14 cm 0 8 cm 2 cm Figure 37 Rtnj amb VS PCB copper area in open box free air condition RTHj amb cw SO 8 at 2 pins connected to TAB 110 105 100 95 90 85 80 75 70 T T T 0 0 5 1 1 5 2 2 5 PCB Cu heatsink area cm 2 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and PCB thermal data Figure 38 SO 8 thermal impedance junction ambient single pulse ZTH C W 1000 10 0 1 0 0001 0 001 0 01 0 1 1 10 100 1000 Time s Figure 39 Thermal fitting model of an OMNIFET Il in SO 8 Tj C1 C2 c3 C4 c5 C6 tf tt tt t Rna I rR R3 T m T 13 ps T m f AW AW ANN AW AW AW Pd I T amb Equation 1 Pulse calculation formula ZrQ8 Bru Zggap 1 9 where 6 tp T Table 5 SO 8 thermal parameter Area island cm Footprint 2 R1 C W 0 2 R2 C W 0 9 R3 C W 3 5 R4 C W 21 R5 C W 16 R6 C W 58 28 C1 W s C 3 00E 04 Doc ID 7383 Rev 3 21 37 Package and PCB thermal data VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1
6. 2 Electrical specifications 000 cece eee ee 7 2 1 Absolute maximum ratings 0 0000 eee eee 7 2 2 Thermal data T TTC 8 2 3 Electrical characteristics llle 8 3 Protection features 2ozud eR Rr rw he RE ene RRr E 10 3 1 Electrical characteristics curves llle 13 3 2 SO 8 maximum demagnetization energy 0 eee eee eee 17 3 3 DPAK maximum demagnetization energy llle 18 3 4 SOT 223 maximum demagnetization energy lusus 19 4 Package and PCB thermal data LL 20 4 1 SOS thermal dle aix edes toris RARE S RES E PAAR Reis va pei 20 4 2 SOT 223 thermal data augaseced am bera pr sb RE Ebr so eee dpa 22 4 3 DPAK thermal data s d exea wie trs pe oe ted pn RR E Re eae 24 5 Package and packing information leeeeess 27 5 1 TO 251 IPAK mechanical data 0 02 c eee eee 27 5 2 TO 252 DPAK mechanical data 0 0000 c eee eee 28 5 3 SO1 223 mechanical data cic ceiveto divas iindrhebeewiewnd es 29 5A SOS8mechanical dala ER nnceeu sede RR ye RR RR 30 5 5 SOl 223 packing information cde RERR ESCOLAR RR wee Ceeeds 32 5 6 50 8 packing information o2 csiccedeeeeneeige eoeteradisd RE ES ER 33 5 7 DPAK packing information llllseel ee 34 5 8 IPAK packing information lsslllleeeBBBssh 35 6 Revision histOfy 2 ro RR RRRREA UR EEE EEEE ERE E 36 2 37 Doc ID 7383 Re
7. C 3 00E 04 Doc ID 7383 Rev 3 23 37 Package and PCB thermal data VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Table 6 SOT 223 thermal parameter continued Area island cm Footprint 2 C2 W s C 9 00E 04 C3 W s C 3 00E 02 C4 W s C 0 16 C5 W s C 1000 C6 W s C 0 5 2 4 3 DPAK thermal data Figure 44 DPAK PC board h 7 Note Layout condition of Ri and Zy measurements PCB FR4 area 60 mm x 60 mm PCB thickness 2 mm Cu thickness 35um Copper areas from minimum pad lay out to 8 cm2 Figure 45 Rthj amb VS PCB copper area in open box free air condition RTH j_amb C W 90 80 70 60 50 40 30 N 0 2 4 6 8 10 PCB CU heatsink area cm 2 24 37 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and PCB thermal data Figure 46 DPAK thermal impedance junction ambient single pulse ZTH C W 1000 100 10 0 1 0 0001 0 001 0 01 0 1 1 10 100 1000 TJ C1 C2 c3 C4 C5 C6 Equation 3 Pulse calculation formula ZrQ8 Bru Zggap 1 7 9 where t T Table 7 DPAK thermal parameter Area island cm Footprint 6 R1 C W 0 1 R2 C W 0 35 R3 C W 1 20 R4 C W 2 R5 C W 15 R6 C W 61 24 Doc ID 7383 Rev 3 25 37 Package and PCB thermal data VNN7NV04 VNS7NV04 VND
8. Drain current limit Vin 5 V Vps 13 V 6 9 12 A tuim response current Vin 5 V Vps 13 V 40 us Over temperature o Tish shutdown 150 175 200 C Tis Over temperature reset 135 C lot Fault sink current Vin 5 V Vpg 13 V Ti Tish 15 mA ena nen starting Tj 25 C Vpp 24 V Eas nita se avaancie Vine5 V Rgen Rin min 150 L 24mH 200 mJ see figures Figure 6 amp Figure 8 1 Pulsed Pulse duration 300 us duty cycle 1 5 ky Doc ID 7383 Rev 3 9 37 Protection features VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 3 10 37 Protection features During normal operation the input pin is electrically connected to the gate of the internal Power MOSFET through a low impedance path The device then behaves like a standard Power MOSFET and can be used as a switch from DC up to 50 kHz The only difference from the user s standpoint is that a small DC current liss typ 100pA flows into the input pin in order to supply the internal circuitry The device integrates Overvoltage clamp protection internally set at 45 V along with the rugged avalanche characteristics of the Power MOSFET stage give this device unrivalled ruggedness and energy handling capability This feature is mainly important when driving inductive loads Linear current limiter circuit limits the drain current Ip to liim whatever the input pin voltages When the current limiter is active the device operates in the linear region so power dissipation may exceed the c
9. Figure 45 Figure 46 Figure 47 Figure 48 4 37 Block diagram we iid Gabe oid dp rem Dare ehe aedes aded n aede pA E due the 6 Configuration diagram top view ilssssseeeeee III n 6 Current and voltage conventions 00 er 7 Switching time test circuit for resistive load 0 00 eee 11 Test circuit for diode recovery times lille 11 Unclamped inductive load test circuits 22i 12 Input charge test circuit insisi Pener Ee e 12 Unclamped inductive waveforms llllseeeeeee ee 12 Derating CUVE v 44 oues puede ERA seed GRE PUE YR PAIRE ene dx Rug edes 13 Transconductance serii risonris idt bin ieia ee hh mr rn 13 Static drain source on resistance vs input voltage part 1 2 nananana nannaa aaan 13 Static drain source on resistance vs input voltage part 2 2 a nus saaana aaea 13 Source drain diode forward characteristics llle 13 Static drain source on resistance l l 13 Turn on current slope part 1 2 anasa eee 14 Turn on current slope part 2 2 2 0 eee 14 Transfer characteristics llle eh 14 Static drain source on resistance vs 1d 2 ees 14 Input voltage vs input charge iliseleleelee II III 14 Turn off drain source voltage slope part 1 2 liliis eel 14 Turn off drain source voltage slope part 2 2 liliis lel 15 Capacitance variations 0 0 ern 15 Output characteristics 0 0 teeta 15 Normalize
10. 7NV04 VND7NV04 1 26 37 Table 7 DPAK thermal parameter continued Area island cm Footprint C1 W s C 0 0006 C2 W s C 0 0021 C3 W s C 0 05 C4 W s C 0 3 C5 W s C 0 45 C6 W s C 0 8 Doc ID 7383 Rev 3 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and packing information 5 5 1 Package and packing information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACKO is an ST trademark TO 251 IPAK mechanical data Table 8 TO 251 IPAK mechanical data Doc ID 7383 Rev 3 millimeters Symbol Min Typ Max A 2 2 2 4 A1 0 9 1 1 A3 0 7 1 3 B 0 64 0 9 B2 5 2 5 4 B3 0 85 B5 0 3 B6 0 95 C 0 45 0 6 C2 0 48 0 6 D 6 6 2 E 6 4 6 6 G 4 4 4 6 H 15 9 16 3 L 9 9 4 L1 0 8 1 2 L2 0 8 1 27 37 Package and packing information VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Figure 48 TO 251 IPAK package dimensions H 5 2 TO 252 DPAK mechanical data Table 9 TO 252 DPAK mechanical data millimeters Symbol Min Typ Max A am TL 20 A1 0 90 1 10 A2 0 03 0 23 B 0 64 0 90 B2 5 20 5 40 C 0 45
11. N7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Protection features Figure 4 Switching time test circuit for resistive load 2200 3 3 H a Vop Figure 5 Test circuit for diode recovery times mA m M A D FAST m OMNIFET ope A PETOQUP 2 w B o B 1509 D Vpp Rgen l j OMNIFET Vgen s ky Doc ID 7383 Rev 3 11 37 Protection features VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Figure 6 Unclamped inductive load test Figure 7 circuits Input charge test circuit 2200 33 F Voo SCO7860 Figure8 Unclamped inductive waveforms VCLAMP Vpp SC07872 12 37 Doc ID 7383 Rev 3 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Protection features 3 1 Electrical characteristics curves Figure 9 Derating curve Figure 10 Transconductance GC16960 Gfs S 20 18 Vds 13V 16 Tj 40 C 14 Tj 25 C 100 Tj 150 C 12 10 Piot 50 8 4 2 0 56 100 T C 0 1 2 3 he 5 6 7 8 Figure 11 Static drain source on resistance Figure 12 Static drain source on resistance vs input voltage par
12. Over Limiter Temperature 3 SOURCE FC01000 Figure 2 Configuration diagram top view SO 8 Package SOURCE q 1 8 DRAIN SOURCE q DRAIN SOURCE 1 DRAIN INPUT 4 51 DRAIN 1 Forthe pins configuration related to SOT 223 DPAK IPAK see outlines at page 1 Doc ID 7383 Rev 3 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Electrical specifications 2 2 1 4 Electrical specifications Figure 3 Current and voltage conventions INPUT DRAIN SOURCE Absolute maximum ratings Table 2 Absolute maximum ratings Value Symbol Parameter Unit SOT 223 SO 8 DPAK IPAK Vps Drain source voltage Vjy 0 V Internally clamped V VIN Input voltage Internally clamped V lin Input current 20 mA Rin min Minimum input series impedance 150 Q Ip Drain current Internally limited A IR Reverse DC output current 10 5 A Electrostatic discharge R 1 5 KQ VESD C 100 pF 4000 V Electrostatic discharge on output pin VEsp2 only R 330 Q C 150 pF 6900 V Piot Total dissipation at T 25 C 7 4 6 60 W Maximum switching energy Emax L 0 7 mH R 0 Q Vpat 13 5 V 40 40 mJ Tjstart 150 C l 9 A Maximum switching energy EMAX L 0 6 mH R 0 Q Vpat 13 5 V 37 mJ Tjstart 150 9C l 9 A Ti Operating junction temperature Internally limited C Te Case operating te
13. Q ty 2500 Bulk Q ty 2500 A max 330 c B min 1 5 No elo a C 0 2 13 i I F 20 2 G 21 0 16 4 1 4 G measured N min 60 N Tape sit anu T max 22 4 in core for tape start 2 5mm min width i TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width Ww 16 Tape Hole Spacing PO 0 1 4 piven Component Spacing P 8 TAPE Hole Diameter D 0 1 0 1 5 JL AL Hole Diameter D1 min 1 5 Hole Position F 0 05 7 5 Compartment Depth K max 6 5 K Hole Spacing P1 0 1 2 All dimensions are in mm End Tj f f O1 0O 9 aro o C O 0 o Pb E l 4 Ew d Start Top No components Components No components cover a oo tape 500mm min an Empty components pockets 500mmmin bw saled with cover tape cai User Direction of Feed User direction of feed 34 37 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and packing information 5 8 IPAK packing information Figure 57 IPAK tube shipment no suffix Base Q ty 75 Bulk Q ty 3000 Tube length 0 5 532 A 6 B 21 3 C 0 1 0 6 All dimensions are in mm Doc ID 7383 Rev 3 35 37 Revision history VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 6 36 37 Revision history Table 12 Document revision history Date Revision Changes 01 Feb 2003 1 Initial Release Added Ta
14. RIE Gts transconductance Vop 13 V Ip 3 5 A 4 a Coss Output capacitance Vps 13 V f 1 MHz Vjy 0 V 220 pF 8 37 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV 04 VND7NV04 1 Electrical specifications Table 4 Electrical characteristics continued Symbol Parameter Test conditions Min Typ Max Unit Switching Tj 25 C unless otherwise specified ta on Turn on delay time 100 300 ns tp Rise time e qud A 470 1500 ns 5 V 150 Q F gen l lgen IN MIN ta off Turn off delay time see figure Figure 4 500 1500 ns lr Fall time 350 1000 ns ta on Turn on delay time 0 75 2 3 Hs t Rise time Youre V Ip 3 5 A 46 14 0 us Vgen75 V Rgen 2 2 KQ ta off Turn off delay time see figure Figure 4 5 4 16 0 us lr Fall time 3 6 11 0 Hs Vpp 15 V Ip 3 5 A dl dt Turn on current slope 6 5 A us A Vgen 5 V Rgen Rin min 150 Q Vpp 12 V Ip 3 5 A Vin 5 V Qi Total input charge 18 nC 3 lgen72 13 mA see figure Figure 7 Source drain diode Tj 25 C unless otherwise specified Vsp Forward on voltage Isp 3 5 A Viy 0 V 0 8 V in Reverse recovery time Isp 3 5 A di dt 20 A us 220 ns Qrr Reverse recovery charge Vpp 30 V L 200 uH 0 28 uC IRAN Reverse recovery current see test circuit figure Figure 5 25 A Protections 40 C lt Tj lt 150 C unless otherwise specified liim
15. WISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2010 STMicr
16. a in open box free air condition 2000 24 DPAK thermal impedance junction ambient single pulse llle sees 25 Thermal fitting model of an OMNIFET Il in DPAK 0000 000 eee ee eee 25 TO 251 IPAK package dimensions 0 0 00 cece eee eee eh 28 Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 List of figures Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 TO 252 DPAK package dimensions 00 cece eee eee 29 SOT 223 package dimensions 0 0 eens 30 SO 8 package dimensions auas cc teen eee eens 31 SOT 223 tape and reel shipment suffix TR 0 0 0 0 0 eee 32 SO 8 tube shipment no SUffiX 2 6 tenet 33 SO 8 tape and reel shipment suffix TR 00 ccc ee 33 DPAK footprint and tube shipment no suffix llle 34 DPAK tape and reel shipment suffix TR 0000 c eee ee 34 IPAK tube shipment no suffix lllississsssess ee Ih 35 Doc ID 7383 Rev 3 5 37 Block diagram and pin description VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 1 6 37 Block diagram and pin description Figure 1 Block diagram DRAIN 2 Overvoltage a Clamp INPUT l z Gate ts pale Control _ A ps A i Ho M Linear Current a
17. apability of the heatsink Both case and junction temperatures increase and if this phase lasts long enough junction temperature may reach the over temperature threshold Tigh Over temperature and short circuit protection these are based on sensing the chip temperature and are not dependent on the input voltage The location of the sensing element on the chip in the power stage area ensures fast accurate detection of the junction temperature Over temperature cutout occurs in the range 150 to 190 C a typical value being 170 C The device is automatically restarted when the chip temperature falls of about 15 C below shutdown temperature Status feedback in the case of an over temperature fault condition T gt Tjsh the device tries to sink a diagnostic current lo through the input pin in order to indicate fault condition If driven from a low impedance source this current may be used in order to warn the control circuit of a device shutdown If the drive impedance is high enough so that the input pin driver is not able to supply the current ly the input pin will fall to O V This will not however affect the device operation no requirement is put on the current capability of the input pin driver except to be able to supply the normal operation drive current liss Additional features of this device are ESD protection according to the Human Body model and the ability to be driven from a TTL logic circuit Doc ID 7383 Rev 3 ky VN
18. b amme 200 0 td on 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 0 3 25 3 5 3 75 4 4 25 4 5 4 75 5 5 25 Doc ID 7383 Rev 3 15 37 Protection features VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Figure 27 Normalized input threshold voltage Figure 28 Normalized current limit vs junction temperature vs temperature Vin th 1 15 i aN 1 05 Vds Vin Id 1mA 50 25 0 25 50 75 100 125 150 175 T C Vds 13V Vin 5V Figure 29 Step response current limit Tdlim us 7 6 5 Vin 5V Rg 1500hm 6 Vdd V 16 37 Doc ID 7383 Rev 3 x VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Protection features 3 2 SO 8 maximum demagnetization energy Figure 30 SO 8 maximum turn off current versus load inductance ILMAX A 100 10 0 1 1 10 100 L mH Legend A Single Pulse at T 4447150 C B Repetitive pulse at T 444 100 C C Repetitive Pulse at T 4447125 C Conditions Vcc 13 5 V Values are generated with RH 0 Q In case of repetitive pulses Tjstart at beginning of each demagnetization of every pulse must not exceed the temperature specified above for curves B and C Figure 31 SO 8 demagnetization Vine IL Demagnetization Demagnetization Demagnetization Doc ID 7383 Rev 3 17 37 Protection features VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 3 3 18 37 DPAK maximum de
19. ble 1 Device summary on page 1 and Section 4 28 Apr 2009 2 Package and PEB thermal data on page ae Updated Section 5 Package and packing information on page 27 10 Sep 2010 3 Updated Table 4 Electrical characteristics Doc ID 7383 Rev 3 VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHER
20. d on resistance vs temperature 0 0 aaa 15 Switching time resistive load part 1 2 llis 15 Switching time resistive load part 2 2 0 0 0 0 0c ccs 15 Normalized input threshold voltage vs temperature 0 0 00 cee eee eee 16 Normalized current limit vs junction temperature 0 000 eee eee 16 Step response current limit 0 0 0 0 000 cc tetas 16 SO 8 maximum turn off current versus load inductance 0 0000ee eee eae 17 SO 8 demagnetization uasa aaea 17 DPAK maximum turn off current versus load inductance sassa saaa aaaea 18 DPAK demagnetization 0 0 18 SOT 223 maximum turn off current versus load inductance issus 19 SOT 223 demagnetization aaue 19 SO 8 PC Dodafd ved tendre toe a ord SCR RO NR ER RR RON RE un ca ARD E 20 Rthj amb vs PCB copper area in open box free air condition 00055 20 SO 8 thermal impedance junction ambient single pulse 000000 eee eee 21 Thermal fitting model of an OMNIFET Il in SO 8 2 2 ee 21 SOT 223 PC board puse Eu c Ro agen P RR REIR RR NOR UR CLER S 22 Rthj amb vs PCB copper area in open box free air condition 0000 22 SOT 223 thermal impedance junction ambient single pulse 0 00 23 Thermal fitting model of an OMNIFET Il in SOT 223 1 0 cee 23 DPAK PC boardy d paca Eat Pos acti n EE E acer ies Ned Boat MUR 24 Rthj amb vs PCB copper are
21. llimeters Symbol Min Typ Max A2 1 25 b 0 28 0 48 C 0 17 0 23 p 4 80 4 90 5 00 E 5 80 6 00 6 20 E10 3 80 3 90 4 00 e 1 27 h 0 25 0 50 L 0 40 1 27 L1 1 04 k 0 8 ccc 0 10 1 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15 mm in total both side 2 Dimension E1 does not include interlead flash or protrusions Interlead flash or protrusions shall not exceed 0 25 mm per side Figure 51 SO 8 package dimensions D Ed Doc ID 7383 Rev 3 SEATING PLANE C 0 25 mm GAGE PLANE 0016023 D 31 37 Package and packing information VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 5 5 32 37 SOT 223 packing information Figure 52 SOT 223 tape and reel shipment suffix TR 40mm min Access hole at slot location Full radius H F4 Tape slot j in core for tape start 2 5mm min width TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width Ww 12 Tape Hole Spacing PO 0 1 4 Component Spacing P 8 Hole Diameter D 0 1 0 1 5 Hole Diameter D1 min 1 5 Hole Position F 0 05 5 5 Compartme
22. magnetization energy Figure 32 DPAK maximum turn off current versus load inductance ILM AX A 100 10 0 01 0 1 1 10 100 L mH Legend A Single Pulse at T 4447150 C B Repetitive pulse at T 444 100 C C Repetitive Pulse at T 4447125 C Conditions Vcc 13 5 V Values are generated with RH 0 Q In case of repetitive pulses Tjctart at beginning of each demagnetization of every pulse must not exceed the temperature specified above for curves B and C Figure 33 DPAK demagnetization Vine IL Demagnetization Demagnetization Demagnetization Doc ID 7383 Rev 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Protection features 3 4 SOT 223 maximum demagnetization energy Figure 34 SOT 223 maximum turn off current versus load inductance ILMAX A 100 10 0 01 0 1 1 10 L mH Legend A Single Pulse at T 4442150 C B Repetitive pulse at T Jstat 100 C C Repetitive Pulse at T ja442125 C Conditions Vcc 13 5 V Values are generated with RH 0 Q In case of repetitive pulses Tis at beginning of each demagnetization of every pulse must not exceed the temperature specified above for curves B and C Figure 35 SOT 223 demagnetization Vine IL Demagnetization Demagnetization Demagnetization Doc ID 7383 Rev 3 19 37 Package and PCB thermal data VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 4 4
23. mperature Internally limited C Tstg Storage temperature 55 to 150 C Doc ID 7383 Rev 3 7 37 Electrical specifications VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 2 2 Thermal data Table 3 Thermal data Value Symbol Parameter Unit SOT 223 SO 8 DPAK IPAK Rthj case Thermal resistance junction case max 18 2 1 2 1 C W Rihj lead Thermal resistance junction lead max 27 C W Rthj amb Thermal resistance junction ambient max 9e go e5 102 C W 1 When mounted on a standard single sided FR4 board with 0 5 mm of Cu at least 35 uim thick connected to all DRAIN pins 2 3 Electrical characteristics 40 C T 150 C unless otherwise specified Table 4 Electrical characteristics Symbol Parameter Test conditions Min Typ Max Unit Off Drain source clamp ONE VCLAMP voltage Vin 0 V 1523 5 A 40 45 55 V Drain source clamp DUE VCLTH threshold voltage Vine V Ip 2 mA 36 M ViNTH Input threshold voltage VpszViw Ip21 mA 0 5 2 5 V liss d current from input Vps 0 V Viy 5 V 100 150 UA V Input source clamp liyz1 mA 6 6 8 8 V INCL voltage liy 1 mA 1 0 0 3 Zero input voltage drain Vpg 13 V Viy 0 V Tj 25 C 30 aa DSS lourrent V y 0 V Vps 25 V Vin 0 V 75 On R Static drain source on Viy 5 V Ip 3 5 A Tj 25 C 60 DS on resistance Vin 5 V Ip 3 5 A 120 Dynamic T 225 C unless otherwise specified a Forward E
24. nsions are in mm TAPE DIMENSIONS According to Electronic Industries Association EIA Standard 481 rev A Feb 1986 Tape width Ww 12 Tape Hole Spacing PO 0 1 4 Component Spacing P 8 A Hole Diameter D 0 1 0 1 5 Hole Diameter D1 min 1 5 Hole Position F 0 05 5 5 K Compartment Depth K max 4 5 Hole Spacing P1 0 1 2 All dimensions are in mm x bes t d es ted Lad doo Jar dex Chad Joe r j l j jl 0o000000V A Sian Top No components Components No components cover tape 500mm min Aa Empty components pockets 500mm min a X saled with cover tape d User Direction of Feed User direction of feed 4 Doc ID 7383 Rev 3 33 37 Package and packing information VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 5 7 DPAK packing information Figure 55 DPAK footprint and tube shipment no suffix 6 7 8 3 0 1 6 E c Base Q ty 75 T Bulk Q ty 3000 6 7 p y Tube length 0 5 532 2 3 A 6 C 0 1 0 6 Figure 56 DPAK tape and reel shipment suffix TR Ls 40mm min Iu Access hole REEL DIMENSIONS at slot location Base
25. nt Depth K max 4 5 Hole Spacing P1 0 1 2 All dimensions are in mm User Direction of Feed G measured athub REEL DIMENSIONS Base Q ty 1000 Bulk Q ty 1000 A max 330 B min 1 5 C 0 2 13 F 20 2 G 21 0 12 4 N min 60 T max 18 4 user Direction of Feed End oO pHa dio 9 q O Oq No components Components 500mm min a EH saled with cover tape User direction of feed No components Empty components pockets 500mm min Start Doc ID 7383 Rev 3 q VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Package and packing information 5 6 SO 8 packing information Figure 53 SO 8 tube shipment no suffix 4 3 i C Base Q ty 100 a Bulk Q ty 2000 Tube length 0 5 532 ail A 3 2 LEF j B 6 L C 0 1 0 6 Figure 54 SO 8 tape and reel shipment suffix TR omm min REEL DIMENSIONS Access hole at slot location Base Q ty 2500 Bulk Q ty 2500 mA N A max 330 P o c B min 15 f HEA ese ee enm C 0 2 13 i F 202 i Ne EN G 2 0 12 4 i N N G measured ie Fulladus A e pum N min 60 w i n s T max 18 4 Y eer tape start 2 5mm min width 4r All dime
26. oelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com ky Doc ID 7383 Rev 3 37 37
27. t 1 2 vs input voltage part 2 2 Rds on mOhm aston Rn 140 120 110 100 SST 120 iners 90 Tj 150 C 100 BRE ccm 80 Id 6A 70 80 Id 1A 60 2 EHI RN 60 ae Tj 25 C ne 40 i 40 1 Id 6A i _ ced em E oon wen j 40 20 s DA 10 0 0 a 35 4 4 5 5 55 6 6 5 4 3 35 4 45 5 55 6 65 Vin V Vin V Figure 13 Source drain diode forward Figure 14 Static drain source on resistance characteristics Vsd mV Rds on mohms 1000 150 950 Es Vin 0V 125 Vin 5V 850 100 Tj 150 C 800 an en ae 750 75 700 650 29 r rp ome 600 Tj 40 C 25 a 550 500 0 0 2 4 6 8 10 12 14 0 1 2 3 4 5 6 Id A Id A q Doc ID 7383 Rev 3 13 37 Protection features VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 Figure 15 Turn on current slope part 1 2 Figure 16 Turn on current slope part 2 2 di dt A us di dt A us 2 25 8 2 T Vin 3 5V 1 75 Vdd 15V 6 Id 3 5A 15 5 1 25 4 1 3 0 75 2 0 5 1 0 25 0 100 200 300 400 500 600 700 800 900 1000 1100 100 200 300 400 500 600 700 800 900 1000 1100 Rg ohm Rg ohm Figure 17 Transfer characteristics Figure 18 Static drain source on resistance vs Id Idon A Rds on mOhm 10 140 9 Tj 25 C Vds 13 5V UE 120 8 Tj 150 C ee a te E 7 100 Tj 150 C ee eee aed T Vin 5V B 80 60 ee 1 Vin 3 5V Tj 25 C Vin 5V a Se yw Tj 40 C rs a S a T E Vin 5V 20
28. v 3 ky VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 List of tables List of tables Table 1 Device SUMMA iue nain xe dae a eae ea Pace et deat ea eae Seeded oak 1 Table 2 Absolute maximum ratings 0 0 0 0 nn 7 Table 3 Thermal data celta nia ae ee ee ete pe Bea amiche a ee ee ee 8 Table 4 Electrical characteristics so serres ruiende EE E A a EEE EREEREER 8 Table 5 SO 8 thermal parameter anana aana anaa 21 Table 6 SOT 223 thermal parameter nananana 23 Table 7 DPAK thermal parameter 0 0 0 0 eee hr 25 Table 8 TO 251 IPAK mechanical data 0 0 2 0 0 cee tee 27 Table 9 TO 252 DPAK mechanical data 0 000 cece 28 Table 10 SOT 223 mechanical data 0000 c teas 29 Table 11 SO 8 mechanical data 0 00 30 Table 12 Document revision history 0 00 cee eee 36 Doc ID 7383 Rev 3 3 37 List of figures VNN7NV04 VNS7NV04 VND7NV04 VND7NV04 1 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44
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