ST 74V1G03 SINGLE 2-INPUT OPEN DRAIN NAND GATE handbook
Contents
1. O 0 7401603 0 I 47 74V1G03 SINGLE 2 INPUT OPEN DRAIN NAND GATE PRELIMINARY DATA e C HIGH SPEED tpp 3 7 ns TYP at Vcc 5V LOW POWER DISSIPATION lcc 1 uA MAX at Ta 25 C HIGH NOISE IMMUNITY VNIH VNIL 28 Vcc MIN POWER DOWN PROTECTION ON INPUTS OPERATING VOLTAGE RANGE Vcc OPR 2V to 5 5V IMPROVED LATCH UP IMMUNITY DESCRIPTION The 74V1G03 is an advanced high speed CMOS SINGLE 2 INPUT OPEN DRAIN NAND GATE fabricated with sub micron silicon gate and double layer metal wiring CMOS technology The internal circuit is composed of 3 stages including buffer output which provide high noise immunity and stable output PIN CONNECTION AND IEC LOGIC SYMBOLS 14 1B GND 5212240 September 1999 SOT23 5L ORDER CODE 74V1G03S 74V1G03C SC 70 This device can with an external pull up resistor be used in wired AND configuration This device can also be used as a led driver in any other application requiring a current sink Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage This device can be used to interface 5V to 3V 1 a her LC13610 1 7 74V1G03 INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION ESD PROTEC 5011940 ABSOLUTE MAXIMUM RATINGS uma vi foe mavo oro VI oma Absolute Maximum Ratings are those values beyond which damage to the device may occur Functional operation2. ain Sweden Switzerland Taiwan Thailand United Kingdom U S A http www st com ar 77
3. e following equation Icc opr Cro Voc fin lcc 3 7 x 74V1G03 TEST CIRCUIT PULSE GENERATOR C 15 50 pF or equivalent includes jig and probe capacitance Ri Ri 1KQ or equivalent Rr Zour of pulse generator typically 500 WAVEFORM PROPAGATION DELAYS f 1MHz 50 duty cycle 3012741 4 7 SOT23 5L MECHANICAL DATA 74V1G03 SC 70 MECHANICAL DATA 6 7 2 74V1G03 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specification mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a trademark of STMicroelectronics 1999 STMicroelectronics Printed in Italy All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco The Netherlands Singapore Sp
4. under these condition is not implied cc Vi O lik OK TL A A A A C C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Value Unit Supply Voltage 2 0 to 5 5 Input Voltage 0 to 5 5 dt dv Input Rise and Fall Time see note 1 Vcc 3 3 0 3V 0 to 100 ns V V cc 5 0 0 5V 0 to 20 ns V 1 Vin from 30 to 70 of Vcc 2 7 2 74V1G03 DC SPECIFICATIONS Parameter Test Conditions Value 7 High Level Input Voltage 3 0 to 5 5 Low Level Input 20 Voltage 3 0 to 5 5 Low Level Output Voltage High Impedance Output Leakage Current Vi Vin or Vit Vo Voc or GND 0 to 5 5 5 5V or GND AC ELECTRICAL CHARACTERISTICS Input t t 3 ns Symbol Parameter i CL Ta 25 C 40 to 85 C pF Propagation Delay uu a se onen ns 507 15 Ri 1ke 37 55 10 65 ata ad taz Propagation Delay 380 so Im ro 90 114 10 130 vine 507 so fm tke 60 75 10 85 Voltage range is 3 3V 0 3V Voltage range is 5V 0 5V CAPACITIVE CHARACTERISTICS Symbol Parameter FA Test Conditions Value Ta 25 C 40 to 85 C Brenn eu _ ZV C V rn ES Cro Power Dissipation Capacitance note 1 1 Cro isdefined as the value of the IC s internal equivalent capacitance which is calculated fromthe operating current consumption without load Referto Test Circuit Average operating current can be obtained by th
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ST 74V1G03 SINGLE 2 INPUT OPEN DRAIN NAND GATE handbook