ATMEL TS80C31X2 8-bit CMOS Microcontroller ROMless handbook
Contents
1. SCON Serial Control Register 98h 7 6 5 4 3 2 1 0 FE SM0 SM2 8 Bit Mnemonic Description Framing Error bit SMOD0 1 Clear to reset the error state not cleared by a valid stop bit Set by hardware when an invalid stop bit is detected must be set to enable access to the FE bit SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection SMODO must be cleared to enable access to the SMO bit SMI Serial port Mode bit 1 SMO SMI Mode Description Baud Rate Shift Register 8 bit UART 9 bit UART 9 bit UART 1 12 6 2 mode Variable 1 64 1 32 32 16in X2 mode Variable oo0o Q SM2 Serial port Mode 2 bit Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature Set to enable multiprocessor communication feature in mode 2 and 3 and eventually mode 1 This bit should be cleared in mode 0 Reception Enable bit Clear to disable serial reception Set to enable serial reception TB8 Transmitter Bit 8 Ninth bit to transmit in modes 2 and 3 Clear to transmit a logic 0 in the 9th bit Set to transmit a logic 1 in the 9th bit RB8 Receiver Bit 8 Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0 Set by hardware if 9th bit received is a logic 1 In mod2. 0 TSS0C31X2 amp nb pil AMEL ET WIRELESS amp uC TS80C31X2 8 bit CMOS Microcontroller ROMless 1 Description TS80C31X2 is high performance CMOS and versions of the 80C51 CMOS single chip 8 bit microcontroller The TS80C31X2 retains all features of the TSC80C31 with 128 bytes of internal RAM a 5 source 4 priority level interrupt system an on chip oscilator and two timer counters In addition the TS80C31X2 has a dual data pointer a more versatile serial channel that facilitates multiprocessor communication EUART and a X2 speed improvement mechanism 2 Features e 80C31 Compatible 8031 pin and instruction compatible e Four 8 bit I O ports e Two 16 bit timer counters e 128 bytes scratchpad RAM e High Speed Architecture e 40 MHz 5V 30MHz 3V e X2 Speed Improvement capability 6 clocks machine cycle 30 MHz 5V 20 MHz 3V Equivalent to 60 MHz 5V 40 MHz 3V Dual Data Pointer Asynchronous port reset Rev C 15 January 2001 The fully static design of the TS80C31X2 allows to reduce system power consumption by bringing the clock frequency down to any value even DC without loss of data The TS80C31X2 has 2 software selectable modes of reduced activity for further reduction in power consumption In the idle mode the CPU is frozen while the timers the serial port and the interrupt system are still operating In the power down mode the RAM is saved and all
3. PORT OPERATION DPL OR Rt OUT OLD DATA NEW DATA P0 PINS SAMPLED P0 PINS SAMPLED MOV DEST P0 EY MOV DEST PORT P2 P3 P1 P2 P3 PINS SAMPLED P1 P2 P3 PINS SAMPLED INCLUDES INTO INTI TO T1 p Y gt l L Y gt l RXD SAMPLED RXD SAMPLED SERIAL PORT SHIFT CLOCK TXD MODE 0 Figure 21 Clock Waveforms This diagram indicates when signals are clocked internally The time it takes the signals to propagate to the pins however ranges from 25 to 125 ns This propagation delay is dependent on variables such as temperature and pin loading Propagation also varies from output to output and component Typically though 25 fully loaded RD and WR propagation delays are approximately 50ns The other signals are typically 85 ns Propagation delays are incorporated in the AC specifications 40 Rev C 15 January 2001 SE WIRELESS amp uC TS80C31X2 8 Ordering Information TS 80C31X2 M C B R mm mm T M VCC 5V 10 Packages 40 MHz standard mode A PDIL 40 20 MHz X2 mode B PLCC 44 V VCC 5V 10 C PQFP FI 13 9 mm footprint 40 MHz standard mode E VQFP 44 1 4mm 30 MHz X2 mode L VCC 2 7 to 5 5 V 30 MHz standard mode 20 MHz X2 mode E Samples Conditioning R Tape amp Reel D Dry Pack B Tape amp Reel and Temper ature Range Dry Pack C Commercial 0 to 70 C I Industrial 40 to 85 C Table 28 Maximum Clock Frequency
4. t care bits provide the flexibility to address one or more slaves at a time The following example illustrates how a given address is formed To address a device by its individual address the SADEN mask byte must be 1111 1111b For example SADDR 0101 0110b SADEN 111111005 Given 0101 01XXb The following is an example of how to use given addresses to address different slaves Slave A SADDR 1111 0001b SADEN 111110105 Given 1111 OXOXb Slave B SADDR 1111 0011b SADEN 1111 1001b Given 1111 OXX1b Slave C SADDR 1111 00105 SADEN 1111 1101b Given 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately For slave A bit 0 the LSB is a don t care bit for slaves B and C bit 0 is a 1 To communicate with slave only the master must send an address where bit 0 is clear e g 1111 00000 For slave A bit 1 is a 1 for slaves B and C bit 1 is a don t care bit To communicate with slaves B and C but not slave A the master must send an address with bits O and 1 both set e g 1111 00115 To communicate with slaves A B and C the master must send an address with bit O set bit 1 clear and bit 2 clear e g 1111 00015 6 3 4 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don t care bits e g SADDR 0101 0110b SADEN 111111005 Broadcast SADDR OR SADEN 1111 111Xb The use of don t care bits p
5. 5ID 6 E F8h FFh FOh B F7h 0000 0000 8 EFh ACC E0h 000 0000 E7h D8h DFh PSW DOh 000 0000 D7h C8h CFh C7h IP SADEN B8h xXxo 0000 0000 0000 BEH P3 IPH BOh 111 111 XXX0 0000 B7h IE SADDR A8h oxxo 0000 0000 0000 Ah P2 AUXRI 111 111 XXXX ATh SCON SBUF 98h 0000 0000 XXXX XXXX AFi Pi 90h Hiii 97h 88h TCON TMOD TLO TLI THO THI CKCON 8Fh 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 XXXX XXX0 80h PO SP DPL DPH PCON 87h 111 111 0000 0111 0000 0000 0000 0000 00X1 0000 0 8 1 9 2 A 3 B AIC 5 D 6 E reserved TS80C31X2 5 Pin Configuration P1 0 T2 P1 1 T2EX P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 RST P3 0 RxD P3 1 TxD P3 2 INTO P3 3 INTL P3 4 TO P3 5 TI P3 6 WR P3 7 RD XTAL2 XTALI VSS P1 5 1 6 P1 7 RST P3 0 RxD NIC P3 1 TxD P3 2 INTO P3 3 INTI P3 4 TO P3 5 TI NIC No Internal Connection PDIL CDIL40 VCC P0 0 0 0 1 1 P0 2 2 P0 3 P0 4 A4 P0 5 A5 P0 6 A6 P0 7 A7 EA VPP ALE PROG PSEN P2 7 15 P2 6 14 P2 5 A13 P2 4 A12 P2 3 A11 P2 2 A10 P2 1 A9 P2 0 A8 VSSI NIC AIMEL Sey r WIRELESS amp pC PIS 7 P0 4 AD4 P1 6 5 5 P1 7 P0 6 AD6 RST 7 7 P3 0 RxD U EA EA NIC PLCC44 NIC P3 1 TxD U ALE P3 2 INTO PSEN P3 3 INTI P2 7 A15 P3 4 TO P2 6 A14 P3 5 TI P2 5 A13 4 25 26 27 LIL IL IL IL IL IL S
6. Conditions Icc Power Supply Current Maximum values X1 3 0 6 Freq operating mode 92 mA Vcc 5 5 VIR 16MHz 12 6 Icc Power Supply Current Maximum values X1 0 25 0 3Freq Q MHz 2 dl mode mA 5 5 na Q 12MHz 3 9 16MHz 5 1 7 4 DC Parameters for Low Voltage TA 0 C to 70 C Vss 0 V Vcc 2 7 V to 5 5 V 10 F 0 to 30 MHz TA 40 C to 85 C Vss 0 V Vcc 2 7 V to 5 5 V 10 F 0 to 30 MHz Table 15 DC Parameters for Low Voltage Symbol Parameter Unit Test Conditions Input Low Voltage 0 5 0 2 Vcc 0 1 V Input High Voltage except XTAL1 RST 0 2 Vcc 0 9 Vcc 0 5 V Input High Voltage XTAL1 RST 0 7 Vcc 0 5 V VoL Output Low Voltage ports 1 2 3 6 0 45 IoL 0 8 mA Output Low Voltage port 0 ALE PSEN 6 0 45 IoL 1 6 mA Output High Voltage ports 1 2 3 0 9 Vcc V 10 pA Output High Voltage port 0 ALE PSEN 0 9 Voc V 40 pA In Logical 0 Input Current ports 1 2 and 3 50 Vin 0 45 Hi Input Leakage Current 10 uA 045 V lt Vin lt Logical 1 to 0 Transition Current ports 1 2 3 650 uA Vin 2 0 V Rest RST Pulldown Resistor 50 90 200 Capacitance of I O Buffer 10 pF 1 MHz TA 25 C Ipp Power Down Current 20 50 Vee 2 0 V to 5 5 VO 10 30 Vec 2 0 V to 3 3 VO Power Supply Current Maximum values 1 1 0 2 Freq u
7. DPS Bit Bit D inti 1 Number Mnemonic 7 Reserved 7 value read from this bit is indeterminate Do not set this bit 6 _ Reserved The value read from this bit is indeterminate Do not set this bit 5 _ Reserved The value read from this bit is indeterminate Do not set this bit 4 _ Reserved The value read from this bit is indeterminate Do not set this bit 3 _ Reserved The value read from this bit is indeterminate Do not set this bit 2 _ Reserved The value read from this bit is indeterminate Do not set this bit l _ Reserved The value read from this bit is indeterminate Do not set this bit Data Pointer Selection 0 DPS Clear to select DPTR0 Set to select DPTR1 Reset Value XXXX XXX0 Not bit addressable Application Software can take advantage of the additional data pointers to both increase speed and reduce code size for example block operations copy compare search are well served by using one data pointer as a source pointer and the other one as a destination pointer 10 Rev C 15 January 2001 AMEL E e RE RS WIRELESS amp uC ASSEMBLY LANGUAGE Block move using dual data pointers Destroys DPTRO DPTRI PSW note DPS exits opposite of entry state unless an extra INC AUXRI is added 00A2 AUXRI EQU 0A2H 0000 909000MOV DPTR ZSOURCE 0003 05A2 INC AUXRI 0005 904000 MOV DPTR DEST 0008 LOOP 0008 05A2 INC AUXRI 000A EO MOVX A DPTR 00
8. Do not set this bit 3 _ Reserved The value read from this bit is indeterminate Do not set this bit 2 _ Reserved The value read from this bit is indeterminate Do not set this bit l _ Reserved The value read from this bit is indeterminate Do not set this bit CPU and peripheral clock bit 0 2 Clear to select 12 clock periods per machine cycle STD mode Fosc Fxrar 2 Set to select 6 clock periods per machine cycle X2 mode Fosc FxrAL Reset Value XXXX XXX0b Not bit addressable For further details the X2 feature please refer to ANM072 available on the web http www atmel wm com Rev C 15 January 2001 WIRELESS amp uC AMEL TS80C31X2 6 2 Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways The dual DPTR structure is a way by which the chip will specify the address of an external data memory location There are two 16 bit DPTR registers that address the external memory and a single bit called DPS AUXR1 bit0 See Table 5 that allows the program code to switch between them Refer to Figure 3 External Data Memory AUXRI A2H DPH 83H DPL 82H Figure 3 Use of Dual Pointer Rev C 15 January 2001 9 TS80C31X2 Table 4 AUXRI Auxiliary Register 1 AMEL aay c WIRELESS amp uC 7 6 5 4 3 2 0
9. Instruction FloatAfter PSEN Tpxay PSEN to Address Valid Taviv Address to Valid Instruction In PSEN Low to Address Float Table 19 AC Parameters for Fix Clock V V L X2 mode 30 MHz 60 MHz equiv X2 mode 20 MHz 40 MHz equiv standard mode 40 MHz L standard mode 30 MHz Min Max Min Max 33 50 32 Rev C 15 January 2001 AMEL TS80C31X2 Seay WIRELESS amp uC Table 20 AC Parameters for a Variable Clock derating formula Standard L Units Clock 15 ns 20 ns 20 ns 35 ns 15 ns 25 ns 45 ns 0 ns 15 ns 45 ns 10 ns 7 5 3 External Program Memory Read Cycle 12 Tru ALE K gt TLLA 4 Tras TAVLL 5 E ERN ADDRESS PORT2 Nw SFR P2 d ADDRESS 8 15 4 ADDRESS A8 A15 Figure 14 External Program Memory Read Cycle Rev C 15 January 2001 33 TS80C31X2 7 5 4 External Data Memory Characteristics Table 21 Symbol Description AMEL L 0 WIRELESS amp uC Symbol Parameter TRLRH RD Pulse Width Tat wt WR Pulse Width TrLpv RD to Valid Data In TRHDX Data Hold After RD TRHDZ Data Float After RD TLLpv ALE to Valid Data In TAVDV Address to Valid Data In TLLWL ALE to WR or RD TAVWL Address to WR or RD Tovwx Data Valid to WR Transition TovwH Data set up to WR High D
10. machine cycles while the oscillator is running resets the device An internal diffused resistor to Vss permits a power on reset using only an external capacitor to Voc ALE 30 33 27 D Address Latch Enable Output pulse for latching the low byte of the address during an access to external memory In normal operation ALE is emitted at a constant rate of 1 6 1 3 in X2 mode the oscillator frequency and can be used for external timing or clocking Note that one ALE pulse is skipped during each access to external data memory PSEN 29 32 26 Program Store ENable The read strobe to external program memory When executing code from the external program memory PSEN is activated twice each machine cycle except that two PSEN activations are skipped during each access to external data memory PSEN is not activated during fetches from internal program memory 31 35 29 External Access Enable EA must be externally held low to enable the device to fetch code from external program memory locations 19 21 15 Crystal 1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits 18 20 14 Crystal 2 Output from the inverting oscillator amplifier Rev C 15 January 2001 TS80C31X2 AIMEL WIRELESS amp pC 6 TS80C31X2 Enhanced Features In comparison to the original 80C31 the TS80C31X2 implements some n
11. y WIRELESS amp uC TS80C31X2 Table 7 Priority Level Bit Values IPH x Interrupt Level Priority 0 0 0 Lowest 0 1 1 1 0 2 1 1 3 Highest A low priority interrupt can be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt can t be interrupted by any other interrupt source If two interrupt requests of different priority levels are received simultaneously the request of higher priority level is serviced If interrupt requests of the same priority level are received simultaneously an internal polling sequence determines which request is serviced Thus within each priority level there is a second priority structure determined by the polling sequence Table 8 IE Register IE Interrupt Enable Register A8h 7 6 5 4 3 2 1 0 ES ET1 EX1 ETO E Description ipti Number Mnemonic 5 Enable interrupt bit Clear to disable all interrupts 7 EA Set to enable all interrupts If EA 1 each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit 6 _ Reserved The value read from this bit is indeterminate Do not set this bit 5 Reserved i The value read from this bit is indeterminate Do not set this bit Serial port Enable bit 4 ES Clear to disable serial port interrupt Set to enable serial port interrup
12. 0 INC DPTR 000C 05A2 INC AUXRI 000EF0 MOVX DPTR A 000 DPTR 0010 70 6 2 LOOP 0012 05 2 AUXRI TS80C31X2 address of SOURCE switch data pointers address of DEST switch data pointers get a byte from SOURCE increment SOURCE address switch data pointers write the byte to DEST increment DEST address check for 0 terminator optional restore DPS INC is a short 2 bytes and fast 12 clocks way to manipulate the DPS bit in the AUXR1 SFR However note that the INC instruction does not directly force the DPS bit to a particular state but simply toggles it In simple routines such as the block move example only the fact that DPS is toggled in the proper sequence matters not its actual value In other words the block move routine works the same whether DPS is 0 or 1 on entry Observe that without the last instruction INC AUXR1 the routine will exit with DPS in the opposite state Rev C 15 January 2001 11 WIRELESS amp pC TS80C31X2 ATMEL 6 3 TS80C31X2 Serial I O Port The serial I O port in the TS80C31X2 is compatible with the serial I O port in the 80C31 It provides both synchronous and asynchronous communication modes It operates as an Universal Asynchronous Receiver and Transmitter UART in three full duplex modes Modes 1 2 and 3 Asynchronous transmission and reception can occur simultaneously and at different baud rates S
13. 168225 et cedo 3 ow lt lt lt G Oy Ay PQFP44 VQFP44 P2 0 A8 P2 2 A10 P2 3 A11 P2 4 A12 Rev C 15 January 2001 AMEL Seay WIRELESS amp uC TS80C31X2 Table 2 Pin Description for 40 44 pin packages MNEMONIC PIN NUMBER DIL LCC 1 4 AND FUNCTION 20 16 Ground 0V reference 39 Optional Ground Contact the Sales Office for ground connection Vcc 40 38 Power Supply This is the power supply voltage for normal idle and power down operation P0 0 P0 7 39 32 37 30 IO Port 0 Port 0 is an open drain bidirectional I O port Port 0 pins that have 1s written to them float and can be used as high impedance inputs Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption Port 0 is also the multiplexed low order address and data bus during access to external program and data memory In this application it uses strong internal pull up when emitting 1s 1 0 7 1 8 2 9 40 44 1 3 UO Port 1 Port 1 is 8 bit bidirectional I O port with internal pull ups Port 1 pins that have Is written to them are pulled high by the internal pull ups and can be used as inputs As inputs Port 1 pins that are externally pulled low will source current because of the int
14. 7 2 Power consumption measurement Since the introduction of the first C51 devices every manufacturer made operating Icc measurements under reset which made sense for the designs were the CPU was running under reset In Atmel Wireless amp Microcontrollers new devices the CPU is no more active during reset so the power consumption is very low but is not really representative of what will happen in the customer system That s why while keeping measurements under Reset Atmel Wireless amp Microcontrollers presents a new way to measure the operating Icc Using an internal test ROM the following code is executed Label SJMP Label 80 FE Ports 1 2 3 are disconnected Port 0 is tied to FFh EA RST Vss XTAL2 is not connected and XTAL I1 is driven by the clock This is much more representative of the real operating Icc 26 Rev C 15 January 2001 AMEL y WIRELESS amp uC 7 3 DC Parameters for Standard Voltage TS80C31X2 TA 0 C to 70 C Vss 0 V Vcc 5 V 1096 F 0 to 40 MHz TA 40 C to 85 C Veg 0 V Voc 5 V 10 F 0 to 40 MHz Table 14 DC Parameters in Standard Voltage Symbol Parameter Min Typ Max Unit Test Conditions Vit Input Low Voltage 0 5 0 2 Vcc 0 1 V Input High Voltage except XTAL1 RST 0 2 Vcc 0 9 Vcc 0 5 V Input High Voltage XTAL1 RST 0 7 Vcc Vcc 0 5 V Vor Output Low Voltage ports 1 2 3 9 0 3 V
15. Code M V L Unit Standard Mode oscillator frequency 40 40 30 MH Standard Mode internal frequency 40 40 30 2 X2 Mode oscillator frequency 20 30 20 MHz X2 Mode internal equivalent frequency 40 60 40 Rev C 15 January 2001 41 TS80C31X2 AMEL Sey r WIRELESS amp uC Table 29 Possible Ordering Entries TS80C31X2 ROMIess TR X X X X X X X X X X X X X X X X X X t A w for samples Reel available for B and E packages e Dry pack mandatory for E packages 42 Rev C 15 January 2001
16. Igi 100 pa 0 45 V 4 i5 M IoL 1 6 mA IoL 3 5 mA Output Low Voltage port 0 6 0 3 V ToL 200 HAH 0 45 V IoL 3 2 mA 1 0 y eee IoL 7 0 mA VoL2 Output Low Voltage ALE PSEN 0 3 V Ig 100 HATH 0 45 V 4 10 1 6mA IoL 3 5 mA Output High Voltage 1 2 3 Vcc 0 3 V 10 0 7 V 30 1 5 lon 60HA 5 10 Output High Voltage port 0 Vcc 0 3 200 HA 0 7 3 2 mA Vec 1 5 V loan 7 0 mA Vcc 5 V 10 Output High Voltage ALE PSEN Vcc 0 3 V 100 pA Vcc 0 7 V 1 6 mA Vec 1 5 V 3 5 Vcc 5 V 10 Rest RST Pulldown Resistor 50 90 200 lg Logical 0 Input Current ports 1 2 and 3 50 Vin 0 45 V Hi Input Leakage Current 10 045 V lt Vin lt Iq Logical 1 to 0 Transition Current ports 1 2 3 650 uA Vin 2 0 V Capacitance of UO Buffer 10 pF 1 gt TA 25 C Ipp Power Down Current 20 5 50 20 lt 5 5 Power Supply Current Maximum values 1 0 4 Freq under mode 7 MHz Vcc 5 5 va RESET 12MHz5 8 mA 16MHz 7 4 Rev C 15 January 2001 27 TS80C31X2 AMEL G WIRELESS amp uC Symbol Parameter Min Typ Max Unit Test
17. Refer to PX0H for priority level Reset Value 0 0000b Bit addressable 20 Rev C 15 January 2001 AIMEL TS80C31X2 e WIRELESS amp pC Table 10 IPH Register IPH Interrupt Priority High Register B7h 7 6 5 4 3 2 1 0 PSH PT1H PX1H PTOH PX0H m D Description Number Mnemonic p 7 Reserved The value read from this bit is indeterminate Do not set this bit 6 _ Reserved The value read from this bit is indeterminate Do not set this bit 5 _ Reserved The value read from this bit is indeterminate Do not set this bit Serial port Priority High bit PSH PS Priority Level 0 0 Lowest 4 PSH 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit 1 1 Priority Level 3 PTIH 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit PXIH 1 Priority Level 2 PXIH 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PTOH Priority Level 1 PTOH 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit Priority Level 0 PX0H 0 0 Lowest 0 1 1 0 1 1 Highest Reset Value XXX0 0000b Not bit addressable Rev C 15 January 2001 21 TS80C31X2 AMEL aay c WIRELESS amp uC 6 5 Idle mode An instruction that sets PCON O causes that to be the last instruction executed before going into the Idle mode In the Idle mode the inter
18. Timings in Modes 2 and 3 6 3 2 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled SM2 bit in SCON register is set Implemented in hardware automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame Only when the serial port recognizes its own address the receiver sets RI bit in SCON register to generate an interrupt This ensures that the CPU is not interrupted by command frames addressed to other devices If desired you may enable the automatic address recognition feature in mode 1 In this configuration the stop bit takes the place of the ninth data bit Bit RI is set only when the received command frame address matches the device s address and is terminated by a valid stop bit To support automatic address recognition a device is identified by a given address and a broadcast address NOTE The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 i e setting SM2 bit in SCON register in mode 0 has no effect Rev C 15 January 2001 13 TS80C31X2 AIMEL WIRELESS amp pC 6 3 3 Given Address Each device has an individual address that is specified in SADDR register the SADEN register is a mask byte that contains don t care bits defined by zeros to form the device s given address The don
19. Weak pull up Float Weak pull up Weak pull up Weak pull up Active 24 Rev C 15 January 2001 AMEL TS80C31X2 fec WIRELESS amp pC 6 8 Power Off Flag The power off flag allows the user to distinguish between a cold start reset and a warm start reset A cold start reset is the one induced by switch on A warm start reset occurs while Vcc is still applied to the device and could be generated for example by an exit from power down The power off flag POF is located in PCON register See Table 13 POF is set by hardware when Vcc rises from 0 to its nominal voltage The POF can be set or cleared by software allowing the user to determine the type of reset The POF value is only relevant with a Vcc range from 4 5V to 5 5V For lower Vcc value reading POF bit will return indeterminate value Table 13 PCON Register PCON Power Control Register 87h 7 6 5 4 3 2 1 0 SMODI SMODO0 POF GF1 IDL s es Description Number Mnemonic Serial port Mode bit 1 7 SMODI Set to select double baud rate in mode 1 2 or 3 Serial port Mode bit 0 6 SMODO Clear to select SMO bit in SCON register Set to to select FE bit in SCON register 5 Reserved The value read from this bit is indeterminate Do not set this bit Power Off Flag 4 POF Clear to recognize next reset type Set by hardware when Vcc rises from 0 to i
20. ata Hold After WR TRLAZ RD Low to Address Float TwHLH RD or WR High to ALE high 34 Rev C 15 January 2001 AMEL WIRELESS amp uC V X2 mode 30 MHz V standard mode 40 MHz TS80C31X2 Table 22 AC Parameters for a Fix Clock L X2 mode 20 MHz L standard mode 30 MHz Units 60 MHz equiv 40 MHz equiv Min Max Min Max Max 85 125 ns ns 137 ns ns 42 ns 222 ns 235 ns 130 ns ns ns 60 ns TwHox 15 9 17 10 18 ns TRLAZ 0 0 0 0 0 ns TwHLH 10 40 7 27 15 35 5 45 13 53 ns Rev C 15 January 2001 TS80C31X2 AMEL Sey r WIRELESS amp uC Table 23 AC Parameters for a Variable Clock derating formula Standard L Units Clock 25 ns 25 ns 30 ns 0 ns 25 ns 45 ns 65 ns 30 ns 30 ns 30 ns 20 ns 20 ns 15 ns 0 ns 20 ns 20 ns 7 5 5 External Data Memory Write Cycle gt ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR P2 ADDRESS A8 A15 OR SFR P2 Figure 15 External Data Memory Write Cycle 36 Rev C 15 January 2001 TS80C31X2 RET WIRELESS amp pC 7 5 6 External Data Memory Read Cycle PORT 0 ADDRESS PORTA OR SFR P2 Figure 16 External Data Memory Read Cycle 7 5 7 Serial Port Timing Shift Register Mode Table 24 Symbol Description Parameter Serial port clock cycle time Outp
21. by hardware when reset occurs Set to enter power down mode Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs Set to enter idle mode Reset Value 00X1 0000b Not bit addressable Power off flag reset value will be 1 only after a power on cold reset warm reset doesn t affect the value of this bit Rev C 15 January 2001 17 WIRELESS amp pC TS80C31X2 AIMEL 6 4 Interrupt System The TS80C31X2 has a total of 5 interrupt vectors two external interrupts INTO and INT1 two timer interrupts timers 0 and 1 and the serial port interrupt These interrupts are shown in Figure 7 High priority interrupt TFO Interrupt polling sequence decreasing from high to low priority 1 RI TI Low priority interrupt Individual Enable Global Disable Figure 7 Interrupt Control System Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register See Table 8 This register also contains a global disable bit which must be cleared to disable all interrupts at once Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register See Table 9 and in the Interrupt Priority High register See Table 10 shows the bit values and priority levels associated with each combination 18 Rev C 15 January 2001 AMEL
22. chmitt Trigger use is not necessary 5 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and 5V 6 Under steady state non transient conditions Ig must be externally limited as follows Maximum Io per port pin 10 mA Maximum Io per 8 bit port Port 0 26 mA Ports 1 2 and 3 15 mA Maximum total Ig for all output pins 71 mA If Io exceeds the test condition Voy may exceed the related specification Pins are not guaranteed to sink current greater than the listed test conditions 7 Forother values please contact your sales office 8 Operating is measured with all output pins disconnected XTALI driven with Terca 5 ns see Figure 13 Vj Vss 0 5 Vin Vcc 0 5V XTAL2 N C EA Port 0 Vcc RST The internal ROM runs the code 80 FE label SJMP label would be slightly higher if a crystal oscillator is used Measurements are made with OTP products when possible which is the worst case Rev C 15 January 2001 other pins are disconnected Figure 9 Icc Test Condition under reset 29 TS80C31X2 AMEL Sey r WIRELESS amp uC Reset Vss after a high pulse during at least 24 clock cycles All other pins are disconnected Reset Vss after a high pulse during at least 24 clock cycles L NO CLOCK SIGNAL All other pins are disconnected Reset Vss after a high pulse dur
23. d range in pF M L Port 0 100 50 100 Port 1 2 3 80 50 80 ALE PSEN 100 30 100 Table 18 Table 21 and Table 24 give the description of each AC symbols Table 19 Table 22 and Table 25 give for each range the AC parameter Table 20 Table 23 and Table 26 give the frequency derating formula of the AC parameter To calculate each AC symbols take the x value corresponding to the speed grade you need M V or L and replace this value in the formula Values of the frequency must be limited to the corresponding speed grade Table 17 Max frequency for derating formula regarding the speed grade M X1 mode M X2 mode V X1 mode V X2 mode L X1 mode Freq MHz 40 20 40 30 30 T ns 23 50 25 33 3 33 3 L X2 mode 20 50 Example Ty in X2 mode for a V part at 20 MHz 1 20 6 50 ns x 25 Table 20 T 50ns 2T x 2 x 50 25 75ns Rev C 15 January 2001 31 TS80C31X2 7 5 2 External Program Memory Characteristics Table 18 Symbol Description AMEL L 0 WIRELESS amp uC Symbol Parameter T Oscillator clock period Tin ALE pulse width TAVLL Address Valid to ALE TLLAX Address Hold After ALE ALE to Valid Instruction In ALE to PSEN Pulse Width Tpriv PSEN to Valid Instruction In Tpxix Input Instruction Hold After PSEN Tpxiz Input
24. e 1 if SM2 0 RB8 is the received stop bit In mode 0 is not used TI Transmit Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes Receive Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0 see Figure 5 and Figure 6 in the other modes Reset Value 0000 0000b Bit addressable 16 Rev C 15 January 2001 AMEL I WIRELESS amp uC TS80C31X2 Table 6 PCON Register PCON Power Control Register 87h 7 6 5 4 3 2 1 0 SMOD1 SMODO POF GF1 GF0 PD IDL Pi En Description ipti Number Mnemonic p Serial port Mode bit 1 7 SMODI Set to select double baud rate in mode 1 2 or 3 Serial port Mode bit 0 6 SMODO Clear to select SMO bit in SCON register Set to to select FE bit in SCON register 5 Reserved The value read from this bit is indeterminate Do not set this bit Power Off Flag 4 POF Clear to recognize next reset type Set by hardware when VCC rises from 0 to its nominal voltage Can also be set by software General purpose Flag 3 GFI Cleared by user for general purpose usage Set by user for general purpose usage General purpose Flag 2 GFO Cleared by user for general purpose usage Set by user for general purpose usage Power Down mode bit 1 PD Cleared
25. eration Diagram 6 Rev C 15 January 2001 WIRELESS amp uC AMEL TS80C31X2 XTALI 2 j I I STD Mode gt lt X2 Mode gt lt STD Mode Figure 2 Mode Switching Waveforms The X2 bit in the CKCON register See Table 3 allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa At reset the standard speed is activated STD mode Setting this bit activates the X2 feature X2 mode CAUTION In order to prevent any incorrect operation while operating in X2 mode user must be aware that all peripherals using clock frequency as time reference UART timers will have their time reference divided by two For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms UART with 4800 baud rate will have 9600 baud rate Rev C 15 January 2001 7 TS80C31X2 Table 3 CKCON Register CKCON Clock Control Register 8Fh AMEL Sey r WIRELESS amp uC 7 6 5 4 3 2 0 2 2 Bit Bit D ipti 2 1 Number Mnemonic 7 i Reserved The value read from this bit is indeterminate Do not set this bit 6 _ Reserved The value read from this bit is indeterminate Do not set this bit 5 _ Reserved The value read from this bit is indeterminate Do not set this bit 4 _ Reserved The value read from this bit is indeterminate
26. erial I O port includes the following enhancements Framing error detection Automatic address recognition 6 3 1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes modes 1 2 and 3 To enable the framing bit error detection feature set SMODO bit in PCON register See Figure 4 SCON 98h Set FE bit if stop bit is 0 framing error SMODO 1 SMO to UART mode control SMOD 0 framing error control Figure 4 Framing Error Block Diagram When this feature is enabled the receiver checks each incoming data frame for a valid stop bit An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs If a valid stop bit is not found the Framing Error bit FE in SCON register See Table 5 bit is set 12 Rev C 15 January 2001 AMEL TS80C31X2 E WIRELESS amp uC Software may examine FE bit after each reception to check for data errors Once set only software or a reset can clear FE bit Subsequently received frames with valid stop bits cannot clear FE bit When FE feature is enabled RI rises on stop bit instead of the last data bit See Figure 5 and Figure 6 an E ua T 5 S tart Data byte Stop bit bit RI SMODO X FE SMODO 1 Figure 5 UART Timings in Mode 1 RXD Data byte 1 Stop bit bit bit RI J SMOD0 0 RI J SMODO 1 FE A SMODO0 1 Figure 6 UART
27. ernal pull ups P2 0 P2 7 21 28 24 31 18 25 IO Port 2 Port 2 is an 8 bit bidirectional I O port with internal pull ups Port 2 pins that have Is written to them are pulled high by the internal pull ups and can be used as inputs As inputs Port 2 pins that are externally pulled low will source current because of the internal pull ups Port 2 emits the high order address byte during fetches from external program memory and during accesses to external data memory that use 16 bit addresses MOVX DPTR In this application it uses strong internal pull ups emitting 1s During accesses to external data memory that use 8 bit addresses MOVX port 2 emits the contents of the P2 SFR P3 0 P3 7 10 17 11 13 19 UO Port 3 Port 3 is an 8 bit bidirectional 1 port with internal pull ups Port 3 pins that have Is written to them are pulled high by the internal pull ups and can be used as inputs As inputs Port 3 pins that are externally pulled low will source current because of the internal pull ups Port 3 also serves the special features of the 80C51 family as listed below RXD P3 0 Serial input port TXD P3 1 Serial output port INTO P3 2 External interrupt 0 INTI P3 3 External interrupt 1 TO P3 4 Timer external input T1 P3 5 Timer 1 external input WR P3 6 External data memory write strobe RD P3 7 External data memory read strobe Reset Reset A high on this pin for two
28. ew features which are e The X2 option e The Dual Data Pointer e The 4 level interrupt priority system The power off flag The ONCE mode Enhanced 6 1 X2 Feature The TS80C31 X2 core needs only 6 clock periods per machine cycle This feature called X2 provides the following advantages e Divide frequency crystals by 2 cheaper crystals while keeping same CPU power Save power consumption while keeping same CPU power oscillator power saving Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes Increase CPU power by 2 while keeping same crystal frequency In order to keep the original C51 compatibility a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core phase generator This divider may be disabled by software 6 1 1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals This allows any cyclic ratio to be accepted on XTALI input In X2 mode as this divider is bypassed the signals XTAL1 must have a cyclic ratio between 40 to 60 Figure 1 shows the clock generation block diagram X2 bit is validated on XTAL1 2 rising edge to avoid glitches when switching from X2 to STD mode Figure 2 shows the mode switching waveforms XTAL1 2 FxTAL state machine 6 clock cycles CPU control Fosc CKCON reg Figure 1 Clock Gen
29. ing at least 24 clock cycles All other pins are disconnected Figure 12 Icc Test Condition Power Down Mode 0 5 0 7Vcc MS 1 TcLcH Terca 508 Figure 13 Clock Signal Waveform for Tests in Active and Idle Modes 30 Rev C 15 January 2001 AMEL TS80C31X2 IEEE WIRELESS amp uC 7 5 AC Parameters 7 5 1 Explanation of the AC Symbols Each timing symbol has 5 characters The first character is always a T stands for time The other characters depending on their positions stand for the name of a signal or the logical status of that signal The following is a list of all the characters and what they stand for Example T ay Time for Address Valid to ALE Low Time for ALE Low to PSEN Low TA 0 to 70 C commercial temperature range Vss 0 V Vcc 5 V 10 M and V ranges TA 40 C to 85 C industrial temperature range Vss 0 V Voc 5 V 10 M and V ranges TA 0 to 70 C commercial temperature range Vss 0 V 2 7 V lt Vcc lt 5 5 V L range TA 40 C to 85 C industrial temperature range Vss 0 V 2 7 V lt Voc lt 5 5 V L range Table 16 gives the maximum applicable load capacitance for Port 0 Port 1 2 and 3 and ALE and PSEN signals Timings will be guaranteed if these capacitances are respected Higher capacitance values be used but timings will then be degraded Table 16 Load Capacitance versus spee
30. iven at Vcc 0 5 for a logic 1 and 0 45V for a logic 0 Timing measurement are made at Vm min for a logic 1 and max for a logic 0 7 5 12 Float Waveforms FLOAT 0 1 VLOAD 0 1 V VLoap 0 1 V Figure 20 Float Waveforms Rev C 15 January 2001 39 TS80C31X2 AMEL Sey WIRELESS amp uC For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when 100 mV change from the loaded level occurs 2 20mA 7 5 13 Clock Waveforms Valid in normal clock mode In X2 mode XTAL2 signal must be changed to XTAL2 divided by two INTERNAL CLOCK STATE4 STATES 5 6 STATE STATE2 STATE3 STATE4 STATES Jer fer ory re m pm m joo pij lor gt Pi P2 Pi P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION PSEN DATA PCL OUT DATA PCL OUT DATA PCL OUT SAMPLED SAMPLED SAMPLED FLOAT DE MR P2 EXT INDICATES ADDRESS TRANSITIONS READ CYCLE RD PCL OUT IF PROGRAM MEMORY IS EXTERNAL DPL OR Rt OUT Y ge 08 4 2 INDICATES DPH OR 2 SFR TO PCH TRANSITION WRITE CYCLE WR PCL OUT EVEN IF PROGRAM MEMORY IS INTERNAL PCL OUT IF PROGRAM PO para OUT MEMORY IS EXTERNAL P2 INDICATES DPH P2 SFR TO PCH TRANSITION
31. nal clock signal is gated off to the CPU but not to the interrupt Timer and Serial Port functions The CPU status is preserved in its entirely the Stack Pointer Program Counter Program Status Word Accumulator and all other registers maintain their data during Idle The port pins hold the logical states they had at the time Idle was activated ALE and PSEN hold at logic high levels There two ways to terminate the Idle Activation of any enabled interrupt will cause 0 to be cleared by hardware terminating the Idle mode The interrupt will be serviced and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle The flag bits GFO and can be used to give and indication if an interrupt occured during normal operation or during an Idle For example an instruction that activates Idle can also set one or both flag bits When Idle is terminated by an interrupt the interrupt service routine can examine the flag bits The over way of terminating the Idle mode is with a hardware reset Since the clock oscillator is still running the hardware reset needs to be held active for only two machine cycles 24 oscillator periods to complete the reset 6 6 Power Down Mode To save maximum power a power down mode can be invoked by software Refer to Table 6 PCON register In power down mode the oscillator is stopped and the instruction that invoked power down mode i
32. nder mode 7 MHz Vcc 3 3 RESET 12MHz 3 4 ma 16MHz 4 2 Icc Power Supply Current Maximum values X1 1 0 3 Freq MHz 8 t mode Vcc 3 3 V 12MHz4 6 mA 16MHz 5 8 28 Rev C 15 January 2001 AMEL WIRELESS amp uC TS80C31X2 Symbol Parameter Min Typ Max Unit Test Conditions Power Supply Current Maximum values 1 0 15 Freq idle mode MHz 0 2 mA Voc 233 vo 12MHz 2 16MHz 2 6 NOTES 1 lec under reset is measured with all output pins disconnected XTALI driven with Terca 5 ns see Figure 13 Vgs 0 5 V Vin Vcc 0 5V XTAL2 N C EA RST Port 0 Vcc Icc would be slightly higher if a crystal oscillator used 2 Idle I is measured with all output pins disconnected XTALI driven with Terca Tcuct 5 ns Vj Vss 0 5 V Vcc 0 5 V XTAL2 N C Port 0 Voc EA RST Vss see Figure 11 3 Power Down Icc is measured with all output pins disconnected EA Vss PORT 0 Vcc XTAL2 NC RST Vss see Figure 12 4 Capacitance loading on Ports 0 2 may cause spurious noise pulses to be superimposed on the Vors of ALE and Ports I and 3 The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation In the worst cases capacitive loading 100pF the noise pulse on the ALE line may exceed 0 45V with maxi Vor peak 0 6V A S
33. other functions are inoperative e Interrupt Structure with e 5 Interrupt sources e 4 priority level interrupt system e Full duplex Enhanced UART e Framing error detection e Automatic address recognition Power Control modes e Idle mode Power down mode Power off Flag Once mode On chip Emulation Power supply 4 5 5 5V 2 7 5 5V Temperature ranges Commercial 0 to 70 C and Industrial 40 to 85 C Packages 40 PLCC44 VQFP44 1 4 PQFP F1 13 9 footprint TS80C31X2 AMEL Sey r WIRELESS amp uC 3 Block Diagram XTALI XTAL2 PSEN IB bus Parallel I O Ports amp Ext Bus RD WR Port 0 P2 P3 E Z 12 1 Alternate function of Port 3 Rev C 15 January 2001 AMEL E WIRELESS amp uC 4 SFR Mapping The Special Function Registers SFRs of the TS80C31X2 fall into the following categories C51 core registers DPH DPL PSW SP AUXRI port registers PO 2 P3 Timer registers TCON THO TH1 TMOD TLO TL1 Serial I O port registers SADDR SADEN SBUF SCON Power and clock control registers PCON Interrupt system registers IE IP IPH Others CKCON TS80C31X2 Table 1 All SFRs with their address and their reset value Rev C 15 January 2001 Bit Non Bit addressable address able 0 8 1 9 2 3 B AIC
34. rovides flexibility in defining the broadcast address however in most applications a broadcast address is FFh The following is an example of using broadcast addresses Slave A SADDR 1111 00015 SADEN 1111 1010b Broadcast 1111 1X11b Slave B SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B Slave C SADDR 1111 0010b SADEN 111111015 Broadcast 1111 111160 For slaves bit 2 is don t care bit for slave bit 2 is set communicate with all of the slaves the master must send an address FFh To communicate with slaves A and B but not slave C the master can send and address FBh 14 Rev C 15 January 2001 REE WIRELESS amp pC TS80C31X2 6 3 5 Reset Addresses On reset the SADDR and SADEN registers are initialized to 00h i e the given and broadcast addresses XXXX XXXXb all don t care bits This ensures that the serial port will reply to any address and so that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition SADEN Slave Address Mask Register B9h 7 6 S 4 3 2 1 0 Reset Value 0000 0000b Not bit addressable SADDR Slave Address Register A9h 7 6 5 4 3 2 1 0 Reset Value 0000 0000b Not bit addressable Rev C 15 January 2001 15 TS80C31X2 AMEL Sey r WIRELESS amp uC Table 5 SCON Register
35. s the last instruction executed The internal RAM and SFRs retain their value until the power down mode is terminated Vcc can be lowered to save further power Either a hardware reset or an external interrupt can cause an exit from power down To properly terminate power down the reset or external interrupt should not be executed before is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize Only external interrupts INTO and INTI are useful to exit from power down For that interrupt must be enabled and configured as level or edge sensitive interrupt input Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 8 When both interrupts are enabled the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released In this case the higher priority interrupt service routine is executed Once the interrupt is serviced the next instruction to be executed after RETI will be the one following the instruction that put TS80C31X2 into power down mode Np AW Active phase ____sle Power down phase gt lt Oscillator restart gt Active phase Figure 8 Power Down Exit Waveform Exit from power down by reset redefines all the SFRs exit from power down by external interrupt does no affect the SFRs Exit from po
36. t Timer 1 overflow interrupt Enable bit 3 Clear to disable timer 1 overflow interrupt Set to enable timer 1 overflow interrupt External interrupt 1 Enable bit 2 1 Clear to disable external interrupt 1 Set to enable external interrupt 1 Timer 0 overflow interrupt Enable bit 1 Clear to disable timer overflow interrupt Set to enable timer 0 overflow interrupt External interrupt 0 Enable bit 0 Clear to disable external interrupt 0 Set to enable external interrupt 0 Reset Value 0XX0 0000b Bit addressable Table 9 IP Register Rev C 15 January 2001 19 TS80C31X2 IP Interrupt Priority Register B8h AMEL aay r WIRELESS amp uC 7 6 5 4 3 2 1 0 PS 1 1 0 PX0 Bit Bit Description ipti Number Mnemonic P 7 _ Reserved The value read from this bit is indeterminate Do not set this bit 6 _ Reserved The value read from this bit is indeterminate Do not set this bit 5 i Reserved The value read from this bit is indeterminate Do not set this bit 4 Serial port Priority bit Refer to PSH for priority level 3 1 Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level 2 1 External interrupt 1 Priority bit Refer to PX1H for priority level l Timer 0 overflow interrupt Priority bit Refer for priority level 0 PX0 External interrupt 0 Priority bit
37. ts nominal voltage Can also be set by software General purpose Flag 3 GFI Cleared by user for general purpose usage Set by user for general purpose usage General purpose Flag 2 GFO Cleared by user for general purpose usage Set by user for general purpose usage Power Down mode bit 1 PD Cleared by hardware when reset occurs Set to enter power down mode Idle mode bit 0 IDL Clear by hardware when interrupt or reset occurs Set to enter idle mode Reset Value 00X1 0000b Not bit addressable Rev C 15 January 2001 25 TS80C31X2 AMEL Sey r WIRELESS amp uC 7 Electrical Characteristics 7 1 Absolute Maximum Ratings Ambiant Temperature Under Bias C commercial 0 C to 70 C I industrial 40 C to 85 C Storage Temperature 65 C to 150 C Voltage on to Vss 0 5 Vto 7V Voltage on Vpp to Vss 0 5 V to 13 V Voltage Any Pin to Vss 0 5 V to Vcc 0 5 V Power Dissipation 1 wO NOTES 1 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions may affect device reliability 2 This value is based on the maximum allowable die temperature and the thermal resistance of the package
38. ut data set up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Table 25 AC Parameters for a Fix Clock V V L L X2 mode standard mode X2 mode standard mode 30 MHz 40 MHz 20 MHz 30 MHz 60 MHz equiv 40 MHz equiv Min Max i Min Max 200 300 Rev C 15 January 2001 37 TS80C31X2 Sey ons WIRELESS amp pC Table 26 AC Parameters for a Variable Clock derating formula Symbol Type Standard X2 Clock M V L Units Clock ns 50 ns 20 ns 0 ns 133 ns 7 5 8 Shift Register Timing Waveforms INSTRUCTION 0 2 3 4 5 6 7 8 ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI Figure 17 Shift Register Timing Waveforms Rev C 15 January 2001 ey WIRELESS amp uC AMEL TS80C31X2 7 5 9 External Clock Drive Characteristics XTAL1 Table 27 AC Parameters Symbol Parameter Min Max Units Oscillator Period 25 ns High Time 5 ns Cyclic ratio 2 mode 40 60 7 5 10 External Clock Drive Waveforms Figure 18 External Clock Drive Waveforms 7 5 11 AC Testing Input Output Waveforms 0 5 V cedo 0 2Vcc 0 9 INPUT OUTPUT jasy 0 2 0 1 Figure 19 AC Testing Input Output Waveforms AC inputs during testing are dr
39. wer down by either reset or external interrupt does not affect the internal RAM content NOTE If idle mode is activated with power down mode IDL and PD bits set the exit sequence is unchanged when execution is vectored to interrupt PD and IDL bits are cleared and idle mode is not entered 22 Rev C 15 January 2001 AMEL E WIRELESS amp pC Table 11 The state of ports during idle and power down modes TS80C31X2 Pi AUR Mode Dust ALE PSEN PORTO PORTI PORT2 PORT3 Memory Idle External 1 1 Floating Port Data Address Port Data Power Down External 0 0 Floating Port Data Port Data Port Data Rev C 15 January 2001 23 TS80C31X2 AIMEL WIRELESS amp pC 6 7 ONCE M Mode ON Chip Emulation The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without removing the circuit from the board The ONCE mode is invoked by driving certain pins of the TS80C31X2 the following sequence must be exercised Pull ALE low while the device is in reset RST high and PSEN is high e Hold ALE low as RST is deactivated While the TS80C31X2 is in ONCE mode an emulator or test CPU can be used to drive the circuit Table 26 shows the status of the port pins during ONCE mode Normal operation is restored when normal reset is applied Table 12 External Pin Status during ONCE Mode ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1 2 Weak pull up
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