intel 8XC198 handbook
Contents
1. Used to indicate that Ports 3 and 4 contain a command address PROG Programming Falling edge indicates valid data on PBUS and the beginning of programming Rising edge indicates end of programming PVAL Program Valid This signal indicates the success or failure of programming in the Auto Programming Mode A zero indicates successful programming Program Verification Used in Slave Programming and Auto CLB Programming Modes Signal is low after rising edge of PROG if the programming was not successful v lt m D gt 2 O Auto Increment Active low signal indicates that the auto increment mode is enabled Auto Increment will allow reading or writing of sequentiat EPROM locations without addr ss transactions across the PBUS for each read write PORTS 3 and 4 Address Command Data Bus Used to pass commands addresses and data to when programming and from slave mode 87C196KBs Used by chips in Auto Programming Mode to pass command addresses and data to slaves Also used in the Auto Programming Mode as a regular system bus to access external memory Should have pullups to Voc 15 a 4626175 0163681 BOS NN PRELIMINARY This Material Copyrighted By Its Respective Manufacturer intel 4 8XC198 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS NOTICE This data sheet contains preliminary infor mation on new products in production It is valid for the devices ind2. System Bus Timings 8XC198 ADDRES OUT ADDRESS OUT 272034 23 5 EH 4826175 397 WM En This Material Copyrighted By Its Respective Manufacturer 8XC198 intel READY Timings One Wait State TatrH 2Tosc Tkeov 2 Tavpv 2 Tose Co 25 l READ BUS ADDRESS 0UT TwuwH 2 F 2 Tosc BUS ADDRESS OUT X DATA OUT ADDRESS WRITE 272034 24 EXTERNAL CLOCK DRIVE Parameter Oscillator Frequency 12 MHz Oscillator Frequency 16 MHz Oscillator Period 12 MHz Oscillator Period 16 MHz High Time Low Time Rise Time Fall Time 272034 25 oscillator may encounter much as 100 pF load at XTAL1 when it starts up This is due to interaction between the amplifier and its feedback capacitance Once the external signai meets the Vi and Vin specifications the capacitance will not exceed 20 pF EN 4826175 Dlb3L547 PRELIMINARY This Material Copyrighted By Its Respective Manufacturer intel 8XC198 EXTERNAL CRYSTAL CONNECTIONS EXTERNAL CLOCK CONNECTIONS 87C198 EXTERNAL CLOCK INPUT clock driver 87C198 no connect Quartz Crystal or Ceramic Resonator 272034 32 272034 33 Keep oscillator components close to chip and use short direct traces to XTAL1 XTAL2 and Vss When using
3. B0C198 doesn t use any of the programming pins 3 64 EN 4826175 0163679 157 Tree This Material Copyrighted By Its Respective Manufacturer intel 8XC198 PIN DESCRIPTIONS Symbol Function Main supply voltage 5V The PLCC package has 5 Vss pins and the QFP package has 12 Vss pins All must be connected to digital ground s Reference voltage for the A D converter 5V is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function ANGND Reference ground for the A D converter Must be held at nominally the same potential as Vss Vpp Programming Voltage Also timing pin for the return from powerdown circuit i5 XTAL1 Input of the oscillator inverter and of the internal clock generator XTAL2 Output of the oscillator inverter Reset input to and open drain output from the chip Input low for at least 4 state times to reset the chip The subsequent low to high transition commences the 10 state Reset Sequence lt lt lt aa 2 INST Output high during an external memory read indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is activated only during external memory accesses and output low for a data fetch Input for memory select External Access EA equal to a TTL high caus
4. Serial Port Clock Falling Edge to Rising Edge BRR 8001H Output Data Hold after Clock Rising Edge 2 50 Output Data Valid after Glock Rising Edge Tove input Data Setup 1o Ciok Rng Ege TS Tax Input Data aftr GiookRsingEdge o WAVEFORM SERIAL PORT SHIFT REGISTER MODE SERIAL PORT WAVEFORM SHIFT REGISTER MODE 272034 31 EN 44826175 0163693 527 3 78 PRELIMINARY This Material Copyrighted By Its Respective Manufacturer intel FUNCTIONAL DEVIATIONS Devices marked with an E F have the following errata 1 HIGH SPEED INPUTS The High Speed Input HSI has three deviations from the specifications NOTE Events are defined as one or more pin tran sitions Entries are defined as the recording of one or more events A The resolution is nine states instead of eight states Events occurring on the same pin more frequently than once every nine states may be lost B A mismatch between the nine state HSI resolu tion and the eight state hardware timer causes one time tag value to be skipped every nine timer counts Events may receive a time tag one count later than expected C If the FIFO and Holding Register are empty the first event will transfer into the Holding Register leaving the FIFO empty again The next event that occurs will be the first event lo
5. o T2RST P2 4 AINC 15 4 7 T2CLK P2 3 C 272034 2 Figure 4 52 Pin PLCC Package NOTE The above pinout diagram applies to the OTP 87C198 device The OTP device uses all of the programming pins shown above The ROM 83C198 device only uses programming pins AINC PALE PMODE n and PROG The ROMIess B0C198 doesn t use any of the programming pins 22 YY EN 4526175 0163678 210 EM 3 63 This Material Copyrighted By Its Respective Manufacturer 8XC198 L TAD2 P3 2 AD1 P3 1 ADO P3 0 on U N N C N C N C N C ACH6 P0 6 PMODE 2 7 PMODE 3 N C 5 5 PMODE 1 ACHA PO 4 PMODE O NOTE AD3 P3 3 1 404 P3 4 J 05 3 5 2 AD7 P3 7 08 4 0 2 AD9 P4 1 AD10 P4 2 2 AD11 P4 3 14D12 P4 4 4D15 P4 5 AD14 P4 6 3 015 4 7 a o a INTEL 870198 80 PIN QFP TOP VIEW ro 51 0 510 0 RXD P2 1 PALE N C means No Connect do not connect these pins NOTE Figure 5 80 Pin QFP Package HSI 1 SID 1 P T2CLK P2 3 Vss READY T2RST P2 4 AINC N C WR PWM P2 5 N C HS0 1 HS0 0 HSO 5 HSI 3 SID 3 Vss HS0 4 HSI 2 SID 2 272034 4 The above pinout diagram applies to the OTP 87C198 device The OTP device uses all of the programming pins shown above The ROM 83C198 device only uses programming pins AINC PALE PMODE n and PROG The ROMIess
6. crystals C1 20 pF C2 20 pF When using ceramic resonators consult manufacturer for recom mended capacitor values NOTE Required if open collector TTL driver used Not need ed if CMOS driver is used AC TESTING INPUT OUTPUT WAVEFORMS FLOAT WAVEFORMS 2 4 2 0 2 0 Vi oapr9 20 Vou 0 20 V TIMING REFERENCE 5 Y s gt TEST POINTS CT LOAD 0 45 VLoAp 9 20 V 0 20 V 272034 26 272034 27 AC Testing inputs are driven at 2 4V for a Logic 1 and 0 45V for For Timing Purposes a Port Pin is no Longer Floating when a a Logic 0 Timing measurements are made at 2 0V for a Logic 200 mV change from Load Voltage Occurs and Begins to Float 1 and 0 8V for a Logic 0 when 200 mV change from the Loaded Vor VoL Level occurs 15 mA EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by for time The characters in a pair indicate a signal and its condition respectively Symbois represent the time between the two signal condition points Conditions Signals High A Address L Low D DATA Valid L ALE ADV X No Longer Valid Q DATA OUT Z Floating R RD W WR X XTAL1 Y READY PRELIMINARY 4426175 D153568 d This Material Copyrighted By Its Respective Manufacturer This Material Copyrighted 8XC198 10 BIT AID CHARACTERISTICS At a clock speed of 6 MHz or less the clock prescal er sho
7. A 13 mA 6 Typicals are based on a limited number of samples and are not guaranteed The values listed are at room temperature and Vngr 5V 60 log Max 50 Typical 40 lec mA idio Max 20 Idle Typical 10 9 4 MHz 8 MHz 12MHz 16 MHz loc 3 88 x FREQ 8 43 1 65 x FREQ 22 FREQUENCY 272034 22 Figure 8 Icc vs Frequency EN 44626175 0153543 b EN PRELIMINARY This Material Copyrighted By Its Respective Manufacturer intel AC CHARACTERISTICS 8XC198 Test Conditions Capacitive load on all pins 100 pF Rise and fall times 10 ns Fosc 12 16 MHz The system must meet these specifications to work with the 87C198 Address Valid to Ready Setup 2 Tosc 75 Non READY Time No upper limit READY Hold after ALE Low Tosc 15 2 Tosc 40 Address Valid to Input Data Valid TRLDV RD Active to Input Data Valid Tosc 55 Tosc 23 Tuus beter Data Hold after RD Inactive NOTES 1 If max is exceeded additional wait states will occur 2 When using wait states add 2 n where number of wait states PRELIMINARY NN 4826175 0163684 514 EXIIT 3 69 This Material Copyrighted By Its Respective Manufacturer 8XC198 AC CHARACTERISTICS Test Conditions Capacitive load on all pins 100 pF Rise and fa
8. C Low AINC Pulse Width PVER Hold after Low 5 AINC Low to PROG Low PROG High to PVER Low DC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Vpp Supply Current When Programming PRELIMINARY 4826175 0163690 18 EB is This Material Copyrighted By Its Respective Manufacturer 8XC198 intel EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE s ADDR COMMAND Y ADDR COMMAND TSHLL TLLAX Tove F lt PALE TLHPL PROG 272034 28 SLAVE PROGRAMMING MODE IN WORD DUMP OR DATA VERIFY MODE WITH AUTO INCREMENT RESET ADDR ADDR 2 i ADDR COMMAND VER BITS WD DUMP VER BITS WO DUMP TeLov 272034 29 3 76 EN 4426175 754 EN This Material Copyrighted By Its Respective Manufacturer i ntel 8XC198 SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM MODE WITH REPEATED PROG PULSE AND AUTO INCREMENT ADDR 2 EB 4826175 690 3 77 PRELIMINARY This Material Copyrighted By Its Respective Manufacturer 8XC198 intel CHARACTERISTICS SERIAL PORT SHIFT REGISTER MODE SERIAL PORT TIMING SHIFT REGISTER MODE a DNE to Rising Edge BRR 2 8002H Serial Port Glock Period B001
9. PROM device Port 0 PRELIMINARY gm 5 0163680 979 NR 3 65 This Material Copyrighted By Its Respective Manufacturer 8XC198 intel DESCRIPTIONS Continued Name and Function Port 2 Multi functional port All of its pins are shared with other functions in the 80C198 Ports 3 and 4 8 bit bidirectional O ports with open drain outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Available as only on the ROM and EPROM devices TxD The TxD pin is used for serial port transmission in Modes 1 2 and 3 In mode 0 the pin is used as the serial clock output Serial Port Receive pin used for serial port reception In mode 0 the pin functions as input or output data EXTINT A positive transition on the EXTINT pin will generate an external interrupt T2CLK The T2CLK pin is the Timer2 clock input or the serial port baud rate generator input T2RST A rising edge on the T2RST pin will reset Timer2 PWM The PWM output Programming Mode Select Determines the EPROM programming algorithm that is performed PMODE is sampled after a chip reset and should be static while the part is operating programming verification acknowledgement Slave ID Number Used to assign each slave pin of 4 to use for passing D gt Programming ALE Input Accepted by the 87C196KB when it is in Slave Programming
10. READY CONTROL MODE IRC 1 Loco LOC1 Jens LOCK MODE 272034 7 Figure 2 Memory Map WARNING Reserved memory locations must not be written or read The contents and or function of these locations may change with future revisions of the device Therefore a program that relies on one or more of thesa locations may not function properly WR BH 4826175 015357 384 5 This Material Copyrighted By Its Respective Manufacturer intel 8XC198 PACKAGING The 8XC198 is available in a 52 pin PLCC package and an 80 pin QFP package Contact your local sales office to determine the exact ordering code for the part desired Package Designators N 52 pin PLCC S 80 pin QFP Thermal Characteristics Package Type PLCC 40 C W QFP 70 C W 4C W All thermal impedance data is approximate for static air conditions at 1W of power dissipation Values will change depending on operating conditions and application See the Intel Packaging Handbook Order Number 240800 for a description of Intel s thermal impedance test methodology ALE ADV ACH7 P0 7 PMODE 5 o ACH6 6 2 ADO P3 0 AD1 P3 1 XTAL2 gt gt 5 5 1 8 ACH4 P0 4 PMODE 0 9 EXTINT P2 2 PROG C I RESET RXD P2 1 PALE E TOP VIEW TXD P2 0 PVER C 87C198 HSI 0 SID 0 C HSI 1 SID 1C 50 4 51 2 510 2 C 50 5 51 3 510 3 C
11. RESET and XTAL1 lo 200 pA Output High Voltage Standard Outputs MEUSE EN 4826175 0163682 741 dies This Material Copyrighted By Its Respective Manufacturer 8XC198 intel 2 DC CHARACTERISTICS Continued Symbol Description Active Mode Current in Reset XTAL1 16 MHz A D Converter Reference Current Vcc Vrer 5 5V hove Idle Mode Current Icca Active Mode Current XTAL1 3 5 MHz ipp Powerdown Mode Current Vpp Vrer 5 5V Pnsr Cs Pin Capacitance Any Pinto Vss TEST 1 0 MHz NOTES Notes apply to specifications 1 Standard Outputs include AD0 15 RD WR ALE INST HSO pins PWM P2 5 RESET Ports and 4 TXD P2 0 and in serial made 0 The Vox specification is not valid for RESET Ports and 4 are open drain outputs 2 Standard Inputs include HSI pins EA READY AXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 Maximum current per pin must be externally limited to the following values if is held above 0 45V is held below Vcc 0 7V lo on Output pins 10 mA on Standard Output pins 10 mA 4 Maximum current per bus pin data and control during normal operation is 3 2 mA 5 During normal non transient conditions the following total current limits apply HSO P2 0 RXD RESET 29 mA 26 mA P2 5 WR lot 13 mA 11 mA ADO AD15 lot 52 mA 52 mA RD ALE INST lou 13 m
12. aded into the empty FIFO If the first two events into an empty FIFO not counting the Holding Register occur coincident with each other both are recorded as one entry with one time tag If the second event occurs within 9 states after the first the events will be entered separately with time tags at least one count apart If the second event enters the FIFO coincident with the skipped time tag situ ation see B above the time tags will be at least two counts apart 2 CMPL with RO Using CMPL with register 0 can set incorrect flags Don t use register 0 with the compare long instruc tion Use another tong word register and set it equal to zero See Techbit 0692 PRELIMINARY This Material Copyrighted 8XC198 REVISION HISTORY This data sheet 272034 003 is valid for devices marked with an F or at the end of the top side tracking number Data sheets are changed as new device information becomes available Verify with your local Intel sales office that you have the latest version before finalizing a design or ordering devices The following differences exist between this data sheet and the previous version 002 1 This data sheet added the ROMless and ROM devices 80C198 and 830198 respectively 2 The description of the A D converter prescalar bit was improved mm 4826175 0163694 MA 215 By Its Respective Manufacturer
13. es memory accesses to locations 2000H through 3FFFH to be directed to on chip ROM EPROM equal to a TTL low causes accesses to these locations to be directed to off chip memory gt ADV Address Latch Enable or Address Valid output as selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive high at the end of the bus cycle ALE ADV is activated only during external memory accesses Read signal output to external memory RD is activated only during external memory reads Write output to external memory WR will go low for every external write READY Ready input to lengthen external memory cycles When the external memory is not being used READY has no effect Internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of CCR a HSI Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 and HSI 3 Two of them HSI 2 and HSI 3 are shared with the HSO Unit HSO Outputs from High Speed Output Unit Six HSO pins are available HSO 0 HSO 1 HSO 2 HSO 3 HSO 4 and HSO 5 Two of them HSO 4 and HSO 5 are shared with the HSI Unit 4 bit high impedance input only port These pins can be used as digital inputs and or as analog inputs to the on chip A D converter These pins set the Programming Mode on the E
14. i N80C 1987 0 0 PRELIMINARY 8XC198 COMMERCIAL EXPRESS CHMOS MICROCONTROLLER 8 Kbytes of OTPROM m 8 Kbytes of On Chip OTPROM or ROM m 16 MHz Standard m 232 Byte Register File m Full Dupiex Serial Port m Register to Register Architecture m High Speed 1 0 Subsystem 28 Interrupt Sources 16 Vectors m 16 Bit Timer m 1 75 us 16 x 16 Multiply 16 MHz m 16 Bit Counter m 3 0 us 32 16 Divide 16 MHz m Pulse Width Modulated Output m Powerdown and Idle Modes m Four 16 Bit Software Timers m 16 Bit Watchdog Timer m 10 Bit A D Converter with Sample Hold 8 Bit External Bus m Extended Temperature Available The 8XC198 family offers low cost entry into Intel s powerful MCS 96 16 bit microcontroller architecture Intel s CHMOS process provides a high performance processor along with low power consumption To further reduce power requirements the processor can be placed into Idle or Powerdown Mode The 8XC198 is the 8 bit bus version of the 8XC196KB The prefixes mean 80 ROMIess 83 ROM 87 OTP One Time Programmable The ROM and OTP are available in 8 Kbytes Bit byte word and some 32 bit operations are available on the 8XC198 With a 16 MHz oscillator a 16 bit addition takes 0 50 us and the instruction times average 0 37 p s to 1 1 p s in typical applications Four high speed capture inputs are provided to record times when events occur Six high speed outputs are available for pulse or waveform generation The high speed output can al
15. icated in the revision history The specifications are subject to change without notice Ambient Temperature gt WARNING Stressing the device beyond the Absolute 55 C to 125 Maximum Ratings may cause permanent damage Storage Temperature 65 to 150 C These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex Voltage on Vpp or EA to tended exposure beyond the Operating Conditions Vss or ANGND 0 3V to 13 0V may affect device reliability Voltage on Any Other Pin to Vss 0 5V to 7 0V Power Dissipation 1 1 5W NOTE 1 Power dissipation is based on package heat transfer lim itations not device power consumption OPERATING CONDITIONS All characteristics in this data sheet apply to these operating conditions unless otherwise noted Symo mm U T Ambient Temperature UnderBias o lt Vos DiaitalSuppiy Voltage 5 v Analog Supply Voltage ANGND and Vss should nominally at the same potential DC CHARACTERISTICS Symbol Description Test Conditions Vu o8 v Vit ViH Output Low Voltage lu Mu Input Leakage Current Std Inputs Logical 0 Input Current in Reset ALE RD INST NOTE 1 AII pins except
16. ll times 10 ns Fosc 12 16 MHz The 87C198 will meet these specifications Symbol FXTAL FXTAL Tosc Tosc TAVLL Description Frequency on XTAL1 16 MHz intel Notes Note 1 Note 1 MHz 1 FxrAL 12 MHz 1 FxrAL 16 MHz Ti HLH ALE Cycle Time ALE High Period Address Setup to ALE Falling Edge Address Hold after ALE Falling Edge TRHLH TRLAZ TLLWL RD Low Period RD Rising Edge to ALE Rising Edge RD Low to Address Float ALE Falling Edge to RD Falling Edge Tose 35 ALE Falling Edge to WR Falling Edge 16 286 ns Note 3 Tosco 20 Tosc 40 Tosc 25 Note 3 Note 2 ee Tosc 10 Data Stable to WR Rising Edge Tosc 23 ns 3 WR Low Period TWHLH TwHBx TRHAX NOTES Data Hold after WR Rising Edge WR Rising Edge to ALE Rising Edge INST Hold after WR Rising Edge INST Hold after ALE Rising Edge AD8 15 Hold after RD Rising Edge Tosc 15 Tosc 5 ns Notes Tosc 15 Tosc 10 ns Note 2 1 Testing performed at 3 5 MHz However the part is static by design and will typically operate below 1 Hz 2 Assuming back to back bus cycles 3 When using wait states add 2 n where n number of wait states 70 This Material Copyrighted EN u52b5175 0163685 450 NN PRELIMINARY By Its Respective Manufacturer intel
17. rescaler Off 8 Sampling Capacitor NOTES LSB as used here has value of approximately 5 mV Power Supply Rejection 6 o 1 Typical values expected for most devices at 25 C but are not tested or guaranteed 2 DC to 100 KHz 3 Multiplexer Break Before Make Guaranteed 4 Resistance from device pin through internal MUX to sample capacitor 3 74 EN 4826175 0163689 NNI PRELIMINARY By Its Respective Manufacturer intel 8XC198 EPROM SPECIFICATIONS EPROM PROGRAMMING OPERATING CONDITIONS NOTES 1 Vpp and Vngr should nominally be at the same voltage during programming 2 Vea and Vpp must never exceed the maximum voltage for any amount of time or the device may be damaged 3 Vss and ANGND should nominally be at the same voltage OV during programming AC EPROM PROGRAMMING CHARACTERISTICS Symbol Description Min Max Leu Reset High to Frat PACE 1100 Tun PALE PulseWidth Te Tau _Addressseuprme o Tua AddessHodTim so Tos Tum PAtLowtoPVERLw Tos Tosc Tove DataSetupTime o Tos Tx DaaHodTme 50 Tos massa s s Tru _ PROGHightoNextPALELow 10 Tos Ti PALEHightoPROGLow 20 Tos PROG High to Next PROG Low 120 PROG High to AIN
18. so generate four software timers or start an A D conversion Events can based on the timer or counter Also provided on chip are an A D converter serial port watchdog timer and a pulse width modulated output signal With the commercial standard temperature option operational characteristics are guaranteed over the tem perature range of 0 C to 70 the extended temperature range option operational characteristics are guaranteed over the temperature range of 40 to 85 C MCS 96 is a registered trademark of Intel Corporation October 1992 Order Number 272034 003 3 61 4426175 OLb3b7L 448 This Material Copyrighted By Its Respective Manufacturer 8XC198 in VREF ANGND FREQUENCY REFERENCE 8 KBYTES OTPROM ROM MEMORY CONTROLLER CONTROL SIGNALS A D CONVERTER SERIAL PORT ALTERNATE FUNCTIONS 272034 1 Figure 1 87C198 Block Diagram OFFFFH EXTERNAL MEMORY OR 4000H INTERNAL ROM EPROM OR EXTERNAL MEMORY 7 e s 32 1 o CHIP CONFIGURATION REGISTER POWERDOWN MODE ENABLE SET TO 0 RESERVED LOWER 8 INTERRUPT VECTORS PLUS 2 SPECIAL INTERRUPTS Figure 3 Chip Configuration 2018H PORT 3 AND PORT 4 EXTERNAL MEMORY OR INTERNAL MEMORY REGISTER FILE STACK POINTER RAM AND SFRS EXTERNAL PROGRAM CODE MEMORY SET TO 0 ADDRESS VALID STROBE SELECT ALE ADV IRC0 INTERNAL
19. uld be disabled This is accomplished by set ting 2 4 1 At higher frequencies greater than 6 MHz the clock prescaler should be turned on IOC2 4 0 to allow the comparator to settle The tabie below shows two different clock speeds and their corresponding A D conversion and sample times intel State times are calculated as follows state time TxTAL1 The converter is ratiometric so the absolute accura cy is directly dependent on the accuracy and stability of Yrer must be close to Vec since it supplies both the resistor ladder and the digital section of the converter See the MCS 96 A D Converter Quick Reference for definition of A D terms Example Sample and Conversion Times AID Clock Prescaler 10 2 4 0 ON IOC2 4 1 OFF A D CONVERTER SPECIFICATIONS Clock Speed States Sample Time Conversion Time at Clock Speed us Conversion Time States Sample Time at Clock Speed us Typical Minimum Maximum Units Notes Absolute Error Full Scale Error 0252050 Is Zero Offset Error 0 25 0 50 LSBs 1 5 25 3 LSBs Differential Non Linearity Error Channel to Channel Matching Repeatability 0 25 Temperature Coefficients Offset 0 009 Full Scale 0 009 Differential Non Linearity 0 009 Off Isolation Feedthrough Input Series Resistance DC Input Leakage Sample Time Prescaler On 15 P
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intel 8XC198 handbook