Home

intel 80C186EA/80C188EA/80L186EA/80L188EA handbook

1. CLKIN Frequency 1 Ms CLKIN Period AA 1 CLKIN High Time 12 oo 1 2 TeL CLKIN Low Time 12 1 2 Tor CLKIN Rise Time 1 8 1 3 Tor CLKIN Fall Time 1 8 1 3 OUTPUT CLOCK CLKIN to CLKOUT Delay 0 45 1 4 T CLKOUT Period 2 Tc 1 CLKOUT High Time 1 2 5 1 2 5 1 CLKOUT Low Time 2 5 2 5 1 CLKOUT Rise Time 1 12 1 5 CLKOUT Fall Time 1 12 1 5 OUTPUT DELAYS ALE LOCK 3 27 ns 1 4 6 7 53 0 LCS UCS 3 32 ns 1 4 PCS6 0 WR 6 8 REST 9 16 Tcov LOCK RESOUT HLDA TOOUT T1OUT gt RD WR MCS3 0 LCS UCS PCS6 0 INTA1 0 Io G 513 2 TcLova RFSH DEN 19 16 015 0 15 8 7 0 5 52 0 40 ns 146 TCHOF RD WR 27 27 ns 1 DT R LOCK 2 0 A19 16 TcLorF DEN AD15 0 15 8 AD7 0 27 27 ns 1 NOTES See AC Timing Waveforms for waveforms and definition Measured at for high time VIL for low time Only required to guarantee Maximum limits are bounded by and Specified for a 50 pF load see Figure 13 for capacitive derating information Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF See Figure 14 for rise and fall times Tcuov1 app
2. An 80C186EA 80L186EA with a STEPID value of 01H or 02H has the following known errata A device with a STEPID of 01H or 02H can be visually identi fied by noting the presence of an B or C alpha character next to the FPO number The FPO number location is shown in Figures 5 6 and 7 1 An internal condition with the interrupt controller can cause no acknowledge cycle on the INTA1 line in response to INT1 This errata only occurs when Interrupt 1 is configured in cascade mode and a higher priority interrupt exists This errata will not occur consistantly it is dependent on in terrupt timing An 80 186 801186 with a STEPID value of 03H has no known errata device with a STEPID of 03H can be visually identified by noting the presence of a D or E alpha character next to the number The FPO number location is shown in Fig ures 5 6 and 7 1 131 Powered by ICminer com Electronic Library Service CopyRight 2003
3. si NIS3H si NISIH 194e spoued 1 san220 L SALON 91 26 242 Spo 49d 100X79 f 110912 Sng 1813 03 NISJA NISIH 100534 1538 3501 N30 4 10 num ee Tee 0 5 0 0V 8 61 0 5107 91 95 617 757 gt 05 37 wan SON 10011710001 0 9538 521 san 1108195 2 Figure 16 Warm Reset Waveforms PRELIMINARY EN 4426175 0164973 1 116 ice CopyRight 2003 Library Serv 1c Electron Powered by ICminer com intel 80 186 80 188 801 186 801 188 BUS CYCLE WAVEFORMS Figures 17 through 23 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine the critical timing analysis needed for a given application CLKOUT RFSH A15 8 015 0 VALID 07 0 272432 17 NOTES 1 During the data phase of the bus cycle A19 S6 is driven high for a OMA or refresh cycle 2 Pin names in parentheses apply to the 80 188 Figure 17 Read Fetch and Refresh Cycle Waveform PRELIMIN
4. 1 89 TEST CONDITIONS 1 111 DIFFERENCES BETWEEN THE AC TIMING WAVEFORMS 1 111 BOR ANB THE Tun DERATING CURVES 1 114 Pinout Compatibility 1 89 Operating Modes 1 89 RESET 1 114 TTL CMOS Inputs 1 89 BUS CYCLE WAVEFORMS 1 117 Timing Specifications 1 89 EXECUTION TIMINGS 1 124 PACKAGE INFORMATION 1 90 Prefix Identification 1 90 INSTRUCTION SET SUMMARY 1145 Pin Descriptions 1 90 REVISION HISTORY 1 131 80 186 Pinout 1 96 ERRATA 1 131 PRELIMINARY 4426175 0161940 150 NE 1 83 Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 801 186 801 188 SIN TSIN 4044 1 SON 0 29 9553 LINN 71094403 123135 1V SS2d 503151939 71034405 543151924 7031405 583151939 14103 8 91 543 NOIINNILS3Q 119 02 43104 328005 19 05 0 7084405 1050 10011 508 1531 583161938 9 18 91 LINA 7031405 538338 7031409 LINN NOIL1n23X3 1 508 IVNYJINI 583151538 7081405 541151939 1081403 503151933 LNNOD 18 91 4311031403
5. Location ADO 64 ALE QSO 10 RESIN 55 UCS AD1 BHE RFSH RESOUT Lcs AD2 So CLKIN 50 51 OSCOUT 82 CLKOUT 42 AD5 76 RD OSMD TEST BUSY 43 AD6 78 WR QS1 PCSO 54 AD7 80 ARDY PCST 52 65 SRDY PCS2 51 ADS 9 67 DT R INT1 SELECT 50 AD10 A10 69 INT2 INTAO 49 AD11 A11 71 LOCK INT3 INTAT 48 AD12 A12 75 HOLD 47 AD13 A13 77 HLDA 57 AD14 A14 79 59 AD15 15 1 56 A16 3 58 A17 4 Power 61 A18 5 Name Location 60 A19 S6 6 Location 12 18 24 53 62 2 33 34 44 72 73 Pin names in parentheses apply to the 80C186EA 80L188EA 135 EN 4326175 0161955 NN PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 intel 80C186EA 80C 188EA 801 186 801 188EA Table 7 QFP EIAJ Package Location with Pin Names Location Location AD15 A15 ERROR DRQO Vss A16 N C A17 ADO A18 A8 A19 S6 AD1 BHE RFSH ADS A9 WR QS1 LOCK AD2 RD QSMD TEST BUSY AD10 A10 ALE QSO NMI INTO AD11 A11 Vss INT1 SELECT Vss AD4 N C INT2 INTAO AD12 A12 CLKIN INT3 INTA1 5 OSCOUT IRQ AD13 A13 RESOUT DT R AD6 CLKOUT PDTMR AD14 A14 ARDY DEN MCSO PEREQ NOTE Pin names in parentheses apply to the 186 80_188 PCSS A1 PCS6 A2 MCS3 NCS MCS 1 ERROR 3 Vec gt P aa
6. 54 A10 POTMR 55 402 DEN 56 5 49 MCSO PEREQ AD sc MCS1 ERROR 58 ani MCS2 C159 2 3 a8 MCS3 NCS o LI gt a PCS6 A2 PCS5 A1 O 272432 7 Figure 7 Shrink Quad Flat SQFP Pinout Diagram NOTES 1 XXXXXXXXD indicates the Intel FPO number 2 Pin names in parentheses apply to the 80C188EA PACKAGE THERMAL the ambient temperature can be calculated SPECIFICATIONS from c4 thermal resistance from the case to ambi ent with the following equation The 80C186EA 80L186EA is specified for operation when Tc the case temperature is within the range Ta X Oca of 0 to 85 C PLCC package or O C to 106 N QFP EIAJ package may be measured in Typical values for at various airflows are given environment to determine whether the processor is in Table 10 within the specified operating range The case tem perature must be measured at the center of the top P the maximum power consumption specified in surface watts is calculated by using the maximum ICC as tabulated in the DC specifications and Vcc of 5 5V Table 10 Thermal Resistance at Various Airflows in C Watt Airflow Linear ft min m sec 2 03 3 04 4 06 5 07 71 25 21 se 17 165 ea ru cu aca arr Pe 4826175 0161958 390 1 101 Powered by ICminer com Ele
7. EUM 0 905 EM all floating outputs driven to or ud all Units Notes mA V MHz 12 outputs loaded to 50 pF including CLKOUT and OSCOUT 2 Typical is calculated at 25 C with ail outputs loaded to 50 pF except CLKOUT and OSCOUT which are not loaded RY 4826175 0161962 81 PRELIMINA 1 105 Powered by ICminer com Electronic Library Service CopyRight 2003 186EA 80C 188EA 801 186 801 188 intel SPECIFICATIONS Characteristics 80C186EA25 80C 186EA20 80C 186EA13 Parameter Max INPUT CLOCK 25 MHz 12 CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time MCS3 0 LCS UCS 6 0 NCS RD WR BHE RFSH DEN LOCK RESOUT HLDA TOOUT T1OUT A19 16 LOCK 52 0 1 9 16 1 106 4826175 0161963 758 EB PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 ntel 5 80 186 80 188 801 186 801 188 SPECIFICATIONS Continued Characteristics 80C 186EA25 80C 186EA20 80C186EA 13 symbol Parameter Min Max Min Max Units Notes 25mHz02 SYNCHRONOUS INPUTS TEST
8. SB80C186EA 13 in PRELIMINARY 80 186 80 188 AND 80L186EA 80L188EA 16 BIT HIGH INTEGRATION EMBEDDED PROCESSORS m 80C186 Upgrade for Power Critical Applications m Fully Static Operation m True CMOS Inputs and Outputs m integrated Feature Set m Speed Versions Available 3V Static 186 CPU Core 13 MHz 80L186EA13 80L188EA13 Power Save Idle and Powerdown 8 MHz 80L186EAB BOL188EA8 Modes Direct Addressing Capability to Clock Generator 1 Mbyte Memory and 64 Kbyte 1 0 2 Independent DMA Channels 3 Programmable 16 Bit Timers m Supports 80C187 Numeric Coprocessor Dynamic RAM Refresh Contro Unit Interface 80C186EA only Programmable Memory and m Available in the Following Packages Peripheral Chip Select Logic 68 Pin Plastic Leaded Chip Carrier Programmable Wait State Generator PLCC Local Bus Controller 80 Pin EIAJ Quad Flat Pack QFP System Level Testing Support 80 Pin Shrink Quad Flat Pack SQFP high impedance rest Mode m Available in Extended Temperature Speed Versions Available 5V Range 40 C to 85 25 MHz 80C 186EA25 80C 188EA25 20 MHz 80C186EA20 80C 188EA20 13 MHz 80C186EA13 80C 188EA 13 The 80C186EA is a CHMOS high integration embedded microprocessor The 80C186EA includes all of the features of an Enhanced Mode 80C186 while adding the additional capabilities of Idle and Powerdown Modes Numerics
9. Timer 0 Count Timer Compare Reserved Reserved 54H Timer 0 Compare 56H Timer 0 Control Reserved Reserved 1EH Reserved 20H 22H Reserved End of Interrupt 24H Poll 26H Status 28H Interrupt Mask H AH Priority Mask rach Timer 2 Compare Reserved A2H LMCS A4H PACS A6H Timer 2 Control Reserved 30H Interrupt Status 70H Reserved Timer Control 72H Reserved tnt Control 74H Reserved Int Control INTO Control 78H Reserved INT1 Control INT2 Control INT3 Control 7CH Reserved 7EH Reserved DMAO Count Ci C C 2H 4H 6H 8H H H EH DOH D2 H D E H D4H D6H DAH DC EH OH 2H 4H 6H Figure 3 Peripheral Control Block Registers PRELIMINARY 4826175 0161944 8 Powered by ICminer com Reserved EAH Reserved Reserved ECH Reserved EEH Reserved Power Save 8 2H 4H 6H 8H H H EH F 1 87 Electronic Library Service CopyRight 2003 80 186 80 188 801 186 801188 Function 2
10. 11 26 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for ali memory transfers 1 128 Powered ICminer com 4826175 0161985 319 PRELIMINARY Electronic Library Service CopyRight 2003 Powered ICminer com Intel 80C 186EA 80C 188 80L186EA 80L188EA INSTRUCTION SET SUMMARY Continued Function CONTROL TRANSFER Continued Return from CALL Within segment Within seg adding immed ta SP Intersegment intersegment adding immediate to SP Jump on equal zero JL JNGE Jump on less not greater or equal JLE JNG Jump on less or equal not greater JB JMAE Jump on below not above equal Jump on below or equal not above MP JPE Jump on parity parity even Jump on overflow JS Jump on sign JNE JNZ Jump not equal not zero JNL JGE Jump on not less greater or equal JNLE JG Jump on not less or equal greater JNB JAE Jump on not below above or equal Jump not below equal above JNP JPO Jump on not par par odd Jump on not overflow 4 5 Jump on not sign JCXZ Jump CX zero LOOP Loop CX times LOOPZ LOOPE Loop while zerc equal LOOPNZ LOOPNE Loop while not zero equal INT Interrupt IType specified 3 INTO interrupt on overflo
11. AD7 0 272432 21 NOTE lt oO Q b 2 gt v 8 S a Figure 21 HOLD HLDA Waveform PRELIMINARY 4426175 0161974 189 1 121 lectronic Library Service CopyRight 2003 E Powered by ICminer com a 80C186EA 80C 188EA 801 186 801 188 ntel CLKOUT HOLD 19 16 lt 7 4 4 j RFSH ______ _ NEUE 121 PNE WR LOCK AD15 0 NE A15 8 AD7 0 elem PERPE CE i 1 i i A i 272432 22 NOTE 1 Pin names in parentheses apply to the 80C188EA Figure 22 DRAM Refresh Cycle During Hold Acknowledge EN 4826175 0161975 015 NNI 4 122 PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 801 186 801 188 CLKOUT e e lt N EE p KES Leto 4 Q 1 1 fe F pr c 5 a I e 8 gis 8 J m ea pm ze o 24 gt lt 5 1 4 f 4 1 14 Sg 35
12. Apa O 65 40 E1ucso PEREQ abit 66 39 EDEN ag 67 38 02 E1568 57 A10 apio 2 69 36 CI INT3 INTAI IRO 05 2 70 35 2 A11 40112371 lt 80 18 20 34 DI vec Yoo 472 See Note sp 00 473 32 1 5 04 74 51 INTO 12 012 75 aos 75 A13 AD13 77 28 Lock ape 78 27 A 14 014 79 26 HOLD 07 O 25 ABE 17 gt aigo 19 56 gt RFSH C wR os1C o E ALE oso C CLKIN ET oscour RESOUT EJ CLKOUT E NOTES 272432 6 1 The nine character alphanumeric code XXXXXXXXD underneath the product number is the Intel FPO number 2 Pin names in parentheses apply to the 80C186EA 80L188EA Figure 6 Quad Flat Pack EIAJ Pinout Diagram mar EE 4826175 510 NN Lud Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 801 186EA 80L188EA 1 AD1 3 AD2 6 ADS 8 AD4 12 ADS 14 AD6 16 AD7 18 8 8 2 ADS 9 5 10 10 7 AD11 11 9 12 12 13 13 13 15 AD14 14 17 15 15 19 A16 S3 21 17 54 22 18 85 23 A19 S6 24 NOTE Pin names in parentheses apply to the 80C186EA BOL188EA NOTE 1 ADO 2 AD6 A8 3 AD1 4 N C 5 9 A9 6 AD2 7 AD10 A10 8 AD
13. NOTE RESIN measured to CLKIN not CLKOUT Figure 11 Input Setup and Hold 1 112 4826175 0161969 176 PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 intel li 80C186EA 80C188EA 80L186EA 80L188EA CLKOUT 00 15 00 7 19 16 19 8 ov 272432 12 1 Toxor for write cycle followed by read cycle 2 Pin names in parentheses apply to tthe 80C188EA Figure 12 Relative Signal Waveform PRELIMINARY 4826175 0 998 1448 Powered ICminer com Electronic Library Service CopyRight 2003 Powered ICminer com 80C 186EA 80C 188 801 186 801 188 DERATING CURVES 5 25 C gt in 74 5 gt lt 5 5 2 272432 13 Figure 13 Typical Output Delay Variations Versus Load Capacitance RESET The processor performs a reset operation any time the RESIN pin is active The RESIN pin is actually synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power on state RESIN must be held active low in order to guarantee cor rect initialization of the processor Failure to pro vide RESIN while the device is powering up will result in unspecified operation of the device Figure 15 shows the correct reset sequence when first applying power to the processor An external
14. source Figure 2 shows the various operating modes of the oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide by two counter This counter is used to drive all internal phase clocks and the exter nal CLKOUT signal CLKOUT is a 5096 duty cycle processor clock and can be used to drive other sys tem components All AC timings are referenced to CLKOUT The following parameters are recommended when choosing a crystal Temperature Range Application Specific string move instructions that operate at full bus Equivalent Series Resistance 600 max bandwidth ten new instructions and static opera CO Shunt Capacitance of Crystal 7 0 pF max tion The Bus Interface Unit BIU is the same as that Load Capacitance 20 pF 2 pF found on the original 80C186 family products An Drive Level 2 mW independent internal bus is used to allow communi cation between the BIU and internal peripherals 4826175 0161942 T23 PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 80L186EA 80L188EA 272432 3 Crystal Connection NOTE External Clock Source BOC186EA 272432 4 B Clock Connection The L4C network is only required when using a third overtone crystal Figure 2 Clock Configurations 80C186EA PERIPHERAL ARCHITECTU
15. 00 ES 01 cs 10 ss 11 DS REG is assigned according to the following table 16 1 8 0 000 000 AL 001 CX 001 CL 010 DX 010 DL O11 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS seg ment register The physical addresses of the desti nation operands of the string primitive operations those addressed by the DI register are computed using the ES segment which may not be overridden 1 130 4826175 01619487 191 PRELIMINARY Electronic Library Service CopyRight 2003 intel REVISION HISTORY Intel B0C186EA 80L186EA devices are marked with a 9 character alphanumeric intel FPO number un derneath the product number This data sheet up date is valid for devices with an D or E as the ninth character in the FPO number as illustrated in Figure 5 for the 68 lead PLCC package Figure 6 for the 84 lead QFP EIAJ package and Figure 7 for the 80 lead SQFP device Such devices may also be identified by reading a value of 01H 02H from the STEPID register This data sheet replaces the following data sheets 272019 002 80C186EA 272020 002 80 188 272021 002 80L186EA 272022 002 80L188EA 272307 001 SB80C186EA SB80L186EA 272308 001 SB80C188EA SB80L138EA o 4402175 0161988 025 80 186 80 188 801 186 801 188
16. 80L186EA 80L188EA PDTMR PIN DELAY CALCULATION The PDTMH pin provides a delay between the as sertion of NMI and the enabling of the internal clocks when exiting Powerdown A delay is required only when using the on chip oscillator to allow the Crystal or resonator circuit time to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted i e a device reset during Pow erdown is similar to a cold reset and RESIN must remain activo until after tho oscillator has stabi lized To calculate the value of capacitor required to pro vide a desired delay use the equation 440 X t 5 25 C Where t desired delay in seconds Cpp capacitive load on PDTMR mi crofarads EXAMPLE To get a delay of 300 us a capacitor value of Cpp 440 x 300 x 10 6 0 132 pF is required Round up to standard available capaci tivo values NOTE The above equation applies to delay times greater than 10 us and will compute the TYPICAL tance needed to achieve the desired delay A delay variance of 50 or 25 can occur due to temperature voltage and device process ex tremes In general higher and or lower tem perature will decrease delay time while lower and or higher temperature will increase delay time Table 11 Device in Reset Device Idle 1 is calculated at
17. B0C186EA is object code compatible with the 80C186XL embedded processor The 80L186EA is the 3V version of the 80C186EA The 80L186EA is functionally identical to the 80C186EA embedded processor Current 80C186EA customers can easily upgrade their de signs to use the 80L186EA and benefit from the re duced power consumption inherent in 3V operation The feature set of the 80C186EA 80L186EA meets the needs of low power space critical applications Low power applications benefit from the static de sign of the CPU core and the integrated peripherals well as low voltage operation Minimum current consumption is achieved by providing a Powerdown Mode that halts operation of the device and freezes the clock circuits Peripheral design enhancements ensure that non initialized peripherals consume little Current Space critical applications benefit from the inte gration of commonly used system peripherals Two flexible DMA channels perform CPU independent data transfers A flexible chip select unit simplifies memory and peripheral interfacing The interrupt unit provides sources for up to 128 external interrupts and will prioritize these interrupts with those generat ed from the on chip peripherals Three general pur pose timer counters round out the feature set of the 80C186EA Figure 1 shows a block diagram of the 80C186EA 80C188EA The Execution Unit EU is an enhanced 8086 CPU core that includes dedicated hardware to speed up
18. Mode the 80C186EA interfaces directly with an 80C187 Numerics Coprocessor 272432 1 4426175 0161939 439 NH October 1995 1 82 Order Number 272432 003 Powered by ICminer com Electronic Library Service CopyRight 2003 intel 80C186EA 80C 188EA 801 186 801 188 186 8 188 AND 801 186 801 188 16 Bit High Integration Embedded Processor CONTENTS PAGE CONTENTS PAGE INTRODUCTION 1 85 PACKAGE THERMAL SPECIFICATIONS 1 101 B0C186EA CORE ARCHITECTURE 1 85 Bus Interface Unit 1 85 ELECTRICAL SPECIFICATIONS 1 102 Absolute Maximum Ratings Clock Generator 1 85 Recommended Connections 80C186EA PERIPHERAL ARCHITECTURE 1 86 DC SPECIFICATIONS Interrupt Control Unit 1 86 Icc versus Frequency and Voltage 1 105 Timer Counter Unit 1 86 PDTMR Pin Delay Calculation 1 105 DIREC OSE UR 188 SPECIFICATIONS 1 106 188 Characteristics 80C186EA20 13 1 106 Refresh Control Unit 1 88 AC Characteristics 80L186EA13 8 1 108 Power Management 1 88 Relative Timings 1 110 806187 Interface 80 186 Only 1 89 ONCE Test Mode
19. NMI INT3 0 1 01 ARDY TEST NMI INT3 0 T1 0IN ARDY Tous AD15 0 AD7 0 ARDY SRDY DRQ1 0 AD15 0 AD7 0 ARDY SRDY DRQ1 0 HOLD PEREQ ERROR 80 186 Only HOLD PEREQ ERROR 80C186EA Only Tous RESIN to CLKIN RESIN from CLKIN NOTES See AC Timing Waveforms for wavetorms and definition Measured at for high time Vi for low time Only required to guarantee Maximum limits are bounded by Tc and Specified for a 50 pF load see Figure 13 for capacitive derating information Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF Seo Figure 14 for rise and fall times 1 applies to RFSH LOCK and A19 16 only after a HOLD release applies to RD and WR only after a HOLD release Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 applies to RFSH and A19 16 only after HOLD release 12 Operating conditions for 25 MHz are 0 C to 70 C 5 0V 10 Pin names in parentheses apply to the 80C188EA 80L188EA pine PAR 5525175 DOLbl1H5u b94 NN 1 107 gt Powered by ICminer com Electronic Library Service CopyRight 2003 80C186EA 80C188EA 80L186EA 80L 188 ntel AC SPECIFICATIONS AC E EE Parameter KN CLOCK
20. and infor mation see the Intel Packaging Outlines and Dimen sions Guide Order Number 231369 With the extended temperature range operational characteristics are guaranteed over a temperature range corresponding to 40 to 85 C ambient Package types are identified by a two letter prefix to the part number The prefixes are listed in Table 1 Table 1 Prefix Identification Temperature Range Extended Extended Extended Commercial Commercial Commercial NOTE 1 The 25 MHz version is only available in commercial tem perature range corresponding to 0 to 70 C ambient Pin Descriptions Each pin or logical set of pins is described in Table 3 There are three columns for each entry in the Pin Description Table The Pin Name column contains a mnemonic that describes the pin function Negation of the signal name for example RESIN denotes a signal that is active low The Pin Type column contains two kinds of informa tion The first symbol indicates whether a pin is pow er P ground input only I output only or itd 4326175 0161947 505 NN intel input output Some pins have multiplexed functions for example A19 S6 Additional symbols indicate additional characteristics for each pin Table 3 lists all the possible symbols for this column The Input Type column indicates the type of input asynchronous or synchronous Asynchronous pins requir
21. are available for all memory and bus cycles whether they are generated by the CPU the DMA unit or the Refresh Control Unit Refresh Control Unit The Refresh Control Unit RCU automatically gen erates a periodic memory read bus cycle to keep dynamic or pseudo static memory refreshed A 9 bit counter controls the number of clocks between re fresh requests A 9 bit address generator is maintained by the RCU with the address presented on the 9 1 address lines during the refresh bus cycle Address bits A19 13 are programmable to allow the refresh ad dress block to be located on any 8 Kbyte boundary Power Management The 80 186 has three operational modes to trol the power consumption of the device They are Power Save Mode Idle Mode and Powerdown Mode Power Save Mode divides the processor clock by a programmable value to take advantage of the fact that current is linearly proportional to frequency An unmasked interrupt NMI or reset will cause the 80C186EA to exit Power Save Mode idle Mode freezes the clocks of the Execution Unit and the Bus Interface Unit at a logic zero state while all peripherals operate normaily Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator All internal registers hold their values provided is maintained Current consumption is reduced to tran sistor leakage only is EN 4426175 0161945 732 Powe
22. effective address calculations enhance execution speed for multiple bit shift and rotate in structions and for multiply and divide instructions 80 186 80 188 80L186EA 80L188EA 80C186EA CORE ARCHITECTURE Bus Interface Unit The 80C186EA core incorporates a bus controller that generates local bus control signals In addition it employs a HOLD HLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data for write operations in formation It is also responsible for reading data off the local bus during read operation SRDY and ARDY input pins are provided to extend a bus cycle beyond the minimum four states clocks The local bus controller also generates two control signals DEN and DT R when interfacing to exter nal transceiver chips This capability allows the addi tion of transceivers for simple buffering of the mulit plexed address data bus Clock Generator The processor provides an on chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divide by two counter and two low power operating modes The oscillator circuit is designed to be used with ei ther a parallel resonant fundamental or third over tone mode crystal network Alternatively the oscilla tor circuit may be driven from an external clock
23. ta data if w 1 3 4 3 4 B 16 bit m immediate from accumulator 0010110w d ISBB Subtract with borrow Reg memory and register to either 000110dw mod reg r m 3 10 3 10 11 daa dataitsw 01 4 16 4 16 immediate trom accumulator 0001110 data data ifw 1 3 4 3 4 8 16 bit IDEC Decrement immediate from register memory 100000sw legister memory 1111111w 4001 r m 3 15 3 15 Register 01001 reg 3 3 Ragister memory with register 0011101w mod reg r m 3 10 Register with register memory 0011100 3 10 Immediate with register memory 300000sw mod 111 r m data data ifsw 01 3 10 Immediate with accumulator 0011110w data data ifw 1 3 4 8 16 bit Change sign register memory 1111011w modO11 r m 3 10 AA ASCII adjust for add 8 IDAA Decimal adjust for add 4 AAS ASCI adjust for subtract 00111111 7 IDAS Decimal adjust for subtract 4 IMUL Multiply unsigned 1111011w mod 100 r m Register Byte 26 28 Register Word 35 37 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers 1728 4826175 0161983 54b PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 ntel d 80C186EA 80C 188EA 801 186 801 188 INSTRUCTION SET SUMMARY Continu
24. the pins become handshaking pins for the 80C187 The CoProcessor REQuest input signals that a data transfer is pending ERROR is an input which indicates that the previous numerics coprocessor operation resulted in an exception condition An interrupt Type 16 is generated when ERROR is sampled active at the beginning of a numerics operation Numerics Coprocessor Select is an output signal generated when the processor accesses the 80C187 Peripheral Chip Selects go active whenever the address of a memory or 1 0 bus cycle is within the address limitations programmed by the user H 1 H X These pins provide multiplexed function As additional Peripheral Chip Selects they go active whenever the address of a memory or bus cycle is within the address limitations by the user They may also be programmed to provide latched Address A2 1 signals Timer OUTput pins can be programmed to provide single clock or continuous waveform generation depending on the timer mode selected Timer INput is used either as clock or control signals depending on the timer mode selected DMA ReQuest is asserted by an external request when it is prepared for a DMA transfer Maskable INTerrupt input will cause a vector to a specific Type interrupt routine To allow interrupt expansion INTO and or INT1 can be used with INTAO and INTA1 to interface with an external slave contr
25. 0161980 837 AM lectronic Library Service CopyRight 2003 E Powered by ICminer com Powered ICminer com 80C 186EA 80C 188EA 801 186 801 188 80 186 80 188 EXECUTION TIMINGS A determination of program exeuction timing must consider the bus cycles necessary to prefetch in structions as well as the number of execution unit cycles necessary to execute instructions The fol lowing instruction timings represent the minimum execution time in clock cycle for each instruction The timings given are based on the following as sumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states bus HOLDs occur word data is located on even address bound aries 80 186 only All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address BN 4826175 0141981 273 ntel All instructions which involve memory accesses require one or two additional clocks above the mini mum timings shown due to the asynchronous hand shake between the bus interface unit BIU and exe cution unit With a 16 bit BIU the 80C186EA has sufficient bus performance to endure that an adequate number of prefetched bytes will reside in the queue 6 bytes most of the time Therefor
26. 0H Interrupt Vector 22H Specific 24H Reserved 26H Reserved 28H Interrupt Mask 2AH Priority Mask 2C In Service Interrupt Request Interrupt Status Interrupt Control I SNI 38 TMR1 Interrupt Control 3C Reserved 3E Reserved Figure 4 80C186EA Slave Mode Peripheral Control Block Registers DMA Control Unit The 80C186EA DMA Contol Unit provides two inde pendent high speed DMA channels Data transfers can occur between memory and space in any combination memory to memory memory to 1 0 to to memory Data can be trans ferred in bytes or words Transfers may pro ceed to or from either even or odd addresses but even aligned word transfers proceed at a faster rate Each data transfer consumes two bus cycles a mini mum of eight clocks one cycle to fetch data and the other to store data The chip select ready logic may be programmed to point to the memory or space subject to DMA transfers in order to provide hardware chip select lines OMA cycles run at higher priority than general processor execution cycles intel Chip Select Unit The 80C186EA Chip Select Unit integrates logic which provides up to 13 programmable chip selects to access both memories and peripherals In addi tion each chip select can be programmed to auto matically terminate a bus cycle independent of the condition of the SRDY and ARDY input pins The chip select lines
27. 11111000 2 11110101 2 11111001 2 11111100 2 11111101 2 11111010 2 11111011 2 11110100 2 10011011 6 11110000 2 10010000 3 Powered ICminer com TTT LLL are opcode to processor extension Shaded areas indicate instructions not available 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers The Effective Address EA of the memory operand is computed according to the mod and r m fields ifmod 11thenr mis treated as a REG field ifmod O0then DISP 0 disp low and disp high are absent ifmod 01 then DISP disp low sign ex tended to 16 bits disp high is absent ifmod 10then DISP disp high disp low ifr m 000 then EA SI DISP if r m 001 then EA DI DISP if r m 010then EA SI DISP if r m 011then EA DISP if r m 100 then EA SI DISP ifr m 101 then EA 01 DISP ifr m 110 then EA BP DISP 111 then EA DISP DISP follows 2nd byte of instruction before data if required except if mod 00 110 then EA disp high disp low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenev er appropriate Segment Override Prefix 0 0 1 reg 1 reg is assigned according to the following Segment reg Register
28. 19083311 9033 43151934 INNOD 8331515935 14009 5831 INN 01 193135 LANI 10001 OVINI ZLNI 89 61 9s eiv 0 10 91y 0 610 YOIH 31 8 3148 9 503151933 1430935 32V3d31NI 508 583151939 7031403 LINN IN3H39VNVM nlad WOLVH3N19 100538 32072 NIS38 1109580 NINID 10212 IX INI CLNI ht 2003 ig PRELIMINARY CopyR 1ce Library Servi 1c lectron E 5 5 5 x o 9 a lt e lt o o 3 S iz E EH 4826175 016194 097 NE lt lt ul Q o 5 5 8 5 Q0 H 5 o S 2 E NOTE Powered by ICminer com intel INTRODUCTION Unless specifically noted all references to the 80C186EA apply to the 80 188 80L186EA and 80L188EA References to pins that differ between the 80C186EA 80L186EA and the 80C188EA 80L188EA are given in parentheses The L in the part number denotes low voltage operation Physi cally and functionally the and devices are identical The 80 186 is the second product in a new gen eration of low power high integration microproces Sors It enhances the existing 80C186XL family by offering new features and operating modes The
29. 26175 0161949 355 PRELIMINARY Electronic Library Service CopyRight 2003 18 16 19 56 16 A19 A8 ALE QSO NOTE 80C186EA 80C 188EA 801 186 801 188 Table 3 Pin Descriptions Continued H Z R Z P X These pins provide multiplexed Address during the address phase of the bus cycle Address bits 16 through 19 are presented on these pins and can be latched using ALE A18 16 are driven to a logic 0 during the data phase of the bus cycle On the 8 bit bus versions 15 8 provide valid address information for the entire bus cycle Also during the data phase 56 is driven to a logic 0 to indicate a CPU initiated bus cycle or logic 1 to indicate a DMA initiated bus cycle or a refresh cycle Bus cycle Status are encoded on these pins to provide bus transaction information 82 0 are encoded as follows 50 Bus Cycle Initiated Interrupt Acknowledge Read I O Write Processor HALT Queue Instruction Fetch Read Memory Write Memory Passive no bus activity Address Latch Enable output is used to strobe address 1 oo o o 9 0 0 0 0 information into a transparent type latch during the address queue status information along with 051 Byte High Enable output to indicate that the bus cycle in bus BHE and have the following logical encoding Ao Encoding For 80C186EA 80L186EA Only Even Byte Transfer Odd Byte Transfer On 80C188EA 80L188EA RFS
30. 3 9 AD11 A11 10 11 Voc 12 AD4 13 AD12 A12 14 ADS 15 AD13 A13 16 AD6 17 AD14 A14 18 19 AD15 A15 20 Table 8 SQFP Pin Functions with Package Location Processor Controi RESIN Bus Control ALE QSO BHE RFSH RESOUT 50 CLKIN 32 OSCOUT 33 CLKOUT 36 TEST BUSY 46 NMI 47 INTO 48 INT1 SELECT 49 INT2 INTAO 52 INT3 INTAT 53 Table 9 SQFP Pin Locations with Pin Names A16 S3 Vss 17 54 HLDA 23 A18 S5 HOLD 24 A19 S6 SRDY 25 N C LOCK 26 BHE RFSH TEST BUSY 27 WR QS1 NMI 28 RD QSMD INTO INT1 SELECT Voc ALE QSO Voc INT2 INTAO INT3 INTA1 5 MCS1 ERROR MCS2 MCS3 NPS Pin names in parentheses apply to the 80 186 801 188 1 100 EN 4826175 0161457 454 PRELIMINARY Powered ICminer com Electronic Library Service CopyRight 2003 intel 80C186EA 80C188EA 80L186EA 80L188EA cLkouT RESOUT oscout Vss RD QSMD WR aS1 3 18 56 1417 3 416 3 43 29 28 2 24 Veg 3 KLOA 42 195 4015 15 HOLO 43 1 07 sroy 44 17 3 014 A14 tock 45 16 9 ave TEST BUSY 15 E 015 15 E 47 14 aps 48 15 012 12 SELECT 49 123 04 186 20 XXXXXXXXD See Note INT2 INTAO 52 INTS INTAT IRO L 53
31. 80 186 13 80 188 13 100 pA Output Pin Capacitance 0 15 Tr 1 MHz Note 4 Cin Input Pin Capacitance 0 15 pF 1 MHz NOTES 1 RD QSMD UCS LCS MCSO PEREQ MCS1 ERROR COCK and TEST BUSY have internal pullups that are only acti vated during RESET Loading these pins above ip 275 will cause the processor to enter alternate modes of operation 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and with all outputs loaded as specified in the AC Test Conditions and with the device in RESET RESIN held low RESET is worst case for loc 4 Output capacitance is the capacitive load of a floating output pin 5 Operating conditions for 25 MHz are 0 C to 70 5 0V 1096 PRELIMINARY 4326175 T49 1 103 Powered by ICminer com Electronic Library Service CopyRight 2003 80C186EA 80C188EA 801 186 801 188 intel DC SPECIFICATIONS 801 186 801 188 Voc Supply Voltage I 2 7 5 5 V VIL Input Low Voltage for All Pins 0 5 0 3 Vcc Input High Voltage for All Pins 0 7 Voc Vcc 0 5 V VoL Output Low Voltage 0 45 V 1 6 mA min 5 IP Output High Voltage Voc 0 5 1 mA min Input Hysterisis on RESIN 0 30 lies Input Leakage Current except 10 BA OV
32. AH with flags ISAHF Store AH into flags PUSHF Push flags POPE Pop tage Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers PRELIMINARY 4826175 0461982 m qas Powered by ICminer com Electronic Library Service CopyRight 2003 80C186EA 80C188EA 801 186 801 188 n INSTRUCTION SET SUMMARY Continued 80C186EA 80C188EA Clock Clock Comments Cycles Cycies Function DATA TRANSFER Continued ISEGMENT Segment Override 00101110 2 00110110 2 00111110 2 00100110 2 RITHMETIC DD Add eg mernory with register to either o00000dw modreg r m 3 10 mod 000 ane ane immediate to accumulator 0000010w data data ii w 1 3 4 3 4 B 16 bit Immediate to register memory 100000sw DC Add with carry Rag memory with register to either 000100dw mod reg r m 3 10 3 10 Immediate to register memory 100000sw 10 data if sw 01 4 16 4 16 Immediate to accurnulator 0001010 data ifw 1 3 4 3 4 8 16 bit ING Increment Register memary 1111111 mod000 3 15 3 15 Register 91000 reg a 3 SUB Subtract Heg memory and register to either 001010dw mod reg r m 8 10 3 10 Immediate from register memory 100000sw 101 r m data data ifs 01 4 16 4 16
33. ARY NE 4626175 0161974 533 1 117 Powered by ICminer com Electronic Library Service CopyRight 2003 80C186EA 80C188EA 80L186EA 80L188EA intel CLKOUT BHE RFSH A15 8 AD15 0 AD7 0 MCS3 0 PCS6 0 LCS UCS 272432 18 1 During the data phase of the bus cycle 9 56 is driven high for DMA cycle 2 Pin names in parentheses apply to the 80C188EA Figure 18 Write Cycle Waveform tee 48261475 47T am PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 m intel 80C186EA 80C188EA 80L186EA 80L188EA i i i 19 16 15 8 INVALID NOTE D 1 i 1 4 AD15 0 01 0 INVALID NOTE 272432 19 NOTES 1 The processor drives these pins to 0 during Idle and Powerdown Modes 2 Pin names in parentheses apply to the 80C188EA Figure 19 Halt Cycle Waveform EH 4826175 01 147 30 NN 1 119 Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 801 186 801 188 272432 20 2 Pin names in parentheses apply to the 80C188EA 1 INTA occurs one clock later in Slav NOTES Figure 20 INTA Cycle Waveform PRELIMINARY EN 4826175 016197 242 NH 1 120 lectronic Library Service CopyRight 2003 E Powered by ICminer com 80 186 80 188 80L186EA 80L 188EA AD15 0 A15 8
34. CLKOUT and synchronous o falling CLKOUT ARDY or SRDY must be active to terminate any processor bus cycle unless they are ignored due to correct programming of the Chip Select Unit Synchronous is an input to signal for the end of a bus cycle ARDY or SRDY must be active to terminate any processor bus cycle unless they are ignored due to correct programming of the Chip Select Unit Data ENable output to control the enable of bidirectional transceivers when buffering a system DEN is active only when data is to be transferred on the bus Data Transmit Receive output controls the direction of a bi directional buffer in a buffered system DT R is only available on the package and the SQFP package LOCK output indicates that the bus cycle in progress is not to be interrupted The processor will not service other bus requests such as HOLD while is active This pin is configured as a weakly held high input while RESIN is active and must not be driven low HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instruction boundaries not conditioned by a LOCK prefix DT R R Z P X LOCK 2 R WH P 1 R 0 0 UCS 1 LCS R 1 P 1 NOTE HoLD Acknowledge output to indicate that the processor has relinquished c
35. Eee Sins Powered by ICminer com Electronic Library Service CopyRight 2003 intel lec VERSUS FREQUENCY AND VOLTAGE The current consumption of the processor is essentially composed of two components Ipp and lccs Ipp is the quiescent current that represents internal device leakage and is measured with all inputs or floating outputs at GND or Vcc no clock applied to the device is equal to the Powerdown current and is typically less than 50 pA lccs is the switching current used to charge and discharge parasitic device capacitance when chang ing logic levels Since lccs is typically much greater than lpp can often be ignored when calculating lec lccs is related to the voltage and frequency at which the device is operating It is given by the formula V x x Cpev X f V X f Where V Device operating voltage Device capacitance Device operating frequency lccs Device current Power Measuring Cpey on a device like the 80C186EA would be difficult Instead is calculated using the above formula by measuring Icc at a known and frequency see Table 11 Using this val Icc be calculated at any voltage and fre quency within the specified operating range EXAMPLE Calculate the typical lcc when operating at 20 MHz 4 8V loc Ices 4 8 X 0 515 X 20 49 mA 80 186 80 188
36. H is asserted low to indicate a Refresh bus cycle ReaD output signals that the accessed memory or I O device pin has an alternate function As QSMD it enables Queue Status Mode when grounded Queue Status Mode the about processor instruction queue interaction Queue Operation First Opcode Byte Fetched from the Queue Subsequent Byte Fetched from the Queue phase of the bus cycle Queue Status Mode QSO provides progress is transferring data over the upper half of the data 0 0 Word Transfer 0 1 1 0 1 1 Refresh Operation must drive data information onto the data bus Upon reset this ALE QS0 and WR QS1 pins provide the following information No Queue Operation Empty the Queue Pin names in parentheses apply to the 80C188EA and 80L188EA PRELIMINARY NN 4826175 0161950 Powered ICminer com Electronic Library Service CopyRight 2003 80C 186EA 80C 188EA 801 186 801 188 intel Table 3 Pin Descriptions Continued input Output DL Type States H Z R Z P 1 N gt s lt lt X 6 0 m 52 ZNN Description WRite output signals that data available on the data bus are to be written into the accessed memory or 1 device In Queue Status Mode 051 provides queue status information along with 050 Asychronous ReaDY is an input to signal for the end of a bus cycle ARDY is asynchronous on rising
37. M ub n 28 24 52 4 em 83 4 25 5 NE d S ao kaso ad gt E 08 Purus s Le Seo ma sebo 5 ag 2M deem Sx i A gt gt gt 4 9 mele hs pss 985 ed uineam xUE aoe Fara ys soi E 218582 lt lt bL 4 F P PETS 2 gee Less s A G ETO 5 lt 2 PM unc e BES a _ 2 f 0 4 T gt 2 25037 gt lt Sc o 44 sip ul err Sede SC 2 gt x G VN OK Sos be Fa 19 95458 HIE S e zw 5 8 m 52 2 2 5 25 n gg 5 gt a me uo o oO u 2 55 o SS 290 0 5 z z 55858 5 Sy iy lt gt 2cong lt Z N eo Figure 23 Ready Waveform 1 123 4626175
38. RE The 80 186 has integrated several common sys tem peripherals with a CPU core to create a com pact yet powerful system The integrated peripher als are designed to be flexible and provide logical interconnections between supporting units e g the interrupt control unit supports interrupt requests from the timer counters or DMA channels The list of integrated peripherals include 4 Input Interrupt Control Unit 3 Channel Timer Counter Unit 2 Channel DMA Unit 13 Output Chip Select Unit Refresh Control Unit Power Management logic The registers associated with each integrated peri heral are contained within a 128 x 16 register file called the Peripheral Control Block PCB The PCB can be located in either memory space any 256 byte address boundary Figure 3 provides a list of the registers associated with the PCB when the processor s Interrupt Control Unit is in Master Mode In Slave Mode the defini tions of some registers change Figure 4 provides register definitions specific to Slave Mode Interrupt Control Unit The 80C186EA can receive interrupts from a num ber of sources both internal and external The Inter rupt Control Unit ICU serves to merge these re quests on a priority basis for individual service by the CPU Each interrupt source can be independent ly masked by the Interrupt Control Unit or all inter rupts can be globally masked by the CPU Internal interrupt so
39. Voc INT1 SELECT AD15 A15 AD7 AD14 A14 06 013 13 5 AD12 12 AD4 Voc AD11 A11 ADS AD10 A10 AD2 ADS A9 AD1 ADS A8 ADO TEST BUSY LOCK SRDY HOLD HLDA NOTE Pin names in parentheses apply to the 80C186EA 80L188EA C RD OSMD J ALE Qso 16 1 17 L A 8 19 56 RFSH ss CLKIN RESOUT CLKOUT C ARDY 415 015 N80C186EA20 XXXXXXXXD See Nate TOP pi N gt 5 55 111 wo 5 2 Pin names in parentheses apply to the 80C186EA BOL18BEA Figure 5 68 Lead PLCC Pinout Diagram PRELIMINARY 4826175 O141954 745 M 4 97 Powered by ICminer com MCSO PEREQ 7 MCS1 ERROR MC53 NCS 1 The nine character alphanumeric code XXXXXXXXD underneath the product number is the Intel FPO number 80C 186EA 80C 188 80L186EA 80L188EA Location Name 52 1 S2 ARDY CLKOUT RESOUT OSCOUT CLKIN Vss ALE QSO RD OSMD WR QS1 BHE RFSH A19 S6 A18 A17 A16 272432 5 Electronic Library Service CopyRight 2003 80C186EA 80C188EA 801 186 801 188 intel 5 Table 6 EIAJ Pin Names with Package Location Address Data Bus Bus Control Location Location Location
40. clock connected to CLKIN must not exceed the threshold being applied to the processor This is nor mally not a problem if the clock driver is supplied with the same that supplies processor When attaching a crystal to the device RESIN must remain active until both Voc and CLKOUT are stable the length of time is application specific and de pends on the startup characteristics of the crystal circuit The RESIN pin is designed to operate cor rectly using an RC reset circuit but the designer 1 114 4426175 0161971 424 P c gt lt 59 25 C 272432 14 Figure 14 Typical Rise and Fall Variations Versus Load Capacitance must ensure that the ramp time for is not so long that RESIN is never really sampled at a logic low level when reaches minimum operating conditions Figure 16 shows the timing sequence when RESIN is applied after is stable and the device has been operating Note that a reset will terminate all activity and return the processor to a known operat ing state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately note that most control signals will be driven to their inactive state first before floating While RESIN is active signals RD QSMD UCS LCS MCSO PEREQ MCS1 ERROR LOCK and TEST BUSY are configured as inputs and weakly held high by internal pullup transistor
41. ctronic Library Service CopyRight 2003 186EA 80C 188EA 801 186 801 188 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature 65 C to 150 C Case Temperature under Bias 65 C to 150 Supply Voltage with Respect ION SS yau ritu e ex UE Ta 0 5V to 6 5 Voltage on Other Pins with Respect lo Ves 0 5V to Voc 0 5V Recommended Connections Power and ground connections must be made to multiple and Vss pins Every 80C186EA based circuit board should contain separate power Voc and ground Vss planes All Vcc and Vss pins must be connected to the appropriate plane Pins identi fied as must not be connected in the system Decoupling capacitors should be placed near the processor The value and type of decoupling capac 1 102 intel NOTICE This data sheet contains preliminary infor mation on new products in production It is valid for the devices indicated in the revision history The Specifications are subject to change without notice WARNING Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage These are stress ratings only Operation beyond the Operating Conditions is not recommended and ex tended exposure beyond the Operating Conditions may affect device reliability itors is application and board layout dependent The processor can cause transient power surges when it
42. e actual program exeuc tion time will not be substanially greater than that derived from adding the instruction timings shown The 80C188EA 8 bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue 4 bytes much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown PRELIMINARY Electronic Library Service CopyRight 2003 intel 80 186 80 188 801 186 801188 INSTRUCTION SET SUMMARY BOC ISGEA 80 188 IDATA TRANSFER Move Register to Register Memory 1000100w mod reg Register memory to register Immediate to register momory Immediate to register data Memory to accumulator 1010001 Accumulator to memory Register memory to segment register 10001110 mod 0 reg jegment register to register memory 10001100 mod 0 reg r m IPUSH Push egment register XCHG Exchange Register memory with register 1000011w mod reg r m Register with accumulator Input from Fixed port ss10010w pon ariable port OUT Output to Fixed port 17100116 pot ariable port IXLAT Translate byte to AL LEA Load EA to register ILDS Load pointer to DS mod 11 ILES Load pointer to ES mod e11 Load
43. e that setup and hold times be met only in order to guarantee recognition at a particular clock edge Synchronous pins require that setup and hold times be met to guarantee proper operation For example missing the setup or hold time for the SRDY pin a synchronous input will re sult in a system failure or lockup Input pins may also be edge or level sensitive The possible character istics for input pins are S E S L A E and A L The Output States column indicates the output state as a function of the device operating mode Output states are dependent upon the current activi ty of the processor There are four operational states that are different from regular operation bus hold reset Idle Mode and Powerdown Mode Ap propriate characteristics for these states are also in dicated in this column with the legend for all possi bie characteristics in Table 2 The Pin Description column contains a text de scription of each pin As an example consider AD15 0 1 signifies the pins are bidirectional S L signifies that the input function is synchronous and level sensitive H Z signifies that as outputs the pins are high imped ance upon acknowledgement of bus hold R Z sig nifies that the pins float during reset P X signifies that the pins retain their states during Powerdown Mode PRELIMINARY Electronic Library Service CopyRight 2003 ntel 80 186 80 188 80L186EA 80L188EA Table 2 Pin Descr
44. ed 80C188EA Function Clock Comments Cycles ARITHMETIC Continued IMUL Integer multiply signed 1111013w mod101 r m egister Byte Register Word adjust for multiply AAD ASCI adjust for divide BW Convert byte to word WD Convert word to double word 1101000w mod TTT r m TM tuc TTT Instruction 000 ROL 001 ROR 010 RCL 011 100 SHL SAL 101 SHR 111 SAR IReg memory and register to either 001000 Immediate to register memory 1000000w mod100 4 1 Immediate to accumulator 0010010w data 8 16 bit EST And function to flags no result Register memory and register Immediate data and register memory mod 0 0 0 data if t Immediate data and accumuiator data it w 1 8 16 bit and register to either immediate to register memory 001 data if w 1 immediate to accumulator data data if w 1 8 16 bit Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers For word operations add 4 clock cycles for all memory transfers PRELIMINARY mm 4326175 0161984 482 1 127 Powered by ICminer com Electronic Library Service CopyRight 2003 80C 186EA 80C188EA 80L186EA 80L188EA INSTRUCTION SET SUMMARY Continued Function ILOGIC Continued Exclusive or Reg memory and register to either Immediate to
45. egular opera tion all 80C186EA features including those of the Enhanced Mode 80C186 are present except for the interface to the 80C187 Numerics Mode disables the three chip select pins and reconfigures them for connection to the 80C187 TTL vs CMOS Inputs The inputs of the 80C186EA are rated for CMOS switching levels for improved noise immunity but the 80C186XL inputs are rated for TTL switching levels In particular the 80C186EA requires a minimum of 3 5V to recognize a logic one while the 80C186XL requires a minimum of only 1 9V assuming 5 operation The solution is to drive the 80C186EA with true CMOS devices such as those from the HC and AC logic families or to use pullup resistors where the added current draw is not a problem Timing Specifications 80C186EA timing relationships are expressed in a simplified format over the 80C186XL The AC per formance of an 80 186 at a specified frequency will be very close to that of an 80C186XL at the same frequency Check the timings applicable to your design prior to replacing the 80C186XL Electronic Library Service CopyRight 2003 Powered ICminer com 80C 186EA 80C 188EA 80L186EA 80L188EA PACKAGE INFORMATION This section describes the pins pinouts and thermal characteristics for the 80C186EA in the Plastic Leaded Chip Carrier PLCC package Shrink Quad Flat Pack SQFP and Quad Flat Pack QFP pack age For complete package specifications
46. iption Nomenclature Power Pin Apply Vcc Voltage Ground Connect to 55 Input Only Pin Output Only Pin Input Output Pin Synchronous Edge Sensitive Synchronous Level Sensitive Asynchronous Edge Sensitive Asynchronous Level Sensitive Output Driven to during Bus Hold Output Driven to Vgg during Bus Hold Output Floats during Bus Hold Output Remains Active during Bus Hold Output Retains Current State during Bus Hold Output Weakly Held at Vcc during Reset Output Driven to Vcc during Reset Output Driven to Vss during Reset Output Floats during Reset Output Remains Active during Reset Output Retains Current State during Reset Output Driven to Vcc during Idle Mode Output Driven to Ygs during Idle Mode Output Floats during Idle Mode Output Remains Active during Idle Mode Output Retains Current State during Idle Mode Output Driven to Vcc during Powerdown Mode Output Driven to Vss during Powerdown Mode Output Floats during Powerdown Mode Output Remains Active during Powerdown Mode Output Retains Current State during Powerdown Mode _ 4426175 016948 uu MH 1 91 Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 801 186 801 188 intel Pin Pin input Name Type Type Vcc Table 3 Pin Descriptions Output States Description POWER connections consist of six pins which m
47. lies to RFSH LOCK and A19 16 only after a HOLD release TcHove applies to RD and WR only after a HOLD release Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 11 TcHovs applies to RFSH and A19 16 only after a HOLD release 12 Pin names in parentheses apply to the 80 188 801 188 t 1106 EE 48261075 1 1 5 520 NN PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 intel 80C186EA 80C188EA 80L186EA 80L 188EA AC SPECIFICATIONS AC Characteristics 80L 186EA 13 80L 186EA8 Parameter SYNCHRONOUS INPUTS Tenis TEST NMI INT3 0 T1 0IN ARDY TEST NMI INT3 0 T1 0IN ARDY AD15 0 AD7 0 ARDY SRDY DRQ1 0 Er HOLD RESIN from CLKIN NOTES See AC Timing Waveforms for waveforms and definition Measured at Viu for high time for low time Only required to guarantee Icc Maximum limits are bounded by Tc and Specified for a 50 pF load see Figure 13 for capacitive derating information Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF See Figure 14 for rise and fall times TcHovi applies to RFSH LOCK and 19 16 only after a HOLD release applies to RD and WR only after HOLD release Setup and Hold are required to guarantee recognition 10 Setup and Hold a
48. lt lt RD OSMD UCS LCS MCS0 PEREQ MCS1 LOCK and TEST lite Input Leakage Current 275 uA 0 7 RD QSMD UCS LCS 50 Note 1 MCS1 LOCK and TEST ___ toL Output Leakage Current 0 45 lt Vout lt 10 pA gt Note 2 lccs Supply Current RESET 5 5V 80L186EA 13 65 mA Note 3 80L186EA 8 40 mA Note 3 lcca Supply Current RESET 2 7V Is 80L186EA 13 34 mA Note 3 80L186EA 8 20 mA Note 3 lips Supply Current Idle 5 5V 80L186EA 13 46 mA 80L186EA 8 28 mA __ lips Supply Current Idle 2 7V 80L186EA 13 24 mA 80L186EA 8 14 mA T 1205 Supply Current Powerdown 5 5V 80L1B6EA 13 100 801 186 8 100 Supply Current Powerdown 2 7V 1 80L186EA 13 50 pA 801 186 8 50 pA Output Pin Capacitance 0 15 pF Tr 1 MHz Note 4 CIN input Pin Capacitance 0 15 pF 1MHz 5 1 RD QSMD UCS LCS MCS0 51 LOCK TEST have internal pullups that are only activated during RESET Loading these pins above 275 pA will cause the processor to enter alternate modes of operation 2 Output pins are floated using HOLD or ONCE Mode 3 Measured at worst case temperature and with all outputs loaded as specified in the AC Test Conditions and with the device in RESET RESIN held low 4 Output capacitance is the capacitive load of a floating output pin 1104 BH 9826175 016196 985 PRELIMINARY
49. n Tables 8 and 9 list the 80C186EA B0C188EA pin names with package location for the 80 pin Shrink Quad Flat Pack SQFP component Figure 7 depicts the complete 80C186EA 80C188EA SQFP as viewed from the top side of the component 1 con tacts facing down Table 4 PLCC Pin Names with Package Location A19 S6 9 43 Pin names in parentheses apply to the 80C188EA 80L188EA 1 96 Bus Control Processor Control Location Name Location Location Name Location ADO ALE QSO RESIN 065 34 ADI 15 BHE RFSH 64 RESOUT 57 LCS 33 AD2 13 50 52 CLKIN 59 MCSO PEREQ 38 AD3 11 ST 53 OSCOUT 58 MCS1 ERROR 37 AD4 8 52 54 CLKOUT 56 MCS2 36 ADI 5 RD GSMD 62 TEST BUSY 47 MCS3 NCS 35 es 5 WR QS1 63 PDTMR 40 POSO 25 AD7 2 ABB 55 PCS1 27 ADS 8 16 46 55 28 9 A9 14 id INTO 45 PCS 29 AD10 A10 12 DEN 39 INT1 SELECT 44 PESA 30 AD11 A11 10 LOCK 48 INT2 INTAO 42 1 21 AD12 A12 7 HOLD 50 INT3 INTA1 4i PCS6 A2 32 AD13 A13 5 HLDA 51 IRQ TOOUT 22 AD14 14 3 20 AD15 15 1 23 16 68 21 17 67 18 A18 66 26 60 10 4426175 0161953 409 NM PRELIMINARY Electronic Library Service CopyRight 2003 Table 5 PLCC Package Location with Pin Names me _ MCS3 NCS MCS2 MCS1 ERROR MCSO PEREQ DEN PDTMR INT3 INTA1 IRQ INT2 INTAO
50. n The following sections describe differences in pinout operating modes and AC and DC specifications to keep in mind Pinout Compatibility The 80C186EA requires a pin to time the processor s exit from Powerdown Mode The original pin arrangement for the 80C186XL in the PLCC package did not have any spare leads to use for PDTMR so the DT H pin was sacrificed The ar rangement of all the other leads in the 68 lead PLCC is identical between the 80C186XL the 80C186EA DT R may be synthesized by latching the S1 status output Therefore upgrading a PLCC 80C186XL to PLCC 80 186 is straightforward 80C186EA 80C188EA 80L186EA 80L188EA The 80 lead QFP EIAJ pinouts are different be tween the 80C186XL and the 80 186 In addition to the PDTMR pin the 80C186EA has more power and ground pins and the overall arrangement of pins was shifted A new circuit board layout for the 80C186EA is required Operating Modes The 80C186XL has two operating modes Compati ble and Enhanced Compatible Mode is a pin to pin replacement for the NMOS 80186 except for nu merics coprocessing In Enhanced Mode the proc essor has a Refresh Control Unit the Power Save feature and an interface to the 80C187 Numerics Coprocessor The MCSO MCS1 and MCS3 pins change their functions to constitute handshaking pins for the 80C187 The 80 186 allows all non 80C187 users to use all the MGS pins for chip selects In r
51. n active The rising edge low to high transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location OFFFFOH H 0 RESet OUTput that indicates the processor is currently in the reset state RESOUT will remain active as long as RESIN remains P O active When tied to the TEST BUSY pin RESOUT forces the 80C186EA into Numerics Mode P 1 after an exit from power down before resuming normal operation The duration of time required will depend on the startup characteristics of the crystal oscillator Non Maskable Interrupt input causes a Type 2 interrupt to be serviced by the CPU NMI is latched internally TEST BUSY is sampled upon reset to determine whether the 80C186EA is to enter Numerics Mode In regular operation the pin is TEST TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active low In Numerics Mode the pin is BUSY BUSY notifies the 80C186EA of 80C187 Numerics Coprocessor activity These pins provide a multiplexed Address and Data bus During the address phase of the bus cycle address bits 0 through 15 0 through 7 on the 8 bit bus versions are presented on the bus and can be latched using ALE 8 or 16 bit data information is transferred during the data phase of the bus cycle Pin names in parentheses apply to the 80C188EA and 80L188EA 1 92 Powered by ICminer com 48
52. o RESIN Rising T ns 3 NOTES 1 Assumes equal loading on both pins 2 Can be extended using wait states 3 Not tested 4 Not applicable to latched A2 1 These signals change only on falling T4 5 For write cycle followed by read cycle 6 Operating conditions for 25 MHz are 0 C to 70 5 0V 10 1 110 Powered by ICminer com 4826175 01615947 3T3 EN PRELIMINARY Electronic Library Service CopyRight 2003 80 186 80 188 80L186EA 80L188EA AC TEST CONDITIONS OUTPUT PIN The AC specifications are tested with the 50 pF load shown in Figure 8 See the Derating Curves section to see how timings vary with load capacitance 272432 8 50 pF for all signals Specifications are measured at the 2 crossing point unless otherwise specified See AC Timing Figure 8 AC Test Load Waveforms for AC specification definitions test pins and illustrations AC TIMING WAVEFORMS CLKOUT 272432 9 Figure 9 Input and Output Clock Waveform PRELIMINARY 4826175 0161568 23T Ms Powered by ICminer com Electronic Library Service CopyRight 2003 80C186EA 80C 188EA 80L186EA 80L188EA intel 50 CLKOUT 507 VALID FLOAT NOTE 272432 10 NOTE 20 lt Float lt 80 0v I YALID N NW MIN Vec ov 0v 272432 11
53. oller INT1 becomes SELECT when the ICU is configured for Slave Mode These pins provide multiplexed functions As inputs they provide a maskable INTerrupt that will cause the CPU to vector to a specific Type interrupt routine As outputs each is programmatically controlied to provide an INTerrupt Acknowledge handshake signal to allow interrupt expansion INT3 INTA1 becomes IRQ when the ICU is configured for Slave Mode INT2 INTAO INT3 INTA1 IRQ VO AELOD 2 Pin names parentheses apply to the 80C188EA and 80 188 No Connect For compatibility with future products do not connect to these pins 4826175 0161952 472 MN 1 95 Powered by ICminer com Electronic Library Service CopyRight 2003 Powered ICminer com 80C 186EA 80C 188EA 80L186EA 80L188EA 80 186 PINOUT Tables 4 and 5 list the 80C186EA pin names with package location for the 68 pin Plastic Leaded Chip Carrier PLCC component Figure 9 depicts the complete 80C186EA 80L186EA pinout PLCC pack age as viewed from the top side of the component i e contacts facing down Tables 6 and 7 list the 80C186EA pin names with package location for the 80 pin Quad Flat Pack EIAJ component Figure 6 depicts the complete intel 80C186EA 80C188EA QFP package viewed from the top side of the component i e con tacts facing dow
54. ontrol of the local bus When HLDA is asserted the processor will or has floated its data bus and control signals allowing another bus master to drive the signals directly Upper Chip Select will go active whenever the address of a memory or bus cycle is within the address limitations programmed by the user After reset UCS is configured to be active for memory accesses between OFFCOOH and OFFFFFH During a processor reset UCS and LCS are used to enable ONCE Mode Lower Chip Select will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user LCS is inactive after a reset During a processor reset UCS and LCS are used to enable ONCE Mode Pin names in parentheses apply to the 80C188EA and 801 188 94 4826175 0161951 T36 NM PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 intel E 186EA 80C188EA 80L186EA 80L188EA Table 3 Pin Descriptions Continued Pin Pin Input Name Type MCSO PEREQ MCS1 ERROR MCS2 MCS3 NCS PCS5 A1 PCS6 A2 Description These pins provide a multiplexed function If enabled these pins normally comprise block of Mid Range Chip Select outputs which will go active whenever the address of a memory bus cycle is within the address limitations programmed by the user In Numerics Mode 80 186 only three of
55. re required for proper operation 11 applies to RFSH and 19 16 only after a HOLD release 12 Pin names in parentheses apply to the 80C188EA 80L188EA 525275 ub NN 1 109 Powered by ICminer com Electronic Library Service CopyRight 2003 80 186 80 188 801 186 80 188 AC SPECIFICATIONS Continued Relative Timings 80C 186EA25 20 13 80L186EA 13 8 Symbol Parameter Min Max Unit Notes RELATIVE TIMINGS E ALE Rising to ALE Falling 15 ns TAVLL Address Valid to ALE Falling ns TPLLL Chip Selects Valid to ALE Falling ns 1 TLLAX Address Hold from ALE Falling ns ALE Falling to WR Falling ns 1 ALE Falling to RD Falling ns 1 TRHLH RD Rising to ALE Rising 6T 10 ns 1 TWHLH WR Rising to ALE Rising WT 10 ns 1 Address Float to RD Falling 0 ns TRLRH RD Falling to RD Rising 2 5 ns 2 TWLWH WR Falling to WR Rising 2 T 5 ns T 2 RD Rising to Address Active 15 ns TwHDX Output Data Hold after WR Rising ns Twupex WR Rising to DEN Rising 10 TRHPH RD Rising to Chip Select Rising 10 ns TPHPL CS Inactive to CS Active 10 ns 1 DEN Inactive to DT R Low 0 ns 5 ONCE 065 LCS Active to RESIN Rising ns 3 ONCE 005 LCS t
56. red by ICminer com Electronic Library Service CopyRight 2003 Powered ICminer com intel 80C 187 Interface 80C 186EA Only The 80 187 Numerics Coprocessor may be used to extend the 80C186EA instruction set to include floating point and advanced integer instructions Connecting the 80C186EA RESOUT and TEST BUSY pins to the 800187 enables Numerics Mode operation In Numerics Mode three of the four Mid Range Chip Select MCS pins become handshaking pins for the interface The exchange of data and control information proceeds through four dedicated ports an 80C187 is not present the 80 186 config ures itself for regular operation at reset NOTE The 80C187 is not specified for 3V operation and therefore does not interface directly to the 80L186EA ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system the 80C186EA has a test mode available which forces all output and input output pins to be placed in the high impedance state ONCE stands for ON Circuit Emulation The ONCE mode is selected by forcing the UCS and LCS pins LOW 0 during a processor reset these pins are weakly held to a HIGH 1 level while RESIN is active DIFFERENCES BETWEEN THE 80C186XL AND THE 80C186EA The 80C186EA is intended as a direct functional up grade for 80C186XL designs many cases it will be possible to replace an existing 80C186XL with little or no hardware redesig
57. register memory immediate to accumulator Invert register memory ISTRING MANIPULATION IMOVS Move byte word Compare byte word AS Scan byte word 1005 Load byte wd to AL AX ISTOS Store byte wd from AL AX IMOVS Move string Compare string AS Scan string LODS Load string STOS Store string ALL Call Direct within segment Register memory indirect within segment Direct intersegment Indirect intersegment MP Unconditional jump hort long irect within segment Register memory indirect within segment Direct intersegment Indirect intersegment Repeated by count in CX REP REPE REPZ REPNE REPNZ 80 186 Clock Cycles 80 188 Cycles Format 001100dw mod reg 3 10 1000000w mod 110 data dataitw 4 16 0011010w data 8 4 1111011w 10 r m 3 10 1010010 14 14 1010011 22 1010110 12 12 8 16 bit s n aran 5 22 5 22n 6 9 6 9n 11101000 5 11111111 modo 10 r m 13 19 10011010 segment offset 23 segment selector 11111111 11 r m 11101011 disp ow 14 mod 11 36 11101001 disp low disp high 14 11111111 100 11 17 11101010 segment offset 14 11111111 mod 10 1 r m
58. s Forcing UCS and LCS low selects ONCE Mode Forcing QSMD low selects Queue Status Mode Forcing TEST BUSY high at reset and low four clocks later enables Numerics Mode Forcing LOCK low is prohibited and results in unspecified operation PRELIMINARY Electronic Library Service CopyRight 2003 91 26222 4 4 4 80 186 80 188 80L186EA 80L188EA 1104124 Sng 15314 O UDIH NISJA Niy 13 26 NIS38 914245 NINII 52 552556550666 SKK PESEE 82 sindino 914846 pue 22 v3881209 eui Aldde sesayjuesed seureu Z perduues SI NIS3H 194e N 412 1 11990 uoneziuoJuouAs 10012 L SALON 31v VOIH SON 11011710001 10 79 Figure 15 Powerup Reset Waveforms PRELIMINARY mm 4826175 OlblH7 2 750 1 115 CopyRight 2003 ice Library Servi ic Electron Powered by ICminer com 80 186 80 188 801 186 801 188 73881208 01 Aidde seseuueJed ui Z Papaye eq 10 1 9x 19 usul s si NISIH spoued Om 20 YBIY NONITO si 110412 alum
59. s output buffers transition particularly when con nected to large capacitive loads Always connect any unused input pins to an appro priate signal level In particular unused interrupt pins NMI INT3 0 should be connected to Vss to avoid unwanted interrupts Leave any unused output pin or any N C pin unconnected BH 9825175 0162959 227 Games Electronic Library Service CopyRight 2003 Powered by ICminer com intel A 80C186EA 80C188bEA 80L186EA 80L 188EA DC SPECIFICATIONS 80C186EA 80C188bEA Symbol Parameter Min Max Units Conditions Vcc Supply Voltage 4 5 5 5 v ViL Input Low Voltage for Pins os VH Input High Voltage for All Pins VoL Output Low Voltage lor 3 mA min Output High Voltage Vcc 0 5 Input Leakage Current except 10 m 1 RD QSMD UCS LCS MCSO PEREQ MCS1 ERROR LOCK and TEST BUSY lice Input Leakage Current 275 pA Vin 0 7 RD QSMD UCS LCS 50 MCS1 ERROR LOCK and TEST BUSY lo Output Leakage Current loc Supply Current Cold RESET 80C186EA25 80C188EA25 80C186EA20 80C188EA20 80C186EA13 80C188EA13 lip Supply Current In Idle Mode 80C186EA25 80C188EA25 90 mA Note 5 80C186EA20 80C188EA20 70 mA 80C186EA13 80C188bEA13 46 mA Supply Current In Powerdown Mode 80 186 25 80 188 25 100 Note 5 80 186 20 80 188 20 100 pA
60. urces include the Timers and DMA channels External interrupt sources come from the four input pins INT3 0 The NMI interrupt pin is not controlled by the ICU and is passed direct ly to the CPU Although the timers only have one request input to the ICU separate vector types are generated to service individual interrupts within the Timer Unit Timer Counter Unit The 80C186EA Timer Counter Unit TCU provides three 16 bit programmable timers Two of these are highly flexible and are connected to external pins for control or clocking third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non repeti tive waveforms generate timed interrupts etc 4426175 01613943 1 86 PRELIMINARY Powered by ICminer com Electronic Library Service CopyRight 2003 80C186EA 80C 188EA 801 186 801 188 Reserved PCB Offset Src Lo DMAO Src Hi DMAO Dest Lo Function Feud Function Function Reserved 40H Reserved Reserved Reserved 42H Reserved Reserved 44H Reserved Reserved Reserved 46H Reserved Reserved 48H Reserved Reserved Dest Hi Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
61. ust be shorted externally to a board plane Vss G GROUND connections consist of five pins which must be shorted externally to Vss board plane OSCOUT CLocK INput is an input for an external clock An external oscillator operating at two times the required processor operating frequency can be connected to CLKIN For crystal operation CLKIN along with OSCOUT are the crystal connections to an internal Pierce oscillator OSCillator OUTput is only used when using a crystal to generate the external clock OSCOUT along with CLKIN are the crystal connections to an internal Pierce oscillator This pin is not to be used as 2X clock output for non crystal applications i e this pin is N C for non crystal applications OSCOUT does not float in ONCE mode CLKOUT RESOUT I TEST BUSY 1 A E TEST NOTE A L H WH Power Down TiMeR pin normally connected to an external R Z capacitor that determines the amount of time the processor waits CLocK OUTput provides a timing reference for inputs and outputs of the processor and is one half the input clock CLKIN frequency CLKOUT has a 50 duty cycle and transistions every falling edge of CLKIN RESet IN causes the processor to immediately terminate any bus cycle in progress and assume an initialized state All pins will be driven to a known state and RESOUT will also be drive
62. w IRET Interrupt return Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Format 11000010 11001011 11001010 01110100 21111100 asp 01111111 disp 01110011 01110001 disp 1111001 ase 11001101 type 80 186 Clock Cycles 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 47 45 48 4 28 80 188 Cycles 20 22 30 33 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 47 45 48 4 28 Clock cycles shown for byte transfers word operations add 4 clock cycles for memory transfers 4826175 0161986 255 NH Electronic Library Service CopyRight 2003 JMP not taken JMP taken LOOP not taken LOOP taken if INT taken if INT not taken 1 129 80 186 80 188 801 186 801 188 INSTRUCTION SET SUMMARY Continued Functlon PROCESSOR CONTROL LC Clear carry Complement carry TC Set carry LD Clear direction Set diraction Clear interrupt Set interrupt Halt LOCK Bus lock prefix No Operation 80C 186EA Clock cycles 80 188 Clock Cycles Format Comments

intel 80C186EA/80C188EA/80L186EA/80L188EA handbook

Contents

Download Pdf Manuals

Related Search

Related Contents