FAIRCHILD FST32245 handbook
Contents
1. zero output impedance 7V for tpz Figures 1 2 7V for tpiz Figures Vi V OPEN for tpz Vi Vi 1 2 Capacitance Note 7 Parameter Conditions Control Pin Input Capacitance 5 0V Input Output Capacitance OE 5 0V Note 7 T4 425 C f 1 MHz Capacitance is characterized but not tested AC Loading and Waveforms VI FROM OUTPUT UNDER RD TEST CL Note Input driven by 50 Q source terminated in 50 Q Note C includes load and stray capacitance Note Input PRR 1 0 MHz tw 500 ns FIGURE 1 AC Test Circuit tr 2 5ns SWITCH INPUT 10 GND tPHL OUTPUT VoH OUTPUT 1 5V lez J m V VoL OH VoH 0 3V FIGURE 2 AC Waveforms 3 www fairchildsemi com Sv cce lSd FST32245 Preliminary Physical Dimensions inches millimeters unless otherwise noted 0 496 0 512 12 598 13 005 0 394 0 419 10 008 10 643 LEAD NO 1 1 7 IDENT Y 0 010 wax 0 254 9291 10 299 7 391 7 595 0 010 0 029 0 093 D 104 0 254 0 737 09 2 362 2 642 8 MAX TYP 0 004 0 012 ALL LEADS 0 102 0 305 Eos RH ere ni EN SEATING EE A PLANE 0 009 0 013 0 016 0 050 Tae a 0 050 e a 0014 0 020 pyp 0 229 0 330 ALL LEAD TIPS l 700408 1270j 1 270 0 356 0 508 TYP ALL LEADS TYP ALL LEADS TYP eH 0 008 Typ 0 203 M20B REV F 20 Lead Small Outline Integrat2. O O FST 32243 1 Preliminary EESTI June 2001 FAIRCHILD Revised June 2001 S SEMICONDUCTOR TM FST32245 Octal Bus Switch with 250 Series Resistor in Outputs Preliminary General Description Features The Fairchild Switch FST32245 provides 8 bits of high E 250 switch connection between two ports speed CMOS TTL compatible bus switching in a standard E Minimal propagation delay through the switch 245 pin out The low On Resistance of the switch allows inputs to be connected to outputs without adding propaga tion delay or generating additional ground bounce noise W Zero bounce in flow through mode The device is organized as an 8 bit switch When OE is B Control inputs compatible with TTL level LOW the switch is ON and Port A is connected to Port B When OE is HIGH the switch is OPEN and a high imped ance state exists between the two ports The FST32245 has an equivalent 25Q series resistors to reduce signal reflection noise eliminating the need for external terminating resistors Blow loc Ordering Code Order Number Package Description FST32245WM 20 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide FST32245QSC MQA20 20 Lead Quarter Size Outline Package QSOP JEDEC MO 137 0 150 Wide FST32245MTC MTC20 20 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Log
3. diode current ratings are observed Note 3 Unused control inputs must be held HIGH or LOW They may not float DC Electrical Characteristics T TA 40 Cto4857C 40 C to 85 C Symbol Parameter V Pu LINE Conditions i ES 4 Vik Clamp Diode Voltage Diode Voltage pod ly 18 mA I Input Leakage Current 55 d 0 M 0 lt Vy 5 5V Ron Switch On Resistance e a REOS EUN Vin OV lin 64 mA C E E E Vin 24V y T5MA loc Quiescent Quiescent Supply Current Current BA Vin Vcc or GND lour 0 A lec Increase in e Spey Curent per Input LX 5 ei input at 3 4V Other inputs at Voc or GND Note 4 Typical values are at Voc 5 0V and T4 25 C Note 5 Measured by the voltage drop between A and B pins at the indicated current through the switch On Resistance is determined by the lower of the voltages on the two A or B pins www fairchildsemi com 2 Preliminary Figure t ns Vi OPEN Figures 1 2 AC Electrical Characteristics TA 40 C to 85 C C 50pF RU RD 5000 Symbol Parameter Vec 4 5 5 5V Vcc 4 0V teu PLH Propagation Delay Bus to Bus 1 25 1 25 Note 6 tpHz tpLz Output Disable Time 1 0 5 7 OPEN for lpuz Note 6 This parameter is guaranteed by design but is not tested The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance when driven by an ideal voltage the source
4. does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com A1euiuaag SINGING ur 10 SIS9Y seus UGZ YUM YOUMS sng E190 SrZc 1SJ
5. ed Circuit SOIC JEDEC MS 013 0 300 Wide Package Number M20B 0 341 0 003 0 040 0 005 20 19 0 152 0 003 TOP 0 154 0 003 BOT 0 256 0 005 0 050 40 005 0 030 0 002 0 057 0 002 0 026 t 0 002 ro X 0 015 0 010 0 007 P Lo 5 TYP 5026 0 002 TYP J 0 006 0 002 TYP SEATING PLANE 0 010 0 002 TYP 20 Lead Quarter Size Outline Package QSOP JEDEC MO 137 0 150 Wide Package Number MQA20 M0A20 REV A www fairchildsemi com 4 Preliminary Physical Dimensions inches millimeters unless otherwise noted Continued isi 4 420 1 i ary 42 o2 CtB A 0 65 l ALL LEAD TIPS PIN 1 IDENT LAND PATTERN RECOMMENDATION A Lo 1 c SEE DETAIL A ies ALL LEAD TIPS 0 9918 10 2 wee 9 0 10 Ja BO c 0 09 0 20 0 1 0 05 EON DIMENSIONS ARE IN MILLIMETERS NOTES A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION AC REF NOTE 6 DATE 7 93 B DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS D DIMENSIONS AND TOLERANCES PER ANSI Y 14 5M 1982 SEATING PLANE R0 09 MIN MTC20RevD1 DETAIL A 20 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 4 4mm Wide Package Number MTC20 Technology Description The Fairchild Switch family derives from and embodies Fairchild s proven switch technology used for several years in its 74LVX3L384 FST3384 bus switch product Fairchild
6. ic Diagram Connection Diagram e o o o o Az 9 11 By A1euiuaag sindino ui 10 SISAY SAS UGZ YUM YMS sng E190 SrZc 1SJ 1 2 3 4 5 6 7 8 9 OE 19 k O Pin To me Lm rmm 08 888 2001 Fairchild Semiconductor Corporation DS500473 www fairchildsemi com FST32245 Preliminary Absolute Maximum Ratingsvnote 1 Recommended Operating Supply Voltage Vcc 0 5V to 7 0V Conditions Note 3 DC Switch Voltage Vs 0 5V to 7 0V Power Supply Operating Vcc 4 0V to 5 5V DC Input Voltage Vn Note 2 0 5V to 7 0V Input Voltage Vi OV to 5 5V DC Input Diode Current lik Vin lt OV 50 mA Output Voltage Voyrt OV to 5 5V DC Output lour Sink Current 128 mA Input Rise and Fall Time t tj DC Vcc GND Current lIcc lawp 100 mA Switch Control Input 0 ns V to 5 ns V Storage Temperature Range Tstq 65 C to 150 C Switch I O 0 ns V to DC Free Air Operating Temperature TA 40 C to 85 C Note 1 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating The Recommended Operating Conditions table will define the conditions for actual device operation Note 2 The input and output negative voltage ratings may be exceeded if the input and output
Download Pdf Manuals
Related Search
FAIRCHILD FST32245 handbook