FAIRCHILD FST16862 handbook
Contents
1. com c989L1S4 FST16862 AC Electrical Characteristics 40 C to 85 C 50pF RU RD 5000 f x Figure Symbol Parameter Veo 245 55V Veo 40V Units Conditions Number Min Max Min Max teu Propagation Delay Bus to Bus 0 25 0 25 ns OPEN Figures Note 8 1 2 1 2 tPzL Output Enable Time 1 0 5 0 5 3 ns Vi 7 for tpz Figures V OPEN for tpz 1 2 tpuz 17 Output Disable Time 1 0 6 0 6 3 ns Vi 7V for tpi z Figures V OPEN for toyz 1 2 Note 8 This parameter is guaranteed by design but is not tested The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance when driven by an ideal voltage source zero output impedance Capacitance Note9 Symbol Parameter Typ Max Units Conditions Cin Control Pin Input Capacitance 3 pF Voc 5 0V Vin OV Cio Input Output Capacitance OFF State 6 pF Vcc OE 5 0V Viy OV Note 9 TA 25 C f 1 Mhz Capacitance is characterized but not tested AC Loading and Waveforms V FROM OUTPUT UNDER RD TEST CL Note Input driven by 50Q source terminated in 50Q Note C includes load and stray capacitance Note Input PRR 1 0 MHz ty 500 ns FIGURE 1 AC Test Circuit 2 5 90 3oy 25 58 3 0V INPUT 18V 15V SWITCH INPUT2. D O 1686210 O eee F October 2001 Revised February 2002 SEMICONDUCTOR FST16862 20 Bit Bus Switch General Description Features The Fairchild Switch FST16862 provides 20 bits of high E 40 switch connection between two ports speed CMOS TTL compatible bus switching The low On Minimal propagation delay through the switch Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise W Zero bounce in flow through mode The device is organized as a 20 bit bus switch When OE WB Control inputs compatible with TTL level is LOW the switch is ON and Port A is connected to Port B When OE is HIGH a high impedance state exists between the A and B Ports W Low lcc Ordering Code Package Number FST16862QSP MQA48A 48 Lead Quarter Size Very Small Outline Package QVSOP MO 154 0 150 Wide Preliminary FST16862MTD MTD48 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Order Number Package Description Logic Diagram Es Bi Ag EIS Bg e e e e e e e 5 Bs Bio OE Aere t psum Bu Apr Big e e e e e e e e e e e e A15 Bis B20 OE3 2002 Fairchild Semiconductor Cor
3. GND iPzL 10 GND tPHL OUTPUT i i VoL 0 3V V OUTPUT 1 5V er Le j 9r V VoL VoH 0 3V FIGURE 2 AC Waveforms www fairchildsemi com 4 Physical Dimensions inches millimeters unless otherwise noted PIN ONE IDENTIFIER TOP VIEW le 0 100p C 48x lei 2 00MAX cmm 0 4 0 20 0 10 C 9 25 6 978 C A B 48x 0 SIDE VIEW RO 09 Min 8 NOTES a g A THIS PACKAGE CONFORMS JEDEC M0 154 VERSION AB B ALL DIMENSIONS IN MILLIMETERS 0 50 0 75 C DRAWING CONFORMS TU ASME Y14 5M 1 05 1994 D DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS MQA48AREVA d 24 i 0 30 _ 0 4 LAND PATTERN RECOMMENDATION DETAIL A 1028 10 34 x45 DETAIL A 48 Lead Quarter Size Very Small Outline Package QVSOP JEDEC MO 154 0 150 Wide Package Number MQA48A Preliminary www fairchildsemi com c989L1S4 FST16862 20 Bit Bus Switch Physical Dimensions inches millimeters unless otherwise noted Continued 12 50 0 10 DIMENSIONS ARE IN MILLIMETERS NOTES A CONFORMS TO JEDEC REGISTRATION MO 153 VARIATION AB REF NOTE 6 DATE 7 93 DIMENSIONS ARE IN MILLIMETERS DIMENSIONS ARE EXCLUSIVE OF BURRS MOLD FLASH AND TIE BAR EXTRUSIONS DI
4. MENSIONS AND TOLERANCES PER ANSI Y14 5M 1982 MTD48RevB1 0 10 0 05 30 25 mcm 30 25 1 ZO r 480 920 m 1 l 2 30 1 i PERI 19 ee c e 1 6 19 24 ALLLEAD TIPS E 050 LAND PATTERN RECOMMENDATION 015 SEE DETAIL 0 907915 dens K AER ale GAGE PLANE _f 1 25 0 600 10 i iu SEATING PLANE 1 00 DETAIL A 48 Lead Thin Shrink Small Outline Package TSSOP JEDEC MO 153 6 1mm Wide Package Number MTD48 Technology Description The Fairchild Switch family derives from and embodies Fairchild s proven switch technology used for several years in its 74LVX3L384 FST3384 bus switch product Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use prov
5. ided in the labeling can be rea sonably expected to result in a significant injury to the user 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com www fairchildsemi com
6. l define the conditions for actual device operation ns V to 5 ns V Note 2 Vs is the voltage observed applied at either the A or B Ports across the switch Note 3 The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed Note 4 Unused control inputs must be held HIGH or LOW They may not float Ta 40 to 85 Symbol Parameter Wy Min Units Conditions Note 5 Vik Clamp Diode Voltage 4 5 1 2 11 18 mA HIGH Level Input Voltage 4 0 5 5 2 0 V Vil LOW Level Input Voltage 4 0 5 5 0 8 V li Input Leakage Current 5 5 1 0 uA 0 lt lt 5 5V 0 1 0 pA Viy 5 5V loz OFF STATE Leakage Current 5 5 1 0 0 lt A B lt Voc Ron Switch On Resistance 4 5 4 7 Q Vin OV lin 64 mA Note 6 45 7 Q Vin OV ly 30 mA 45 7 12 Q Vin 2 4V 14 15 mA 4 0 11 20 OQ Vw 24AV liy 15 loc Quiescent Supply Current 5 5 3 uA Vin Vcc or GND lout 0 A lcc Increase in per Input 5 5 2 5 mA One Input at 3 4V Note 7 Other Inputs at Vcc or GND Note 5 Typical values are at 5 0V and T4 25 C Note 6 Measured by the voltage drop between A and B pins at the indicated current through the switch On resistance is determined by the lower of the voltages on the two A or B pins Note 7 Per TTL driven input control pins only www fairchildsemi
7. poration DS500702 www fairchildsemi com sng ig 0c 29891154 FST16862 Connection Diagram OE2 O R Q M o 13 KO GIGS Roc umbrarum quis ee GE JO ON sO Gs 00 WIS OY On de Truth Table Inputs Inputs Outputs OE L A B H Z Pin Descriptions Pin Name Description OE Bus Switch Enables A Bus A B Bus B www fairchildsemi com Absolute Maximum Ratings note 1 Supply Voltage Vcc 0 5V to 7 0V DC Switch Voltage Vs Note 2 0 5V to 7 0V DC Input Voltage Vn Note 3 0 5V to 7 0V DC Input Diode Current lik Vin lt OV 50 mA DC Output lour Current 128 mA DC Vcc GND Current 1 100 mA Storage Temperature Range 65 C to 150 C DC Electrical Characteristics Recommended Operating Conditions Note 4 Power Supply Operating Vcc 4 0V to 5 5V Input Voltage Vix OV to 5 5V Output Voltage Vout OV to 5 5V Input Rise and Fall Time tj Switch Control Input Switch I O 0 ns V to DC Free Air Operating Temperature TA 40 C to 85 C Note 1 The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating The Recommended Operating Conditions table wil
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FAIRCHILD FST16862 handbook