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FAIRCHILD MM74C922 MM74C923 16-Key Encoder 20-Key Encoder handbook

1. 74C922 October 1987 peres Nl ml FAIFPCHILD Revised January 1999 SEMICONDUCTOR TM MM74C922 MM74C923 16 Key Encoder 20 Key Encoder General Description An internal register remembers the last key pressed even after the key is released The 3 STATE outputs provide for The MM74C922 and MM74C923 CMOS key encoders easy expansion and bus operation and are LPTTL compat vide all the necessary logic to fully encode an array of ible SPST switches The keyboard scan can be implemented by either an external clock or external capacitor These encoders also have on chip pull up devices which permit Features switches with up to 50 on resistance to be used No W 50 maximum switch on resistance diodes in the switch array are needed to eliminate ghost E On or off chip clock Switches The internal debounce circuit needs only a single On chip row pull up devices external capacitor and can be defeated by omitting the capacitor A Data Available output goes to a high level 2 key roll over when valid keyboard entry has been made The Data ill Keybounce elimination with single capacitor Available output returns to a low level when the entered W Last key register at outputs key is released even if another key is depressed The Data 3 STATE output LPTTL compatible Available will return high to indicate acceptance of the new key after a normal debounce period this two key roll over amp Wide supply ra
2. Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Tempera ture Range they are not meant to imply that the devices should be oper ated at these limits The table of Electrical Characteristics provides MM74C922 MM74C923 40 C to 85 C Storage Temperature Range 65 C to 150 C Power Dissipation P p Dual In Line 700 mW Small Outline 500 mw DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise specified conditions for actual device operation Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS Positive Going Threshold Voltage Voc 5V ly 2 0 7 mA 3 0 3 6 4 3 V at Osc and KBM Inputs Voc 10V lin 2 1 4 mA 6 0 6 8 8 6 V Voc 15V lin 2 2 1 mA 9 0 10 12 9 V Negative Going Threshold Voltage Voc 5V lin 2 0 7 mA 0 7 1 4 2 0 V at Osc and KBM Inputs Voc 10V lin 2 1 4 mA 1 4 32 4 0 V Voc 15V lin 2 2 1 mA 24 5 6 0 Vin t Logical 1 Input Voltage Voc 5V 3 5 4 5 V Except Osc and KBM Inputs Voc 10V 8 0 9 V Voc 15V 12 5 13 5 V Logical 0 Input Voltage Voc 5V 0 5 1 5 V Except Osc and KBM Inputs Voc 10V 1 2 V Voc 15V 1 5 2 5 V lip Row Pull Up Current at Y1 Y2 Voc 5V Vin 0 1 Voc 2 5 4 Y5 Inputs Voc 10V 10 20 uA Voc 15V 22 45 Vour t Logical 1 Output
3. DATA OUT B ROW Y4 DATA OUT C ROW Y5 DATA QUT D DATA QUT E OUTPUT ENABLE COLUMN X1 GND COLUMN X2 DATA AVAILABLE Top View MM74C923 Truth Tables Pins 0 through 11 Switch 0 1 2 3 4 5 6 7 8 9 10 11 Position 1 1 1 2 1 3 1 4 2 1 2 2 Y2 X3 2 4 1 Y3 X2 Y3 X3 Y3 X4 D A 0 1 0 1 0 1 0 1 0 1 0 1 T B 0 0 1 1 0 0 1 1 0 0 1 1 A C 0 0 0 0 1 1 1 1 0 0 0 0 O D 0 0 0 0 0 0 0 0 1 1 1 1 U 1 0 0 0 0 0 0 0 0 0 0 0 0 Pins 12 through 19 Switch 12 13 14 15 16 17 18 19 Position Y4 X1 4 2 4 3 4 4 Y5 Note 1 Y5 Note 1 Y5 Note 1 Y5 Note 1 X1 X2 X3 X4 D A A 0 1 0 1 0 1 0 1 T B 0 0 1 1 0 0 1 1 A C 1 1 1 1 0 0 0 0 O D 1 1 1 1 0 0 0 0 U E Note 1 0 0 0 0 1 1 1 1 1 Note 1 Omit for MM74C922 www fairchildsemi com Block Diagram 10k DATA AVAILABLE OSC EXT C OR CLOCK INHIBIT KEY BOUNCE ELIMINATION 2704 DECODER ACTIVE LOW OUTPUTS Vec INTERNAL aes ENCODING LOGIC O AND SPST SWITCH 2 ROLL OVER DATA AVAILABLE C OUTPUTS MSB www fairchildsemi com MM74C922 MM74C923 Absolute Maximum Ratings note 2 Voltage at Any Pin Operating Temperature Range Voc 0 3V to V cc t 0 3V Operating Range 3V to 15V Voc 18V Lead Temperature Soldering 10 seconds 260 C Note 2
4. key is released The keyboard may be synchronously scanned by omitting the capacitor at osc and driving osc directly if the system clock rate is lower than 10 kHz www fairchildsemi com MM74C922 MM74C923 Asynchronous Data Entry Onto Bus MM74C922 TO DATA BUS DATA AVAILABLE 1 6 74C04 Outputs are in 3 STATE until key is pressed then data is placed on bus When key is released outputs return to 3 STATE Expansion to 32 Key Encoder MM74C922 5V Ea zs ze a EEEIEI Theory of Operation The MM74C922 MM74C923 Keyboard Encoders imple ment all the logic necessary to interface a 16 or 20 SPST key switch matrix to a digital system The encoder will con vert a key switch closer to 4 MM74C922 or 5 MM74C923 bit nibble The designer can control both the keyboard scan rate and the key debounce period by alter ing the oscillator capacitor Cosg and the key bounce mask capacitor Thus the MM74C922 MM74C923 s performance can be optimized for many keyboards The keyboard encoders connect to a switch matrix that is 4 rows by 4 columns MM74C922 or 5 rows by 4 columns MM74C923 When no keys are depressed the row inputs are pulled high by internal pull ups and the column outputs sequentially output a logic 0 These outputs are open drain and are therefore low for 25 of the time and other wise off The column scan rate is controlled
5. 70 COR I 0 356 0 508 TYP ALL LEADS TYP ALL LEADS 0 008 0 203 M208 REV A 20 Lead Plastic Small Outline Package Package Number M20B www fairchildsemi com EZ6OVZININ MM74C922 MM74C923 16 Key Encoder 20 Key Encoder Physical Dimensions inches millimeters unless otherwise noted Continued 10131440 iSc 2573 2642 2 337 X 0 762 0 032 0 005 MAX DP 0 81320 127 RAD PIN NOT IDENT C 2280 20085 PIN NO 1 IDENT 6 504 0127 0 280 nas OPTION 1 i ca inc 1112 MIN 0 300 0 320 OPTION 2 7820 8128 0 060 NOM 0 040 OPTION 2 i36 uUo 1 524 xk 4 4x 9 065 3302 0 127 1 851 E 3 683 5 080 35 5 EM 90 0 004 0 229 0 381 09020 0 100 0 010 4 0125 0140 0 508 0 0600 005 12540 0254 0 018 0 003 317523555 MIN 0040 1 524 20 127 0 457 0 076 0 015 1018 ss ELT N20A REV 20 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Package Number N20A LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which
6. E 0 DATA OUT VoL OUTPUT 05 V ENABLE 0 m DATA QUT 3 STATE en eee ay 0 FIGURE 2 www fairchildsemi com 6 Typical Performance Characteristics Typical lj vs at Any Y Input 30 p 25 20 15 10 ROW PULL UP CURRENT uA 0 5 10 15 Vec VIN Typical VS Cosc 10k 1k L SE iB 100 Fscan Hz 0 01 1 10 Cosc uF Typical Applications Synchronous Handshake MM74C922 TO DATA BUS MM74C74 BATA AVAILABLE INVITATION ENABLE OUTPUT p RESPONSE The keyboard may be synchronously scanned by omitting the capacitor at osc and driving osc directly if the system clock rate is lower than 10 kHz Typical Ron vs Vout at Any X Output COLUMN OUTPUT IMPEDANCE ko Your Typical Debounce Period vs 1 HH e c 01 id d a o HL thi 3 S 0 01 2 I i e i im 0 001 01 1 10 uF 100 Synchronous Data Entry Onto Bus MM74C922 TO DATA BUS DATA AVAILABLE Outputs are enabled when valid entry is made and go into 3 STATE when
7. N Channel 25 C Isink Output Sink Current Vec 10V Vout 8 16 mA N Channel 25 C AC Electrical Characteristics note TA 25 C C 50 pF unless otherwise noted Symbol Parameter Conditions Min Typ Max Units todo tpat Propagation Delay Time to C 50 pF Figure 1 Logical 0 or Logical 1 Voc 5V 60 150 ns from D A Voc 10V 35 80 ns Voc 15V 25 60 ns tH Propagation Delay Time from 10k C 10 pF Figure 2 Logical 0 or Logical 1 Voc 5V R 10k 80 200 ns into High Impedance State Voc 10V C 10 pF 65 150 ns Voc 15V 50 110 ns tuo tui Propagation Delay Time from 10k C 50 pF Figure 2 High Impedance State to a Voc 5V RL 10k 100 250 ns Logical 0 or Logical 1 Voc 10V C 50 pF 55 125 ns Voc 15V 40 90 ns Cin Input Capacitance Any Input Note 4 5 7 5 pF Cour 3 STATE Output Capacitance Any Output Note 4 10 pF Note 3 AC Parameters are guaranteed by DC correlated testing Note 4 Capacitance is guaranteed by periodic testing www fairchildsemi com MM74C922 MM74C923 Switching Time Waveforms AVAILABLE DATA OUTPUT T1 2 RC 0 7 RC where R 10k and C is external capacitor at KBM input FIGURE 1 OUTPUT ENABL
8. Voltage Voc 5V lo 10 uA 4 5 V Vec 10V lo 10 pA 9 V Vec 15V lo 10 pA 13 5 V Vour o Logical 0 Output Voltage Voc 5V lo 10 uA 0 5 V Voc 10V lo 10 pA 1 V Voc 15V lo 10 pA 1 5 V Ron Column Resistance at Voc 5V Vo 0 5V 500 1400 Q X1 X2 X3 and X4 Outputs Voc 10V Vo 1V 300 700 Q Vcc 15V Vo 1 5V 200 500 loc Supply Current Voc 5V 0 55 14 mA Osc at OV one Y low Voc 10V 1 1 1 9 mA Voc 15V 1 7 2 6 mA Logical 1 Input Current Voc 15V Vin 15V 0 005 1 0 uA at Output Enable Logical 0 Input Current Voc 15V Vin 0V 1 0 0 005 uA at Output Enable CMOS LPTTL INTERFACE Vin t Except Osc and KBM Inputs Voc 4 75V Vcc 1 5 V Except Osc Inputs Voc 4 75V 0 8 V Vour t Logical 1 Output Voltage lo 360 uA Voc 4 75V 2 4 V 360 uA Vour o Logical 0 Output Voltage 360 uA Voc 4 75V 0 4 V 360 uA www fairchildsemi com DC Electrical Characteristics Continued Symbol Parameter Conditions Min Typ Max Units OUTPUT DRIVE See Family Characteristics Data Sheet Short Circuit Current IsoURCE Output Source Current Voc 5V Vout OV 1 75 3 3 mA P Channel 25 C lsouncE Output Source Current Vec 10V Vout OV 8 15 mA P Channel 25 C leiNK Output Sink Current Voc 5V Vout Vcc 1 75 3 6 mA
9. a are intended for surgical implant into the device or system whose failure to perform can be rea body or b support or sustain life and c whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system or to affect its safety or effectiveness instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the www fairchildsemi com user Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications
10. by the oscilla tor input which consists of a Schmitt trigger oscillator a 2 bit counter and a 2 4 bit decoder When a key is depressed key 0 for example nothing will happen when the X1 input is off since Y1 will remain high When the X1 column is scanned X1 goes low and Y1 will go low This disables the counter and keeps X1 low Y1 MM74C922 C 10 T DATA AVAILABLE T DO D1 02 05 BUS 04 100 ko going low also initiates the key bounce circuit timing and locks out the other Y inputs The key code to be output is a combination of the frozen counter value and the decoded Y inputs Once the key bounce circuit times out the data is latched and the Data Available DAV output goes high If during the key closure the switch bounces Y1 input will go high again restarting the scan and resetting the key bounce circuitry The key may bounce several times but as Soon as the switch stays low for a debounce period the closure is assumed valid and the data is latched A key may also bounce when it is released To ensure that the encoder does not recognize this bounce as another key closure the debounce circuit must time out before another closure is recognized The two key roll over feature can be illustrated by assum ing a key is depressed and then a second key is depressed Since all scanning has stopped and all other Y inputs are disabled the second key is not recognized until the first key is lift
11. ed and the key bounce circuitry has reset The output latches feed 3 STATE which is enabled when the Output Enable OE input is taken low www fairchildsemi com Physical Dimensions inches millimeters unless otherwise noted 0 845 0 870 21 48 22 10 50 092 2 29 2 34 18 10 19 939 NL 0 76 PIN NO 1 IDENT 0 245 0 255 6 22 6 48 1 9 0 060 0 300 0 320 1 52 7 62 8 13 0 040 0 125 0 135 9 145 0 200 1 65 1 02 3 18 3 43 3 68 5 08 1 65 4 0 008 0 014 0 20 0 36 909 49 959 59 2 0 280 2 54 TYP 1 0 015 0 021 0 125 0 140 MIN yg ieee jS TYP 0 25 1 02 0 020 Typ 0 310 0 365 N18A REV F 0 51 7 87 9 27 18 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Package Number N18A 0 496 0 512 la 12 598 13 005j 20 19 18 17 16 15 14 13 12 1 0 394 0 419 10 008 10 643 30 TYP LEAD NO 1 1 7 IDENT Y V Q 1 2 3 4 5 6 7 8 9 10 0 010 0 254 0 291 0 299 7 391 7 595 0 000 028 0 093 0 104 0 254 0 737 5 2 362 2 642 0 004 0 012 8 MAX TYP M ALL LEADS 0 102 0 305 W SEATING PLANE 0 009 0 013 am i 0 050 aaa 0 102 0 016 0 050 10 356 0 0154 0 014 0 020 0 229 0 330 ALL LEAD TIPS gt 0406 1270 12
12. nge to 15V is provided between any two switches W Low power consumption Ordering Code Order Number Package Number Package Description MM74C922N N18A 18 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide MM74C922WM M20B 20 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide MM74C923WM M20B 20 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide MM74C923N N20A 20 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Device also available in Tape and Reel Specify by appending suffix letter X to the ordering code Connection Diagrams Pin Assignment for DIP Pin Assignment for SOIC ROW Y1 ROW Y1 ROW Y2 DATA OUT A ROW Y2 DATA QUT A ROW Y3 DATA OUT B ROW Y3 DATA OUT B ROW Y4 DATA QUT C DATA OUT D ROW Y4 DATA OUTC Ne OSCILLATOR NC OSCILLATOR DATA OUT D KEYBOUNCE MASK OUTPUT ENABLE KEYBOUNCE MASK OUTPUT ENABLE COLUMN X4 DATA AVAILABLE COLUMN X3 COLUMN X1 COLUMN X4 DATA AVAILABLE GND COLUMN X2 COLUMN X3 COLUMN X1 Top View GND COLUMN X2 MM74C922 Top View MM94C922 1999 Fairchild Semiconductor Corporation DS006037 prf www fairchildsemi com ey 0z 1epo2u3 91 269vAININ ZZ6OPZININ MM74C922 MM74C923 Connection Diagrams Continued KEYBOUNCE MASK OSCILLATOR COLUMN X4 COLUMN X3 Pin Assignment for DIP and SOIC Package ROW Y1 ROW 2 DATA OUT A ROW

FAIRCHILD MM74C922 MM74C923 16-Key Encoder 20-Key Encoder handbook

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