FAIRCHILD MM74C32 handbook
Contents
1. 0 335 0 344 8 509 8 738 0 228 0 244 5 791 6 198 oT LEAD NO 1 IDENT 0 150 0 157 3 610 3 988 0 010 0 020 0 053 0 069 0 254 0 508 1 346 1 753 B MAX TYP ALL LEADS 0 004 0 010 0 102 0 254 fh SEATING y HH H Y F PLANE A 0 014 0 008 0 010 0 050 0 014 0 020 0 203 0 254 0 016 0 050 03 i27 lt el e oaos TYP ALL LEADS 0 004 0 406 1 270 TYP 0 008 TYP 7 102 TYP ALL LEADS 70 203 ALL LEAD TIPS 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 120 0 150 Narrow Package Number M14A M14A REV H www fairchildsemi com cfOrZinin MM74C32 Quad 2 Input OR Gate Physical Dimensions inches millimeters unless otherwise noted Continued 0 740 0 770 i 18 80 19 56 0 090 2 286 INDEX AREA 0 25040 010_ 6 35040 254 PIN NO 1 _ PIN NO 1 IDENT IDENT 0 092 54 0 030 MAX 2337 0 762 DEPTH OPTION 1 OPTION 02 0 135 0 005 0 300 0 320 3 429 0 127 7 620 8 128 0 065 0 145 0 200 0 060 TYP ww 4 TYP 1 651 8 683 5 080 1 524 a OPTIONAL rte 0 008 0 018 0 020 i 90 4 TYP la 0 203 0 406 0 508 i miN _0 125 0 150 l 0 075 0 015 8 175 3 010 1 905 0 381 ae Ga Bie 0 100 0 010 typ MIN sigh tae 2 540 0 254 0 050 0 010 0 040 0 1 270 0 254 0 325 0 05 1018 0 255 0 381 N14A REV F 14 Lea2. 0 0 MM74C32 0 O Ea FAIRCHILD SEMICONDUCTOR Tw MM74C32 Quad 2 Input OR Gate General Description The MM74C32 employs complementary MOS CMOS transistors to achieve low power and high noise margin these gates provide the basic functions used in the imple Features mentation of digital integrated circuit systems The N and E Wide supply voltage range 3 0V to 15V P channel enhancement mode transistors provide a sym E Guaranteed noise margin 1 0V metrical circuit with output swings essentially equal to the supply voltage This results in high noise immunity over a wide supply voltage range No DC power other than that W Low power TTL compatibility fan out of 2 driving 74L caused by leakage current is consumed during static con October 1987 Revised January 1999 ditions All inputs are protected against static discharge damage E High noise immunity 0 45V Vcc typ Ordering Code Order Number Package Number Package Description MM74C32M M14A 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 120 0 150 Narrow MM74C32N N14A 14 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Connection Diagram Devices also available in Tape and Reel Specify by appending suffix letter X to the ordering code Pin Assignments for DIP and SOIC Top View 1999 Fairchild Semiconductor Corporation DS005881 prf www fairchildsemi com 9185
3. HO Indu z pend ZeorZiW MM74C32 Absolute Maximum Ratings note 1 Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation Pp Dual In Line Small Outline Operating Voc Range 0 3V to Voc 0 3V 40 C to 85 C 65 C to 150 C 700 mW Absolute Maximum Voc 18V Lead Temperature Soldering 10 seconds 260 C Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Tempera ture Range they are not meant to imply that the devices should be oper ated at these limits The Electrical Characteristics table provides conditions for actual device operation 500 mW 3 0V to 15V DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS VING Logical 1 Input Voltage Voc 5 0V 3 5 V Voc 10V 8 0 V ViN o Logical 0 Input Voltage Voc 5 0V 1 5 V Voc 10V 2 0 V Vout 1 Logical 1 Output Voltage Vec 5 0V lo 10 pA 4 5 V Voc 10V lo 10 pA 9 0 V Vout o Logical O Output Voltage Voc 5 0V lo 10 uA 0 5 V Voc 10V lo 10 pA 1 0 V lint Logical 1 Input Current Voc 15V Vin 15V 0 005 1 0 HA lin o Logical O Input Current Voc 15V V
4. d Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Package Number N14A LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications
5. in OV 1 0 0 005 HA loc Supply Current Voc 15V 0 05 15 HA CMOS LPTTL INTERFACE ViNn t Logical 1 Input Voltage Voc 4 75V Vcc 1 5 Vv VINo Logical 0 Input Voltage Voc 4 75V 0 8 Vv VoutT 1 Logical 1 Output Voltage Voc 4 75V Io 360 uA 2 4 V VouT o Logical O Output Voltage Voc 4 75V Io 360 uA 0 4 V OUTPUT DRIVE see Family Characteristics Data Sheet T4 25 C short circuit current IsouRCE Output Source Current Vec 5 0V Voyt 0V 1 75 3 3 mA P Channel IsoURCE Output Source Current Vec 10V Vout 0V 8 0 15 mA P Channel Isink Output Sink Current Vec 5 0V Vout Vec 1 75 3 6 mA N Channel Isink Output Sink Current Vec 10V Vout Vee 8 0 16 mA N Channel AC Electrical Characteristics note 2 Ta 25 C C 50 pF unless otherwise specified Symbol Parameter Conditions Min Typ Max Units toa Propagation Delay Time to Voc 5 0V 80 150 ns Logical 1 or 0 Voc 10V 35 70 ns Cin Input Capacitance Any Input Note 3 5 pF Cpp Power Dissipation Capacitance Per Gate Note 4 15 pF Note 2 AC Parameters are guaranteed by DC correlated testing Note 3 Capacitance is guaranteed by periodic testing Note 4 Cpp determines the no load AC power consumption of any CMOS device For complete explanation see Family Characteristics Application Note AN 90 www fairchildsemi com Physical Dimensions inches millimeters unless otherwise noted
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FAIRCHILD MM74C32 handbook