FAIRCHILD MM74C165 handbook
Contents
1. 65 C to 150 C 18V 700 mW Soldering 10 seconds 3V to 15V 260 C Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed Except for Operating Tempera ture Range they are not meant to imply that the devices should be oper ated at these limits The Electrical Characteristics table provides conditions for actual device operation 500 mW DC Electrical Characteristics Min Max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ Max Units CMOS TO CMOS Vint Logical 1 Input Voltage Voc 5V 3 5 V Voc 10V 8 0 V ViN 0 Logical 0 Input Voltage Voc 5V 1 5 V Voc 10V 2 0 V Vour t Logical 1 Output Voltage Voc SV lg 10 pA 4 5 V Vcc 10V lo 10 uA 9 0 V Vour o Logical 0 Output Voltage Voc 5V lo 410 HA 0 5 V Voc 10V lp 2 0 LA 1 0 V lint Logical 1 Input Current Voc 15V Vin 15V 0 005 1 0 uA lin o Logical O Input Current Voc 15V Vin 0V 1 0 0 005 uA loc Supply Current Voc 15V 0 05 300 uA CMOS TO LPTTL INTERFACE Vin Logical 1 Input Voltage Voc 4 75V Vcc 1 5 V VINo Logical 0 Input Voltage Voc 4 75V 0 8 V Vour 1 Logical 1 Output Voltage Voc 4 75V lo 360 uA 2 4 V Vour o Logical 0 Output Voltage Voc 4 75V lg 360 uA 0 4 V OUTPUT DRIVE See Fami2. 0 200 3 683 5 080 i Tr 952159 0 008 0 016 6 508 MN il ju 0 280 0 203 0 406 0 125 0 150 0 030 0 015 e cim 112 3 175 3 810 005 7 0 762 0 381 MIN 0 014 0 023 i 0 100 0 010 0 325 0 040 0 356 0 584 0 050 0 010 2 540 40 254 NI6E REV F me 1 270 10 254 De 8 255 H ass 1018 TYP 16 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems 2 A critical component in any component of a life support which a are intended for surgical implant into the device or system whose failure to perform can be rea body or b support or sustain life and c whose failure sonably expected to cause the failure of the life support to perform when properly used in accordance with device or system or to affect its safety or effectiveness instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the www fairchildsemi com user Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and sp
3. OO MM74165N 1 Ea FAIRCHILD SEMICONDUCTOR TM MM74C165 General Description The MM74C165 functions as an 8 bit parallel load serial shift register Data is loaded into the register independent of the state of the clock s when PARALLEL LOAD PL is low Shifting is inhibited as long as PL is low Data is sequentially shifted from complementary outputs Q7 and Qs highest order bit P7 first New serial data may be entered via the SERIAL DATA Ds input Serial shifting occurs on the rising edge of CLOCK1 or CLOCK2 Clock inputs may be used separately or together for combined clocking from independent sources Either clock input may be used also as an active low clock enable To prevent double clocking when a clock input is used as an enable October 1987 Revised January 1999 Parallel Load 8 Bit Shift Register the enable must be changed to a high level disabled only while the clock is HIGH Features W Wide supply voltage range 3V to 15V W Guaranteed noise margin 1V W High noise immunity 0 45 Voc typ W Low power TTL compatibility fan out of 2 driving 74L W Parallel loading independent of clock W Dual clock inputs W Fully static operation Ordering Code Order Number Package Number Package Description MM74165N N16E 16 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Connection Diagram Pin Assignments for DIP PARALLEL INPUTS DA SERIAL DATA OUT
4. PUT v P1 PO Ds Q7 PARALLEL CLOCKi P4 P5 P6 P7 OUTPUT GND LOAD N s J a7 PL PARALLEL INPUTS Top View 1999 Fairchild Semiconductor Corporation DS005897 prf www fairchildsemi com 481SI94 HIS 18 9 peoT Jerjeyed S9 LOtZININ MM74C165 Block Diagrams CLOCK 1 15 CLOCK2 PARALLEL TOAD LOAD PL s L s t Please look into Section 8 Appendix D for availability of various package types ees ese ee T T T aE a ae 5 D Q0 D 01 D Q2 D Q3 D Q4 D Qs D Q6 D Q7 0 1 2 3 4 5 6 a7 er rr e e e Pa a PS L1 1 1 ee ee eee eee ee eee eee 13 14 3 4 5 6 PARALLEL INPUTS SERIAL Truth Table State Inputs Internal Outputs PL Clocki Clock2 Ds POthruP7 QO Q1 Q7 Q7 as enable Parallel Load L X X X PO P7 PO P1 P7 P7 Enable H L L X X PO P1 P7 P7 Shift with Ds H T L H X H PO P6 P6 Shift with Ds H T L i X L P5 P5 Hold Disable H T H X X L P5 P5 X Dont Care H Vin L Vino T Clock transition from Vin o to Vinay PO thru P7 Data present and loaded into parallel inputs QO thru Q6 Internal flip flop outputs www fairchildsemi com 2 Absolute Maximum Ratings oie 1 Voltage at Any Pin Operating Temperature Range Storage Temperature Range Absolute Maximum Voc Power Dissipation Dual In Line Small Outline Operating Voc Range Lead Temperature 0 3V to Voc 0 3V 40 C to 85 C
5. V 10 us Voc 10V 5 us Cin Input Capacitance Note 3 5 pF Cpp Power Dissipation Capacitance Note 4 65 pF Note 2 AC Parameters are guaranteed by DC correlated testing Note 3 Capacitance is guaranteed by periodic testing Note 4 Cpp determines the no load AC power consumption of any CMOS device For complete explanation see Family Characteristics application note AN 90 Switching Time Waveform Y CLOCK2 9 5 Voc AS INHIBIT K Vee CLOCK1 0 5 Vec ov SERIAL Vec DATA 0 5 Vec DS av P7 INPUT 0 5 PARALLEL LOAD PL 0 5 Note A The remaining six data and the serial input are LOW Note B Prior to test HIGH level data is loaded into the P7 input www fairchildsemi com 4 Logic Waveform CLOCK 1 CLOCK2 AS ENABLE DS PL Q0 Q1 Q2 Q3 DATA Q4 Q5 Q6 Q7 OUTPUT Q7 OUTPUT Q7 JUUUUUUUUUULU L SJ Uu L ra INHIBIT SERIAL SHIFT LOAD 5 www fairchildsemi com S9LOtZININ MM74C165 Parallel Load 8 Bit Shift Register Physical Dimensions inches millimeters unless otherwise noted 0 740 0 780 ning 18 80 19 81 ECL LL p ea 2 286 IE INDEX AREA 0 250 0 010 6 350 0 254 PIN NO 1 PIN NO 1 IDENT IDENT OPTION 01 OPTION 02 2 eas 0 130 0 005 0 060 3 302 0 127 4 TYP 0 300 0 320 n A RE OPTIONAL 7 7 620 8 128 e EN 0 145
6. ecifications
7. ly Characteristics Data Sheet short circuit current ISOURCE Output Source Current Voc 5V 1 75 3 3 mA P Channel Ta 25 C Vour OV ISOURCE Output Source Current Voc 10V 8 0 15 mA P Channel Ta 25 C Vour OV leiNK Output Sink Current Voc 5V 1 75 3 6 mA N Channel Ta 25 C Vout Vcc lsiNK Output Sink Current Voc 10V 8 0 16 mA N Channel Ta 25 C Vout Vcc www fairchildsemi com S9LOtZININ MM74C165 AC Electrical Characteristics Note 2 Ta 25 C C 50 pF unless otherwise noted Symbol Parameter Conditions Min Typ Max Units pdo todt Propagation Delay Time to a Logical 0 or Vcc 5V 200 400 ns Logical 1 from Clock or Load to Q or Q Voc 10V 80 200 ns pdo todt Propagation Delay Time to a Logical 0 or Vcc 5V 200 400 ns Logical 1 from H to Q or Q Voc 10V 80 200 ns S Clock Inhibit Set up Time Voc 5V 150 75 ns Voc 10V 60 30 ns S Serial Input Set up Time Voc 5V 50 25 ns Voc 10V 30 15 ns H Serial Input Hold Time Voc 5V 50 0 ns Voc 10V 30 0 ns S Parallel Input Set Up Time Voc 5V 150 75 ns Voc 10V 60 30 ns H Parallel Input Hold Time Voc 75V 50 0 ns Voc 10V 30 0 ns w Minimum Clock Pulse Width Voc 5V 70 200 ns Voc 10V 30 100 ns w Minimum Load Pulse Width Vcc 5V 85 180 ns Voc 10V 30 90 ns MAX Maximum Clock Frequency Vec 5V 2 5 6 MHz Voc 10V 5 12 MHz n lt Maximum Clock Rise and Fall Time Voc 5
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FAIRCHILD MM74C165 handbook