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national semiconductor MM70C95/MM80C95 MM70C97/MM80C97 TRI-STATEÉ Hex Buffers MM70C96/MM80C96 MM70C98/MM80C98 TRI-STATE Hex Inverters handbook

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1. GND TL F 5907 3 Top View Order Number MM70C97 or MM80C97 TRI STATE is a registered trademark of National Semiconductor Corporation 70 96 80 96 Veo 06 View Order Number 70 98 80 98 We DS View Order Number OU GND TL F 5907 2 MM70C96 or MM80C96 M TL F 5907 4 MM70C98 or MM80C98 91995 National Semiconductor Corporation TL F 5907 RRD B30M105 Printed in U S A SJ9149AU X9H 31V 1S IH L 86008NIN 86090ZININ 96908WIN 9690ZININ s19jjng 31V 1S IH L 62081 1 1 620 1 S62081NIN 8690ZIAIN Absolute Maximum Ratings note 1 If Military Aerospace specified devices are required please contact the National Office Distributors for availability and specifications Voltage at Any Pin 0 3V to Vcc 0 3V Operating MM70C 80 Temperature Range XX XX Semiconductor Sales 55 C to 125 C 40 C to 85 C Storage Temperature Range Power Dissipation Pp Dual In Line Small Outline Power Supply Voltage Vcc Lead Temperature Soldering 10 seconds 65 C to 150 700 mW 500 mW 18V 260 DC Electrical Characteristics min max limits apply across temperature range unless otherwise noted Symbol Parameter Conditions Min Typ
2. MM QN vationat Semiconductor 70 95 80 95 70 97 80 97 TRI STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI STATE Hex Inverters General Description These gates are monolithic complementary MOS CMOS integrated circuits constructed with N and P channel en hancement mode transistors The MM70C95 MM80C95 and the 70 97 80 97 convert CMOS or TTL out puts to TRI STATE outputs with no logic inversion the 70 96 80 96 and the 70 98 80 98 pro vide the logical opposite of the input signal The MM70C95 80 95 and the MM70C96 MM80C96 have common TRI STATE controls for all six devices The MM70C97 80 97 and the MM70C98 MM80C98 have two TRI STATE controls one for two devices and one for the other four devices Inputs are protected from damage due to stat ic discharge by diode clamps to Vcc GND Features m Wide supply voltage range 3 0V to 15V W Guaranteed noise margin 1 0V W High noise immunity W TTL compatible Applications W Bus drivers February 1988 0 45 Voc typ Drive 1 TTL Load Typical propagation delay into 150 pF load is 40 ns Connection Diagrams Dual in Line Packages MM70C95 MM80C95 Ye 064 Ns QUIS N4 OUT DIS MN GND TL F 5907 1 Top View Order Number MM70C95 or MM80C95 MM70C97 MM80C97 DIS 16 006 054 OUT
3. A F gt 7 1 620 8 128 0 145 0 200 1 xr 3 683 5 080 d Li Li 909 49 TYP DT 0508 MN 0 280 0 125 0 150 0 050 0 015 7 112 5 175 3 810 05 1 0762 0 381 MIN 0 014 0 025 0 100 0 010 0 040 0356 0 584 254020254 0325 0015 1 2700 254 82857 Molded Dual In Line Package Order Number MM70C95N MM70C96N MM70C97N 70 98 80 95 80 96 MM80C97N MM80C98N NS Package Number 16 LIFE SUPPORT POLICY 0 065 1 651 HER 0 008 0 016 0 203 0 406 REV NATIONAL S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury 2 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness to the user National Semiconductor National Sem
4. 25 ns MM70C97 MM80C97 Voc 5V 70 125 ns Voc 10V 50 90 ns 70 98 80 98 Voc 5V 90 170 ns Voc 10V 70 125 ns tH1 to Delay from Disable Input to Logical 1 Level 2 from High Impedance State 10k COR 70 95 80 95 Voc 5V 120 200 ns Voc 10V 50 90 ns MM70C96 MM80C96 Voc 5V 130 225 ns Voc 10V 60 110 ns MM70C97 MM80C97 Voc 5V 95 175 ns Voc 10V 40 80 ns MM70C98 MM80C98 Voc 5V 120 200 ns Voc 10V 50 90 ns Cin Input Capacitance Any Input Note 2 5 0 pF Output Capacitance TRI STATE Any Output Note 2 11 pF Cpp Power Dissipation Capacitance Note 3 60 pF AC Parameters are guaranteed by DC correlated testing Truth Tables MM70C95 MM80C95 MM70C96 MM80C96 Disable Input Disable Input DIS DIS Input Output DIS DIS Input Output 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 X H z 0 1 X 1 0 X H z 1 0 X 1 1 X H z 1 1 X 70 97 80 97 70 98 80 98 Disable Input Disable Input DIS DIS Input Output DIS DIS Input Output 0 0 0 0 0 0 0 0 0 1 1 0 0 1 X 1 X H z X 1 X H z 1 X X H z 1 X X H z Output 5 6 only Output 1 4 only X Irrelevant AC Test Circuits Switching Time Waveforms tpd1 TL F 5907 13 tip and INPUT OUTPUT DISABLE 10k TL F 5907 15 and tHo Vec 10k INPUT OUTPUT DISABLE T 5pF TL F 5907 18 Note Delays measured with input tr t lt 20 ns CMOS to CMOS D
5. ES LI LI CONTROLS FOR ALL SIX DEVICES 1 TL F 5907 9 TL F 5907 10 TL F 5907 8 Schematic Diagrams continued MM70C97 MM80C97 TRI STATE ONE OF TWO FOUR DEVICES 5 CONTROLS 70 98 80 98 5 ONE OF TWO FOUR DEVICES ONE OF TWO 5 CONTROLS TL F 5907 11 TL F 5907 12 Physical Dimensions inches millimeters 9 025 0 64 0 005 0 020 R 0 12 0 51 0 005 0 13 MIN TYP 0 200 5 08 MAX TYP GLASS SEALANT 0 020 0 060 0 51 1 52 0 080 2 03 BOTH ENDS 0 018 0 003 0 46 0 08 YP 0 10020 010 2 54 0 25 Ceramic Dual In Line Package J Order Number MM70C95J MM70C96J MM70C97J MM70C98J MM80C95J MM80C96J MM80C97J or MM80C98J NS Package Number J16A J16A REV 1 70 95 80 95 MM70C97 MM80C97 TRI STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI STATE Hex Inverters Physical Dimensions inches millimeters Continued 0 740 0 780 74 18 80 19 81 0 090 INDEX AREA 0 250 0 010 6 350 0 254 PIN NO 1 PIN NO 1 IDENT went U OPTION 01 OPTION 02 0 130 40 005 0 130 0 005 0 060 49 TYP 0 300 0 320 3 502 10 127 1 524
6. ISABLE 50 Voa 90 OUTPUT o_O N TL F 5907 16 Voc DISABLE 50 ov Voc OUTPUT ox VoL TL F 5907 19 TL F 5907 14 1 1 Voc DISABLE 50 ov n H1 Voc OUTPUT 50 ov TL F 5907 17 tHo DISABLE 50 ov tho Voc OUTPUT 50 0v TL F 5907 20 Typical Performance Characteristics Propagation Delay vs Atpa pF vs Load Capacitance c Power Supply Voltage 150 5 075 T 25 C 4 46 20 nsi gt E 1 lt SEE AC TEST CIRCUIT 100 Q 050 x 5 5 E E amp 5 025 a b ne R 4 0 50 10 15 Cj LOAD CAPACITANCE pF 7 POWER SUPPLY VOLTAGE V TL F 5907 5 THAR S208 N Channel Output Drive at 25 C P Channel Output Drive at 25 C 100 0 9 Voc 15 10 80 lt lt 70 60 c Voc a 740 5 4 8 50 30 20 Voc 7 5V 10 70 0 80 024 6 8 10 12 14 16 16 14 12 10 8 6 4 2 0 Your Veo 7 Your Y TL F 5907 7 Schematic Diagrams 70 95 80 95 TRI STATE E OF SIX DEVICES 0l LI LI LI LI 1 CONTROLS FOR ALL SIX DEVICES op t 70 96 80 96 TRI STATE NE OF SIX DEVIC
7. Max Units CMOS TO CMOS Logical 1 Input Voltage Voc 5V 3 5 V Vcc 10V 8 0 V VIN 0 Logical 0 Input Voltage Voc 5V 1 5 V Voc 10V 2 0 V VouT 1 Logical 1 Output Voltage Voc 5V 4 5 V Vcc 10V 9 0 V Logical 0 Output Voltage Voc 5V 0 5 V Vcc 10V 1 0 V Logical 1 Input Current Voc 15V 0 005 1 0 pA Logical 0 Input Current 1 0 0 005 pA loz Output Current in High Voc 15V Vo 15V 0 005 1 0 pA Impedance State Voc 15V Vo OV 1 0 0 005 pA loc Supply Current Voc 15V 0 01 15 pA TTL INTERFACE 1 Logical 1 Input Voltage 70C Voc 4 5V Voc 1 5 V 80C Voc 4 75V Voc 1 5 V Logical 0 Input Voltage 70C Voc 4 5V 0 8 V 80C Voc 4 75V 0 8 V VouT 1 Logical 1 Output Voltage 70C Voc 4 5V lo 1 6 2 4 V 80C Voc 4 75V lo 1 6 mA 2 4 V VouT 0 Logical 0 Output Voltage 70C Voc 4 5V lo 1 6 mA 0 4 V 80C Voc 4 75V lo 1 6 mA 0 4 V OUTPUT DRIVE Short Circuit Current ISOURCE Output Source Current Voc 5V 5V _ Ta 25 C 639 ISOURCE Output Source Current Voc 10V 10V 20 m TA 25 C Vout ISINK Output Sink Current Voc 5V OV Ta 25 Vout Vcc di Ld ISINK Output Sink Current Voc 10V OV 20 E Ta 25 C Vout Voc Note 1 Absolute Maximum Ratings are those values beyond which the safety of the d
8. evice cannot be guaranteed Except for Operating Temperature Range they are not meant to imply that the device should be operated at these limits The table of Electrical Characteristics provides conditions for actual device operation Note 2 Capacitance is guaranteed by periodic testing Note 3 Cpp determines the no load AC power consumption of any CMOS device For complete explanation see 54C 74C Family Characteristics application note AN 90 AC Electrical Characteristics 1 25 50 pF unless otherwise noted Symbol Parameter Conditions Min Typ Max Units todo Propagation Delay Time to a Logical 0 or Logical 1 from Data Input to Output 70 95 80 95 MM70C97 MM80C97 Voc 5V 60 100 ns Voc 10V 25 40 ns 70 96 80 96 70 98 80 98 Voc 5V 70 150 ns Voc 10V 35 75 ns todo Propagation Delay Time to a Logical 0 Logical 1 from Data Input to Output 70 95 80 95 MM70C97 MM80C97 Voc 5V CL 150 pF 85 160 ns Voc 10V CL 150 pF 40 80 ns 70 96 80 96 70 98 80 98 Voc 5V CL 150 pF 95 210 ns Voc 10V 150 pF 45 110 ns Delay from Disable Input to High Impedance State from Logical 1 or Logical 0 dO piss pre 70 95 80 95 Voc 5V 80 135 ns Voc 10V 50 90 ns 70 96 80 96 Voc 5V 100 180 ns Voc 10V 70 1
9. iconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax 49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 Email cnjwge tevm2 nsc com Ocean Centre 5 Canton Rd Fax 81 043 299 2408 Tel 1 800 272 9959 Deutsch Tel 49 0 180 530 85 85 Tsimshatsui Kowloon Fax 1 800 737 7018 English Tel 49 0 180 532 78 32 Hong Kong Frangais Tel Italiano Tel 49 0 180 532 93 58 4 49 0 180 534 16 80 Tel 852 2737 1600 Fax 852 2736 9960 National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications

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