ST STP08DP05 handbook
Contents
1. 2 2 8 9 om om 1 a CILE 5 1 16 8 4 7419276 PIN 1 IDENTIFICATION 25 30 Package mechanical data 5 5 amp Reel TSSOP16 MECHANICAL DATA DIM Note Drawing not in scale 26 30 STPO8DP05 Package mechanical data SO 16 MECHANICAL DATA mm inch A x 2 x poss o c1 45 typ D 9 8 10 0 385 0 393 E 5 8 6 2 0 228 0 244 e 1 27 0 050 e3 8 89 0 350 F 3 8 4 0 0 149 0 157 G 4 6 5 3 0 181 0 208 L 0 5 1 27 0 019 0 050 M 0 62 0 024 s 8 max L G cl 00160200 27 30 Package mechanical data STPO8DP05 Tape amp Reel SO 16 MECHANICAL DATA mm inch DIM MIN TYP MAX MIN TYP MAX A C D N T Ao Bo Ko Po P 7 9 8 1 0 311 0 319 Y N C Y Y A p Bo pee LO 4000 0 ___ AO 28 Note Drawing not in scale 28 30 STPO8DP05 Revision histo2. 5 3 2 Thermal data m tete occa tae eet ed CEE ae 5 3 3 Recommended operating conditions 6 4 Electrical characteristicS 7 5 Switching characteristics 8 6 Equivalent circuit and outputs 9 7 Truth table and timing diagram 11 7 1 c 11 7 2 Timing 12 8 Typical characteristics 14 9 Test CIICUIE i uuo ERREUR e URS RE 16 10 Detection mode functionality 18 10 1 Phase one entering in detection mode 18 10 2 Phase two error detection 19 10 3 Phase three resuming to normal 20 10 4 Error detection 5 21 11 Package mechanical data 22 12 Revision history dae RR E Ko 29 2 30 STPO8DP05 Summary description 1 Summary description Table 2 Typical current accuracy Current accuracy Ou
3. 1 510410 94 HD pes uy oX 1X X X 1 005 gt 2 8 Z BOXN 10 14 V X 1 oas X X X 9 1 9 045 4 4 4 1 0 lt gt 7 7 1 4 4 4 1915 11 lt 2 X 5 uius HIUS LON X X B A Nf SN LJ X Z J N VN N NZ NZ N N na 3 ox Z sesind x N sesing 19 X N gt 504080415 lt 509080415 1 045 4 3 9504080915 lt 504080415 904080915 lt 0 145 005 905 L 05 005 17 30 Detection mode functionality STPO8DP05 10 10 1 18 30 Detection mode functionality Phase one entering in detection mode From the Normal Mode condition the device can switch to the Error Mode by a logic sequence on the OE DM2 and LE DM1 pins as showed in the following table and diagram Table 10 Entering in detection truth table CLK 1 2 3 4 5 OE DM2 H L H H H LE DM1 L L L H L Figur
4. Table 9 Output resistor Output Current mA 3 5 10 20 50 80 130 Rext 0 6740 3930 1913 963 386 241 124 14 30 STPO8DP05 Typical characteristics Figure 12 Power dissipation vs temperature package 517640 W 3 5 5 0 2 5 DIP TSSOP EXP PAD 2 0 SOP TSSOP 25 50 75 100 125 Te C Note The Exposed Pad should be soldered to the PBC to realize the thermal benefits 15 30 STPO8DP05 16 30 9 Test circuit Figure 13 DC characteristics OE DM2 CLK LE DM1 SD 519790 Figure 14 characteristics WORD GENERATOR OE DM2 CLK LE DM1 SDI GND 515470 Test circui STPO8DP05 Figure 15 Timing example for open and or short detection ul 04080415 10 N Z 40 Aq 4ejsibea snipis Josa eu 8519 312 eow euo 1 M 40443 sepoj 40211 9uj Duipbey snos 40413 ey Buuoejeg ej
5. 5 57 STPO8DP05 Low voltage 8 Bit constant current Led sink with full outputs error detection Features Low voltage power supply down to 3V m 8constant current output channels m Adjustable output current through external resistor Short and open output error detection Serial Data IN Parallel data OUT 3 3V micro driver able Output current 5 100mA 30MHz clock frequency Available in high thermal efficiency TSSOP exposed pad ESD protection 2 5kV HBM 200V MM Description The STPO8DPO5 is a monolithic low voltage low current power 8 bit shift register designed for LED panel displays The STPO8DP05 contains a 8 bit serial in parallel out shift register that feeds a 8 bitD type storage register In the output stage eight regulated current sources were designed to provide 5 100 constant current to drive the LEDs The STPO8DP05 is backward compatible in the functionality and footprint with STP8C L596 and extends its functionality with open and short detection on the outputs The detection circuit checks 3 different conditions that can occur on the output line short to GND short to or open line The data detection results are loaded in the shift register and shifted out via the serial line output Table 1 Device summary TSSOP16 Exposed pad WWM TSSOP16 The detection functionality is implemented without increasing the pin number through a secondary fun
6. twen OE DM2 pulse width 200 ns Vpp 3 0 to 5 0V tsETUP D Setup time for DATA 7 ns tuorp p Hold time for DATA 4 ns tseTUP L Setup time for LATCH 15 ns Clock frequency Cascade operation 1 30 MHz 1 If the device is connected in cascade it may not be possible achieve the maximum data transfer Please consider the timings carefully 6 30 STPO8DP05 Electrical characteristics Table 7 Electrical characteristics 4 Electrical characteristics 3 3 to 5V T 25 C unless otherwise specified Symbol Parameter Test conditions Min Typ Max Unit Vin Input voltage high level 0 7Vpp V Input voltage low level GND 0 3 Output leakage current 20V 0 5 10 LA Output voltage _ VoL Serial OUT 1 0 03 0 4 V Output voltage 22 _ Vou Serial OUT lou imA 0 4 V lout Vo 0 3V Rext 3 9kQ 4 25 5 5 75 loi Output current Vo 0 3V 9700 19 20 21 mA lois Vo 1 3V Rg4 1900 96 100 104 Output current error Vos AloL2 between bit Vo 0 3VRgxr 9700 1 5 3 Kog Vo 1 8 1900 12 3 Rsin up Pull up resistor 150 300 600 RsiN down Pull down resistor 100 200 400 KQ 980 4 5 DD OFF1 OUT 0 to 7 OFF Supply current OFF 250 IDD O
7. Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 30 30
8. FF2 OUT 0 to 7 OFF er 195 5 mA ExT 980 IDD ON1 OUT 0107 3 Supply current ON 250 IDD ON2 OUT 6 117 135 Thermal Thermal protection 1 170 C 1 Guaranteed by desing not tested The thermal protection switches OFF only the outputs current ky 7 30 Switching characteristics STPO8DP05 5 Switching characteristics Table 1 Switching characteristics 5V T 25 C unless otherwise specified Symbol Parameter Test conditions Min Typ Max Unit Propagation delay time 3 3V 35 70 CLK OUTn LE DM1 H ns OE DM2 L 5 18 35 Propagation delay time Vpp 3 3V 48 90 tpi LE DM1 OUTn ns OE DM2 L 5V 30 60 Propagation delay time Vpp 3 3V 55 110 tpi OE DM2 OUTn ns LE DM1 H 5V 36 75 Propagation delay time 3 3V 7 14 PLH CLK SDO Vpp 5V 4 8 Propagation delay time 3 3V 10 20 1 CLK OUTn LE DM1 H 3 3V lt Vpp ns OE DM2 L GND C 10pF 5V 7 14 Propagation delay time lo 20mA VL 3 0V vpp 3 3V 24 50 tPHL2 LE DM1 OUTn Rext 1KQ 2600 ns 2 L 5V 20 40 Propagation delay time Vpp 3 3V 20 40 3 OE DM2 OUTn ns LE DM1 H 5V 17 35 i Propagation delay time 3 3V 22 30 WE PHL CLK SDO 5V 18 25 Outp
9. RRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2007 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia
10. a In order to meet environmental requirements ST offers these devices in ECOPACK packages These packages have a Lead free second level interconnect The category of second Level Interconnect is marked on the package and on the inner box label in compliance with JEDEC Standard JESD97 The maximum ratings related to soldering conditions are also marked on the inner box label ECOPACK is an ST trademark ECOPACK specifications are available at www st com STPO8DP05 Package mechanical data Plastic DIP 16 0 25 MECHANICAL DATA 23 30 Package mechanical data STPO8DP05 TSSOP16 MECHANICAL DATA DIM A Al 0 05 A2 0 8 1 0 19 0 09 54 0 193 0 197 0 201 6 6 0 244 0 252 0 260 5 0 65 0 0256 K L 0 45 0 60 0 75 0 018 0 024 0 030 SY i PIN 1 IDENTIFICATION f 0080338D 24 30 4 STPO8DP05 Package mechanical data TSSOP16 EXPOSED PAD MECHANICAL DATA DIM MIN A A1 A2 0 8 b 0 19 0 09 4 9 D1 1 7 6 2 1 4 3 2 1 5 0 L 0 45 0 60 0 75 0 018 0 024 0 030 0 25 mm GAUGE PLANE
11. ating sections of this specification is not implied Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability Refer also to the STMicroelectronics SURE Program and other relevant quality documents Absolute maximum ratings Table 4 Absolute maximum ratings Symbol Parameter Value Unit Supply voltage lenp 0 to 7 V Vo Output voltage 0 5 to 20 V lo Output current 100 mA lenp GND terminal current 800 mA Clock frequency 50 MHz Topn Operating temperature range 40 to 125 C Storage temperature range 55 to 150 C Thermal data Table 5 Thermal data 16 0 DIP 16 50 16 880 16 1550 16 Unit Thermal resistance junction ambient 60 75 85 37 5 C W 1 The Exposed Pad should be soldered to the PBC to realize the thermal benefits 5 30 Maximum rating STPO8DP05 3 3 Recommended operating conditions Table 6 Recommended operating conditions Symbol Parameter Test conditions Min Typ Max Unit Vbo _ Supply voltage 3 0 5 5 Output voltage 20 V lo Output current OUTn 5 100 mA Output current SERIAL OUT 1 mA lot Output current SERIAL OUT 1 mA Input voltage 0 7Vpp 3 V Input voltage 0 3 0 3Vpp V LE DM1 pulse width 20 twcLk CLK pulse width 20 ns
12. ction of the output enable and latch pin DM1 and 2 respectively dedicated logic sequence allows the device to enter or leave from detection mode Through an external resistor users can adjust the STP08DP05 output current controlling in this way the light intensity of LEDs in addition user can adjust LED s brightness intensity from 0 to 100 via OE DM2 pin The STP08DP05 guarantees a 20V output driving capability allowing users to connect more LEDs in series The high clock frequency 2 also satisfies the system requirement of high volume data transmission The 3 3V of voltage supply is well useful for applications that interface any micro from 3 3V Compared with a standard TSSOP package the TSSOP exposed pad increases heat dissipation capability by a 2 5 factor Part Number Package Packaging STP08DP05B1R DIP 16 25 parts per tube STP08DP05MTR SO 16 Tape amp Reel 2500 parts per reel STP08DP05TTR TSSOP16 8 Reel 2500 parts per reel STP08DP05XTTR TSSOP16 amp Reel 2500 parts per reel May 2007 Rev 2 1 30 www st com STPO8DP05 Contents 1 Summary description 8 RC 3 1 1 Pin connection and description 3 2 Block diagram nee eee een 4 3 Maximum 5 3 1 Absolute maximum ratings
13. e 16 Entering in detection timing diagram CLK OE DM2 LE DM1 519510 After these five CLK cycles the device goes into the Error Detection and 6 rise front of CLK the SDI data are ready for the sampling STPO8DP05 Detection mode functionality 10 2 Phase two error detection The eight data bits must be set 15 in order to set ON all the outputs during the detection The data are latched by LE DM1 and after that the outputs are ready for the detection process When the Micro controller switches the OE DM2 to LOW the device drives the LEDs in order to analyze if an OPEN or SHORT condition has occurred Figure 17 Detection diagram z E Er i rd AT LEAST 1 us T i H H H H 7 6 5 4 Data Source of From Pin SDI From Error Detector From Pin SDI Shift Register 0819530 The LEDs status will be detected least 1 microsecond and after this time the microcontroller sets OE DM2 in HIGH state and the output data detection result will go to the microprocessor via SDO Detection mode and normal mode use both the same format data As soon as all the detection data bits are available on the serial line the device may go back to normal mode of operation To re detect the status the device must go back in normal mode and re enteri
14. n 3 Dn 5 5 x H Dn 3 OFF 5 OUTO to OUT7 when Dn OUTO to OUT7 OFF when L 11 30 Truth table and timing diagram STPO8DP05 7 2 Timing diagram Figure 7 Timing diagram normal mode LE DM1 O S 0 HIGH OE DM2 ov ON OUTO rT S S OFF OUT1sfvfbv OFF 0012 oo uo In 3J OFF ON OUT7 OFF HIGH s YW ov Figure 8 Clock serial in serial out DLYspo gt 4 12 30 STPO8DP05 Truth table and timing diagram Figure 9 Clock serial in latch enable outputs CLK 50 SDI tsetup2 LE DM1 50 50 war twena OE DM2 50 50 tseTups 50 tenis 517060 Figure 10 Outputs OFF 517070 13 30 Typical characteristics STPO8DP05 8 Typical characteristics Figure 11 Output resistor 2000 o 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 Ouput Current mA Temp 25 C Vdd 3 0V 0 3V 1 2V Iset 3mA 5mA 10mA 20mA 50mA 80
15. ng in error detection mode 19 30 Detection mode functionality STPO8DP05 10 3 Note 20 30 Phase three resuming to normal mode The sequence for re entering in normal mode is showed in the following Table and diagram Table 11 Resuming to normal mode timing diagram CLK 1 2 3 4 5 OE DM2 H L H H H LE DM1 L L L L L Figure 18 Resuming to normal mode timing diagram 1 5 OE DM2 L H LE DM1 L L Voltage Low For proper device operation the Entering in detection sequence must be follow by a Resume Mode sequence isn t possible to insert consecutive equal sequence STPO8DP05 Detection mode functionality 10 4 Note Error detection conditions Table 12 Detection condition Vpp 3 3 to 5 V Temperature range 25 C Open Line or Output SW 1 or SW 3b Short to GND gt lopec lt 0 5 x l NO eror Joss lopec gt 0 5 x lo detected detected Short on LED or Short No error u V lt 2 2 V SW 2 SW 3a to V LED detected ages ey detected 0 Where the output current programmed by the the detected output current in detection mode Figure 19 Detection circuit V LED 522590 21 30 Package mechanical data STPO8DP05 11 22 30 Package mechanical dat
16. ry 12 Revision history Table 13 Revision history Date Revision Changes 3 Apr 2007 1 First release 21 May 2007 2 Updated Table 7 on page 7 29 30 5 5 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WA
17. tput voltage Output current Between bits Between ICs 21 3V 1 5 5 20 to 100mA 1 1 Pin connection and description Figure 1 Connections diagram G 5 SDO L 0 0017 0 0016 0 0015 0 01014 CS19730 Note The Exposed pad is electrically not connected Table 3 Pin description PIN N Symbol Name and function 1 GND Ground terminal 2 SDI Serial data input terminal 3 CLK Clock input terminal 4 LE DM1 Latch input terminal 5 12 OUT 0 7 Output terminal 13 OE DM2 Output enable input terminal active low 14 SDO Serial data out terminal 15 R EXT Constant current programming 16 5V Supply voltage terminal 437 3 30 Block diagram STPO8DP05 2 Block diagram Figure 2 Normal mode block diagram OUTO OUT6 OUT7 UVLO E R EXT I REG 8 Open Short circuit detector Thermal Shutdown OENDM2 j X Output Enable 6 Control LENDM1 Logic 2 2 8X Data Latch 2 8X Shift Latch o SDO CLK N gt 4 30 STPO8DP05 Maximum rating 3 3 1 3 2 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Oper
18. ut rise time 3 3V 25 60 ton 10 90 of voltage _ ns waveform 5V 10 25 Output fall time 3 3V 5 15 torr 90 10 of voltage ns waveform 5V 4 12 t CLK rise time 0 5000 ns t CLK fall time 5000 ns 1 In order to achieve high cascade data transfer please consider tr tf timings carefully 8 30 STPO8DP05 Equivalent circuit and outputs 6 Equivalent circuit and outputs Figure 3 OE DM2 terminal Vpp e R Kup 300 OEN DM2o C SN 1KQ A Le GND 05151802 Figure 4 LE DM1 terminal 9 ENDM1 1 R I down 200K0 GND 05151907 Figure 5 CLK SDI terminal Vpp 9 CLK SDI o 1 GND o 05152002 9 30 Equivalent circuit and outputs 5 5 10 30 Figure 6 SDO terminal GND 05152202 500 STPO8DP05 Truth table and timing diagram 7 Truth table and timing diagram 7 1 Truth table Table 8 Truth table Clock LE DM1 2 SDI OUTO OUTO OUT7 SDO L Dn Dn Dn 5 Dn 7 Dn 7 L L Dn 1 No Change Dn 7 L Dn 2 Dn 2 Dn 3 Dn 5 Dn 5 X L Dn 3 Dn 2 D
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ST STP08DP05 handbook