FAIRCHILD 74F112 handbook
Contents
1. Applied to Output in LOW State Max 0 5V to Voc 0 5V to 5 5V twice the rated Io mA DC Electrical Characteristics Recommended Operating Conditions 0 C to 70 C 4 5V to 5 5V Free Air Ambient Temperature Supply Voltage Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired Functional operation under these conditions is not implied Note 2 Either voltage limit or current limit is sufficient to protect inputs Conditions Recognized as a HIGH Signal Recognized as a LOW Signal Min lin 18 mA Min lon 1 mA log 1 mA lip 19 uA All other pins grounded Vin 0 5V Jh Kn Vin 0 5V CP Vin 0 5V Con Spn Symbol Parameter Min Typ Max Units VoH Output HIGH 10 Voc 2 5 V Voltage 5 Voc VoL Output LOW 10 Vec lo 20 mA Voltage liH Input HIGH B 5 0 uA Max Vin 2 7V Current IBvi Input HIGH Current 70 A Ma TERT l xX T Breakdown Test i N ICEX Output HIGH V V Leakage Current ET Vip Input Leakage Test l lop Output Leakage Circuit Current liL Input LOW Current los Output Short Circuit Current 60 150 locH Power Supply Current 12 19 Vo HIGH locL Power Supply Current 12 19 Vo LOW 3 www fairchildsemi com clldvl 74F112 AC Electrical Characteristics k fax Maximum Clock Frequency PLH Propagation Delay tPHL CP to Qn or Qn tPLH Propagation Delay tPHL Con Spn to Qh Qn AC Oper2. 20 1 _ 0 4 0 8 TYP 0 35 0 50 M16D REV B 16 Lead Small Outline Package SOP EIAJ TYPE Il 5 3mm Wide Package Number M16D 5 www fairchildsemi com cllLdvl 74F112 Dual JK Negative Edge Triggered Flip Flop Physical Dimensions inches millimeters unless otherwise noted Continued 0 740 0 780 18 80 19 81 0 090 2 286 MRE PIN NO 1 IDENT OPTION 01 0 130 0 005 le Se 0 060 3 302 0 127 1 524 TYP 0 145 0 200 3 683 5 080 MIN Q 508 0 125 0 150 3 175 3 810 0 014 0 023 0 356 0 584 0 050 0 010 TYP eee 1 270 0 254 TYP 4 TYP aE OPTIONAL Se INDEX AREA 0 250 0 010 6 350 0 254 PIN NO 1 IDENT OPTION 02 ap 0 300 0 320 7 7 620 8 128 i or 4 95 5 0 008 0 016 O 4 Paci SEEN nad 0 203 0 406 P 0 030 0 015 7 112 0 762 0 381 MIN 0 100 0 010 0 040 2 540 0 254 0 325 0 015 ae N1GE REV F 8 255 ESHS 16 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL
3. OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user www fairchildsemi com 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsemi com
4. UO AF U U ee April 1988 FAIRCHILD Revised July 1999 SEMICONDUCTOR TM 74F112 Dual JK Negative Edge Triggered Flip Flop General Description Simultaneous LOW signals on Sp and Cp force both Q and The 74F112 contains two independent high speed JK flip i flops with Direct Set and Clear inputs Synchronous state Asynchronous Inputs changes are initiated by the falling edge of the clock Trig LOW input to Sp sets Q to HIGH level gering occurs at a voltage level of the clock and is not LOW input to Ga sets Q to LOW level directly related to the transition time The J and K inputs i can change when the clock is in either state without affect Clear and Set are independent of clock ing the flip flop provided that they are in the desired state Simultaneous LOW on Cp and Sp makes both Q during the recommended setup and hold times relative to and Q HIGH the falling edge of the clock A LOW signal on Sp or Cp prevents clocking and forces Q or Q HIGH respectively Ordering Code Order Number Package Description doj4 dij4 poo66uy o6py eanebon yr eng Zkkldtz 74F112SC Mi6A 16 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow 74F112SJ M16D 16 Lead Small Outline Package SOP EIAJ TYPE II 5 3mm Wide 74F112PC N16E 16 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide Devices also available in Tape and Reel Specify by appending the suffix letter X to the ordering code Logic Symbols Connec
5. ating Requirements Parameter Setup Time HIGH or LOW J or Kp to CP CP Pulse Width HIGH or LOW Pulse Width LOW Con or Spn Recovery Time SDr Con to CP www fairchildsemi com Min Typ Max Mn typ es 2 0 2 0 2 0 2 0 Ta 25 C Vec 5 0V 4 0 5 0 3 0 3 5 ns Hold Time HIGH or LOW J or Kp to CP 4 5 5 0 ns 4 5 5 0 Ta 0 C to 70 C Vcc 5 0V rs Units CL 50 pF MHz ns ns Ta 0 C to 70 C Vec 5 0V Units ns i Physical Dimensions inches millimeters unless otherwise noted 0 386 0 394 9 804 10 00 0 228 0 244 30 5 791 6 198 TYP LEAD NO 1 IDENT 0 010 MAX 0 254 0 150 0 157 3 810 3 988 0 010 0 020 0 053 0 069 0 254 0508 E 1 346 1 753 0 004 0 010 8 MAX TYP 0 102 0 254 ALL LEADS Wo Sh Y SEATING a rote Tt B j PLANE as 0 014 014 ve ue eae sane 0355 q 0 014 0 020 typ 0 203 0 254 aaa si ay 0 356 0 508 TYP ALL LEADS ed A TYP 0 004 TYP ALL LEADS 8 typ 0 102 o 205 M16A REV H ALL LEAD TIPS 16 Lead Small Outline Integrated Circuit SOIC JEDEC MS 012 0 150 Narrow Package Number M16A 16 9 a T ai 0 295 0 319 7 5 8 1 0 205 0 213 5 2 5 4 Tone SEA yp i i 0 15 0 25 0 067 0 083 Sra Ga nP 1 7 2 1 t gt 0 006 0 15 SEATING x 0 049 0 050 _ y TYP i i PLANE 1 27 YP ay CEERI Cr z5y TYP 0 016 0 031 0 014 0 0
6. tion Diagram 1999 Fairchild Semiconductor Corporation DS009472 www fairchildsemi com 74F112 Unit Loading Fan Out Input ali Description HIGH LOW Output loH loL J1 Jo Ky Ko Data Inputs 1 0 1 0 20 uA 0 6 mA CP CP Clock Pulse Inputs Active Falling Edge 1 0 4 0 20 pA 2 4 mA Cp1 Cp2 Direct Clear Inputs Active LOW 1 0 5 0 20 uA 3 0 mA Sp1 Sp2 Direct Set Inputs Active LOW 1 0 5 0 20 uA 3 0 mA Q4 Qo Q4 Qv Outputs 50 33 3 1 mA 20 mA Truth Table 0 Ol o S z H X L X L X H pe H H pE H H h HIGH Voltage Level L I LOW Voltage Level X Immaterial HIGH to LOW Clock Transition Qo Qog Before HIGH to LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH to LOW clock transition Logic Diagram One Half Shown Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays www fairchildsemi com 2 Absolute Maximum Ratings note 1 Storage Temperature 65 C to 150 C Ambient Temperature under Bias 55 C to 125 C Junction Temperature under Bias 55 C to 150 C Voc Pin Potential to Ground Pin 0 5V to 7 0V Input Voltage Note 2 0 5V to 7 0V Input Current Note 2 30 mA to 5 0 mA Voltage Applied to Output in HIGH State with Vec OV Standard Output 3 STATE Output Current
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FAIRCHILD 74F112 handbook