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ST AN2632 Application note handbook

1. C77 AN2632 Sf Application note Communication between small page NAND and ST72651AR6 using VO s Introduction This application note presents the practical example of communication between microcontroller and NAND Flash using general purpose input output ports GPIOs This document describes the hardware connections and software necessary to establish communication between the STMicroelectronics small page NAND Flash memory and input output ports of the ST7 microcontroller We have used the ST72651AR6 for the firmware description but any ST7 MCU can be used as well The devices covered by this application note are m NAND128W3A m NAND256W3A m NAND512W3A m NANDO1GW3A October 2007 Rev 1 1 12 www st com Contents AN2632 Contents 1 NAND Flash overview 00000 cece ee eee eee eee eee eee 3 1 1 Signal description as ss be EERDER ED ee Bad WE ER DA HE Ee ee oe 3 1 2 Memory array organization se ee ee es see ee ek ke eee 4 2 Hardware interface with microcontroller 0 0000ee ewes 6 3 Firmware oerset deg Ee eee een eee cede PEGG eee eels 6 3 1 NAND basic functions 0 0 0 ce ee ee ee eee 6 3 2 Remaining NAND functions EE EE EE Ee ee ee 10 4 Reler nces osse SEE ED ED ED AD SEE Ee De aus 10 5 REVISION history ss rs Ee ee N Ee RES Ke ov wees GR RR RR SEWE es 11 2 12 ky AN2632 NAND Flash overview NAND Flash overview The NAND Flash 528 Byte 264 Word page is a
2. accept any program or erase operations 3 12 NAND Flash overview AN2632 Table 1 Small page NAND Flash signal description continued Signal Vcc Signal name Description VCC provides the power supply to the internal core of the memory device It is the Supply voltage main power supply for all operations read program and erase It is in the range of 1 65 1 95 V for 1 8 V devices and 2 7 3 6 V for 3 V devices Vss Ground is the reference for the power supply It must be connected to the system Ground ground 1 2 4 12 Figure 1 Logic diagram of NAND Flash E VO 8 VO16 x16 R VO 0 VOT7 x8 x16 W NAND AL Flash CL WP Memory array organization The memory array is organized in blocks where each block contains 32 pages The array is split into two areas the main area and the spare area The main area of the array is used to store data whereas the spare area is typically used to store error correction codes software flags or bad block identification In x8 devices the pages are split into a main area with two half pages of 256 Bytes each and a spare area of 16 Bytes In the x16 devices the pages are split into a 256 Word main area and an 8 Word spare area In this application note the communication with x8 devices is explained Thus the memory map is divided as BLOCKS each having 32 pages and each page in turn having 528 Bytes The n
3. family of non volatile Flash memories that uses the Single Level Cell SLC NAND cell technology It is referred to as the small page family The devices range from 128 Mbits to 1Gbit and operate with eithera 1 8 V or 3 V voltage supply The size of a page is either 528 Bytes 512 16 spare or 264 Words 256 8 spare depending on whether the device has an x8 or x16 bus width The address lines are multiplexed with the data input output signals on a multiplexed x8 or x16 input output bus 1 1 Signal description Table 1 describes all the small page NAND Flash signals Figure 1 shows the logical diagram of NAND Flash Table 3 describes the microcontroller signals used to connect to the small page NAND devices Table 1 Small page NAND Flash signal description Signal Signal name Description 08 15 Data input outputs Input outputs 8 to 15 are only available in x16 devices They are used to output the data during a read operation or input data during a write operation Input outputs 0 to 7 are used to input the selected address output the data during a i read operation or input a command or data during a write operation VOO 7 Data input outputs P p The inputs are latched on the rising edge of write enable VOO VO7 can be left floating when the device is deselected or the outputs are disabled AL Address latch The address latch enable activates the latching of the address inputs in the command enable Interface When AL is high
4. d also the block number which is to be addressed With the user specified information this function reads the page data and stores it in an array data readi The user can read this array in his main program to get the data received from NAND signature This function when called reads the electronic signature and serial number of the device These data are stored in the variable named as manufacturer_code for electronic signature and device_code for serial number statusreg_read This function is used to read the status register of NAND and return the status Figure 6 shows the different signal status for data output cycle 9 12 References AN2632 3 2 10 12 Figure 6 Data output cycle tRLRL gt E Read Cycle time R High Hbid tme tBHRL RB lt gt tRHOX Write protect writeprotect_enable and writeprotect_disable This cycle is used to protect the device from any write and erase operation When the write protect signal is low then the device is write protected Calling the writeprotect_enable function protects the device from any access to the information stored in it while writepotect_disable function makes the device accessible Remaining NAND functions There are additional functions used in the NAND VO communication 1 nand_io_init this function is used to initialize the I O s to the default state for communication with NAND Flash 2
5. d interface The commands are input on 1 O0 I O7 and are latched on the rising edge of write enable when the command latch enable signal is high Device operations are selected by writing specific commands to the command register The command registers are summarized in Table 4 Figure 3 shows the signal status at different lines for command input operation AN2632 Firmware g Table 4 Command register Bus write operations Command Command accepted during busy 15t cycle 2 d cycle 3 d cycle Read A OOh Read B oth Read C 50h ae Read status register 70h Yes Page program 80h 10h Copy back program 00h 8Ah 10h Block erase 60h DOh Reset FFh Yes 1 The bus cycles are only shown for issuing the codes The cycles required to input the addresses or input output data are not shown 2 Any undefined command sequence is ignored by the device Inside the header file nand_io h the command types are defined as e define nand_area_A 0x00 define nand_area_B 0x01 define nand_area_C 0x50 define nand _readstatusreg 0x70 define nand _pageprogram 0x80 define nand _endpageprogram 0x10 define nand _read_electsign 0x90 define nand _blockerase 0x60 define nand _confirmerase OxDO define nand _reset OXFF 7 12 Firmware AN2632 Figure 3 Command input bus operations CL tCLHWL tWHCLL CL Setup time CL Hold time _tELWL tWHEH E Setup time E Ho
6. ld time E tWLWH WwW tALLWL tWHALH ALSetup time AL Hold time A ea tDVWI tWHDX Data Setup time Data Hold time 2 Address input cycle address column address page address block address Address Input bus operations are used to input the memory address Three bus cycles are required to input the addresses for the 128 Mb and 256 Mb devices and four bus cycles are required to input the addresses for the 512 Mb and 1 GB devices refer Table 1 Thus the user can access any specific location in the memory by giving its column location page location and block number There are 256 columns in both the first half page area A and the second half page area B The total number of pages is 32 in each block and the total number of blocks in NAND 512W3A is 4096 Figure 4 shows the signal status during the address transmission Figure 4 Address input bus operation lt gt tCLLWL CL Setup time CL _ tELWL tWLWL gt lt twLWL gt lt twLwL gt E Setup time E tWLWH E WwW tALHWL tWHWL gt AL Setup time tWHAL AL Hoki time i AL tDVWH Data Setup time tWHDX VO 3 Data input cycle nand write unsigned char data page number column number block number number of bytes Data Input bus operations are used to input the data to be programmed Data is accepted only when chip enable is low address latch is low command latch enable is low and read enable i
7. ment shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2007 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com g 12 12
8. ntroller In this application note we have used the ST72651AR6 microcontroller The I O pins and their connections with NAND are explained in Table 3 Table 3 Port mapping of microcontroller and NAND Pins port of microcontroller NAND pin PBO PB7 Port B 1 00 1 O7 PAO Port A pin0 CLE PA1 Port A pin1 WE PA2 Port A pin2 ALE PA3 Port A pin3 R PA4 Port A pin4 R B PA7 Port A pin7 WP PEO Port E pin0 CE Firmware The example firmware for NAND communication through I O s is organized in two files nand_io c and nand_io h In the header file nand_io h there are function prototypes In the file nand_io c all the functions to use the NAND Flash device are implemented All the source files are in C language and the application uses ST7 firmware library functions The source files are only for guidance STMicroelectronics shall not be liable for any direct indirect or consequential damages with respect to any claim arising from use of this software NAND basic functions There are 5 basic operations in NAND Flash which control its functionality 1 Command Input command command type Command input bus operations are used to give commands to the memory Commands are accepted when chip enable is low command latch enable is high address latch enable is low and read enable is high All bus write operations to the device are interpreted by the memory comman
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10. readpulses this function is used to generate the pulsating read pulses in the case of nand read mode 3 writepulses this function is used to generate write pulses in the case of writing to NAND Flash 4 block erase block number this function is used to erase the complete block The user needs to enter the block number which is to be erased 5 bad block decleration block number this function is used to declare the block as bad block The user must pass the block number which is to be declared as bad block References 1 STNAND512W3A datasheet 2 ST7 software library user manual AN2632 Revision history 5 Revision history Table 5 Document revision history Date Revision Changes 18 Oct 2007 1 Initial release 11 12 AN2632 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express o
11. s high The data is latched on the rising edge of the write enable signal The data is input seguentially using the write enable signal This function is 8 12 ky AN2632 Firmware Note called nand writing The user must pass the address of the variable which stores the data which is to be written in NAND User can store the data bulk in an array in the main program and then finally pass the array pointer to this function for writing NAND Flash supports the page write mode Thus for the same page only three consecutive write cycles are allowed and after that the user has to erase the whole block before being able to write again Refer datasheet of NAND Signal status at the time of sending the data is shown in Figure 5 Figure 5 Data input cycle e gt tWHCLH CL Hoki time cL gt tWHEH E Hod time ml AL 4 Data output cycle Data output bus operations are used to read the data in the memory array the status register electronic signature and serial number Data is output when chip enable is low write enable is high address latch enable is low and command latch enable is low The data is output sequentially using the read enable signal a c nand_read bytes page number block number This function is used to read bytes from the specified page of a specified block The user must pass the number of bytes to be read 0 512 bytes the page number from where to read an
12. the inputs are latched on the rising edge of write enable Command iat h The command latch enable activates the latching of the command inputs in the CL enable Command Interface When CL is high the inputs are latched on the rising edge of write enable E Chip enable The chip enable input activates the memory control logic input buffers decoders and P sense amplifiers When chip enable is low VIL the device is selected The Read Enable controls the seguential data output during Read operations Data is R Read enable valid after the falling edge of R The falling edge of R also increments the internal column address counter by one The Ready Busy output is an open drain output that can be used to identify if the P E R controller is currently active When ready busy is low VOL a read program or erase operation is in progress R B Ready bus My When the operation completes ready busy goes high VOH The use of an open drain output allows the ready busy pins from several memories to be connected to a single pull up resistor A low then indicates that one or more of the memories is busy aw Write enable The write enable input controls writing to the command interface input address and data latches Both addresses and data are latched on the rising edge of write enable The write protect pin is input that gives hardware protection against unwanted WP Write protect program or erase operations When write protect is low VIL the device does not
13. umber of BLOCKS is decided on the basis of the NAND Flash we are using This application note explains the communication using NAND512W3A NAND Flash The memory organization for NAND512W3A is as follows 4096 BLOCKS 32 pages in each BLOCK 528 Bytes in each page Figure 2 shows the memory arrangement for x8 devices AN2632 NAND Flash overview Figure 2 Memory arrangement for x8 NAND Flash x8 DEVICES Block 32 Pages Page 528 Bytes 512 16 Page Buffer 512 Bytes Byes 8 bits A Thus to access the specific location in Flash the user must address the column number page number and the block number The addressing is done through the address insertion on the data line The address cycles for x8 devices are shown in Table 2 Table 2 Address insertion x8 devices Bus cycle 1 07 1 06 1 05 1 04 1 03 1 02 1 01 1 00 jet A7 A6 A5 A4 A3 A2 A1 AO pnd A16 A15 A14 A13 A12 A11 A10 A9 grd A24 A23 A22 A21 A20 A19 A18 A17 4th VIL VIL VIL VIL VIL VIL A26 A25 Note A8 is don t care in x16 devices any additional address input cycles are ignored the 4 cycle is only required for 512 Mb and 1Gb devices ky 5 12 Hardware interface with microcontroller AN2632 2 3 1 6 12 Hardware interface with microcontroller NAND Flash is connected to the microcontroller through the I O ports All the signals of the NAND Flash are connected to the I O ports of the microco

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