ST AN1365 APPLICATION NOTE Manual
Contents
1. ST72F264 Option Bytes aa ee o USER OPTION BYTE 1 USER OPTION BYTE 0 OSC OSC OSC OSC TYPE TYPE RNGE RNGE 1 0 2 1 LVD low and high configuration levels have been swapped 11 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 Figure 8 ST72C254 and ST72F264 LVD Configuration Levels ST72C254 ST72F264 Configuration LVD1 LVDO Configuration LVD Off 1 1 LVD Off Highest threshold 0 Highest threshold Medium threshold Medium threshold Lowest threshold Lowest threshold Moreover please take note that LVD levels values between the ST72C254 and the ST72F264 may differ a little bit Please refer to the datasheet of the respective devices Electrical param eters part to get them 12 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME AS A RESULT STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH A NOTE AND OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS Information furnished is believed to be accurate and reliable However STMicroelectroni2. been added to the ST72F264 By default the interrupt manage ment is concurrent Some dedicated registers ISPRx make it possible for the user to con figure the priority level up to 4 for all the interrupts Please refer to the datasheet for more in formation 5 2 16 BIT TIMER PWM AND ONE PULSE MODE The 16 bit timer of the ST72C254 has been modified in the ST72F264 to improve the PWM and One Pulse modes If you use either of these two modes you may need to change your software when transferring code from the ST72C254 to the ST 72F 264 All the other modes of the timer do not change 5 2 1 PWM Mode To avoid any uncontrolled status on the PWM output a double buffering on the output com pare registers 2 x 16 bits is implemented in the ST72F264 This double buffering is not present in the ST72C254 In the ST72F264 PWM mode any new values written in the four OC1R and OC2R registers are taken into account only at the end of the PWM period OC2 event to avoid spikes on the PWM output Note Any modification on the OC1R and OC2R registers must be done just after the OC2 event using the ICF1 interrupt routine for example 5 2 2 One Pulse Mode When the ICAP1 event occurs on falling or rising edge the following sequence occurs 1 IC1R is loaded with the value of the counter when the event occurred not FFFDh as in the ST72C254 2 The counter is immediately reset to FFFCh not at the end like in the ST72C254 3 OLVL2 is appli
3. 64 device and subsets there is no backup oscillator frequency 3 3 PHASE LOCKED LOOP PLL A PLL has been added in the ST72F264 in order to be able to multiply the oscillator frequency by 2 for a fosc input frequency between 2 and 4 MHz This PLL is activated through an op tion bit Figure 1 PLL Diagram 2 PLL OPTION BIT Note Use of the PLL with the internal RC oscillator is not supported 3 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 3 4 WATCHDOG TIMINGS In the ST72F264 the watchdog timeout does not have an exact duration as in the ST72C254 It may vary between the min and max times specified in Figure 3 To guarantee upward compatibility you have to take this into account when you develop your software The reason for this change is that the watchdog counter has been grouped with the Active HALT counter and SLOW mode prescaler to enhance power consumption and EMC performance Figure 2 Watchdog Block Diagram CODES 6 BIT DOWNCOUNTER CNT 12 BIT MCC RTC COUNTER WDG PRESCALER TB 1 0 bits DIV 4 The watchdog counter is no longer clocked by fcpy as it was for the ST72C254 but by fosc2 divided by 16384 fosc2 is the PLL output frequency when the PLL is activated or fog 2 fcpu if the PLL is disabled In the ST72F264 datasheet the linear relationship between the 6 bit value to be loaded in the Watchdog Counter CNT and the resulting timeout duration in milliseconds is desc
4. AN1365 ky APPLICATION NOTE GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 INTRODUCTION This application note provides information on using ST72264 new series in an application orig inally designed for the ST 72254 215 216 104 series 1 FEATURE OVERVIEW Feature S172104 S172215 S172216 ST720254 ST72260 5172262 ST72F264 SDIP32 S028 no change 128 bytes no change 28 pins see Section 2 2 Pinout 2 minor change in pee eS ee Yes xi Yes 10 bi Emulator _ST MDTI EMU2B and STIMTDI DVP2_ ___ST7MDTIO EMUS og orong ST7MDT1 EPB2 and ST7MTD1 DVP2 ST7MDT10 EPB and ST7MDT10 tools DVP3 Note 1 refer to the corresponding datasheets for more information on electrical characteristics Note 2 Go to http www st com gt Products gt Product Support gt Microcontrollers Forum for information on third party tools Rev 2 0 AN1365 0504 1 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 2 PINOUT COMPATIBILITY 2 1 PACKAGE All devices are available in SDIP32 and SO28 packages 2 2 PINOUT Some pins have been changed in the pinout of the ST72F264 and subsets device to add the SCI peripheral see Table 1 and to move the ISP pins which have become ICC pins see Table 2 For more information about ICC In Circuit Communication protocol please refer to the ST7 FLASH Programming and ICC Reference Manuals available on Internet http www st com Table 1 Additi
5. IGRATING ST72C254 APPLICATIONS TO ST72F264 Figure 4 Register Map Modifications ST72C254 ST72F264 Register Label Register Bloor Fr aon sca SPIDR SPICR SPICSR fooesn orsa Er SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR ADCCSR ADCDRH ADCDRL 7 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 4 2 REGISTER MODIFICATIONS 4 2 1 CRSR Register The CRSR Clock Reset and Supply Register register has been replaced by the SICSR System Integrity Control Status Register register see Figure 5 This SICSR register con tains the bits related to the AVD feature Figure 5 CRSR Register Changes CRSR 0025h SICSR 0025h Clock Reset and Supply Register System Integrity Control Status Register 7 css 0 D 4 2 2 SPI SS pin The SPI SS pin alternate function is controlled from the MISCR2 like previously but these control bits have also been duplicated into the SPICSR register in three unused locations Figure 6 SS pin control WCO MOD SPIF L F SPICSR 0023h SPI Control Status Register MISCR2 0040h Both registers can be used to control the SS pin 8 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 5 NEW FEATURES AND PERIPHERALS 5 1 NESTED INTERRUPTS A nested interrupt feature has
6. cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2004 STMicroelectronics All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States www st com 13 13
7. ed to OCMP1 pin if OC1E 1 4 ICF1 is set 9 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 5 3 SPI 5 3 1 Control Status register bits The SPISR in the ST72C254 has been replaced by the SPICSR in the ST72F264 refer to Figure 4 Their differences are the following ones the SPI SS pin alternate function is controlled from the MISCR2 as previously but these control bits have also been duplicated into the SPICSR register a the Overrun flag has been added into the ST72F264 SPICSR register 5 3 2 HALT mode The ST72F264 is able to exit from HALT mode through an SPI interrupt This is not the case in the ST72C254 To guarantee upward compatibility if the SPI is used in slave mode the SPI interrupt must be masked via the SPE or SPIE bits during HALT mode to avoid any un wanted wake up events 5 4 10 BIT ADC To meet application requirements for increased resolution the ST72F264 has a 10 bit ADC compared to the 8 bit ADC in the ST72C254 For upward compatibility both ADCs have iden tical control registers and operating modes The 8 most significant bits of the ST72F264 data register ADCDRH are used in place of the ADCDR register of the ST72C254 The 8 least significant bits of the ST72F264 data register ADCDRL have been added to reach a 10 bit conversion If ADCDRL is read first ADCDRH is locked until read which means that no max imum time is imposed between an ADCDRL read and an ADCDRH read and a 10 b
8. it conver sion will be performed Then ADCDRL and ADCDRH are ensured to correspond to the same conversion If ADCDRH is read first ADCDRL is lost and an 8 bit conversion equivalent to the ST72C 254 one will be performed 5 5 MISCELLANEOUS Many new features have been added in the ST72F264 refer to Figure 4 a MCC Main Clock Controller a ITC Interrupt Controller a FSCR register Flash Status Control Register a SCI Serial Communication Interface peripheral Please refer to the datasheet for more information concerning the operation of all these fea tures and peripherals 10 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 6 OPTION BYTES Option bits have been added split or replaced in the ST72F264 compared to the ST72C254 see Figure 7 Oscillator type bits have been added in order to select a best range of backup safe oscillator CFC Clock Filter Control bit has been removed FMP Full Memory Protection bit has been split into 2 bits FMP_R read protection and FMP_W write protection SEC 1 0 bits have been added to select the ST72F264 sector 0 size PLL selection bit has been added External RC clock option is no longer supported with ST72F264 device For more information concerning these option bits please refer to the datasheet Figure 7 ST72C254 and ST72F264 Option Bytes ST72C254 Option Bytes USER OPTION BYTE 0 USER OPTION BYTE 1 Reserved
9. n writing to the CR register 5 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 4 REGISTER MAP In the ST72F264 some register addresses and bit locations are changed These changes have made it possible to use the free locations to add new features Note For easy software migration two general rules have to be followed All reserved byte memory areas must never be read or write a All reserved or unused bits must be left unchanged when accessing the byte 4 1 REGISTER ADDRESS These changes are classified in three groups 1 New features added Interrupt Controller ITC Main Clock Controller MCC Serial Com munications Interface SCI Flash Control Status Register FCSR 2 CRSR Clock Reset Supply Control Status Register has been replaced by the SICSR System Integrity Control Status Register Two bits relative to the AVD Auxiliary Voltage Detector feature have been added into the SICSR register Bits relative to the CSS are no longer used SPISR Serial Peripheral Interface Status Register changed to SPICSR Serial Peripheral Interface Control Status Register Refer to the Section 5 3 1 for more information 3 ADC registers changed Please refer to the datasheet for the description of the new features Note These register address changes can be easily performed if you group all the register definitions in a single header file 6 13 GUIDELINES FOR M
10. on of SCI Pins ST72F264 only SDIP32 Package TDO pin 20 RDI pin 22 028 Package TDO pin 18 RDI pin 20 Table 2 Pin Changes ST72C254 and Subsets ST72F264 and Subsets SDIP32 Package SO28 Package SDIP32 Package S028 Package ICCCLK pin 29 ICCCLK pin 25 ISPCLK pin 5 ISPCLK pin 5 ISPDATA pin 6 ISPDATA pin 6 ICCDATA pin 28 ICCDATA pin 24 TDO is the Transmit Data Output pin and RDI is the Receive Data Input pin of the SCI Serial Communication Interface peripheral 2 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 3 TIMING 3 1 CYCLE ACCURACY All timings are compatible between the ST72C254 and the ST72F264 devices except internal timings linked to the cycle accuracy The ST72C254 is based on latches gates while the ST72F264 is based on RTL flip flop Therefore a difference of a half cycle may occur be tween those two devices This means that all software with timings based on fixed processor cycle times a practice not recommended must be verified in detail An example of this would be a software wait loop im plemented as a sequence of NOP instructions as opposed to polling a busy bit This internal difference does not affect the general timings 3 2 CLOCK SECURITY SYSTEM CSS The backup oscillator of CSS available in the ST72C254 device and subsets has a fixed fre quency between 250 kHz and 550 kHz in normal conditions T 25 and Vdd 5V In the ST72F2
11. ribed This can be used for a quick calculation without taking the timing variations into account If more precision is needed use the formulae in Figure 3 4 13 GUIDELINES FOR MIGRATING ST72C254 APPLICATIONS TO ST72F264 Figure 3 Exact Timeout Duration tmin and tax fosc2 8 MHz tmino LSB 128 x 64 x tosce tmaxo 16384 x tosc2 tosc2 125ns if fosc2 8 MHz CNT Value of T 5 0 bits in the WDGCR register 6 bits MSB and LSB are values from the table below depending on the timebase selected by the TB 1 0 bits in the MCCSR register TB1 Bit TBO Bit Selected MCCSR MCCSR MCSA Res MCCSR MCSA Reg Timebase To calculate the minimum Watchdog Timeout tmin 16384 X CNT Xt osc2 IF CNT lt MEE THEN tain tring 4CNT ELSE th MSB n mino 16384 x enT ise 4CNT 192 LSB x 64x Tee J tosc2 To calculate the maximum Watchdog Timeout tmax IF CNT lt MOS THEN taa t 16384 X CNT Xt max0 osc2 4CNT 4CNT ELSE thax tmaxo 16384 x NT HN 192 LSB x 64x F525 Set aks Note In the above formulae division results must be rounded down to the next integer value Example With 2ms timeout selected in MCCSR register Min Watchdog Max Watchdog Value of T 5 0 Bits in Timeout ms Timeout ms WDGCR Register Hex tmin tmax 1 496 2 048 128 128 552 Note The timing variation shown in Figure 3 is due to the unknown status of the prescaler whe
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ST AN1365 APPLICATION NOTE Manual