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ST AN432 APPLICATION NOTE handbook

1. 4 4 12 USING ST62xx I O PORTS SAFELY 2 1 0 PIN OPTIONS Each ST62 I O pin with Analog capability can work as a push pull output an open drain output a schmitt trigger input with internal 100K pull up a schmitt trigger input without pull up an interrupt input with schmitt trigger and internal 100K pull up an analog input connected to the Analog to Digital converter As described in the previous section each bit of the I O port can have different characteristics each bit is completely independent of the others each bit has its own control bits defining its operation mode the bit operation modes can be changed by software at any time Figure 4 I O port with pins in different functions data reg option reg data dir reg pin core interrupt VR001529 An example of a potential I O port configuration is shown in Figure 4 Pin 0 is in push pull output mode outputting a high level pin 1 is in open drain output mode and presents a high impedance this is because DR is 1 causing the pull down resistor to be turned off Pin 2 is in input mode with pull up pin 3 is in input mode without pull up while pins 4 and 5 are inter rupt inputs pin 6 is analog input and pin 7 is an input without pull up Only one pin of an ST62XX should be switched to analog input mode at any time Otherwise all pins switched to analog input mode will be connected together via the analog switches RD
2. AN432 Ky APPLICATION NOTE USING ST62xx I O PORTS SAFELY by J Stockinger INTRODUCTION All members of the ST62 Series of Microcontrollers from STMicroelectronics feature I O ports with configurable bit functions In addition many I O bits may be set as inputs to the on chip Analog to Digital Converter This port bit function is in addition to the normal I O functions of input with or without internal pull up resistor output open drain or push pull or edge level selectable interrupt input with pull up This flexibility makes the ST62 series suitable for many industrial control applications and for many other uses This application note explains the architecture of the I O bit associated with these port func tions and provides some indications on the correct use of these features for functions such as keyboard scanning and analog inputs The correct manner to switch between these function is also demonstrated in order to prevent potential malfunctions in operation Rev 1 1 AN432 1203 1 12 USING ST62xx I O PORTS SAFELY 1 1 0 PORT STRUCTURE The ST62 I O Port with Analog Input hereafter referred to as I O port is comprised of 8 iden tical bit structures as shown in Figure 1 These include the interface to the ST62 internal dat abus and the three registers selecting the programmable options I O Ports without the analog capability are identical with the exception of the analog input buffer and control logic The control regi
3. SON 1 4 kQ ky 5 12 USING ST62xx I O PORTS SAFELY When using the interrupt input with more than one pin configured for this function all pins will be connected together in a logical AND function to the same core interrupt input line A low signal at any of the inputs will pull the core interrupt line low signifying an interrupt event To get a high signal at the core interrupt line ALL interrupt inputs must be high Figure 5 Interrupt schematic for one I O pin PORT BIT ENABLE SINGLE BIT VRO01530 lt 4 6 12 USING ST62xx I O PORTS SAFELY 3 OPERATION OF SINGLE BIT INSTRUCTIONS The ST62XxX instruction set includes four different instructions operating on single bits The first two instructions use a read modify write cycle SET Set Bit in Register RES Reset Bit in Register JRS Jump Relative IF Bit in Register is set JRR Jump Relative IF Bit in Register is reset The single bit instructions read a whole byte 8 bits perform an AND RES JRR or OR SET JRS operation with a single bit mask operand e g 01h for bit 0 04h for bit 2 and in the case of SET and RES write the result back to the source Thus the whole byte is processed even if only one bit is modified or tested This causes some constraints in using these instructions with the Data Register Table 2 Example for the operation of a single bit instruction RAM Before RAM After Address Data Addre
4. ain open drain Tin pushpull pushpull XXX DDR OR DR VR001533 lt 4 11 12 USING ST62xx I O PORTS SAFELY THE PRESENT NOTE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME AS A RESULT STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH A NOTE AND OR THE USE MADE BY CUSTOMERS OF THE INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2003 STMicroelectronics All rights reserved STMicroelectronics GROUP OF COMPANIES Australia Be
5. ddress for 3 purposes writing to the DR reading the DR content reading the state of the I O pin With this convention the data read from the DR register may come from two different sources the DR output and the I O pin The source is selected by a multiplexer controlled by the state of the DDR If the DDR bit corresponding to the I O pin contains a 1 the port pin is set to output Subse quent read accesses to DR will return the content of the DR ky 3 2 USING ST62xx I O PORTS SAFELY If the DDR bit corresponding to the I O pin contains a O the port pin is set to input Subse quent read accesses to DR will return the state of the I O pin This means that the DR bit is ef fectively Read Only when the bit is in Output mode To read the content of any DR bit set to input mode a copy of the DR content previously written must be saved in Data RAM Writing to the DR bit is possible in both input and output modes It is important to note this as in input mode DR is used to set the input pin characteristics table 1 Due to the flexibility of programming each I O bit individually some pins of a port may be configured to input mode and others to output mode Reading the DR will return some DR bit contents from pins in output mode and some O pin states from pins in input mode combined in the one byte As will be shown in a following section this can create serious system malfunctions if care is not taken lt
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7. mmended that the OR should be used primarily for switching of pin input operating modes This register switches the port bits from input without pull up to analog input or switches from input mode with pull up to interrupt input with pull up Transition diagrams showing the optimum coding sequence for modifying the states are shown in the following fig ures 4 8 12 USING ST62xx I O PORTS SAFELY 4 MODE TRANSITION DIAGRAMS Figure 6 shows the recommended transfer sequence for changing from one state to another no other transitions should be used Figure 6 Diagram for safe transitions input pullup interrupt pullup analog in open drain pushpull pushpull XXX R OR DR ganas VROO1531 Figure 7 illustrates the transitions which are most likely to cause a change of operation mode causing unwanted side effects such as false interrupt generation or two pins being shorted to gether via the analog input line 9 12 USING ST62xx I O PORTS SAFELY Figure 7 Diagram for risky transitions input pullup interrupt pullup open drain pushpull pushpull XXX R OR DR pee VROO1532 Figure 8 demonstrates the False transitions that can occur with SET RES instructions de pending on the state of the I O pins 10 12 USING ST62xx I O PORTS SAFELY Figure 8 Diagram for I O data register False transitions input pullup a O pin 1 input interrupt pullup b 1 O pin 0 c 1 O pin 0 d O pin 1 open dr
8. ss Data SET 3 085h 085h 055h 055h 01010101 B 085h 05Ch OR 008h 00001000 B 05Ch 01011101 B Restrictions in using SET and RES instructions As an example let us assume that one or more of the pins of the port are set to input mode A SET RES operation on a bit of DR will read the state of the corresponding input pin instead of the content of DR After modifying the specified bit the result will be written as a byte back into DR Depending on the state of the specified inputs the contents of DR may be changed This can cause a Change of the input mode by accident that is depending on the state of the corre sponding bit in OR the pin operation mode can be switched from input mode with pull up to input mode without pull up or vice versa or from interrupt mode to analog input or vice versa These side effects on the I O port may be avoided if a copy of the DR content is kept in a RAM location Now SET RES instructions can be executed on the RAM location and the result then written to DR as shown in Table 3 lt 4 7 12 USING ST62xx I O PORTS SAFELY Table 3 Example of a SET sequence with RAM buffer for DR DRA def 00ch Offh Offh DRof IOP3 DRBUFF def 090h Offh Offh buffer for IOP3 DR SET 2 DRBUFF LD A DRBUFF LD DRA A Such a sequence is only required for DR address when some bits are set to input No restric tions apply for operating on OR or DDR It is reco
9. sters are named the Data Register DR the Data Direction Register DDR and the Option Register OR The DDR and OR are accessed directly at their addresses for read and write cycles i e data is written to the register and can be read from the register The OR Register has a different operation and care must be taken when reading and writing to this register Figure 1 ST62XX I O port structure with A D input RESET DATA DIRECTION REGISTER SIN CONTROLS o INPUT OUTPUT SOUT TO INTERRUPT TO ADC VAOA413 Note The control registers are located in the ST62 Dataspace please refer to the individual device da tasheets for the specific addresses for the I O ports with analog capability lt 4 2 12 USING ST62xx I O PORTS SAFELY Figure 2 Data register access Figure 3 Read multiplexing write into data write into data reg address reg address Data Data Register Register read from data read from data reg address reg address read from data read from data reg address reg address 1 0 PIN state of data dir reg Data bus VRO01528 DDR OR DR I O pin input output modes 0 0 0 input with pull up 0 0 1 input no pull up 0 1 0 interrupt input with pull up 0 1 1 analog input 1 0 DR open drain output 1 1 DR push pull output For most microcontrollers which use programmable flexibility for I O pins it has been common to reduce the number of registers to use the data register a

ST AN432 APPLICATION NOTE handbook

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