PERICOM PI6C20800S PCI Express 1:8 HCSL Clock Buffer handbook
Contents
1. Max wnis 330 Core Supply vores 38 348 330 Supply vota Tos BEER Se Jon 6 x Output HIGH Current Inr 2 32mA Cim Pame Ca 07 0237 7 PS8887B 10 19 07 PI6C20800S PER OM PCI Express 1 8 HCSL Clock Buffer AC Switching 12 3 Vpp 3 345 A 3 3 5 oma o e e e SRC SRC Input Frequency PLL Mode SRC SRC Input Frequency Bypass Mode Tze Tfal Rise and Fall Time measured between 0 175V to 0 525V ATrise Rise and Fall Time Variation AT fall Mode 5 f ps Vinon Vonage mOn EC EECH Min votage Vans Absolte crossing poig 5 ie Deiere Tpc Jitter Cycle to cycle PLL Mode Measurement for differential T osos waveform Jitter Cycle to cycle BYPASS mode as additive jitter Additive RMS phase jitter for PCIe Notes Test configuration is Rs 33 20 Rp 49 90 and 2pF Measurement taken from Single Ended waveform Measurement taken from Differential waveform Measured using M1 timing analyzer from Amherst Additive jitter is calculated from input and output RMS phase jitter by using PCIe Gen II filter Jaaa V output jitter input jitter 0 5 downnspread input in OVOP eg Configuration Test Load Board Termi2. PI6C 20800SV ETE hy Fa Lj PERICOM PCI Express 1 8 HCSL Clock Buffer Features Description Phase jitter filter for PCIe application 6 208005 is a PCI Express high speed low noise differential clock buffer designed to be a companion to PI6C410BS PCI EES ee Express clock generator for Intel server chipsets The device Low skew lt 50ps distributes the differential SRC clock from PI6C410BS to eight Low Cycle to cycle jitter lt 50ps differential pairs of clock outputs either with or without PLL The input SRC clock can be divided by 2 when SRC_DIV is LOW The clock outputs are controlled by input selection of Output Enable for all outputs Outputs Tristate control via SMBus SRC_STOP PWRDWN and SMBus SCLK and SDA When Power Management Control input of either SRC_STOP or PWRDWNz is LOW the output Programmable PLL Bandwidth clocks are Tristated When PWRDWN is LOW the SDA and SCLK inputs must be Tristated PLL or Fanout operation 3 3V Operation Packaging Pb Free amp Green 48 Pin SSOP V 48 Pin TSSOP A Block Diagram Pin Configuration SRC_DIV VDD OE_INV Vss OE 0 7 Output SRC SRC_STOP Control PWRDWN SRCH OE 0 OE 3 OUT SCLK OUTO OUT 8 SMBus SDA Controller OUTO OE_INV VDD A VSS A IREF LOCK OE 7 OE 4 Jo P HG vss VDD VDD OUT6 OUT1 OUT6 OUT1 OE_6 OE 1 OE 5 OE 2 OUT5 OUT2 OUT5 OUT2 Vss PLL_BW Vss VDD VDD OU
3. Protocol Data Start Slave Register Data Stop Note 1 Register offset for indicating the starting register for indexed block write and indexed block read Byte Count in write mode cannot be 0 07 0237 9 PS8887B 10 19 07 e 16 208005 PERII OM PCI Express 1 8 HCSL Clock Buffer Data Byte 0 Control Register Bit Descriptions SRC_DIV 0 Divide by 2 1 Normal PLL BYPASS 0 Fanout 1 PLL PLL Bandwidth 2 0 HIGH Bandwidth RW 1 LOW Bandwidth RESERVED E RESERVED RESERVED H 2 SRC_STOP 0 Driven when stopped 1 Tristate PWRDWN 0 Driven when stopped R 1 Tristate Data Byte 1 Control Register Bit Power Up Condition Output s Affected 1 Enabled JTO OU 1 OUTO OUTO OUTPUTS enable OUT4 OUT4 W 0 Disabled Enabled OUTS OU 1 Enabled OUT6 OUT6 1 Enabled O 1 Enabled JT4 OU 1 UT7 OUT7 07 0237 3 PS8887B 10 19 07 e 16 208005 PERII OM PCI Express 1 8 HCSL Clock Buffer Data Byte 2 Control Register 0 Free runing assertion of SRC_STOP 0 Freerunning 3 o RW o RW o Allow control of OUTPUTS with RW RW RW RW RW RW RW RW RESERVED Power Up Condition Output s Affected 07 0237 A PS8887B 10 19 07 e 16 208005 PERII OM PCI Express 1 8 HCSL C
4. TA OUT3 OUT4 OUT3 PLL_BW PLL BYPASS SRC_STOP SCLK PWRDWNZ SDA Vss PLL BYPASS SRC_DIV SRC 07 0237 1 PS8887B 10 19 07 16 208005 PERII OM PCI Express 1 8 HCSL Clock Buffer Pin Descriptions SRC DIVA Be 1 3 3V LVTTL input for selecting input frequency divide by 2 active LOW SRC amp SRC 0 7V Differential SRC input from PI6C410 clock synthesizer OE 0 7 Input 6 7 36 3 3V LVTTL input for enabling outputs active HIGH 3 3V LVTTL input for inverting the OE SRC_STOP and PWRDWN pins REY When 0 same stage When 1 OE 0 7 SRC STOPZ PWRDWN inverted 8 9 12 13 16 17 OUT 0 7 amp OUT 0 7 Output 20 21 29 30 33 34 0 7V Differential outputs 37 38 41 42 22 SV LTTE input for selecting fan out of PLL operation input 23 SMBus compatible SCLOCK inp P24 SMmssmpableSDATA O O U U y O BEE 27 33V LTTE input for SRC stop active LOW 3 22 1 ion 23 1 27 1 1 45 47 48 Input PWRDWN Input 3 3V LVTTL input for Power Down operation active LOW 3 3V LVTTL output transition high when PLL lock is achieved LOCK Output Latched output A F Serial Data Interface SMBus 16 20800 is a slave only SMBus device that supports indexed block read and indexed block write protocol using a single 7 bit address and read write bit as shown below Address assignment or qo o j 0 0o Ww Data
5. lock Buffer Functionality PWRDWN Figure 1 Power down sequence Power Down PWRDWN De assertion Tstable PWRDWN Tdrive_PwrDwn lt 300us 200mV Figure 2 Power down de assert sequence 07 0237 5 PS8887B 10 19 07 e 16 208005 PERII OM PCI Express 1 8 HCSL Clock Buffer Current mode output buffer characteristics of OUT 0 7 OUT 0 7 VDD 3 3V 5 Slope 1 Rs Ros lout Vout 0 85V max Figure 9 Simplified diagram of current mode output buffer Differential Clock Buffer characteristics 4750 1 Nominal test load for given 12 12 IREF 2 32mA configuration NOMINAL NOMINAL E5 Note 1 INOMINAL refers to the expected current based on the configuration of the device Differential Clock Output Current Board Target Trace Term Z Reference R Iref Vpp 3xRr Output Current 1000 Rrer 4750 1 1000 differential 15 coupling ratio IREF 2 32mA 07 0237 6 PS8887B 10 19 07 e 16 208005 PERII OM PCI Express 1 8 HCSL Clock Buffer Absolute Maximum Ratings Over operating free air temperature range symbol Parameters Mm Vpp 3 3V UO Supply Voltage Input HIGH Voltage Input LOW Voltage Note 1 Stress beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device DC Electrical Characteristics 3 3 5 Vpp a 3 3 5 F symbol Parameters
6. nation PI6C20800 07 0237 8 PS8887B 10 19 07 e 16 208005 PERIL OM PCI Express 1 8 HCSL Clock Buffer Packaging Mechanical 48 Pin SSOP V Gauge Plane 0 25 DENOTES DIMENSIONS IN MILLIMETERS SEATING PLANE Max DENOTES DIMENSIONS IN MILLIMETERS 07 0237 9 PS8887B 10 19 07 e 16 208005 PERII OM PCI Express 1 8 HCSL Clock Buffer Ordering Information t 2 Ordering Code Package Code Package Description PI6C20800SVE 48 pin 300 mil wide SSOP Pb Free and Green PI6C20800SAE 48 pin 240 mil wide TSSOP Pb Free and Green Notes 1 Thermal characteristics can be found on the company web site at www pericom com packaging 2 E Pb free and Green Pericom Semiconductor Corporation 1 800 435 2336 www pericom com 07 0237 10 PS8887B 10 19 07
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