ST STM32F051x4 STM32F051x6 STM32F051x8 Low- medium-density advanced ARM -based 32-bit MCU with 16 to 64 Kbytes Flash timers ADC DAC comm. interfaces handbook
Contents
1. STM32F051x Description Table 2 STM32F051xx family device features and peripheral counts Peripheral STM32F051Kx STM32F051Cx STM32F051Rx Flash Kbytes 16 32 64 16 32 64 16 32 64 SRAM Kbytes 4 8 4 8 4 8 Advanced 1 16 bit control Timers General 5 16 bit purpose 1 32 bit Basic 1 16 bit SPI 125 0 1 1 2 2 1 1 1 2 2 1 1 1 2 2 1 Coin 19 2 19 2 19 2 interfaces USART 10 2 10 2 10 2 1 12 bit synchronized ADC number of channels 1 10 ext 3 int 1 16 ext 3 int Operating temperature Ambient operating temperature 40 C to 85 40 C to 105 C GPIOs 27 39 55 Capacitive sensing 14 17 18 channels 12 bit DAC 1 number of channels 1 Analog comparator 2 Max CPU frequency 48 MHz Operating voltage 2 0 to 3 6 V Junction temperature 40 C to 125 C Packages UFQFPN32 LQFP48 LQFP64 SPI2 is not present 12 2 is not present USART2 is not present The SPI1 interface can be used either in SPI mode or in 125 audio mode Doc ID 018746 Rev 2 7 9 Device overview STM32F051x 2 Device overview Figure 1 Block diagram SWCLK Serial Wire Vom H SWDAT Debug eps Vpp 2 to 3 6V 1 8V VOLT REG 5 FLASH 3 3 V TO 1 8V Vss N 64KB GVpp CORTEX MO CPU gt 8 32 bits2. uondiosep uid pue s nouid 904261115 9p28L0 AI 500 06 06 Table 13 Alternate functions selected through GPIOB AFR registers for port Pin name AFO AF1 AF2 AF3 PBO EVENTOUT TIM3_CH3 TIM1_CH2N TSC G3 102 PB1 TIM14 1 TIM3_CH4 TIM1_CH3N TSC G3 IOS PB2 TSC G3 104 SPI1 SCK I281 EVENTOUT TIM2 CH2 TSC G5 IO1 PB4 SPI1 MISO I281 TIM3_CH1 EVENTOUT TSC G5 102 PB5 SPI1 MOSI I281 SD TIM3_CH2 TIM16_BKIN 12 1 5 USART1_TX 1201 501 TIM16 CH1N TSC G5 103 PB7 USART1_RX 12C1_SDA TIM17_CH1N TSC G5 104 PB8 CEC I2C1_SCL TIM16_CH1 TSC_SYNC PB9 IR_OUT 12 1 5 17 1 10 12 2 SCL TIM2 TSC SYNC PB11 EVENTOUT 2 2 SDA TIM2 CH4 TSC G6 101 PB12 SPI2 NSS EVENTOUT TIM1_BKIN TSC G6 102 PB13 SPI2 SCK TIM1_CH1N TSC_G6_IO3 PB14 SPI2_MISO TIM15_CH1 TIM1_CH2N TSC G6 104 PB15 SPI2 MOSI TIM15 CH2 TIM1_CH3N TIM15 CH1N 904261115 uondiosep uid pue sinouid STM32F051x Memory mapping 5 Memory mapping Figure 6 STM32F051x memory map OxFFFF FFFF 7 0 010 0000 0 000 0000 0 000 0000 0 000 0000 0 8000 0000 0 6000 0000 0 4000 0000 0 2000 0000 0 0000 0000 Cortex MO Internal Peripherals Peripherals SRAM CODE Reserved OxiFFF FFFF reserved Ox1FFF
3. Option Bytes Ox1FFF F800 System memory Ox1FFF ECOO l reserved 0x0801 0000 Flash memory 0x0800 0000 reserved 0x0001 0000 Flash system memory or SRAM depending on BOOT configuration 0x0000 0000 0x4800 17FF 0x4800 0000 0x4002 43FF 0x4002 0000 0x4001 8000 0x4001 0000 0x4000 8000 0x4000 0000 AHB2 reserved l AHB1 reserved APB reserved APB MS19840V1 Doc ID 018746 Rev 2 31 33 Memory mapping STM32F051x 32 33 Table 14 5 32 051 peripheral register boundary addresses Bus Boundary address Size Peripheral 0x4800 1800 OxSFFF FFFF 384 MB Reserved 0x4800 1400 0x4800 17FF 1KB GPIOF 0x4800 1000 0x4800 13FF 1KB Reserved 0 4800 0x4800 OF FF 1KB GPIOD aen 0x4800 0800 0x4800 OBFF 1KB GPIOC 0x4800 0400 0x4800 07FF 1KB GPIOB 0x4800 0000 0x4800 03FF 1KB GPIOA 0 4002 4400 0x47FF FFFF 128 MB Reserved 0x4002 4000 0x4002 43FF 1KB TSC 0x4002 3400 0x4002 3FFF 3KB Reserved 0x4002 3000 0x4002 33FF 1KB CRC 0x4002 2400 0x4002 2FFF 3KB Reserved AHB1 0x4002 2000 0x4002 23FF 1KB FLASH Interface 0x4002 1400 0x4002 1FFF 3KB Reserved 0x4002 1000 0x4002 13FF 1KB RCC 0 4002 0400 0x4002 OFFF 3KB Reserved 0 4002 0000 0x4002 1KB DMA 0x4001 8000 0x4001 FFFF 32KB Res
4. 48 MHz lt POR SUPPLY 1 Reset SUPERVISION NRST 5 SRAM VppA N E POR PDR NVIC u Ke s 5 9 RC HS 14 MHz PVD 8 RC HS 8 MHz GP DMA 5 Rcis LS DD 5 channels mese 0501 oscin Pro PLL 4 32 MHz OSCOUT PF1 IWWDG gt AHBPCLK Power 1 APBPCLK Controller reser A VgA171 65 V to 3 6 V CLOCK gt CECCLK e vsw gt USARTCLK rice IN gt HCLK By F PA 15 0 27 GPIO port A OSC32 OUT 5 5 PB 15 0 gt GPIO port B KN RTC TAMPER RTC lt 8 reg I lt T ALARM OUT LM o T 15 0 75 GPIO port KN 5 Kc RTC interface 4 channels 2 lt lt IK KC gt 3 compl channels BRK ETR input as AF PF 7 4 lt a GPIO port F KS gt lt TIMER 2 K ch ETR as AF 6 groups of Analo Cc gt lt TIMER 3 4 ch ETR as AF 4 channels gt ine monon M lt ontroller SZ lt gt TIMER 14 1 channel as AF SYNC gt AHB en KP APB lt gt TIMER AS Ka 1 compl BRK as AF TIMER 16 1 channel 2 lt 1 compl BRK as AF 55AF E WKUP TIMER 17 1 channel wwoe gt K gt KIMY 1 compl BRK as MOSI SD IR OUT as AF MISO MCK lt E I z T o SES CTS RTS NSS WS AF TX CTS RTS 2 KC KO OSA SCK 2 SPI K USART2 RX TX CTS RTS
5. 10 3 1 ARMQ CortexTM MO core with embedded Flash and SRAM 10 3 2 MOmOEI6S orate ac ew ee vdd 8 10 3 3 Cyclic redundancy check calculation unit CRC 10 3 4 Direct memory access controller DMA 11 3 5 Nested vectored interrupt controller NVIC 11 3 6 Extended interrupt event controller 11 3 7 1 12 3 8 RR 12 3 9 Power management 12 3 9 1 Power supply schemes 12 3 9 2 Power supply supervisors 12 3 9 3 Voltage regulator 13 3 10 Low power modes 13 3 11 Real time clock RTC and backup registers 14 4 12 Timers and watchdogs 15 3 12 1 Advanced control timer TIM1 15 3 12 2 General purpose timers TIM2 3 14 17 16 3 12 3 Basic timer TIM6 16 3 12 4 Independent window watchdog IWWDG 17 3 12 5 System window watchdog WWDG 17 3 12 6 SysTickti
6. as AF CK as AF SYSCFG IF SCL SDA SMBal lt K I2C1 KEE 20 tor FM 11 as K gt 2 2 KD SCLSDA INPUT lt GP Comparator 1 as AF INPUT gt OUTPUT GP Comparator 2 as AFJ G VppA KC HDMI CEC gt Temp sensor AD inputs 12 bit ADA IF gt 12 bit DAC1 TMER6 gt lt gt IF 1 DAC1_OUT as AF 1 Vssa Vppa 1 Vppa MS19315V1 8 9 Doc ID 018746 Rev 2 ky STM32F051x Device overview Figure 2 Clock tree FLITFCLK gt to Flash programming interface HSI to 12C1
7. y STM32F051x4 STM32F051x6 STM32F051x8 Low medium density advanced ARM based 32 bit MCU with 16 to 64 Kbytes Flash timers ADC DAC and comm interfaces Features m Operating conditions Voltage range 2 0 V to 3 6 V e m ARM 32 bit Cortex8 MO CPU 48 MHz max LQFP64 10x10 LQFP48 7x7 UFQFPN32 5x5 m Memories Up to 11 timers 16to 64 Kbytes of Flash memory One 16 bit 7 channel advanced control 8 Kbytes of SRAM with HW parity checking timer for 6 channels PWM output with m CRC calculation unit deadtime generation and emergency stop m Clock management 4to 32 MHz crystal oscillator 32 kHz oscillator for RTC with calibration Internal 8 MHz RC with x6 PLL option Internal 40 kHz RC oscillator Calendar RTC with alarm and periodic wakeup from Stop Standby One 32 bit and one 16 bit timer with up to 4 IC OC usable for IR control decoding One 16 bit timer with 2 IC OC 1 OCN deadtime generation and emergency stop Two 16 bit timers each with IC OC and OCN deadtime generation emergency stop and modulator gate for IR control One 16 bit timer with 1 IC OC Independent and system watchdog timers m Reset and supply management Mida Power on Power down reset POR PDR umer Programmable voltage detector PVD zone m Low power Sleep Stop and Standby modes non interfaces Up to two IC interface
8. D Alternate functions Additional functions 33 K gt TIM3_CH4 TIM14_CH1 27 19 15 PB1 TTa CH3N TSC G3 103 9 28 20 16 PB2 TSC G3 104 12 2 SCL CEC 2 29 21 10 TSC SYNC 12 2 SDA 2 CH4 PRISES PEN UB ET TSC 96 101 EVENTOUT 31 23 0 VSS Digital ground 32 24 17 VDD Digital power supply SPI2 NSS TIM1_BKIN 39 25 VO FT TSC 96 102 EVENTOUT SPI2 SCK TIM1 CH1N 34 26 PB13 TSC G6 103 SPI2_MISO TIM1_CH2N 39 ee PETS Vo En 15 1 TSC G6 104 SPI2_MOSI TIM1 36 28 15 TIM15 CHIN 15 RTC REFIN 37 PC6 CH1 38 2 39 40 9 4 USART1 CK TIM1 1 41 29 18 PA8 EVENTOUT USART1 TX 1 2 en este PA9 VO 4 TIM15 BKIN G4 101 USART1_RX TIM1 23 91 29 PAIC Vo 2 17 BKIN G4 102 USART1_CTS 1 4 44 32 21 11 COMP1 OUT TSC G4 EVENTOUT USART1_RTS TIM1 ETR 45 33 22 PA12 2 OUT 5 64 104 EVENTOUT PA13 46 34 23 VO FT 3 IR OUT SWDAT SWDAT 47 35 PF6 12 2 SCL 48 36 y o FT 12 2 SDA y Doc ID 018746 Rev 2 27 30 Pinouts and pin description STM32F051x Tab
9. SYSCLK to 12 1 8 MHz HSI Bai to CEC HSI RC 2 HCLK to AHB bus core memory and DMA PLLSRC i PLLMUL SW 8 to cortex System timer HSI FHCLK Cortex free running clock PLL AHB APB X2 X3 prescaler H prescaler POLK to APB peripherals x16 HSE 1 2 512 1 2 4 8 16 SYSCLK 1 2 css L f APB1prescaer y to TIM1 2 3 6 3 16 1 x1 else x2 14 15 16 17 1 Prescaler OSC OUT 4 32 MHz 14 MHz HSI14 E OSC IN HSE OSC HSI14 RC PCLK SYSCLK 4 OSTIN SE si LSE OSC P LSE OSC32 OUT 32 768kHz LSE RTCSEL 1 0 LSI RC LSI gt to IWWDG 40kHz IWWDGCLK Main clock output HSI MCO 4 29 HSH4 HSE SYSCLK MCO MS19935V2 3 Doc ID 018746 Rev 2 9 9 Functional overview STM32F051x 3 3 1 3 2 3 3 10 22 Functional overview ARM Cortex Mo core with embedded Flash and SRAM The ARM Cortex MO processor is the latest generation of ARM processors for embedded systems It has been developed to provide a low cost platform that meets the needs of MCU implementation with a reduced pin count and low power consumption while delivering outstanding computational performance and an advanced system response to interrupts The ARM Cortex MO 32 bit RISC processor features exceptional code efficiency delivering the high performance expected from an ARM core in the memory size usually associated with 8
10. 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 5 500 0 2165 0 500 0 0197 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits 36 37 Doc ID 018746 Rev 2 ky STM32F051x Package characteristics Figure 11 32 32 lead ultra thin fine pitch Figure 12 quad flat no lead package outline 5 x 52 UFQFPN32 recommended footprint 0 Seating plane 14 T 3 Bottom view 380 A0B8 Drawing is not to scale All leads pads should also be soldered to the PCB to improve the lead pad solder joint life There is an exposed die pad on the underside of the UFQFPN package This pad is used for the device ground and must be connected It is referred
11. 2BFF 1KB RTC 0x4000 2400 0x4000 27FF 1KB Reserved 0x4000 2000 0x4000 23FF 1KB TIM14 0x4000 1400 0x4000 1FFF 3KB Reserved 0x4000 1000 0x4000 13FF 1KB TIM6 0 4000 0800 0x4000 OF FF 2KB Reserved 0x4000 0400 0x4000 07FF 1KB 0 4000 0000 0x4000 1KB TIM2 Doc ID 018746 Rev 2 33 33 Package characteristics STM32F051x 6 6 1 34 37 Package characteristics Package mechanical data In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark Doc ID 018746 Rev 2 ky STM32F051x Package characteristics Figure 7 LQFP64 10 x 10 mm 64 low profile 8 Recommended footprint quad flat package outline o 32 A 2 127 z 1 gt Pin 1 identification 1 7 8 Tam ai14909 1 Drawing is not to scale 2 Dimensions are in millimeters Table 15 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data mi
12. STM32F051x List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 4 4 Ecc 1 STM32F051xx family device features and peripheral 7 Timer feature 2 15 Comparison of I2C analog and digital filters _ _ 17 STM32F051xx 2 18 STM32F051xx USART implementation 19 STM32F051x SPI I2S implementation 19 Capacitive sensing GPIOs available on STM32F051x devices 20 No of capacitive sensing channels available on STM32F051xx devices 21 Legend abbreviations used in the 25 Pin definitions e lO y Hoe ORE Rn tee 25 Alternate functions selected through GPIOA AFR registers for port A 29 Alternate functions selected through GPIOB registers for port B 30 STM32F051x peripheral register boundary addresses 32 LQFP64 10 x 10 mm 64 pin low profile quad flat package mechanical data 35 LQFP48 7 x 7mm 48
13. TC Standard 3 3V I O B Dedicated BOOTO pin RST Bidirectional reset pin with embedded weak pull up resistor Notes Unless otherwise specified by a note all I Os are set as floating inputs during and after reset 2 Functions selected through GPIOx AFR registers Pin functions iti Functions directly selected enabled through peripheral registers Table 11 Pin definitions Pin number o Pin functions e Pin name 8 9 2 functionafter 2 Notes LLL reset D Alternate functions Additional functions 5 1 1 VBAT S Backup power supply RTC 1 2 12 PC13 Tc 0 RTC TS OUT WKUP2 PC14 OSC32 IN B T 00 2 IN 313 14 OSC32 15 4 4 OSC32 OUT yo TC OSC32_OUT PC15 PF0 OSC_IN 5 5 2 T VO FT OSC IN PFO PF1 OSC OUT T 6 6 3 PF1 O OSC_OU 7 7 4 NRST VO RST Device reset input internal reset output active low ky Doc ID 018746 Rev 2 25 30 Pinouts and pin description STM32F051x Table 11 Pin definitions continued Pin number Pin functions 8 8 9 2 functionafter 2 Notes T E reset Alternate functions Additional functions LL gt 8 PCO TTa EVENTOUT ADC_IN10 9 PC1 TTa EVENTOUT ADC_IN11 10 PC2 TTa EVENTOUT ADC_IN12 11 PC3 TTa EVENTOUT ADC_IN13 121810 VSSA S
14. X Independent clock X SMBus X Wakeup from STOP X 1 X supported Universal synchronous asynchronous receiver transmitters USART The device embeds up to two universal synchronous asynchronous receiver transmitters USART1 and USART2 which communicate at speeds of up to 6 Mbit s They provide hardware management of the CTS RTS and RS485 DE signals multiprocessor communication mode master synchronous communication and single wire half duplex communication mode The USART1 supports also SmartCard communication ISO 7816 IrDA SIR ENDEC LIN Master Slave capability auto baud rate feature and has a clock domain independent from the CPU clock allowing the USART1 to wake up the MCU from Stop mode The USART interfaces can be served by the DMA controller Serial peripheral interface SPI Refer to Table 6 for the differences between USART1 and USART2 Doc ID 018746 Rev 2 ky STM32F051x Functional overview 3 15 Table 6 STM32F051xx USART implementation USART modes features USART1 USART2 Hardware flow control for modem Continuous communication using DMA X X Multiprocessor communication X X Synchronous mode X X Smartcard mode X Single wire half duplex communication X X IrDA SIR ENDEC block X LIN mode X Dual clock domain and wakeup from Stop mode X Receiver timeout interrupt X Modbus communication X Auto baud rate detection X Driver Enable X X
15. and 16 bit devices The STM32F051xx family has an embedded ARM core and is therefore compatible with all ARM tools and software Figure 1 shows the general block diagram of the device family Memories The device has the following features e Upto 8 Kbytes of embedded SRAM accessed read write at CPU clock speed with 0 wait states and featuring embedded parity checking with exception generation for fail critical applications e The non volatile memory is divided into two arrays 16 to 64 Kbytes of embedded Flash memory for programs and data Option bytes The option bytes are used to write protect the memory with 4 KB granularity and or readout protect the whole memory with the following options Level 0 no readout protection Level 1 memory readout protection the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected Level 2 chip readout protection debug features Cortex MO serial wire and boot in RAM selection disabled Cyclic redundancy check calculation unit CRC The CRC cyclic redundancy check calculation unit is used to get a CRC code from a 96 bit data word and a fixed generator polynomial Among other applications CRC based techniques are used to verify data transmission or storage integrity In the scope of the EN IEC 60335 1 standard they offer a means of verifying the Flash memory integrity The CRC calculation unit helps compute a sign
16. and Standby modes on timestamp event detection The RTC clock sources can be A 32 768 kHz external crystal A resonator or oscillator The internal low power RC oscillator typical frequency of 40 kHz The high speed external clock divided by 32 Doc ID 018746 Rev 2 ky STM32F051x Functional overview 3 12 Timers and watchdogs The STM32F051xx family devices include up to six general purpose timers one basic timer and an advanced control timer Table 3 compares the features of the advanced control general purpose and basic timers Table 3 Timer feature comparison Timer Timer Counter Counter Prescaler DMA request Capture compare Complementary type resolution type factor generation channels outputs Any integer lr TIM1 16 bit 2 between 1 Yes 4 Yes p and 65536 Any integer TIM2 32 bit h between 1 Yes 4 No n and 65536 Any integer TIM3 16 bit 1 2 between 1 Yes 4 No B and 65536 Any integer TIM14 16 bit Up between 1 No 1 No 65536 TIM15 16 bit Up between 1 Yes 2 Yes and 65536 Any integer e 16 bit Up between 1 Yes 1 Yes and 65536 Any integer Basic TIM6 16 bit Up between 1 Yes 0 No and 65536 3 12 1 Advanced control timer TIM1 The advanced control timer TIM1 can be seen as a three phase PWM multiplexed on 6 channels It has complementary PWM outputs with programmable inserted dead times It can also be seen
17. corresponding clock sources are not stopped by entering Stop or Standby mode Doc ID 018746 Rev 2 13 22 Functional overview STM32F051x 3 11 14 22 Real time clock RTC and backup registers The RTC and the 5 backup registers are supplied through a switch that takes power either on Vpp supply when present or through the pin The backup registers are five 32 bit registers used to store 20 bytes of user application data when Vpp power is not present They are not reset by a system or power reset or when the device wakes up from Standby mode The RTC is an independent BCD timer counter Its main features are the following Calendar with subsecond seconds minutes hours 12 or 24 format week day date month year in BCD binary coded decimal format Automatically correction for 28 29 leap year 30 and 31 day of the month Programmable alarm with wake up from Stop and Standby mode capability On the fly correction from 1 to 32767 RTC clock pulses This can be used to synchronize it with a master clock Digital calibration circuit with 1 ppm resolution to compensate for quartz crystal inaccuracy 2 anti tamper detection pins with programmable filter The MCU can be woken up from Stop and Standby modes on tamper event detection Timestamp feature which can be used to save the calendar content This function can triggered by an event on the timestamp pin or by a tamper event The MCU can be woken up from Stop
18. pin low profile quad flat package mechanical data 36 2 32 lead ultra thin fine pitch quad flat no lead package 5 x 5 package mechanical data 37 Document revision history 39 Doc ID 018746 Rev 2 ky STM32F051x List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Block diagtatm urere dod Rh aue A pde YS 8 Clock SS PM CL 9 LQFP64 64 pin package 1 23 LQFP48 48 pin package 24 UFQFPN32 32 pin package 24 STM32F051x memory map 1 31 LQFP64 10 10 mm 64 pin low profile quad flat package outline 35 Recommended footprint T 35 LQFP48 7 x 7mm 48 pin low profile quad flat package 36 Recommended footprint niox ate qa dod e Pe a 36 UFQFPN32 32 lead ultra thin fine pitch quad flat no lead package outline 5 5 37 UFQFPN32 recommended 37 Doc ID 018746 Re
19. the DAC interface is generating it s own DMA requests Fast low power comparators and reference voltage The device embeds two fast rail to rail comparators with programmable reference voltage internal or external hysteresis and speed low speed for low power and with selectable output polarity The reference voltage can be one of the following e External I O e DAC output pin e Internal reference voltage or submultiple 1 4 1 2 3 4 Refer to Table 21 Embedded internal reference voltage for the value and precision of the internal reference voltage Both comparators can wake up from STOP mode generate interrupts and breaks for the timers and can be also combined into a window comparator The internal voltage reference is also connected to ADC_IN17 input channel of the ADC Serial wire debug port SW DP An ARM SW DP interface is provided to allow a serial wire debugging tool to be connected to the MCU Doc ID 018746 Rev 2 ky STM32F051x Pinouts and pin description 4 3 Pinouts and pin description Figure 3 LQFP64 64 pin package pinout 0 gt H BOOTO Q Q o ma t m m mm gt n Dn nn n l 64 63 62 61 60 59 58 57 56 55 VBAT PC13 PC14 OSC32 IN PC15 OSC32 OUT PFO OSC IN PF1 OSC OUT NRST PCO PC1 PC2 PC3 VSSA VDDA PAO PA1 PA2 O Q WD LQFP64 10 11 12 13 14 15 16 1 PF7 P
20. to 105 C Options XXX programmed parts TR tape and real Doc ID 018746 Rev 2 STM32F051x Revision history 8 Revision history Table 18 Document revision history Date Revision Changes 09 Feb 2012 1 Initial release Added Table 2 STM32F051xx family device features and 14 Feb 2012 2 peripheral counts Updated Table 7 STM32F051x SPIN2S implementation Doc ID 018746 Rev 2 39 40 STM32F051x Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or conside
21. to as pin O in Table 11 Pin definitions 4 Dimensions are in millimeters Table 17 UFQFPN32 32 lead ultra thin fine pitch quad flat no lead package 5 x 5 package mechanical data mm inches Dim Min Typ Max Min Typ Max A 0 5 0 55 0 6 0 0197 0 0217 0 0236 Al 0 00 0 02 0 05 0 0 0008 0 0020 A3 0 152 0 006 b 0 18 0 23 0 28 0 0071 0 0091 0 0110 D 4 90 5 00 5 10 0 1929 0 1969 0 2008 D2 3 50 0 1378 E 4 90 5 00 5 10 0 1929 0 1969 0 2008 E2 3 40 3 50 3 60 0 1339 0 1378 0 1417 e 0 500 0 0197 L 0 30 0 40 0 50 0 0118 0 0157 0 0197 ddd 0 08 0 0031 Number of pins N 32 1 Values in inches are converted from mm and rounded to 4 decimal digits ky Doc ID 018746 Rev 2 37 37 Ordering information scheme STM32F051x 7 38 38 Ordering information scheme For a list of available options memory package and so on or for further information on any aspect of this device please contact your nearest ST sales office Example STM32 Device family STM32 ARM based 32 bit microcontroller Product type F F General purpose Sub family 051 051 STM32F051xx Pin count R K 32 pins C 48 pins R 64 pins Code size 4 16 Kbytes of Flash memory 6 32 Kbytes of Flash memory 8 64 Kbytes of Flash memory Package UFOFN T LQFP Temperature range 6 40 to 85 C 7 40
22. 1 X supported Serial peripheral interface SPI Inter integrated sound interfaces 125 Up to two SPIs are able to communicate up to 18 Mbits s in slave and master modes full duplex and simplex communication modes The 3 bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits One standard 125 interface multiplexed with SPI1 supporting four different audio standards can operate as master or slave at simplex communication mode It can be configured to transfer 16 and 24 or 32 bits with16 bit or 32 bit data resolution and synchronized by a specific signal Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8 bit programmable linear prescaler When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency Refer to Table 7 for the differences between SPI1 and SPI2 Table 7 STM32F051x SPI I2S implementation SPI features SPI SPI2 Hardware CRC calculation X X Rx Tx FIFO X X NSS pulse mode X X 125 mode X TI mode X X 1 supported Doc ID 018746 Rev 2 19 22 Functional overview STM32F051x 3 16 3 17 3 18 20 22 High definition multimedia interface HDMI consumer electronics control CEC The device embeds a HDMI CEC controller that provides hardware support for the Consumer Electronics Control CEC protocol Supplement 1 to the HDMI standard This pro
23. 13 Independent window watchdog IWWDG The independent window watchdog is based on an 8 bit prescaler and 12 bit downcounter with user defined refresh window It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock it can operate in Stop and Standby modes It can be used either as a watchdog to reset the device when a problem occurs or as a free running timer for application timeout management It is hardware or software configurable through the option bytes The counter can be frozen in debug mode System window watchdog WWDG The system window watchdog is based on a 7 bit downcounter that can be set as free running It can be used as a watchdog to reset the device when a problem occurs It is clocked from the APB clock PCLK It has an early warning interrupt capability and the counter can be frozen in debug mode SysTick timer This timer is dedicated to real time operating systems but could also be used as a standard down counter It features e A 24 bit down counter e Autoreload capability e Maskable system interrupt generation when the counter reaches 0 e Programmable clock source HCLK or HCLK 8 Inter integrated circuit interfaces Up to two I C interfaces I2C1 and I2C2 can operate in multimaster or slave modes Both can support Standard mode up to 100 kbit s or Fast mode up to 400 kbit s and I2C1 supports also Fast Mode Plus up to 1 Mbit s with 20 mA out
24. Analog ground 131915 VDDA S Analog power supply USART2 CTS IM E 14 10 6 PAO TTa TIM2_CH1_ETR RTC TAMP2 1 OUT 5 01 101 WKUP1 USART2_RTS TIM2_CH2 ADC_IN1 S TSC 91 102 EVENTOUT COMP1 1 USART2 TX TIM2 ADC IN2 16 12 8 2 TTa TIM15 CH1 COMP2 OUT COMP2 INM6 TSC_G1_103 E USART2 RX TIM2_CH4 ADC_INS PAS VO Ta TIM15_CH2 TSC_G1_IO4 COMP2_INP 18 PF4 EVENTOUT 19 PF5 EVENTOUT SPI1 NSS I2S1 WS 2 20 14 10 PA4 TTa USART2_CK TIM14_CH1 TSC G2 101 COMP2_INM4 DAC1_OUT ADC_IN5 SPI1_SCK l2S1_CK d 21 15 11 COMP1 INM5 2 CH ETR TSC G2 102 COMP2 INMS SPI1 MISO I281 TIM3_CH1 TIM1_BKIN 22 16 12 16 CH1 1 OUT ADC_IN6 TSC G2 EVENTOUT SPI1 MOSI I281 SD TIM3 CH2 TIM14_CH1 23 17 13 PA7 TTa TIM1 CH1N 17 CH1 COMP2 OUT 5 02 104 EVENTOUT 24 PC4 TTa EVENTOUT ADC_IN14 25 PC5 TTa TSC_G3_101 ADC_IN15 TIM3_CH3 TIM1_CH2N 26 18 14 PBO TTa G3 102 EVENTOUT ADC IN8 26 30 Doc ID 018746 Rev 2 ky STM32F051x Pinouts and pin description Table 11 Pin definitions continued Pin number o Pin functions Pin name 8 8 5 9 Z functionafter 2 Notes LEE reset
25. F6 PA13 PA12 11 10 PA9 PA8 PC8 PC7 PC6 PB15 PB14 PB13 PB12 MS19843V1 Doc ID 018746 Rev 2 23 30 Pinouts and pin description STM32F051x Figure 4 LQFP48 48 pin package pinout VBAT PF7 PC13 PF6 PC14 OSC32 IN PA13 PC15 0SC32 OUT pele PFO OSC IN PA11 PF1 OSC OUT T PA10 NRST PA9 VSSA PA8 VDDA PB15 PAO PB14 PAI PB13 PA2 PB12 MS19842V1 Figure 5 UFQFPN32 32 pin package pinout e l m O m cm tdm m dm lt amna a c oao 32 3130 29 28 27 26 25 VDD 7000084 24 1 PA14 PFO OSC IN 222 20 1 23 PA13 PF1 OSC OUT 123 22C1 12 NRST 74 VSS 72151 11 VDDA 25 VSSA 20 PA10 PAO 26 192 PA1 27 18 PAS e alivio iR 17 0 2 vo 111213 MS 7 VOP C LIL LAA MS19844V2 24 30 Doc ID 018746 Rev 2 STM32F051x Pinouts and pin description Table 10 Legend abbreviations used in the pinout table Name Abbreviation Definition Ein abs Unless otherwise specified in brackets below the pin name the pin function during and after reset is the same as the actual pin name S Supply pin Pin type Input only pin y o Input output pin FT 5 V tolerant I O FTf 5 V tolerant I O FM capable TTa 3 3 V tolerant I O directly connected to ADC structure
26. PB4 5 62 103 PA6 5 TSC G5 PB6 TSC G2 104 PA7 TSC G5 104 PB7 TSC G3 101 PBO TSC G6 101 PB11 TSC G3 102 PB1 TSC G6 102 PB12 3 _ 3_103 2 i TSC G6 IOS PB13 TSC G3 104 PC5 TSC G6 104 PB14 Doc ID 018746 Rev 2 ky STM32F051x Functional overview 3 19 3 19 1 3 19 2 Table 9 No of capacitive sensing channels available on STM32F051xx devices Number of capacitive sensing channels Analog I O group STM32F051Rx STM32F051Cx STM32F051Kx G1 3 3 3 G2 3 3 3 G3 3 2 2 G4 3 3 3 G5 3 3 3 G6 3 3 0 Number of capacitive 18 17 14 sensing channels Analog to digital converter ADC The 12 bit analog to digital converter has up to 16 external and 3 internal temperature sensor voltage reference VBAT voltage measurement channels and performs conversions in single shot or scan modes In scan mode automatic conversion is performed on a selected group of analog inputs The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all selected channels An interrupt is generated when the converted voltage is outside the programmed thresholds Temperature sensor The temperature sensor generates a voltage that varies linearly with temperature The conversion range is between 2 V lt Vppa lt 3 6 V The temperature sensor is internally connected to the ADC_IN16 input chan
27. as a complete general purpose timer The 4 independent channels can be used for e Input capture e Output compare e PWM generation edge or center aligned modes e One pulse mode output If configured as a standard 16 bit timer it has the same features as the TIMx timer If configured as the 16 bit PWM generator it has full modulation capability 0 100946 The counter can be frozen in debug mode Many features are shared with those of the standard timers which have the same architecture The advanced control timer can therefore work together with the other timers via the Timer Link feature for synchronization or event chaining Doc ID 018746 Rev 2 15 22 Functional overview STM32F051x 3 12 2 3 12 3 16 22 General purpose timers TIM2 3 TIM14 17 There are six synchronizable general purpose timers embedded the STM32F051 xx devices see Table 3 for differences Each general purpose timer can be used to generate PWM outputs or as simple time base TIM2 TIM3 STM32F051 xx devices feature two synchronizable 4 channel general purpose timers TIM2 is based on a 32 bit auto reload up downcounter and a 16 bit prescaler TIM3 is based ona 16 bit auto reload up downcounter and a 16 bit prescaler They feature 4 independent channels each for input capture output compare PWM or one pulse mode output This gives up to 12 input captures output compares PWMs on the largest packages The TIM2 and TIMS general purpo
28. ation previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2012 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 40 40 Doc ID 018746 Rev 2 ky
29. ature of the software during runtime to be compared with a reference signature generated at link time and stored at a given memory location Doc ID 018746 Rev 2 STM32F051x Functional overview 3 4 3 5 3 6 Direct memory access controller DMA The 5 channel general purpose DMAs manage memory to memory peripheral to memory and memory to peripheral transfers The DMA supports circular buffer management removing the need for user code intervention when the controller reaches the end of the buffer Each channel is connected to dedicated hardware DMA requests with support for software trigger on each channel Configuration is made by software and transfer sizes between source and destination are independent DMA can be used with the main peripherals SPI 125 2 USART all TIMx timers except TIM14 DAC and ADC Nested vectored interrupt controller NVIC The STM32F051xx family embeds a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels not including the 16 interrupt lines of Cortex MO and 16 priority levels e Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of late arriving higher priority interrupts Support for tail chaining Processor state automatically saved Interrupt entry restored on interrup
30. erved 0x4001 5 00 0x4001 7FFF 9KB Reserved 0x4001 5800 0x4001 5BFF 1KB DBGMCU 0 4001 4 00 0x4001 57FF 3KB Reserved 0x4001 4800 0x4001 4BFF 1KB TIM17 0x4001 4400 0x4001 47FF 1KB TIM16 0x4001 4000 0x4001 43FF 1KB TIM15 0x4001 3 00 0x4001 3FFF 1KB Reserved 0x4001 3800 0x4001 3BFF 1KB USART1 0 4001 3400 0x4001 37FF 1KB Reserved 0x4001 3000 0x4001 33FF 1KB 5 11 251 0x4001 2 00 0x4001 2FFF 1KB TIM1 0x4001 2800 0x4001 2BFF 1KB Reserved 0x4001 2400 0x4001 27FF 1KB ADC 0x4001 0800 0x4001 23FF 7KB Reserved 0x4001 0400 0x4001 07FF 1KB EXTI 0x4001 0000 0x4001 1KB SYSCFG COMP 0x4000 8000 0x4000 FFFF 32KB Reserved Doc ID 018746 Rev 2 STM32F051x Memory mapping Table 14 5 32 051 peripheral register boundary addresses continued Bus Boundary address Size Peripheral 0x4000 7C00 0x4000 7FFF 1KB Reserved 0 4000 7800 0x4000 7BFF 1KB CEC 0x4000 7400 0x4000 77FF 1KB DAC 0x4000 7000 0x4000 73FF 1KB PWR 0x4000 5 00 0x4000 6FFF 5KB Reserved 0x4000 5800 0x4000 5BFF 1KB 12 2 0x4000 5400 0x4000 57FF 1KB 12 1 0x4000 4800 0 4000 53FF 3KB Reserved 0x4000 4400 0x4000 47FF 1KB USART2 0 4000 3 00 0x4000 43FF 2KB Reserved 0 4000 3800 0x4000 3BFF 1KB SPI2 ad 0x4000 3400 0x4000 37FF 1KB Reserved 0x4000 3000 0x4000 33FF 1KB IWWDG 0x4000 2 00 0x4000 2FFF 1KB WWDG 0x4000 2800 0x4000
31. le 11 Pin definitions continued Pin number Pin functions Pin name 8 8 5 9 Z functionafter 2 Notes LEE reset D Alternate functions Additional functions LL 5 PA14 49 37 24 yo rr 9 2 TX SWCLK SWCLK SPl1_NSS I2S1_WS 50 38 25 PA15 VO FT USART2_RX TIM2_CH_ETR EVENTOUT 51 PC10 VO FT 52 PC11 VO FT 53 PC12 VO FT 54 PD2 VO FT TIM3_ETR SPI1_SCK I2S1_CK 55 39 26 PB3 VO FT TIM2_CH2 TSC_G5_101 EVENTOUT SPI1_MISO I2S1_MCK 56 40 27 PB4 VO FT TIM3_CH1 TSC G5 102 EVENTOUT SPI1_MOSI l2S1_SD 57 41 28 PB5 VO FT 12C1_SMBA 16 TIM3 2 12 1 501 USART1 TX ae de TIM16 CH1N TSC G5 103 12 1 5 USART1_RX ded TIM17 1 TSC G5 104 60 44 31 BOOTO B Boot memory selection 12 1 501 CEC TIM16 61 45 32 PB8 VO FTf TSC SYNC 12C1_SDA IR OUT TIM17 CH1 EVENTOUT 63 47 0 VSS S Digital ground 64 48 1 VDD S Digital power supply 1 PC13 PC14 and PC15 are supplied through the power switch Since the switch only sinks a limited amount of current 3 mA the use of GPIO PC13 to PC15 in output mode is limited The speed should not exceed 2 MHz with a maximum load of 30 pF these GPIOs must not be used as a current sources e g to drive an LED 2 After the first backup domain power up PC13 PC14 and PC15 operate as GPIOs Their functio
32. llimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 11 800 12 000 12 200 0 4646 0 4724 0 4803 D1 9 800 10 000 10 200 0 3858 0 3937 0 4016 D 7 500 11 800 12 000 12 200 0 4646 0 4724 0 4803 E1 9 800 10 00 10 200 0 3858 0 3937 0 4016 e 0 500 0 0197 k 0 3 5 7 0 3 5 7 L 0 450 0 600 0 75 0 0177 0 0236 0 0295 L1 1 000 0 0394 ccc 0 080 0 0031 Number of pins N 64 1 Values in inches are converted from mm and rounded to 4 decimal digits ky Doc ID 018746 Rev 2 35 37 Package characteristics STM32F051x Figure 9 LQFP48 7 x 48 pin low profile quad flat Figure 10 Recommended package outline footprint 00 0 50 Di ccc C 1 20 D3 E a 0 30 36 125 1 b E 37 124 co 020 Co 970 580 790 4 ES EHE ESL M 5 E 1 identification 1 12 5 80 1 Drawing is not to scale 2 Dimensions are in millimeters Table 16 LQFP48 7 x 7mm 48 low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 Al 0 050 0 150 0 0020 0 0059 A2
33. mer 17 3 13 Inter integrated circuit interfaces 2 17 3 14 Universal synchronous asynchronous receiver transmitters USART 18 3 15 Serial peripheral interface SPI Inter integrated sound interfaces 25 19 3 16 High definition multimedia interface HDMI consumer electronics control CEC 20 3 17 General purpose inputs outputs 20 3 18 Touch sensing controller TSC 20 2 3 Doc ID 018746 Rev 2 ky STM32F051x Contents 3 19 Analog to digital converter 21 3 19 1 Temperature 21 3 19 2 Vpar battery voltage 0 21 3 20 Digital to analog converter DAC 22 3 21 Fast low power comparators and reference voltage 22 3 21 1 Serial wire debug port SW DP 22 Pinouts and pin description 23 Memory mapping 31 Package characteristics 34 6 1 Package mechanical data 34 Ordering information scheme 38 Revision history 39 Doc ID 018746 Rev 2 3 3 List of tables
34. n then depends on the content of the Backup registers which is not reset by the main reset For details on how to manage these GPIOs refer to the Battery backup domain and BKP register description sections in the reference manual 3 After reset these pins are configured as SWDAT and SWCLK alternate functions and the internal pull up on SWDAT pin and internal pull down on SWCLK pin are activated 28 30 Doc ID 018746 Rev 2 0 6c 9p28L0 AI od Table 12 Alternate functions selected through GPIOA AFR registers for port A Pin name AFO AF1 AF2 AF3 AF4 AF5 AF6 AF7 PAO usanr2 2 IO COMP1_OUT PA1 EVENTOUT USART2 RTS TIM2 CH2 TSC G1 102 PA2 TIM15 CH1 USART2 TX TIM2 TSC G1 103 COMP2 OUT PA3 TIM15_CH2 USART2_RX TIM2_CH4 TSC_G1_l04 SPI1 NSS PA4 1251 WS USART2 CK TSC G2 101 TIM14 CH1 SPH SCK TIM2_CH1_ PA5 1281 CK CEC ETR TSC G2 102 PA6 TIM3 CH1 TIM1_BKIN TSC G2 103 TIM16 CH1 EVENTOUT COMP1 OUT SPI1 MOSI PA7 2S1 SD TIM3 CH2 TIM1 CH1N TSC G2 104 TIM14 CH1 TIM17 CH1 EVENTOUT COMP2 OUT PA8 MCO USART1_CK TIM1_CH1 EVENTOUT PAQ TIM15_BKIN USART1_TX TIM1_CH2 5 64 101 10 TIM17 USART1 RX TIM1_CH3 TSC G4 102 PA11 EVENTOUT USART1 CTS TIM1 CH4 TSC G4 103 COMP1 OUT PA12 EVENTOUT USART1 RTS TIM1 ETR TSC G4 104 COMP2 OUT PA13 SWDAT OUT PA14 SWCLK USART2 TX SPI1_NSS TIM2_CH1_ PA15 1251 WS USART2_RX ETR EVENTOUT
35. nel which is used to convert the sensor output voltage into a digital value As the offset of the temperature sensor varies from chip to chip due to process variation the internal temperature sensor is mainly suitable for applications that detect temperature changes instead of absolute temperatures If an accurate temperature reading is needed then an external temperature sensor part should be used battery voltage monitoring This embedded hardware feature allows the application to measure the Vpaz battery voltage using the internal ADC channel ADC_IN18 As the voltage may be higher than Vppa and thus outside the ADC input range the pin is internally connected to a bridge divider by 2 As a consequence the converted digital value is half the voltage Doc ID 018746 Rev 2 21 22 Functional overview STM32F051x 3 20 3 21 3 21 1 22 22 Digital to analog converter DAC The 12 bit buffered DAC channel can be used to convert digital signals into analog voltage signal outputs The chosen design structure is composed of integrated resistor strings and an amplifier in non inverting configuration This digital Interface supports the following features e Leftorright data alignment 12 bit mode e Synchronized update capability e DMA capability e External triggers for conversion Five DAC trigger inputs are used in the device The DAC is triggered through the timer trigger outputs and
36. put drive Both support 7 bit and 10 bit addressing modes multiple 7 bit slave addresses 2 addresses 1 with configurable mask They also include programmable analog and digital noise filters Table 4 Comparison of I2C analog and digital filters Analog filter Digital filter Pulse width of Programmable length from 1 to 15 gt 50 ns suppressed spikes I2C peripheral clocks 1 Extra filtering capability vs Benefits Available in Stop mode standard requirements 2 Stable length Variations depending on Disabled when Wakeup from Stop Drawbacks temperature voltage process mode is enabled Doc ID 018746 Rev 2 17 22 Functional overview STM32F051x 3 14 18 22 In addition I2C1 provides hardware support for SMBUS 2 0 and PMBUS 1 1 ARP capability Host notify protocol hardware CRC PEC generation verification timeouts verifications and ALERT protocol management 12 1 also has a clock domain independent from the CPU clock allowing the I2C1 to wake up the MCU from Stop mode on address match 2 interfaces can be served by the DMA controller Refer to Table 5 for the differences between I2C1 and I2C2 Table5 5 32 051 12 implementation I2C features I2C1 I2C2 7 bit addressing mode X X 10 bit addressing mode X X Standard mode up to 100 kbit s X X Fast mode up to 400 kbit s X X Fast Mode Plus with 20mA output drive I Os up to 1 Mbit s
37. red as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY TWO AUTHORIZED ST REPRESENTATIVES ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all inform
38. s one supporting m Veat supply for RTC and backup registers Fast Mode Plus 1 Mbit s with 20 mA m 5 channel DMA controller current sink SMBus PMBus and wakeup m 1 12 bit 1 0 us ADC up to 16 channels from STOP Conversion range 0 to 3 6V Separate analog supply from 2 4 up to 3 6 Two fast low power analog comparators with programmable input and output Up to two USARTs supporting master synchronous SPI and modem control one with 1507816 interface LIN IrDA capability auto baud rate detection and wakeup feature Upto two SPls 18 Mbit s with 4 to 16 m One 12 bit D A converter 26 programmable bit frame 1 with m Up to 55 fast I Os interface multiplexed All mappable on external interrupt vectors HDMI CEC interface wakeup on header Up to 36 I Os with 5 V tolerant capability reception m Upto 18 capacitive sensing channels supporting touchkey linear and rotary touch Table 1 Device summary sensors m 96 bit unique ID m Serial wire debug SWD STM32F051x4 STM32F051K4 STM32F051C4 STM32F051R4 STM32F051x6 STM32F051K6 STM32F051C6 STM32F051R6 STM32F051x8 STM32F051C8 STM32F051R8 STM32F051K8 Doc ID 018746 Rev 2 1 1 February 2012 www st com Contents STM32F051x Contents 1 Description wens Aare meee ee 6 2 Device overvieW 8 3 Functional overview
39. se timers can work together or with the TIM1 advanced control timer via the Timer Link feature for synchronization or event chaining 2 and both have independent DMA request generation These timers are capable of handling quadrature incremental encoder signals and the digital outputs from 1 to 3 hall effect sensors Their counters can be frozen in debug mode TIM14 This timer is based on a 16 bit auto reload upcounter and a 16 bit prescaler TIM14 features one single channel for input capture output compare PWM or one pulse mode output Its counter can be frozen in debug mode TIM15 TIM16 and TIM17 These timers are based on a 16 bit auto reload upcounter and a 16 bit prescaler TIM15 has two independent channels whereas TIM16 and TIM17 feature one single channel for input capture output compare PWM or one pulse mode output The TIM15 TIM16 and TIM17 timers can work together and TIM15 can also operate with TIM1 via the Timer Link feature for synchronization or event chaining TIM15 can be synchronized with TIM16 and TIM17 TIM15 TIM16 and TIM17 have a complementary output with dead time generation and independent DMA request generation Their counters can be frozen in debug mode Basic timer TIM6 This timer is mainly used for DAC trigger generation It can also be used as a generic 16 bit time base Doc ID 018746 Rev 2 ky STM32F051x Functional overview 3 12 4 3 12 5 3 12 6 3
40. t exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency Extended interrupt event controller EXTI The external interrupt event controller consists of 24 edge detector lines used to generate interrupt event requests and wake up the system Each line can be independently configured to select the trigger event rising edge falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The EXTI can detect an external line with a pulse width shorter than the internal clock period Up to 55 GPIOs can be connected to the 16 external interrupt lines Doc ID 018746 Rev 2 11 22 Functional overview STM32F051x 3 7 3 8 3 9 3 9 1 3 9 2 12 22 Clocks and startup System clock selection is performed on startup however the internal RC 8 MHz oscillator is selected as default CPU clock on reset An external 4 32 MHz clock can be selected in which case it is monitored for failure If failure is detected the system automatically switches back to the internal RC oscillator A software interrupt is generated if enabled Similarly full interrupt management of the PLL clock entry is available when necessary for example on failure of an indirectly used external crystal resonator or oscillator Several prescalers allow the application to configure the frequency of the AHB and the APB domains The maxim
41. that VppA should arrive first and be greater than or equal to Vpp e The PDR monitors both the Vpp and supply voltages however the power supply supervisor can be disabled by programming a dedicated Option bit to reduce the power consumption if the application design ensures that Vppa is higher than or equal to Vpp Doc ID 018746 Rev 2 ky STM32F051x Functional overview 3 9 3 3 10 Note The device features an embedded programmable voltage detector PVD that monitors the Vpp power supply and compares it to the Vpyp threshold An interrupt can be generated when Vpp drops below the Vpyp threshold and or when Vpp is higher than the Vpyp threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software Voltage regulator The regulator has three operating modes main MR low power LPR and power down e is used in normal operating mode Run e be used in Stop mode where the power demand is reduced e Power down is used in Standby mode the regulator output is in high impedance the kernel circuitry is powered down inducing zero consumption but the contents of the registers and SRAM are lost This regulator is always enabled after reset It is disabled in Standby mode providing high impedance output Low power modes The STM32F051xx family supports three low power modes to achieve the best compromise bet
42. tocol provides high level control functions between all audiovisual products in an environment It is specified to operate at low speeds with minimum processing and memory overhead It has a clock domain independent from the CPU clock allowing the HDMI_CEC controller to wakeup the MCU from Stop mode on data reception General purpose inputs outputs GPIOs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as peripheral alternate function Most of the GPIO pins are shared with digital or analog alternate functions The I O configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I Os registers Touch sensing controller TSC The device has an embedded independent hardware controller TSC for controlling touch sensing acquisitions on the I Os Up to 18 touch sensing electrodes can be controlled by the TSC The touch sensing I Os organized in 6 acquisition groups with up to 4 I Os in each group Table 8 Capacitive sensing GPIOs available on STM32F051x devices Group Capacitive sensing Pin Group Capacitive sensing Pin signal name name signal name name TSC G1 IO1 pao 18004101 PA TSC G1 102 PA1 TSC G4 102 PA10 TSC G1 103 PA2 TSC G4 103 PA11 TSC G1 104 PA3 TSC G4 104 PA12 TSC G2 101 PA4 TSC G5 101 PB3 TSC G2 102 PA5 TSC G5 102
43. um frequency of the AHB and the APB domains is 48 MHz Boot modes At startup the boot pin and boot selector option bit are used to select one of three boot options e Boot from User Flash e Boot from System Memory e Boot from embedded SRAM The boot loader is located in System Memory It is used to reprogram the Flash memory by using USART1 Power management Power supply schemes Vpp 2 0 to 3 6 V external power supply for I Os and the internal regulator Provided externally through Vpp pins VppA 2 0to 3 6 V external analog power supply for ADC Reset blocks RCs and PLL minimum voltage to be applied to Vppa is 2 4 V when the ADC and DAC are used The VppA voltage level must be always greater or equal to the Vpp voltage level and must be provided first 1 6 to 3 6 V power supply for RTC external clock 32 kHz oscillator and backup registers through power switch when Vpp is not present For more details on how to connect power pins refer to Figure 9 Power supply scheme Power supply supervisors The device has integrated power on reset POR and power down reset PDR circuits They are always active and ensure proper operation above a threshold of 2 V The device remains in reset mode when the monitored supply voltage is below a specified threshold Vpon ppn Without the need for an external reset circuit e The POR monitors only the Vpp supply voltage During the startup phase it is required
44. v 2 5 5 Description STM32F051x 1 Description The STM32F051 xx family incorporates the high performance ARM 32 bit RISC core operating at a 48 MHz frequency high speed embedded memories Flash memory up to 64 Kbytes and SRAM up to 8 Kbytes and an extensive range of enhanced peripherals and I Os All devices offer standard communication interfaces up to two 2 5 two SPIs 125 one HDMI and up to two USARTs one 12 bit ADC one 12 bit DAC up to five general purpose 16 bit timers a 32 bit timer and an advanced control PWM timer The STM32F051xx family operates in the 40 to 85 C and 40 to 105 C temperature ranges from a 2 0 to 3 6 V power supply A comprehensive set of power saving modes allows the design of low power applications The STM32F051 xx family includes devices in three different packages ranging from 32 pins to 64 pins Depending on the device chosen different sets of peripherals are included The description below provides an overview of the complete range of peripherals proposed in this family These features make the STM32F051xx microcontroller family suitable for a wide range of applications such as application control and user interfaces handheld equipment A V receivers and digital TV PC peripherals gaming and GPS platforms industrial applications PLCs inverters printers scanners alarm systems video intercoms and HVACs 6 9 Doc ID 018746 Rev 2 ky
45. ween low power consumption short startup time and available wakeup sources e Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interrupt event occurs e Stop mode Stop mode achieves very low power consumption while retaining the content of SRAM and registers All clocks in the 1 8 V domain are stopped the PLL the HSI RC and the HSE crystal oscillators are disabled The voltage regulator can also be put either in normal or in low power mode The device can be woken up from Stop mode by any of the EXTI lines The EXTI line source can be one of the 16 external lines the PVD output RTC alarm COMPx 12 1 USART1 or the CEC 2 1 USART1 and the CEC can be configured to enable the HSI RC oscillator for processing incoming data If this is used the voltage regulator should not be put in the low power mode but kept in normal mode e Standby mode The Standby mode is used to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire 1 8 V domain is powered off The PLL the HSI RC and the HSE crystal oscillators are also switched off After entering Standby mode SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry The device exits Standby mode when an external reset NRST pin a IWDG reset a rising edge on the WKUP pins or an RTC alarm occurs The RTC the IWDG and the
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