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ST AN3261 Application note Dual push-button Smart Reset devices with user-adjustable setup delays handbook

1. way AN3261 Sf Application note Dual push button Smart Reset devices with user adjustable setup delays Introduction The Smart Reset family of devices consists of several products with a combination of features selected to best suit most typical applications Their basic common feature is dual button reset with setup delay that requires both input reset buttons to be continuously pressed for a defined period of time This improves system stability compared to simple manual reset button devices and eliminates the need for a traditional reset access hole e g two standard keys on the mobile phone keyboard can be used as Smart Reset inputs Numerous additional features and device options are factory programmed or can be implemented upon request Common STM65xx Smart Reset family features include Dual button Smart Reset inputs Vcc range 1 0 to 5 5 V active low output valid Industrial operating temperature range 40 C to 85 C Space saving TDFN8 package 2 mm x 2 mm x 0 75 mm RoHS compliance Differentiating features of the devices are m With or without Power on Reset POR m With or without Vog monitoring m Independent battery monitoring feature with battery low warning STM6505 only m Input logic voltage levels standard CMOS or fixed threshold m Smart Reset output characteristics Defined reset pulse duration or push button controlled undefined reset pulse duration Reset pulse duration f
2. Doc ID 17837 Rev 1 17 17
3. TSR 100ka lt STM6503 100 ka si v SR1 i i O O PUSH BUTTON PUSH BUTTON SWITCH SWITCH Figure 4 Timing diagram dual push button Smart Reset SRC A tREC i 1 I RST Doc ID 17837 Rev 1 7 17 Typical application diagrams AN3261 2 3 8 17 Multiple button reset Adding even more input buttons is possible by adding a simple OR gate All of the buttons must then be pressed simultaneously for at least tspc input delay seconds to get a reset pulse on the STM65xx output For a configuration with three input reset buttons connect one button to one SR input as usual and the remaining two buttons to an OR gate and tie its output to the second SR input Figure 5 Three push button delayed Smart Reset typical application diagram STM6503 Voc 100 kQ 100 kQ SRO Oo e STM65xx Doc ID 17837 Rev 1 ky AN3261 Typical application diagrams 2 4 2 5 Figure 6 Timing diagram three push button Smart Reset tsrc Push button 1 i Push button 2 Push button 3 RST Input pull up considerations CMOS fixed levels Inputs without internal pull up resistors can be pulled to a different voltage level than the supply voltage of the STM65xx devices however e the input pull up voltage level should not exceed 5 5 V e the input logic levels specifications must be respected Viymin 0 7Vcc V max 0 3Vcc in
4. case of standard CMOS input cells it is recommended to always keep Vj on the ground level and Vip on the Vcc level Viymin 0 85 V V max 0 3 V in case of the fixed logic levels devices STM6520 STM6522 Output pull up considerations Open drain RST outputs without internal pull up resistors can also be pulled up to any voltage independent of Vcc higher or lower than Vcc but absolute maximum ratings must be respected The STM65xx devices can thus serve also as a simple level shifter Doc ID 17837 Rev 1 9 17 Typical application diagrams AN3261 2 6 10 17 Reliability note Devices with timings adjusted by external components vs environmental considerations For device options with timings tsrc trec adjusted by an external capacitor there are several additional factors to be considered that may affect the accuracy of the timings The given specifications apply to the STM65xx device alone i e with an ideal timing capacitor External tolerances temperature dependencies and leakages are excluded The Smart Reset devices are designed to meet strict requirements for the lowest possible current consumption and to maintain the common timing constant 10 s uF therefore the constant current used to charge the external timing capacitor is very low in the magnitude of 100 nA Any external leakage e g poor quality timing capacitors or excessive humidity especially if dew point is exceeded and moisture condensatio
5. diagram STM6503 7 Timing diagram dual push button Smart Reset cee ee 7 Three push button delayed Smart Reset typical application diagram STM6503 8 Timing diagram three push button Smart Reset M 000 eee 9 Smart Reset demonstration board STM6503 ii 11 The STM65xx interposer boards a dedicated board is available for each STM65xx Smart Reset device ii 12 Smartphone demonstration example shows STM6503 implemented in an actual APppliCa ON been nth A oe esas e KAN ae ERS man Rotan A 13 Smart Reset demonstration in an actual smartphone application 14 Doc ID 17837 Rev 1 3 17 Features AN3261 4 17 Features e The Smart Reset functionality is a feature that introduces a reset output response delay Both of the Smart Reset input buttons must be pressed for a defined tsrc period only after which an output reset pulse is generated This results in a robust hardware reset The reset function can then be assigned to the existing keys of a device which eliminates the traditional reset hole in the back cover of the device while maintaining system stability All the STM65xx family devices have this feature with the exception of the STM6504 e The edge trigger functionality is a reset input with an immediate reset response and a special debounce feature Found only on the STM6504 a device with single button edge trigger immediate
6. is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER
7. 13 17 Demonstration boards promotion tools AN3261 14 17 Smart Reset concept demonstration e Push ON OFF button gt goes into a normal ON state amber display backlight on e Push stuck button goes into stuck mode that simulates frozen smartphone red display backlight on during which it cannot even be turned off e Push SRO and SR1 buttons simultaneously for 2 6 or 10 seconds minimum jumper selectable returns to the normal state from which it can be turned off by pressing the ON OFF button Figure 10 Smart Reset demonsiration in an actual smartphone application Hardware reset without a battery removal or back side reset hole press SAO and SH1 butions lor min 2 6 or 10 seconds Normal mode Stuck mode Normal mode Doc ID 17837 Rev 1 ky AN3261 Conclusion 4 Conclusion The family of Smart Reset devices provides a variety of smartphone or PDA hardware reset solutions some examples of which are shown in this application note others are in the datasheet of the specific device The most up to date information on the Smart Reset portfolio can be found at www st com smartreset Doc ID 17837 Rev 1 15 17 Revision history AN3261 5 16 17 Revision history Table 1 Document revision history Date Revision Changes 22 Sep 2010 1 Initial release Doc ID 17837 Rev 1 AN3261 Please Read Carefully Information in this document
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9. actory programmed or capacitor adjustable Smart Reset delay tri state dual state capacitor adjustable Open drain or push pull reset output Single or dual reset output September 2010 Doc ID 17837 Rev 1 1 17 www st com Contents AN3261 Contents 1 Features ai en aaa na A an EA O ea 4 2 Typical application diagrams c c c ocococococ c c c 5 21 Single button reset ii 5 2 2 Dual button reset Ha AA rra EA RS 7 2 3 Multiple button reset annuau auaa eaaa 8 2 4 Input pull up considerations CMOS fixed levels 9 2 5 Output pull up considerations cia bkan ee amen aa 9 2 6 Reliability NOW sis anar as Kemen dia obs ae Me aa 10 3 Demonstration boards promotion tools 11 3 1 STM6503 demonstration board na 11 3 2 STM65xx interposer boards ii 12 3 3 Smartphone demonstration example ii 13 4 CONCIUSIO Nr dn aa a una aa ee DE RA ea da 15 5 Revision history sn an am aa ha 16 2 17 Doc ID 17837 Rev 1 ky AN3261 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Single button Smart Reset typical application diagram with early warning feature STM6503 oo 5 Timing diagram single push button Smart Reset La 6 Dual push button Smart Reset typical application
10. n occurs on the PCB tracks may cause a significant leakage current which is deducted from the constant charging current that the device provides reducing the effective external timing capacitor charging current which results in extending the tsrc trec timings To minimize this effect the PCB tracks between the SRC TRECap pin and its respective timing capacitor should be as short as possible properly covered with solder mask and isolated from other tracks especially Vss by as great a distance as possible Also low leakage timing capacitors ceramic or film capacitor should be used Doc ID 17837 Rev 1 ky AN3261 Demonstration boards promotion tools 3 3 1 Demonstration boards promotion tools A complete set of demonstration promotion tools is available for various purposes from easy high level application functional demonstration down to tools for detailed testing These tools are based on the STM6503 as the primary representative of the Smart Reset family as the basic Smart Reset functionality is common STM6503 demonstration board Purpose The demonstration board serves as a functional demonstration of the Smart Reset devices and the easily accessible test points provide for basic measurements and testing Figure 7 Smart Reset demonstration board STM6503 ai SW2 SWi Simultaneous push of the SRO and SR1 buttons is indicated by an LED LED and audible indication of the reset pul
11. reset and a single button delayed Smart Reset input independent but with a common reset output e Vcc monitoring undervoltage reset When the monitored Vcc voltage drops below the factory programmed undervoltage reset threshold Vrsz the reset output s immediately go active and remain so until Vcc rises above Vegy and hysteresis plus the defined trec period e Battery low detection is an additional independent voltage monitoring function with a dedicated battery low detection output pin It works as a pure comparator with VreF 1 25 V STM6505 only e Fixed input logic levels are suitable for configurations where the device driving the input buttons keyboard is connected to a lower voltage than the supply voltage of the STM65xx device This is in contrast to the devices with the standard CMOS input logic levels that are relative to Vcc and are suitable only for applications in which the device driving the inputs of the Smart Reset device is powered by the same voltage supply Doc ID 17837 Rev 1 ky AN3261 Typical application diagrams 2 2 1 Typical application diagrams The STM65xx family of Smart Reset products provides a broad variety of options for various types of applications Single button reset The STM65xx devices allow for different reset input configurations In simple applications only one input reset button with delayed reset may be sufficient In this case for product options without internal inp
12. se after tspc reset delay Test points available for easy tracking of the Smart Reset signals Jumper selectable Smart Reset delay 2 6 10 seconds minimum Doc ID 17837 Rev 1 11 17 Demonstration boards promotion tools AN3261 3 2 12 17 STM65xx interposer boards Purpose The dedicated interposer PC boards were created for each STM65xx Smart Reset device for a quick and flexible application testing setup preparation The boards include labels on each pin for easy identification The pitch of the interposer pins easily fits into a breadboard and allows a very flexible application setup testing or soldering wires for external connections to a tester for example Figure 8 The STM65xx interposer boards a dedicated board is available for each STM65xx Smart Reset device Doc ID 17837 Rev 1 ky AN3261 Demonstration boards promotion tools 3 3 Smartphone demonstration example Purpose The STM65xx smartphone demonstration shows the Smart Reset concept and functionality in a real application dual push button delayed reset Figure 9 Smartphone demonstration example shows STM6503 implemented in an actual application rt Reset ends TEA frustration of frozen applications STM65xx Family Dual button delayed reset a Adjustable reset del a 1 65 V to 5 5 V operation ing TDFN 8L a Space saving 2x2x 0 75 mm package www st com smartreset ky Doc ID 17837 Rev 1
13. ut pull up resistors SRO and SR1 can be either connected together or the unused SR input permanently grounded In the case of a product version with internal input pull up resistors just connect the inputs together Permanent grounding of the unused SR input would in this case cause a continuous current to flow through the pull up resistor from Vcc to Vss Figure 1 Single button Smart Reset typical application diagram with early warning feature STM6503 100 kQ STM6503 TA TOOKS Early warning PUSH BUTTON SWITCH Y 1 Early warning feature the input reset push button can be also used as an early warning to the processor through the interrupt input that a reset may come after the tspc reset setup delay Doc ID 17837 Rev 1 5 17 Typical application diagrams AN3261 Figure 2 Timing diagram single push button Smart Reset tsRc SR1 RST 6 17 Doc ID 17837 Rev 1 ky AN3261 Typical application diagrams 2 2 Dual button reset The most freguent application reguires a configuration with two reset buttons which further improves immunity to undesired resets by adding a second input reset button with delayed reset In this case the reset pulse occurs only when both the buttons have been pressed and held for the defined tspc delay Figure 3 Dual push button Smart Reset typical application diagram STM6503 Vcc o e 100 KO

ST AN3261 Application note Dual push-button Smart Reset devices with user-adjustable setup delays handbook

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