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ST AN2559 Application note

1. 1 The Skip mode connector shown in the schematic as S5 S7 is dedicated for the control of Skip mode This connector setting is common for both channels Figure 7 shows the placement of the Skip mode connector while the settings are shown in Table 3 There are three possible settings Standard Skip mode No Audible mode or PWM mode In Standard Skip mode the converter reduces the switching frequency at light load to maintain good efficiency even in this condition There is no lower limit for switching frequency In No Audible mode the converter reduces switching frequency at light load but this frequency never drops below 30 kHz to avoid possible audible noise caused by the mechanical 9 35 PM6680A block AN2559 3 0 3 10 35 construction of passive components inductors or ceramic capacitors In PWM mode the converter maintains a constant switching frequency independently on the load The FSEL pin the PM6680A dedicated for operating frequency setting is connected to GND This means that the switching frequency of the Vcore branch is 200 kHz and switching frequency of Vyo is 300 kHz Figure 7 Skip mode connector A kot Vi o level Vcore level baa V 1 0 1 2 1 3 1 8 3 3 Table 3 Skip mode connector jumper settings Skip mode at light load No Audible Skip mode at light load frequency never drops below 30 kHz SR i PWM mode Constant frequency even
2. ee bores dE Peruri tii ii M t aliri TRET a ES DE ki La ar aaa AA PAN AAN AA APA EZ ARA AA TET TE E sis LL aur to ca Luar tt AAA LL 1 Ch2 10 0mY By M 2 0ps 250MS s 4 ns pt Ch2 10 0m Bw M 2 0ps 250MS s 4 ns pt A Ch2 200p A Ch2 4 2mY 1 0V 3 3 V Figure 24 Start up without setting the sequence M 1 0ms 2 SNS 400nsJpt amp Chi s 124 Chi 5 0Y i M 1 0ms 2 5MS s 400ns pt Chi 5 04 i M 1 0ms 2 5MS s 400ns pt Cha 2 04 A Chl 12V Ch3 2 04 A Chl 1 2Y 26 35 AN2559 Measurements 6 1 3 Start up sequence The correct start up sequence of the supply voltage is typically requested by the FPGA device Therefore there it is possible to set a dedicated start up Sequence on the System Supply board see 3 0 2 Figure 24 shows the start up sequence waveform of Veore and Vio outputs when the jumpers described in Table 2 are set in accordance with line 3 in the table The waveforms shown in Figure 25 illustrate different start up Sequences in accordance with the jumper settings displayed in Table 2 lines 4 and 5 6 1 4 Transient response Transient response refers to the behavior of the output voltage when the load changes fast This test was also performed on the outputs of the PM6680A branch The load was changed between maximum and zero load O 2 A on Vyo output and O 5 4 A on the Vcore output The input voltage was 12 V and output voltage was 3 3 V and 2 5 V respec
3. lout birilli peli LA hu SLI LLLA LLL Eb dle LLLI LLL LL GG E LLLI iti LLL i Li i LLILIL aS Lulu ILL Lui LiL LLL LLILIL eS Chi 1 04 Q Ch2 50 0mY Buy M 40 0ps 125MS s 8 0ns pt Ch1 1 0 Q Ch2 50 0mY By M 40 0ps 125MS s 8 0ns pt A Chi 1 064 A Chi x 1 064 28 35 GI AN2559 6 2 6 2 1 Y Measurements L5970AD blocks measurements Efficiency The L5970AD is a powerful converter with very good performance and efficiency Because a diode is used as a low side switch however the efficiency is a slightly less compared to a synchronous converter such as the PM6680A Theoretically the efficiency declines when output voltage is decreasing and input voltage is increasing Figure 28 displays the efficiency of Output 3 depending on the input voltage at full load 800 mA Figure 29 displays the same measurement for the Analog output The efficiency of the Analog output is better thanks to the higher output voltage level The efficiency of the Analog output voltage was measured in a range of 7 35 V It should be noted that the output voltage is 5 V so the device does not work as a switching converter in cases where the input and output voltage are similar or lower than the required output In this case the L5973AD works with 100 duty cycle Figure 28 Efficiency of output 3 by input voltage level Efficency Al12698 29 35 Measurements AN2559 Figure 29 Efficiency o
4. poof me sm aw oo o fh no me nem aw we fh De me fem NE GI 21 35 Bill of materials AN2559 Table 7 Bill of materials continued pon ren costos Time Sie umur arras _ CI sen se 3s Tw me serm aw we Tel me aware aw we oo mee araro aw ooh por me essre aw oes De me weirm sw we oo me ssena sw we io ww nem aw oe in rese zem 9e we ne mw serm 9e we ff ino mw sem aw oo maf mes Gam aw we qh mele essre ow ooh fie mw orere swo oo DH mw wem ow E qh ie mw sm aw oe oh LI MM NE EE WEN AMNEM GM 122 U4 KF25_ KF25_SOIC8 S08 8 KF25BD TR TR EM Hx STM6719TEWB6F SOT23 6 STM6719TGWB6F a 22 35 AN2559 6 6 1 Y Measurements Measurements The performance and properties of each part of the board is indicated in the measurements below These measurements were performed for the PM6680A and L5971AD blocks independently PM6680A block measurements The performance measurements of the PM6680A part focus mainly on efficiency light load consumption output ripple and transients Efficiency and light load consumption modes Since the device consists of three power parts two controllers and one LDO it makes sense to measure total efficiency Figure 17 displays how efficiency depe
5. O O O e Q e e O O O e 12 35 a AN2559 PM6680A block Figure 10 Jumper placement for Vio voltage level setting ao L I s8 Nal pa pra level U D Vcore level R107 2 34 Table 5 Vyo voltage level jumper settings Y 13 35 PM6680A block AN2559 3 1 14 35 DC DC converters based on the L5970AD There are two converters based on the L5970AD on the System Supply board the analog output and Vsys output voltage Figure 11 shows the arrangement of output voltages on connector J18 Figure 11 Output voltages of L5970A parts ASV 5 V Analog a al I mi La 3 3 V Analog GNO 3 3V 2 5V The L5970AD is a step down monolithic power switching regulator with a switch current limit of 1 5 A capable of delivering more than 1 A of DC current to the load depending on the application conditions The output voltage can be set from 1 235 V to 35 V The device uses an internal P channel D MOS transistor with a typical RDSon of 200 m9 as a switching element to avoid the use of a bootstrap capacitor and to gua
6. 3 or 5 On the other hand digital device consumption can change very quickly Several amps in a few hundred nanoseconds A power supply must be able to react very quickly with a minimum of over or under voltage especially in cases where very low output voltage is required There is additional stress placed on power supplies for digital applications in the industrial environment The industrial standard bus is 24 V but this voltage fluctuates and the maximum input voltage level required can reach 36 V Additional surge protection is also a mandatory part of power supply input for industrial applications The goal of the board described in this application note is to cover all of the issues outlined above It is intended mainly to satisfy industrial input requirements operating voltages up to 36 V and generate several output voltages for mid range power applications up to several amps The main output voltage level can simply be set September 2007 Rev 1 1 35 www st com Contents AN2559 Contents 1 Main characteristics ees 4 2 DCSCHONON E ci a AAN HE ba ew 5 2 1 DUR Da P 6 3 PM6680A block 6 iii rr 7 3 0 1 Power management block 0000 cee eee ees 8 3 0 2 Start up enable block LL 8 3 0 3 Step down parts ee eee ees 10 3 1 DC DC converters based on the L5970AD 14 3 2 acce PRETI 16 4 PCBISVOHE ice 32 e RED Za x ED EU a hee bd e NA E 18
7. Av 80 0m rrT TTTT TTT TTTTTTTTTTTT LALA T Pt tt t HH HHH rTTTTTTT lout BATA TTT TI bung SS LIII LL 1 1 LLL LL Ll DOLL Ss A A IL 1 1 LIL 1 1 L1 LL LL LLL I AL LL LL LL LL Ti LL LL 1 l1 LL LL LULU Lul Ch1 5DOmA lt Q Ch2 50 0mY JN M 40 0ys 125 M5 s 8 ns pt Chi 500mA Q Ch2 50 0mv BW M 40 0ps 125MS s 8 0ns pt Chi 230m A Chi x 140m4 CTTTTITTTTWTTTT TTTTTITTTTTTTTTTTTTTTTTTTTTTTTTTTTT TTTTITITINT TITE MA T TTT TT TTT TrTTT ITTTT ITTT TTTT LI ii HA Vaux TTTT ED HEE T VI E E HHHH ritiiii bees li Lepra al DEREI O LESI LL Ii Chi 100mA 2 Ch2 50 0mY A M 40 0ps 125MS s 8 nspt Chi 100mA 2 Ch2 50 0mY i M 40 0ps 125MS s 8 nspt A Chi 18 0m A Chi x 26 0m 33 35 Y References AN2559 7 References Datasheet PM6680A Datasheet L5970AD Datasheet LK112 Datasheet KF25 STM6719 AN1330 designing with the L5970D 1 A high efficiency DC DC converter OX Cr cow NYS 8 Revision history Table 8 Document revision history CC Ga 25 Sep 2007 Initial release a 34 35 AN2559 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this
8. is made incorrectly the input protection D1 shorts the input voltage It should be pointed out that the total input current is about 4 A at maximum output power and minimum input voltage Figure 4 Location and correct polarity of the input supply connector on the board EN CE GL st com ETHicroslactironica f7 ystem DEN upply PET STEVAL PSQ 6D1U1 br beh TA ou de SZA 6 35 PM6680A block AN2559 PM6680A block 3 Electrical diagram of the PM6680A section Figure 5 CLSVLIV AZ NE E da E a E JU 001 OX LS OY LG 0 9 9EH Sey SNS N3 IHO ON OL VEY Cd pow ds d ON OL LEH ZN Q SNS NI ZHO ZN ES Oda 0899INd E SA LN ON 1394 J3HA N3 sn DA 078 o Le ON 028 fox r6 Jd 021 dI S LNA dd 16 8014 Old ZaN9S 125 802H Z024 120 DAL TAZ ONE DIE WISI DIE BAZ DIL LOZ z0zH ozu voz AL eoty EOLY zoly LOY OY 01 Zed OCA A 9 An zz ovo LINO 400z S0ZH 0P11Sd1S 1094NZS LS ANDA co 6a AE 9 An ogg 629 ON C E 6OLY ASTO OASILOAGIOA L OAL 80 QOZISOLISO os O ss DA Ly OLLY lorisadis CA L3SN3SO CISNISI DN 8 9 ALOAZLOASLOASLOASZO gozu els O visQ sis O ais O zis O jual peg DI 79224 DA 00L0ER qu gL seg I31v91 ZILV9T ve Hnos 1 v9 Hlg 71 LISVHd CISVHd LILVOH CILVOH 8109 A UZX M0S AL E WX NOS J v LLOOg soal veo iad TT S H X A 08 3 zv HZXIA OS an Ly 3uooL HOL 61 9 810 Leo O9
9. layer AY Arete DICI m Ly ysten LE T Ico ta wuppiy A mae 4 1 af toon NI Vio level ee ca BND Reset n N o OE nga m SOTRESIA 51 18 35 AN2559 Bill of materials 5 Bill of materials Table 7 Bill of materials pon Tem esepton po Si Tag aree Cleo EA __ a 9 e mw aw ws e mw sw ooh e vw e wmv 9e s IIA re ee nis sw vee AX easar _ ref e mw aw oo Go ee mw aw ooh Le ew ww aw ws e es wav ow 8 OIEA La om smerev sw s COTE Do es ww 9 ee Do ew sayr sov sw vere CON Dm em ww aw oo ho ol os soo aw es Gao em rar 99 ooh Ta on wo 95 oo qh 2 c swwiesv Sub o AX T Tas o ww aw ess of Tao em r 99 we a om wo aw cos Lm om ssoperosv Asma Sub o AX onsa OIM ETA o AX Tesossrvoosxoos 9 ee ww aw ess om mw we ws oe w sw ws ho 19 35 d KG Bill of materials AN2559 Table 7 Bill of materials continued pon ron costos pe ue munus e ERT 9e ICI EE Ta c ww so II EE E Tas oe f sw osos Ta oo srsaw su sw or H or Bansasor suo wm To oe ssim suo poss ST srs _ Ta bo ssim suo pozem IN ow v sw soo 1 ae s Weenz O ar Wear m 0 als Weens m ho e fede
10. m 80 Vili names m ho 51 Weeks edens m sz 9 Weens m o see m wow Wer m e ws Wee om we mome m mon ESE ar wr maena TW Poo E Ta xs ics m Prom CESE e u ET sw Coa O e wu smnsa sw Coa O Ta 3 somsa Sub Coen Heera aas e u EI Sub Coen vsstosssens e a uA suo Coa veszne aa or Stssoneso suo ST SN GE e e stems suo roma res as stems suo roma m s s99 w 20 35 Ayr AN2559 Bill of materials Table 7 Bill of materials continued a e uve Sue Tag ae CI EIC HH CI E sw co m m wmm aw we m m s aw ooff r wm wem 9e we Fe m emn ow ooh m wmm aw coe fh ml ssa aw co Ge me aa aw ooh Gr an so 95 off Ge ano ara ow we Ge m aw oooh me son aw os oh mm o sw oo aa m ox aw ooh mo o 999 ws m o 99 oo a ms ea sw oooh ms oa 99 ooh Da mr ee aw os a ao wm aw oooh al ms sm aw oo oh m wm 9 ws m me wm aw oo m wm aw oo o ho ms sm aw cee o fh Da ae sm aw os o Doo m wa sw oo Doo me ssa aw oo o me ssa aw oooh Doo me wem aw oo oh al m sm aw ess
11. 4NZSLS szo ozu 094N07S1S zo LO Q UIA 10S 9GMV8 o DN ia o IN HZv Zed old NGHS 0414 ASE 3ME E qu 027 PE 6cH 919 SLO AOL AN LY JU 001 Grex pum PLO 42 vee 6H O O UTA OCIA 7 35 PM6680A block AN2559 3 0 1 3 0 2 8 35 The PM6680A block is most important part of board It contains two DC DC converters Each output has a selectable output voltage level The first converter is capable of delivering up to 4 A for each voltage level while the second converter can deliver up to 2 A on the output Both converters are controlled by the PM6680A device The PM6680A is a dual step down controller specifically designed to provide extremely high efficiency conversion with loss less current sensing The constant on time architecture assures fast load transient response and the embedded voltage feed forward provides nearly constant switching frequency operation An embedded integrator control loop compensates the DC voltage error due to the output ripple The pulse skipping technique increases efficiency at very light loads Moreover a minimum switching frequency of 33 kHz is selectable to avoid audio noise issues The PM6680A provides a selectable switching frequency allowing either 200 300 kHz 300 400 kHz or 400 500 kHz operation of the two switching sections The output voltages OUT1 and OUT2 can be adjusted from 0 9 V to 5 V and from 0 9 V to 3 3 V respectively A detailed description of this device can be found in the d
12. 5 Bill of materials eer Rr 19 6 Measurements i lt s e lt e e x x naar aerea 23 6 1 PM6680A block measurements ellen 23 6 1 1 Efficiency and light load consumption modes 23 6 1 2 Output voltage ripple nananana naaa ees 24 6 1 3 Start up sequence 1 ee rn 27 6 1 4 Transient response ee eee 27 6 2 L5970AD blocks measurements es 29 6 2 1 Efficiency UrTT 29 6 2 2 Output voltage ripple nananana aaa ens 30 6 2 3 lcu q co gce sts 5 oe AA 33 7 MGlerences E DRE ET I OL T COO UT ew ee ee eee rra ee ee 34 8 Revision history scura ea arrendar iS Bu KA 34 2 35 KY AN2559 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 lt The STEVAL PSQ001V1 demo board 5 Block diagram of System Supply board 5 Schematic Of INDUL DOlLs au oe aue stred titrari nen ees reo red as S 6 Location and correct polarity of the input supply connector on the board 6 Electrical diagram of the PM6680A section o 7 The placement of
13. A AN HHHH TEA MEAN eer EN A X x il rl papasa Lcd doti LILILIA a ee LILILIA M 2 0ps 250MIS s 4 Ons pt 10 0mY M 2 0ps 250MIS s 4 Ons pt A Ch2 3 0mY A Ch2 3 0mY ria TED Toa ar Masa Mace Ch2 10 0mY HER LLL HH o lt N a lt Figure 21 Output voltage ripple of Vcore at the maximum output voltage 36 V THT MANA MU KABA TTT O O O O ELLE VR O BARE erre peer LLLA TT TT rallisi PLL a aaa TITI TAN Rana PATA NG TA NG NG KN lerrr t EN TAART naaa TTS ST HSS A TUT T y HH rriz zt J J O O O a aan O A A E aaa Ch2 10 0mY Bw M 2 0ps 250MS s 4 0nsihpt Che 100mv id te pdr AA A Ch2 3 0m ne P SOMME N tn lt 0 9 V Figure 22 Output voltage ripple of Vio at the minimum input voltage 5 V HH HHHH illa tii TTT TTT LAAL Naa ERE TT TrTT TTTTTITTTTTT TL 1a pa Dara ra daa ra La raa AA ili sv siatligs H Ch2 10 0rnv M 2 0ps 250M15 s 4 Ons pt Ch2 10 0mY By M 2 0ps 250M545 4 Onis Apt A Ch2 3 0mY A Ch2 3 0mY o lt a 25 35 Measurements AN2559 Figure 23 Output voltage ripple of Vio at the maximum input voltage 36 V TTT tt AGA AA ANAN AWA AN rrTTTWUTTTD TTTTTTTTTTTTTTTTTTTTTTTTT TTTTTTTTTTTT T T EH ee roritiriritiiig per tii TASA EL ELA E NAAN LS Se RL BT Luy
14. PANZA AJA Applicationnot System power supply board for digital solutions Introduction This document describes a power supply reference board designed for powering digital applications such as CPUs FPGAs memories etc The main purpose of the board is to illustrate the basic principles used for the design of the power supply and to give designers a usable prototype for testing and use The trend in recent years in the supplying of power to MCUs CPUs memories FPGAs etc is to reduce the supply voltage increase the supply current and provide different voltage levels for different devices in one platform A typical example of this situation is the FPGA The FPGA contains a core part which works at a low level voltage the interface part placed between the core and the output the system part etc It is important to note that each FPGA family has a slightly different voltage level and the trend is to decrease the voltage for each new family The lowest operating voltage currently available is 1 V and this can be expected to decrease to 0 9 V or 0 8 V in the near future A similar situation exists with other digital applications Typically the main CPU memory and interfaces require different supply voltage levels Low operating voltages also present another challenge transient Digital devices are typically sensitive to voltage level If the voltage drops below or crosses over a specific limit the device is reset This limit is typically
15. T SPACE LIFE SAVING OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2007 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Y 35 35
16. at light or zero load Step down parts The PM6680A is a dual step down controller and drives two step down converters The schematic of both channels are almost identical with only a few small differences Since each channel is for a different output power the main difference is in the components values Figure 8 displays the output connector polarities of the PM6680A section lt AN2559 Y PM6680A block Figure 8 Output connector 1 0 3 3V 2A 317 The power components of the step down part are input capacitors C23 C24 or C18 C41 the half bridge driver containing two N channel MOSFETs Q2 Q3 or Q1 inductors L4 or L3 and output capacitors C28 C29 C40 or C22 C39 Ceramic high capacitance capacitors are used as input capacitors 60 V MOSFETs are used for the half bridge driver A relatively high breakdown voltage is used to guarantee operation in industrial applications Because the Vo output is designed for lower currents 2 A both MOSFETs are integrated in one SO 8 package Q1 STS4NF60 This helps to reduce the size on the PCB Two discrete MOSFETs STS7NF60 are used for the Vcore higher power output 4 A Schottky diodes are also used in each channel D9 or D8 These diodes work mainly during dead time and are not mandatory for proper functioning but their application increases efficiency The 5 pH inductor L3 is used for the Vua output with saturation current at 3 A The inductor L4 has value o
17. atasheet Figure 5 shows the full electrical diagram of the block with the PM6680A that controls the two DC DC converters The components around the PM6680A form several functional blocks the power management block Vcore step down block Vijo step down block and start up enable control system block Power management block The PM6680A has two supply voltage inputs Vcc and Vin The Voc pin should be connected to the 5 V bus maximum input voltage is 6 V minimum 4 5 V and it is dedicated for the supply of the chip itself The Vin pin should be connected to the input power bus and it is used inside the chip for two reasons The first is to supply the integrated LDO The second is the fact that the controller must sense the converter input voltage level for proper functioning of the converter The Vcc pin is supplied from the integrated LDO connected output of LDO and Voc on the reference board The V5SW feature of the LDO is disabled The power management block consists of components C14 C17 C31 R9 R29 R37 and D10 The important parts of the power management block of the device are the low pass filters R9 C16 C17 and R37 C31 applied to reduce the influence of transience on the device Vcc and Viy main power inputs The resistor R29 and the diode D10 generate the SHDN shut down signal which is active in low level This signal activates the PM6680A immediately after Vi is connected to the input The Vpep and LDO signals start to wo
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19. enuate the affect of the noise to stabilize the SMPS by implementing the so called Virtual ESR network which increases the amplitude of the feedback ripple voltage and improves signal to noise ratio The Virtual ESR network does not increase the output ripple voltage It is recommended to use the Virtual ESR network in cases where the output voltage ripple is below 30 mV However it is necessary to 11 35 PM6680A block AN2559 take into consideration that the influence of noise on the performance of the SMPS strictly depends on the PCB layout Therefore the 30 mV is an indicative value Virtual ESR Networks are applied for each channel on the reference board described in this application note The main reason for this is the fact that the SMPS based on the PM6680A device can generate different output voltages at a wide input voltage range As output voltage ripple depends also on input and output voltage level there are configurations where the Virtual ESR network could be mandatory Virtual ESR networks consists of R40 R39 C35 or R27 R38 or C34 The ESR network can be removed to observe influence of ESR network to board function To remove the Virtual ESR Network R40 and R27 must be removed and R39 and R38 respectively must be shorted Figure 9 Jumper placement for Vcore voltage level setting go Vi o level HD Vcore level R107 2 9V 1 0 1 21 5 1 8 R205 R206 Table 4 Vcore voltage level jumper settings Jumper settings
20. f 3 8 uH with saturation current at 6 A A combination of tantalum low ESR and ceramic type are used as output capacitors Ceramic capacitors help to reduce total output ESR and reduce total output voltage ripple The PM6680A includes a half bridge driver for each channel The external bootstrap diode and capacitor must be applied D7 C19 or C25 in order to drive the gates of the high side MOSFETs The feedback signal is generated by the output voltage divider R10x or R20x The board allows the setting of different output voltages for both channels Figure 9 and Figure 10 display the output voltage connector placement on the board for each channel The jumper settings are shown in Table 4 and Table 5 respectively In classic Constant On Time control the system regulates the valley value of the output voltage and not the average value In this condition the output voltage ripple is a source of DC static error To compensate for this error an integrator network is introduced in the control loop by connecting the signal output voltage to the COMP1 COMP2 pin through a capacitor C20 or C26 An additional R C network R11 and C21 or R20 and C27 is implemented as a low pass filter to reduce noise on the input of the COMP pin Since the feedback signal of the SMPS working in Constant On Time control is directly connected to the PWM comparator the stability of the SMPS is more sensitive to noise injected into the FB signal It is possible to att
21. f analog output by input voltage level Efficency Al14500 6 2 2 Output voltage ripple The output voltage ripple of the switching parts of the Analog and Vsys outputs are shown in Figure 30 and Figure 31 The measurements were made for different input voltages because the current ripple influence on the output voltage ripple depends on the input voltage level The output voltage ripple on the 3 3 V Analog output and the Vaux output are displayed in Figure 32 and Figure 33 As these outputs are generated by LDOs the output voltage ripple is the same independent for all input voltages and is very low Therefore only one output voltage ripple image is shown in the figures 32 and 33 All of the measurements were taken at full output load Figure 30 Analog 5 V output voltage ripple ILALLI LLLA LLL LIA ee E TS LIA L1 LAAL LLL LLLI LLLI M 1 0ps SOOMS s 2 ns pt Ch2 10 0mY Bw M 1 0ps SOOMS s 2 ns pt A Ch2 10 8mY A Ch2 10 8mY Vin 35 V Vin 7 V lt 30 35 AN2559 Measurements Figure 31 Vsys output voltage ripple Tw tt a a a TA riety Ter IE EEA EHHH WEWNNNNNNNNNNRNNNENNRNENNNENNEENENENNNNENNNEEENENENE EMEN a aca adea a aaa aiia T aa a Lacan daa aia a aea Ch2 10 0rnv y By M 1 0ps SOOMS s 2 ns pt Ch2 10 0m y Bw M 1 0ps SOOMS s 2 Ons Apt A Ch2 400p A Ch2 400uY Vin 35 V Vin lt B V Figure 32 Analog 3 3 V output volta
22. ge ripple iD a a 19 684 TT TT Erz pA Ltt rall 4 4 cl LL Ll pasala tori i lira ls ss rere torr tori i tipi laya Ch2 10 0m By M 200ys 125MS s 8 0ns pt A Ch2 3 4mY 31 35 a Measurements AN2559 Figure 33 Vaux 2 5 V output voltage ripple B TWO TTT TT 1T T1 aa a TTTT Terry TUT FT rie D DH HEE ZEE ETTTTTTTTTTTTTTTT AA 9 7 ot 4 4 4 4 L sk L L L L L as L L L H l L Bia Cees ilisr i dissi ili vidi ii tir tii tii tira tii iit Ch2 10 0mY M 20 0ps 125MS5 s 8 0ns pt A Ch2 3 0mY a 32 35 AN2559 Measurements 6 2 3 Transient Transient responses were measured only for Vayx and Vsys The transient responses are displayed in Figure 34 and Figure 35 The transient waveforms of the L5970AD section show the response time The most visible difference between the L5970AD in classic voltage mode and the PM6680A working in Constant On Time mode is the reaction when there is a fast load increase Whereas the PM6680A reacts asfast as possible on the rising load the L5970AD will wait short time as the compensation network is implemented in feedback loop see Figure 24 and Figure 25 Figure 34 Transient response of Vsys based on the L5970AD LANE ANAL AN peter EN ee ES ee EN ANA Tee errr errs er ee ee ee ee E ee ee TCCDA 5455 Y 3 2344 33124 24 N Z 3 3 78 0rmV bung VI 3 234V Vo 3 1 54V 1 AM oY
23. nds on input voltage level at full load output Vcore 2 5 V 4 A VyG9 3 3 V 2 A Figure 17 Efficiency of the dual step down converter at full load Efficency 96 UH TOE AY AAA TT Al12696 The efficiency is in the range of 83 91 It should be noted that the total efficiency strictly depends on the performance of each component The System Supply board was designed to satisfy a wide input voltage range Therefore 60 V MOSFETS are used on the board If the input voltage of the end application is less up to 30 V for instance efficiency can be improved by using lower RDSon 30 V MOSFETs in the same package The expected efficiency gain is about 3 4 The PM6680A can work in several modes with regard to light load These options are mainly used for battery applications where relatively high consumption at light load can drain the battery even when no power is requested The PM6680A allows three modes see 3 0 2 PWM No Audible Noise and Skip Figure 18 shows the consumption of the board for different modes of the PM6680A There is no load on the output and other parts of the SMPS are disabled 23 35 Measurements AN2559 Figure 18 Figure 19 24 35 PM6680A consumption at no load condition in the different modes Pa TO TTT n n Po 0 5 10 15 20 25 30 35 40 Vin V Al12697 In analyzing the data in Figure 18 it should be noted that the consumption is slightly increased by several passive component
24. od after ALL supplies rise above their respective thresholds and MH returns to High This device is guaranteed to be in the correct reset output logic state when Vcc and or Veco is greater than 0 8 V This device is available in a standard 6 pin SOT23 package SZA AN2559 PM6680A block Figure 14 shows the schematic and placement of the reset part on the board Typically in real applications the reset circuit senses if the supply voltage drops below about 10 of nominal value This feature cannot be implemented on the System Supply board due to the fact that the output voltage is selectable while the reset voltage is factory set There are several types of reset circuits in the STM6719 family see datasheet Of these the STM6719TGWBGF was selected as optimal The voltage thresholds of this device are 3 075 V 1 11 V and 0 626 V Figure 14 Schematic of the reset circuit and board placement U6 My Mm CH m L c cC Ld es GND O J15 Reset GND Al12695 Y 17 35 PCB layout AN2559 4 PCB layout The System Supply board utilizes a four layer PCB The copper layout of each layer is shown in Figure 15 and Figure 16 The top and bottom layers show also the placement of the components To reduce the size of board while maintaining the ability to change some components size 0603 was used for the majority of the passive components All views of the PCB are from top side Figure 15 PCB top layer layout and first internal
25. operate Thus the DC the jumper must be shorted for the converter to operate see Figure 13 for board placement of the jumper and Table 6 for the jumper settings 15 35 PM6680A block AN2559 3 2 16 35 Figure 13 Jumper placement for enable disable function of analog output and output3 ani epr jul ay nn st con T Su C Or sv e Padovi STEVAL PSQODIVI cia Table 6 Jumper settings for enable disable function of analog output and output3 sk ati Analog disable U mE There is an LDO linear regulator U2 and U4 on the output of each DC DC converter The LK112_33 is a 3 8 V linear regulator in a SOT23 5 package The KF25 is a very low dropout regulator with an output voltage of 2 5 V and output current of up to 400 mA Reset circuit The board also features a reset circuit which supervises the output voltages It is based on the STM6719 series of low voltage low supply supervisors which are designed to monitor three system power supply voltages Two monitored supplies Vcc and Veco have fixed factory trimmed thresholds VY psr and Vacqo The third voltage is monitored using an externally adjustable RSTIN threshold 0 626 V internal reference If any of the three monitored voltages drop below its factory trimmed or adjustable thresholds or if MR is asserted to logic low an RST is asserted driven low Once asserted RST is maintained at Low for a minimum delay peri
26. rantee high efficiency An internal oscillator fixes the switching frequency at 500 kHz to minimize the size of external components Having a minimum input voltage of only 4 4 V it is particularly suitable for 5 V buses found in all computer related applications Pulse by pulse current limiting with internal frequency modulation offers effective constant current short circuit protection The schematic of both SMPS s is displayed in Figure 12 As the schematic shows designing with the L5970AD is very simple It consists of a power part feedback and enable disable connectors The power part contains an input capacitor C2 or C8 ceramic is recommended an inductor L1 or L2 an output capacitor C5 or C11 and a freewheeling diode D4 or D6 The feedback part consists of a voltage divider R2 R3 R4 or R6 R7 R8 and a compensation RC network R1 C3 C4 or R5 C9 C10 lt PM6680A block AN2559 Figure 12 Schematic of the two SMPS s based on the L5970AD 7696 LIV A v 3d 0L CL omm 1 LNOA XNE A 8010S SCA vn SAS A VONO A9 3N OL EE CLIMI en O s s UIA ON LS cri NI A 2s 4dozz 69 A0S 3 v HNI QNO ONAS 381 dNOO vS L Hi ee Zl avoz6s71 EN OO OO LS LEU 3 Boreue Ls VLi HlOL SI A OS d Z p co Y G L HH cc Fl avoz6s1 LN Both converters can be switched on or off using the inhibit pin of L5970AD connected to jumpers S1 and S2 If the jumper is left open DC converter will not
27. rk simultaneously with activation of the SHDN pin Start up enable block The PM6680A has several inputs and outputs dedicated to the control of each channel Each channel has an independent Enable signal EN active in high level and power good signal PGOOD open collector activated by channel in cases where the output voltage is within 10 tolerance These control pins can be used either for simple enabling disabling or for delaying the start up of one channel rather than another The jumpers S3 and S4 with resistors R28 R31 R32 R34 R35 and R36 are used for systems independently allowing either enabling or disabling of each channel or setting up a different start up sequence of both channels Figure 6 displays the placement of jumpers S3 and S4 on the board and the settings are shown in Table 2 SZA AN2559 Y PM6680A block Figure 6 The placement of the jumpers for start up enable settings R10 2 34 R205 R205 Nal pa pra Vi o level Vcore level Y 15 0 1 21 5 1 8 34 Table 2 Start up enable jumper settings Both channels are disabled An open connector for each channel means that the channel is disabled e E o o z Both channels are disabled Both channels are enabled and start at same time O o e os Vcore Voltage starts first and Vio starts second jo i V jo Voltage starts first and Vcore starts second
28. s which generate inhibit of the L5970ADs Total consumption of these parts at 35 V on the input is about 1 5 mA This is not compensated for in the chart in Figure 18 It is possible to see the effect of the different operating modes of the converter by observing the output ripple voltage waveforms in Figure 19 These measurements are made under the following conditions Vcore output set to 2 5 V no load at 12 V on the input Output voltage ripple in different modes of light load operation Mo Audible Output voltage ripple Output voltage ripple depends on the current ripple flowing through the choke The current ripple depends on the input and output voltage levels Therefore it is mandatory to measure the output voltage ripple for different input and output voltage conditions Figure 20 shows the output voltage ripple of Vcore at the minimum input voltage 5 V while Figure 21 displays the output voltage ripple of Vcore at the maximum output voltage 36 V Figure 22 shows the output voltage ripple of Vio at the minimum input voltage 5 V and Figure 20 displays the output voltage ripple of Vio at the maximum input voltage 36 V All of the figures represent the minimum and maximum output voltages at maximum load 0 9 V and 2 5 V at 4 A for Vcore and 1 V and 3 3 V at 2 A for Vo ATI AN2559 Measurements Figure 20 Output voltage ripple of Vcore at the minimum input voltage 5 V 1 O JA T 37T 7T E AA a a aaa NA HAHHA A
29. sponse on Vygo output ee 28 Efficiency of output 3 by input voltage level lille 29 Efficiency of analog output by input voltage level 30 Analog 5 V output voltage ripple llli 30 Vaya Output VollageTIDple 3 xa e exin thurs Mew Rub see gu AAA 31 Analog 3 3 V output voltage ripple llle 31 Vaca V OUIDUL voltage TIDDIG maa m boner den ee ded RS PR xd aru i 32 Transient response of Vsys based on the L5970AD 0 eee eee 33 Transient response of Vayy generated by the LDO KF25 momo 33 3 35 Main characteristics AN2559 4 35 Main characteristics The main characteristics of the SMPS are listed below e Input 5 V 36 V DC surge protection e Outputs the performance of the 6 outputs are described in Table 1 below Table 1 Output voltages positive version Output Vcore Selectable from 4 A continuous 3 0 9 1 0 1 2 1 5 1 8 or 2 5 V 6 A peak Output2 Vio Selectable from 2 A continuous 3 1 0 1 2 1 5 1 8 2 5 V or 3 3 V 3 A peak a AN2559 Description 2 Description The System Supply board described in this application note is a dedicated design which illustrates a typical solution for complete system supply and can also be used as a direct supply for customer solutions during the design process Figure 1 The STEVAL PSQ001V1 demo board A a L a E k a a o n T 9 FF ress iF F irm The block diagram of the Sys
30. tem Supply board is shown in Figure 2 There are four DC DC converters two linear regulators and a reset circuit These parts are split into five relatively independent units the input part a dual DC DC converter based on the PM6680A and generating 2 outputs Output 1 and Output 2 two single DC DC converters based on the L5970A Output 3 and Output 4 with linear regulator and the reset circuit Figure 2 Block diagram of System Supply board STM6719 Reset signal E D analog Analog NNI 5 V analog 500 mA WE lag hs c T 3 3 V analog 150 mA Output 3 L5970AD FAA Vsys 3 3 V 400 mA KF25 Vaux 2 5 V 400 mA Skip mode settings 20d um Output 2 Vig 1 0 3 3V 2A booood Vi o Voltage settings Output 1 PM6680A E D start up sequence settings Pooood Vcore Voltage settings Al12693 a 5 35 Description AN2559 2 1 Input part The input part shown in Figure 3 consists of the input connectors industrial J16 or power jack J3 input storage capacitor C1 and transil D1 The input electrolytic capacitor and transil serve to reduce input voltage spikes Surge Figure 3 Schematic of input part Al12691 Figure 4 displays the placement of the input connectors on the board The board can be supplied either from the jack connector J3 or the industrial removable terminal plate J16 The polarity of the input voltage must be correctly applied in accordance with the illustration in Figure 4 If the connection
31. the jumpers for start up enable settings 9 Skip MOde CONNECION seem 6055 944040664445 RO RS ae eam ds ais did 10 OUIDULCONNCCION gs 2226 4 a a a ee oe aa a aac RC Eu da 11 Jumper placement for Vcore Voltage level setting 12 Jumper placement for Vyo voltage level setting 0 0 eee ee 13 Output voltages of L5970A parts 14 Schematic of the two SMPS s based on the L5970AD 0 0 eee 15 Jumper placement for enable disable function of analog output and output3 16 Schematic of the reset circuit and board placement 17 PCB top layer layout and first internal layer 18 PCB second internal layer and bottom layer layout 18 Efficiency of the dual step down converter at full load 23 PM6680A consumption at no load condition in the different modes 24 Output voltage ripple in different modes of light load operation 24 Output voltage ripple of Vcore at the minimum input voltage 5V 25 Output voltage ripple of Vcore at the maximum output voltage 36 V 25 Output voltage ripple of Vio at the minimum input voltage 5V 25 Output voltage ripple of Vio at the maximum input voltage 36 V 26 Start up without setting the sequence llle 26 Start up with a set sequence leer 26 Load transient response on VooRre OUIDUL ii 27 Load transient re
32. tively The repetition of load change was 500 Hz The results of the measurements are shown in Figure 26 and Figure 27 The voltage spikes caused by increasing the load are quite low lt is possible to observe that the converter reacts very fast to a rising load and the undervoltage is small left waveform in figures If the load is decreasing fast the overvoltage spikes appear on the output right side of picture This effect depends partly on the reaction of the controller and partly on the parameters of the output filter There is remaining energy stored in the inductor and if the load decreases this energy should be stored in the output capacitor This effect can be reduced by either reducing the value of the inductor to reduce the amount of energy stored in the inductor or by increasing the value of the output capacitor a higher capacitance is capable of absorbing more energy from the inductor Figure 26 Load transient response on Vcore output e O PO vrsili vili so 0l LELLA LL LUI LL LUI Lit pos kay magalaga laagalayyy M 40 0ps 125MS s 8 ns pt Ch 2 04 Q Ch2 50 0mY W M 40 0ps 125MS s 8 0ns pt A Chi 1 084 Chi x 1 084 Y 27 35 Measurements AN2559 Figure 27 Load transient response on Vio output lm at al iia aia a a UE 9 i Sd UNA NAG NANA a TTITTTY L I L E H I YAY HA De UTTTTTTTT LALA T Aa LS Nana TTTT T BELET LELE

ST AN2559 Application note

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