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ALTERA EPM5016 to EPM5192 EPLDS handbook

1. Ta Operating temperature Fremmeuuwe Ta Operating temperature Fornara TT of s e eae TT mel DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions min Typ jel Vo Watvevel TTL oweutvotage e curet Vi o fo Tri state output off state current Vo or GND Vcc supply current standby V or GND 110 150 V cc supply current active Vi or GND No load 115 175 mA f 1 0 MHz See Note 5 Symbol Parameter Min Output capacitance Vout 0 V f 1 0 MHz 140 Altera Corporation ALTERA CORP 47E D 1545372 0002158 82 MALT Data Sheet EPM5016 EPLD AC Operating Conditions See Note 4 T y 9 OF9 External Timing Parameters EPM5016 15 EPM5016 20 Symbol _ amp Conditions Min Max bo Inputtononvegisered ouput Ci 95 pF pa WO putto non registered out tsu Giobalciockseuptime Je o ous forz Ho o toy Isl Aray cekseupime s 1 amay docktoitime sl _ zs iT i aE 7 5016 17 See Note 6 Minimum global Minimum array lockperod acm Max intemal aray dock requeney Sene 1
2. gt o Internal Timing Parameters Note 8 5016 15 5016 17 EPM5016 20 Conditions Mn Wax min Mec wn mex umt ftin inputpadandbuterdely 4 5 woinputpadandbuterceey 4 l5 5l fExpanderaraydeay fo Logicaray delay O Logie control aray say Deer oo tey _ Resistersetuptine j Flowithroughiaich delay Register delay Dombmaoldi H Register hold time s lt lt lt lt EDEN lt lt gt e e e oe me Kan 9 mls FEET Ee E E EH 2 a t t Array clock delay ICS Global clock delay tep Feedback delay PRE Register preset time Register clear time ro fns 9 ns S pns 18 el 1 tn 1 r 9 r 2 ns _ __ 6 nes Altera Corporation 141 ALTERA CORP WE D 0545372 000215 763 WALT 5016 EPLD Data Sheet 7 94 2 A 2 Notes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions 2 Numbers in parentheses are for military and industrial temperature range versions 3 Typical values are for T4 25 C and Vo
3. so Hor 0G oupatcuren perpin 3 25 po Powerdisspaion_ ww Tera Storage temperare 6 10 eeweemeawe melee Recommended Operating Conditions See Note 2 Parameter Conditions Mm Max Unit v Operating temperature s 20 Ho ase temperature Frmmaywe 5 G5 mumeme e DC Operating Conditions See Notes 2 3 4 Symbol _ Parameer Conditions Min Typ Mex unt _ ja2 o Wu Lowievelinutvotage Tae v Von ouput votas Vo Lewieveloupurvotage zema v o 10 log Tiste ouput oftstatocunent Vo Vocorem wo o 225 2005 m leca supply current active Vi or GND No load 250 350 f 1 0 MHz See Note 5 Capacitance Parameter Conditions mn 00 Van TOME m p Page 158 Altera Corporation ALTERA CORP 47E D 0595372 000217 842 ALT Data Sheet EPM5128 EPLD T Y 9 AC Operating Conditions See Note 4 o 7 External Timing Parameters EPM5128 1 Symbol Parameter Conditions Min Max Input to non registered output 35 pF a 6
4. 22 vo KY PIA MACROCELL 88 VO INC M13 80 32 vo KO MACROCELL 87 vo M12 79 D2 26 vo MACROCELL 86 vo 63 N13 78 34 01 27 MACROCELL 85 vo M11 77 35 E2 26 vO _ F gt SF MACROCELL 84 vo 59 N12 76 36 E1 29 vo KA a MACROCELL 83 vo 8 0411 75 F1 INC vo KA MACROCELL 82 vo 57 M10 74 40 G2 NC VO MACROCELL 81 vo 581 N10 73 MACROCELLS MACROCELLS 411048 89 10 96 uso V Y 41 G3 30 vo MACROCELL 72 vo NC 58 42 61 31 vo MACROCELL 71 vo NC 57 45 32 vo MACROCELL 70 vo 55 56 4 61 83 VO MACROCELL 69 KC vo 54 N2 55 47 2 34 F gt MACROCELL 68 vo 53 2 54 355 vo uksa MACROCELL 67 Gol vo 521 041 59 49 K2 INC vo CD MACROCELL 66 vo 51 2 52 50 INC vo RO MACROCELL 65 vo to 5 MACROCELLS MACROCELLS 57 to 64 73 to 80 Altera Corporation Page 163 ALTERA CORP 47E D 0595372 0002181 LOT WALT 5130 EPLD T4 2 02 Data Sheet Absolute Maximum Ratings Note See Operating Requirements for EPLDs in this data book Symbol Supply voltage With respect to GND 2 0 Programming supply voltage See Note 1 20 135 V
5. Vpp i hax pwogesNomme TTT han Pa Power dscpaion c Recommended Operating Conditions See Note 2 _ Supplyvotage 0 0 0 0 0 0 0 475 45 52565 M eee peratng 0 o ir E mamme he 7 DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions V 08 Ve arme ius og UT ae NE 275 375 mA loz Tri state output off state current Vo or GND Voc supply current standby Vi 2 or GND Voc supply current active V or GND No load f 1 0 MHz See Note 5 Capacitance Input capacitance Vin OV f 1 0 MHz Output capacitance Vout OV f 1 0MHz 2 164 Altera Corporation gt o pF ALTERA CORP 7 D 0595372 0002182 046b MALT AC Operating Conditions See Note 4 7 7 07 External Timing Parameters EPM5130 1 EPM5130 Symbol Parameter Conditions Min Max mom Input to non registered output C1 35pF 25 5130 2 O 5 c S gt e 5 3 E 8 amp tonr Minimum global clock period Po
6. Max intemal global clock frequency See Note 5 Minimum array facwr intemal array clock frequency See Note 3 fmax Maximum clocktrequency seene ternal Timing Parameters See Note 8 EPM5130 1 Symbo Parameter Conditions Min Input pad and buffer delay NER WO input pad and bufer delay 5 0009 Regier deartime sl A e o m rnm a ALTERA CORP 7 D 0595372 0002183 MALT 5130 EPLD T 2 2 g Data Sheet Notes to tables 1 Q 3 4 5 6 7 8 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions Numbers in parentheses are for military and industrial temperature range versions Typical values are for 25 C and Voc 5 V Operating conditions Voc 2 5 V 5 T4 0 C to 70 C for commercial use Veco 2 5 V 10 T 40 C to 85 C for industrial use Voc 5 V 10 55 C to 125 C for military use Measured with a device programmed as a 16 bit counter in each LAB This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the t4 cj and tac parameters must be swapped The fmax values represent the highest fre
7. gt 11 AS 80 INPUT COO 14 83 INPUT CO 15 B7 84 INPUT OD 17 2 INPUT gt INPUT 44 N7 67 20 C6 5 INPUT gt CC INPUT 47 18 70 21 A5 6 INPUT CO INPUT 48 N9 71 22 5 INPUT gt lt INPUT 49 M9 72 Dedicated Inputs LABA Global Clock LABH 1 B13 MACROCELL 120 EC vo 100 2 C12 vo KA MACROCELL 119 vo NC 012 99 A13 vo MACROCELL 118 vo 771 013 98 B12 m vo KA MACROCELL 117 vo 76 E12 97 5 A12 12 VO macaoceus P gt lt MAGROCELL 116 K vo 75 E13 96 6 811 133 vo KA Sero PR MACROCELL 115 vo 74 F11 95 7 A11 INC VO TS MACROCELL 114 vo 73 G13 92 810 INC VO MACROCELL 113 vo 72 811 MACROCELLS MACROCELLS 9to 16 121 to 128 LABB LAB G z 23 A4 14 VO MACROCELL 104 vo NC G12 90 gt 24 B4 15 MACROCELL 103 vo NC H13 89 gt 25 16 vo MACROCELL 102 vo 71 13 86 m 26 2 17 vo MACROCELL 101 Evo 70 012 85 e 27 Ba 18 2H macrocera gt lt MACROCELL 100 vo es 84 at 1 ucro HES vo 29 B2 NC VO CS MACROCELL 98 vo 67 13 82 B1 NC VO MACROCELL 97 vo 64 L12 81 MACROCELLS MACROCELLS 251032 Programmable 10510 112 TUE T Interconnect 31
8. 5 V t 10 TA 40 C to 85 C for industrial use Vee 5 V 10 55 C to 125 C for military use b Measured with a device programmed as a 32 bit counter 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the t4 cj and tac parameters must be swapped 7 The fmax values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief 75 Product Availability Operating Temperature Commercial 0 C to 70 C Availability EPM5032 15 EPM5032 17 EPM5032 20 5032 25 5032 25 5032 25 Industrial 40 C to B5 C 55 C to 125 C Military Note Only military temperature range EPLDs are listed above MIL STD 883 compliant product specifications are provided in Military Product Drawings MPDs available by calling Altera Marketing at 408 984 2800 These MPDs should be used to prepare Source Control Drawings SCDs See Military Products in this data book Page 148 Altera Corporation ALTERA CORP Features General Description Altera Corporation 7 D ME 0595370 00021bb 973 WALT EPM5064 EPLD 19 0 High density 64 macrocell general purpose 5000 EPLD 128 shareable expander product terms providing flexible logic expansion Over 32 product terms in a single macrocell 64additional latches pr
9. Max Input pad and butter delay s gt gt Lg et g g 5 000S XVI M Logic array delay Logic control array delay Output buffer and pad delay C1 35 pF Output buffer enable delay Output buffer disable delay C1 5pF t t t t t sy Remesepme rg Flow trough ten dey m Rese teous iy Remerime ug array dock dey 7 posee E cs Global ro eme _ Recisterpresetine Altera Corporation Page 153 N 2 50 CH COMB H ics FD PRE CLA 2 A R a o NIN ALTERA CORP 47E 0595372 0002171 0 EE ALT EPM5064 EPLD Data Sheet T 46 07 Notes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions 2 Numbers in parentheses are for military and industrial temperature range versions 3 Typical values are for 25 C and Voc 5 V 4 Operating conditions Vcc 5 V 5 T4 0 C to 70 C for commercial use Voc 5 V 10 TA 40 C to 85 C for industrial use Voc 5 V 10 55 C to 125 C for military use 5 Measured with a device programmed as a 16 bit counter
10. With respect to GND See Note 1 Recommended Operating Conditions See Note 2 Voc Ne Fxwmmesawe a operating temperature Forausmalue 0 8 _ jem mE DC Operating Conditions See Notes 2 3 4 EE o o A 2 3 49 2 Low level input voltage High level TTL output voltage Low level output voltage EM Input leakage current loz Tri state output off state current or GND No load f 1 0 MHz See Note 5 Input capacitance Vin OV f 1 0 MHz 1 o Output capacitance Vour OV f 1 0 MHz 172 Altera Corporation ALTERA CORP 7 D WE 0555372 0002140 112 Data Sheet EPM5192 EPLD AC Operating Conditions See Note 4 72 0 2 79 Ds A External Timing Parameters EPM5192 2 Parameter Input to non registered output VO input to non registered output teo Itsy Global clock setup time ty Global clock hold time Global clock to output delay Global clock high time Conditions C1 35pF e lt 3 bud C1 35pF Itc Global clock low time tasu Array clock setup time tan Array clock hold time Itacoi Array clock to output delay C1 35 pF Maca Array clock high time See Note 6 Array clo
11. vo 65 63 23 31117 VOI MACROCELL 131 I 10 64 69 62 25 F1 20 OKH ____4 6 51___ MACROCELL 130 vo 61 F10 59 26 H1 21 vo KO Aa MACROCELL 129 vo 160 H11 se MACROCELLS MACROCELLS 53 TO 64 133 TO 144 LABE 27 H2 22 lt MACROCELL 116 E Vo 59 H10 57 28 23 WKS MACROCELL 115 KC vo 58 11 56 29 1 124 4 467___ FZ lt MACROCELL 114 I vo 57 611 55 30 02 5 vo i MACROCELL 113 vo i56 410 54 MACROCELLS MACROCELLS 69 TO 80 117 TO 128 uer V Y Vv 31 01 26 MACROCELL 104 vo 55 10 53 32 K2 27 o KO MACROCELL 103 E vo 151 011 52 31 vO KY MACROCELL 102 vo 50 K9 51 34 L2 321 10 KY MACROCELL 101 vo 149 L10 50 35 03 33 VO macroceuss P gt MACROCELL 100 KC vo 48 19 49 36 34 VO ET 7 MACROCELL 99 vo 47 48 37 L4 35 vo KO MACROCELL 98 KO vo 46 18 47 J5 136 VO KY MACROCELL 97 vo 45 6 46 MACROCELLS MACROCELLS 89 TO 96 105 TO 112 Altera Corporation Page 171 ALTERA CORP 47E 1545372 0002189 WE ALT 5192 EPLD T 6 9 O9 Sheet Absolute Maximum Ratings Note See Operating Requirements for EPLDs in this data book Symbol Parameter Supply voltage Programming supply voltage Vi DC input voltage
12. 5128 EPLD consists of 128 macrocells equally divided into 8 Logic Array Blocks LABs that each contain 16 macrocells see Figure 20 Each LAB also contains 32 expander product terms The EPM5128 EPLD has 8 dedicated input pins one of which may be used as a global synchronous system clock The EPM5128 device contains 52 I O pins that can be configured for input output or bidirectional data flow Four of the LABs have 8 I O pins and the other 4 have 5 I O pins Page 156 Altera Corporation ALTERA CORP 7 D 05953 0002174 MALT Data Sheet 5128 EPLD Figure 20 EPM5128 Block Diagram 7 Ju 49 5 Numbers in parentheses are for PGA packages 1 86 INPUT CLK gt lt INPUT A7 68 2 A6 INPUT gt lt INPUT A8 66 32 L4 INPUT gt lt INPUT L6 36 84 L5 INPUT gt PERMET INPUT K6 35 Dedicated Inputs LABA Global Clock LABH 4 5 0o KA MACROCELL 120 EC vo es 5 84 vo KD MACROCELL 119 A9 64 Vo KO MACROCELL 118 I vo 7 vo MACROCELL 117 KO vo A10 62 8 gt MACROCELL 116 ET vo 810 61 9 A2 VO MACROCELL 115 KT vo 811 60 10 82 VO MACROCELL 114 EC vo 611 59 11 WOKS MACROCELL 113 E vo 10 58 MACROCELLS MACROCELLS 9 16 121 to 128 8 VJ V 12 62 vo KY MACROCELL 101 vo D11
13. 57 13 WKS MACROCELL 100 E vo D10 56 14 02 vo Ln MACROCELL 99 EC vo E11 55 15 D1 vo KO macrocenzo MACROCELL 98 EC vo 53 17 WOKS S MACROCELL 97 EC vo 10 52 MACROCELLS MACROCELLS m y Programmable 10210 112 gt lt T 18 F2 PIA MACROCELL 85 E vo 811 51 19 F1 vo KO MACROCELL 84 E vo 49 21 81 vo KX MACROCELL 83 E vo 0110 48 22 vo 0 MACROCELL 82 vo 1 47 H1 vo KS SI MACROCELL 81 ED vo 01 46 MACROCELLS MACROCELLS 38 to 48 B6 to 96 so V Y V mwe 24 2 Vo KY MACROCELL 72 K vo 45 25 01 WOKS MACROCELL 71 O vo 44 26 vo KA MACROCELL 70 E vo 10 43 27 vo KT MACROCELL 69 Ko vo 09 42 28 2 gt MACROCELL 68 vo 41 29 vo MACROCELL 67 vo 8 40 La vo KO MACROCELL 66 1 0 31 vo KO MACROCELL 65 KO vo 07 38 MACROCELLS MACROCELLS 57 to 64 73 to 80 Altera Corporation Page 157 ALTERA CORP 47E D 1545372 0002175 MALT EPMSt28EPLD qe Sheet 5128 EPLD T 9 09 Data Sheet Absolute Maximum Ratings Note See Operating Requirements for EPLDs in this data book symbot _ Parameter mn max Win respect to GND 2s 79 See Note 1 20 15 v
14. 64 Dedicated Interconnect Expander Inputs Signals Product Terms Expanders are fed by all signals in the LAB One expander may feed all macrocells in the LAB or multiple product terms in the same macrocell Since expanders also feed the secondary product terms of each macrocell complex logic functions can be implemented without using additional macrocells Expanders can also be cross coupled to build additional flip flops or latches VO Control Each LAB has an I O control block Figure 5 that consists of a user configurable I O control function for each I O pin The I O control block Block is fed by the macrocell array The tri state buffer is controlled by a dedicated macrocell product term and drives the I O pad Page 130 Altera Corporation ALTERA CORP Programmable Interconnect Array Timing Model D 545372 0002198 88 MBALT Data Sheet EPM5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices Figure 5 1 0 Control Block T 90 01 The decoupled 1 0 control block features dual feedback to maximize use of device pins from Macrocell 5 OE Control from Macrocell Array VO Pin 1 Macrocell Feedback 1 VO Pin Feedback Each MAX 5000 EPLD has dual feedback a feedback path both before and after the tri state buffer for every I O pin The tri state buffer decouples the I O pins from the macrocells so that all registers within the LAB can be buried Thus I O pins can be config
15. EPLD that is optimized for pin intensive designs It provides a high density replacement for 7400 series SSI and MSI TTL and CMOS logic See Table 3 in this data sheet for QFP pin outs and Table 4 for PGA pin outs Package outlines not drawn to scale J H 9 5130 G Bottom OO F View OOGO E OG D GG c e Goo 66100 6 A lP OOOOOQOOOOOOE 12 8 4 5 6 7 8 9 10 11 12 18 PGA QFP Page 161 gt x lt e ALTERA CORP D 0595372 0002279 551 5130 EPLD 7 amp Data Sheet The 5130 EPLD is available in windowed ceramic 84 pin J lead chip carrier JLCC 100 pin pin grid array PGA and 100 pin quad flat pack WQFP packages as well as OTP plastic J lead PLCC and packages A single EPM5130 EPLD can quickly integrate multiple 20 and 24 pin low density PLDs and high pin count subsystems such as custom DMA controllers In addition it can handle a 32 bit data path application with enough I O to allow the required control signals to be implemented Figure 22 shows output drive characteristics of EPM5130 I O pins and typical supply current versus frequency for the EPM5130 EPLD Figure 22 EPM5130 Output Drive Characteristics and Ic vs Frequency 500 100 Q 400 E lt E Vcc 5 0 V t Vec 5 0 V T 300 Room Temp E Room Temp 8 40 200 amp lt 8
16. Feedbacks Note One global Clock per LAB 8 to 20 Programmable 32 to 64 Dedicated Interconnect Expander Inputs Signals Product Terms eliminating inefficient unused product terms Also expanders can be allocated to enhance the capability of the logic array 501 3 0009 Additional product terms called secondary product terms are used for Output Enable Preset Clear and Clock logic Preset and Clear product terms drive the active low asynchronous Preset and asynchronous Clear inputs to the configurable flip flop The Clock product term allows each register to have an independent Clock and supports positive and negative edge triggered operation Macrocells that drive an output pin may use the Output Enable product term to control the active high tri state buffer in the I O control block These secondary product terms allow 7400 series TTL functions to be emulated exactly The MAX 5000 macrocell configurability makes it possible to efficiently integrate complete subsystems into a single device All macrocell outputs are globally routed within a LAB and also feed the PIA to provide efficient routing of signal intensive designs Clock Each LAB has two clocking modes array asynchronous and global synchronous During array clocking each flip flop is clocked by a product Optio ns term Thus any input or internal logic may be used as a clock Systems that require multiple clocks are easily integrated into MAX 5
17. INPUT 90 C8 84 2 A5 92 INPUT gt 3 INPUT 89 C7 83 41 K6 39 INPUT gt a lt INPUT 42 L7 44 42 J6 40 INPUT gt INPUT 41 J7 43 Dedicated Inputs Global Clock LABA 4 05851 vo MACROCELL 184 vo Be 80 5 A4 96 vo KY MACROCELL 183 vo 85 79 6 497 vo MACROCELL 182 vo 84 78 7 A3198 vo KA MACROCELL 181 vo 831 9 77 8 2 09 vo P gt MACROCELL 180 vo 82 10 76 9 100 a MACROCELL 179 K vo 811 B9 75 10 ADI vo KA MACROCELL 178 IS vo 77 810 74 1 82 vo KS MACROCELL 177 vo re 11 73 MACROCELLS MACROCELLS 9TO 16 185 TO 192 LABB 12 C2 8 KY MACROCELL 164 I vo 75 C10 72 13 8 7 vo MACROCELL 163 FS vo 811 71 14 81 vo KSH F gt MACROCELL 162 2 vo 73 2170 15 02 9 vo Aa MACROCELL 161 vo r2 010 69 MACROCELLS MACROCELLS 21 TO 32 165 TO 176 uec V 7 16 D1 KA MACROCELL 148 I vo 71 011 68 gt 17 vo KS MACROCELL 147 vo 70 E9 67 20 F2 114 vo gt MACROCELL 146 SI vo 61 E11 es 3 21 Fa 15 vo KS MACROCELL 145 KC vo F11 64 MACROCELLS MACROCELLS e Programmable 149 TO 160 T Interconnect a LABD Arra LABI 22 G3 16 KD PIA MACROCELL 132
18. LABA Global Clock LAB D 2 vo MACROCELL 56 EC vo 1 4 vo KO MACROCELL 55 vo 44 5 vo KY MACROCELL 54 vo 42 KA MACROCELL 53 KA vo 41 7 ___ 5 gt MACROCELL 52 KO vo 40 yo MACROCELL 51 vo se MACROCELL 50 lt o MACROCELLS MACROCELL 49 KC vo 37 7 to 16 MACROCELLS 57 to 64 py MACROCELL 38 MACROCELL 37 Programmable T Interconnect LAB B 15 vo KJ 16 Vo KO MACROCELL 18 Vo 5 88 17 vo KA MACROCELL 36 gt 10 28 18 Vo KA MACROCELL 35 vo 27 19 _ macrocera gt MACROCELL 34 vo 26 20 vo KS Bae one MACROCELL 33 vo 24 22 vo KY MACROCELL 23 23 vo KO MACROCELL 24 MACROCELLS 25 to 32 MACROCELLS gt c 39 to 48 S Altera Corporation Page 151 ALTERA CORP 47 D 0595372 0002169 502 MALT EPMsOMEPLD 740 19 09 Datasheet Absolute Maximum Ratings Note See Operating Requirements for EPLDs in this data book conditons er un Yoo Supply voltage With respect to GND 20 70 v Programming supply voltage See Note 1 20 135 V Recommended Operating Conditions See Note 2 o o o pup 4 200 6 19 6 1 18 Mas M vee TT Ta Operating temperaure 0 70 CE DN 5 8 lt lt lt
19. Logic Systems Mentor Graphics and other workstation based CAE tools General MAX 5000 Erasable Programmable Logic Devices EPLDs represent a revolutionary step in programmable logic they combine innovative Descri ption architecture and state of the art process to offer optimum performance logic density flexibility and the highest speeds and densities available in general purpose reprogrammable logic These EPLDs are high speed high density replacements for SSI and MSI TTL and CMOS packages and conventional PLDs For example an EPM5192 replaces over 100 7400 series SSI and MSI TTL and CMOS packages integrating complete subsystems into a single package saving board area and reducing power consumption Page 126 Altera Corporation T 90 01 The MAX 5000 EPLDs range in density from 16 to 192 macrocells They are divided into two groups higher speed EPLDs EPM5016 and EPM5032 and higher density EPLDs EPM5064 EPM5128 EPM5130 and EPM5192 The higher speed devices achieve system clock frequencies of 66 MHz and are capable of counter frequencies of 100 MHz Logic Array Blocks The EPM5016 and EPM5032 EPLDs have a single Logic Array Block LAB The EPM5064 EPM5128 EPM5130 and EPM5192 EPLDs contain multiple LABs Each LAB contains a macrocell array an expander product term array and a decoupled I O block Expander product terms expanders are unallocated inverted product terms that can be used and shared by all ma
20. and PLDS HPS Development Systems or may be purchased separately MAX 5000 EPLDs can also be programmed with third party hardware see the Third Party Development amp Programming Support Data Sheet in this data book Contact Altera or your programming equipment manufacturer for more information Altera Corporation Page 135 ALTERA CORP 7 D NH 0595372 0002153 245 MALT Notes ALTERA CORP 7 D 0595370 0002154 141 WALT EPM5016 EPLD 7 4 G 19 OF Features High speed 20 pin DIP J lead or SOIC single LAB MAX 5000 EPLD Combinatorial speeds with tpp 15 ns Counter frequencies up to 100 MHz Pipelined data rates up to 100 MHz 16 individually configurable macrocells 32 expander product terms expanders that allow 34 product terms in a single macrocell Up to 21 flip flops or 32 latches Up to 10 input latches that can be constructed with cross coupled expanders 24 mA output drivers to allow direct interfacing to system buses Programmable I O architecture allowing up to 16 inputs and 8 outputs Available in 20 pin windowed ceramic DIP package or plastic one time programmable OTP DIP J lead PLCC and 300 mil SOIC packages Doo oo General The Altera EPM5016 EPLD is a Multiple Array MatriX MAX 5000 family HAE CMOS EPLD that is optimized for speed It can integrate multiple SSI and Description MSI TTL and 74HC devices In addition it can replace any 20 pin PAL or PLA device with log
21. are driven at 3 V for Delay aes Ses a logic high and 0 V for a amp mme logic low All timing Logic Array 29 a characteristics ds NIE ET p E DERE measured at 1 5 V tom _ P 60000 i Output Pin Y Array Clock Mode tti ac i je tace ci Clock Pin y y N Clock into 3 Logic Array y N Clock from d Logic Array Nel i 1 toy i t5 Ux eg qu pp PE Logic Array m rar N tons Register Output to local LAB Logic Array FEN Register Output Y to another LAB 22 Global Clock Mode Global Clock Pin Global Clock at Register Data from Logic Array Clock from Logic Array Data from Logic Array Output Pin 133 ALTERA CORP 7 D MI 0545372 000215 472 MALT 5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices Data Sheet Functional Testing MAX PLUS amp MAX PLUS Il Development Systems MAX 5000 EPLDs are fully functionally tested and guaranteed Complete testing of each programmable EPROM bit and all internal logic elements ensures 100 programming yield AC test measurements are performed under the conditions shown in Figure 8 T 90 01 Figure 8 AC Test Conditions Power supply transients can affect AC measure
22. f 1 0 MHz See Note 5 Capacitance Input capacitance Vin OV f 1 0 MHz 10 Output capacitance Vout OV f 1 0 MHz 146 Altera Corporation ALTERA CORP 47 D 0595372 0002164 020 MALT Datasheet PP EPL AC Operating Conditions See Note 4 7241 9 27 External Timing Parameters 5032 15 EPM5032 17 5032 20 5032 25 tasu taco clock to output delay 35 pF acu clock high time See Note 6 tcwr Minimum global clook period fonr tacwr facut fmax 2 lt lt E o a o Max internal global clock frequency See Note 5 76 9 Max internal array clock frequency See Note 5 See Note 7 0009 XVIN Logic array delay Logic control array delay Output buffer disable delay Ci 5pF Register setup time Altera Corporation Page 147 ALTERA CORP 7 0535372 0002 5 Th MALT EPM5032 EPLD 7 4 E 79 2 27 Data Sheet Notes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions 2 Numbers in parentheses are for military and industrial temperature range versions 3 Typical values for T4 25 C and 5 V 4 Operating conditions Voc 2 5 V 5 T4 0 C to 70 C for commercial use Voc
23. the EPM5192 PGA package Table 6 EPM5192 PGA Pin Outs 1 Vo B11 vO F9 K2 vO VO VO Vo INPUT INPUT CLK GND VO VO Vo VO vo vo Vo vcc Vo GND VO vO Page 176 Altera Corporation
24. 000 EPLDs Array Altera Corporation Page 129 ALTERA CORP 47E D NH 0595372 0002147 Tul MALT EPM5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices Data Sheet T 90 01 clocking also allows each flip flop to be configured for positive or negative edge triggered operation giving the macrocell a high degree of flexibility Global clocking is provided by a dedicated Clock signal CLK This direct connection provides enhanced clock to output delay times Since each LAB has one global clock all flip flop clocks within it are positive edge triggered from the CLK pin If the CLK pin is not used as a global clock it may be used as a dedicated input Expa nder The expander product term array Figure 4 contains unallocated inverted product terms that enhance the macrocell array Expanders can be used Product and shared by all product terms in the LAB Wherever extra logic is needed Terms including register control functions expanders can be used to implement the logic These expanders provide the flexibility to implement register and product term intensive designs for MAX 5000 EPLDs Figure 4 Expander Product Terms to Macrocell Array and Expander Product Term Array Expander product terms are unallocated logic that can be used and shared by all macrocells in an LAB Sharing allows efficient integration of complex combinatorial functions Macrocell and I O Feedbacks 81020 Programmable _ 32
25. 02 input to non registered output Global clock setup time Global clock hold time Global clock to output delay C1 35pF Global clock high time Global clock low time EPM5128 2 epmstze 90 35 ns l 15 14 CL Array clock setup time Array clock to output delay C1 35pF 25 Array clock high time See Note 6 Array clock low time N Minimum global clock period Sia Max internal global clock frequency Minimum array clock period 5 Max internal array clock frequency Maximum clock frequency 62 5 Internal Timing Parameters See Note 8 EPM5128 1 Parameter Conditions Input pad and buffer delay Hl input pad and buffer delay ACL CNT CNT ACNT ACNT 00065 Symbol N EXP Expander array delay Logic control array delay Output buffer and pad delay C1 35 pF ZX Output buffer enable delay E NE Xz Output buffer disable delay Register setup time he 24 LATCH Flow through latch delay ie e dm mi E 09 c E E 67 S gt o ajojn Register delay coms Combinatorial delay H tic Array clock delay Register hold time Global clock delay FD Feedback delay tenE Register preset time Register clear time Sri 8 tor Prog Interconnect Array delay Altera Corporation Page 159 ALTERA CORP 47E D 0595372 000217
26. 2 Numbersin parentheses are for military and industrial temperature range versions 3 Typical values are for 25 C and 5 V 4 Operating conditions Vec 2 5 V 5 1 0 C to 70 C for commercial use Voc 7 5 V 10 40 C to 85 C for industrial use 5 V 10 55 C to 125 C for military use 5 Measured with a device programmed as a 16 bit counter in each LAB 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the t4 cy and tac parameters must be swapped 7 The fmax values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief 75 Product Availability Availability EPM5192 1 EPM5192 2 EPM5192 Consult factory Consult factory Commercial 0 C to 70 C Industrial 40 C to 85 C Military 55 C to 125 C Page 174 Altera Corporation ALTERA CORP 7 D 0595372 0002192 T35 MALT Data Sheet 7 4 9 2 5192 EPLD Table 5 shows the pin outs for the EPM5192 QFP package Table 5 EPM5192 Pin Outs INPUT INPUT INPUT CLK INPUT VCC NC yo vO vO yo yo yo gt x e e e o Note NC represents not connected Altera Corporation Page 175 ALTERA CORP 47E D BB 1545372 0002193 321 WALT EPM5192 EPLD T 46 19 O9 Data Sheet Table 6 shows the pin outs for
27. 7 789 WE ALT EPM5128 Data Sheet Notes to tables 7 19 2 7 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions 2 Numbers in parentheses are for military and industrial temperature range versions 3 Typical values are for T4 25 C and Voc 5 V 4 Operating conditions Voc 5 V 5 Ty 05 C to 70 C for commercial use Voc 2 5 V 10 T4 40 C to 85 C for industrial use Vec 5 V 10 55 C to 125 C for military use 5 Measured with a device programmed as a 16 bit counter in each LAB 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the t4 cg and tac parameters must be swapped 7 The fmax values represent the maximum frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief 75 Product Availability Operating Temperature Availability Commercial 0 C to 70 C 5128 1 EPM5128 2 5128 Industrial 40 C to 85 C EPM5128 Military 55 C to 125 C EPM5128 Note Only military temperature range EPLDs are listed above MIL STD 883 compliant product specifications are provided in Military Product Drawings MPDs available by calling Altera Marketing at 408 984 2800 These MPDs should be used to prepare Source Control Drawings SCDs See Military Prod
28. 8 100 75 20 045 4 2 3 4 5 100Hz 1KHz 10KHz 100KHz 1MHz 10MHz 50 MHz Vo Output Voltage V Maximum Frequenc 5130 EPLD consists of 128 macrocells equally divided into 8 Logic Array Blocks LABs each containing 16 macrocells and 32 expander product terms see Figure 23 Expander product terms can be used and shared by all macrocells in the device to ensure efficient use of device resources Because the LAB is very compact the high speeds required by most I O subsystems are maintained The EPM5130 EPLD has 20 dedicated input pins that allow high speed input latching of 16 bit functions One of these inputs can be configured as a global synchronous clock to provide enhanced clock to output delays for bus oriented functions The EPM5130 EPLD also has 64 I O pins 8 in each LAB that can be configured for input output or bidirectional data flow Dual feedback on the I O pins provides the most efficient use of device pin resources Page 162 Altera Corporation ALTERA CORP 47E D 05915372 000280 273 WALT Data Sheet EPMSI3OEPLD Figure 23 EPM5130 Block Diagram 7 96 70 0 Numbers parentheses for packages numbers in brackets are for J lead packages 16 1 INPUT CLK gt INPUT 36 N4 59 lt INPUT 37 M5 60 INPUT 38 5 61 lt INPUT 41 6 64 lt INPUT 42 M7 65 lt T INPUT 43 L7 66 9 10 78 INPUTL 10 79
29. AS 7H EPM 5016ft v RS EPM5016 to EPM5192 EPLDs d Ej High Speed High Density MAX 5000 Devices September 1991 ver 2 Data Sheet Features Complete family of CMOS EPLDs solves design tasks ranging from fast 20 pin address decoders to 100 pin LSI custom peripherals Theadvanced 5000 architecture combines the speed ease of use and familiarity of PAL devices with the density of programmable gate arrays MAX 5000 EPLDs provide 15 ns combinatorial delays counter frequencies up to 100 MHz pipelined data rates of 100 MHz and high complexity designs with true system clock rates up to 66 MHz Q Available in a wide variety of packages including DIP SOIC J lead PGA and formats in windowed ceramic and plastic one time programmable versions MAX PLUS and MAX PLUS II PC and workstation based development tools compile large designs in minutes Anindustry standard EDIF interface to workstation and third party CAE tools is available Figure 1 shows the MAX 5000 modular architecture gt X e o o Figure 1 MAX 5000 Modular Architecture EPM5192 EPM5130 5128 5064 5032 5016 Macrocells 16 128 192 Maximum Flip Flops 21 168 252 Maximum Latches 32 256 384 Pins 20 100 84 68 100 84 Altera Corporation Page 125 Family x Highlights 0 Multiple Array MatriX MAX 5000 architecture solves speed density and design flexibility
30. ELL 32 MACROCELL 31 KL vo 26 5 gt x e e e Expander Product Term Array 64 Altera Corporation Page 145 ALTERA CORP 7 D 0595372 0002163 194 WALT 5032 EPLD 7746 02 Data Sheet Absolute Maximum Ratings Note See Operating Requirements for EPLDs in this data book 77 Ls Supply voltage With respect to GND 20 ro v Programming supply voltage See Note 1 20 135 v DC input voltage TsrG Storage temperature Ambient temperature Under bias Recommended Operating Conditions See Note 2 Symo Parameter Conditions Min Mex Vos E T EE SSS Mo owwwep 1 9 ves Ta Operating emparar Fwemmecawe 9 o Fra Operating temperature Tm e ws E Case temperature For military use DC Operating Conditions See Notes 2 3 4 Symbol Parameter Conditions Mn 193 29 JHam evel TTL lon lt amao 24 Vie Low level input voltage Vor Low level output voltage lo 8mADC a EN Input leakage current Vi or GND 10 Tri state output off state current Vo or GND 0 40 na Vin VoL 40 V cc supply current standby Vi Voc or GND 150 200 V cc supply current active Vi or GND No load 125 155 225 mA
31. Operating temperature rormusmause Case temperature For military use 55 125 c Input rise time DC Operating Conditions Notes 2 3 4 Symbol Parameter Concitions Vil i fu current v Vogorens loz Tri state output off state current Voc Supply current active Vi or GND No load f 1 0 MHz See Note 5 Capacitance Cin input capacitance Vin OV 10 MHz Cour Ouputcapactanes Vour OVT TONE Page 152 Altera Corporation ALTERA CORP 47E D 0595372 0002170 324 MALT Data Sheet 5064 EPLD AC Operating Conditions See Note 4 7 amp 47 External Timing Parameters EPM5064 1 5064 2 EPm5064 mne Coni wn wax min ue o Input to non registered output Ci 35pF MEJ VO input to non registered output Global clock setup time o Global clock hold time IEEE CO1 Global clock to output delay C1 35pF Array clock setup time gt gt l Array clock hold time IEEE SES Array clock to output delay C1 35pF Array clock high time See Note 6 ACL Array clock low time Minimum global clock period CNT Max internal global clock frequency See Note 5 Max internal array clock frequency See Note 5 E fmax Maximum clock frequency See Note 7 6251 5 Internal Timing Parameters See Note 8 Symbol Parameter Conditions Min
32. c 5 V 4 Operating conditions Vac 5 V 5 T 0 C to 70 C for commercial use Vcc 25 V 10 T 40 C to 85 C for industrial use 5 Measured with a device programmed as a 16 bit counter 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the t cy and tac parameters must be swapped 7 The fmax values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief 75 Product Availability Operating Temperature Availability Commercial 0 C to 70 C 5016 15 5016 17 5016 20 Industrial 40 C to 85 C 5016 20 Military 55 C to 125 C Consult factory Page 142 Altera Corporation ALT ERA CORP 7 D 0535372 0002160 485 MALT EPM5032 EPLD Features High speed 28 pin DIP J lead or SOIC single LAB MAX 5000 EPLD Combinatorial speeds with tpp 15 ns Counter frequencies up to 76 MHz Pipelined data rates up to 83 MHz 32 individually configurable macrocells 64 expander product terms expanders that allow 66 product terms on a single macrocell Up to 42 flip flops or 64 latches Up to 21 input latches that can be constructed with cross coupled expanders Programmable I O architecture allowing up to 24 inputs and 16 outputs Available in 28 pin windowed ceramic or plastic one time programmable OTP DIP and J lead packag
33. ck low time Minimum global clock period Max internal global clock frequency See Note 5 Minimum array clock period Max internal array clock frequency See Note 5 fmax Maximum clock frequency See Note 7 Internal Timing Parameters See Note 8 Symbol Parameter Conditions Input pad and buffer delay VO input pad and buffer delay p fes ww Fa ofe fes ww o rz Ld a ES m AJN 7 mS 0 5 OS 79 Logic array delay Logic control array delay N Output buffer and pad delay C1 35pF Output buffer enable delay U A Output buffer disable delay Register setup time Flow through latch delay ap Register delay Combinatorial delay Register hold time Array clock delay Global clock delay Feedback delay Register preset time Register clear time Prog Interconnect Array delay aj o m p 2 a o w 25 E lt lt gt E 52 Altera Corporation Page 173 ALTERA CORP 47E 0545372 0002191 059 EPM5192 EPLD Data Sheet 7 44 19 09 Notes to tables 1 Minimum DC input is 0 3 V During transitions the inputs may undershoot to 2 0 V or overshoot to 7 0 V for periods shorter than 20 ns under no load conditions
34. crocells in the LAB to create combinatorial and registered logic Thus expressions requiring up to 66 product terms can be implemented in a single macrocell Signals in the higher density devices are routed between multiple LABs by a Programmable Interconnect Array PIA that ensures 100 routability This multiple array architecture enables MAX 5000 EPLDs to offer the speed of smaller arrays with the integration density of larger arrays Modular Architecture The modular architecture of MAX 5000 EPLDs provides integration solutions over a wide range of logic densities Migration from one type of device to another is easy For example the EPM5128 and EPM5130 EPLDs have the same logic capacity but have packages optimized to handle different I O requirements Over the entire family a wide range of packaging options for both through hole and surface mount applications is available Plastic one time programmable OTP packages are available for economical volume production gt 9 Logic Design Entry Logic designs are created and programmed into MAX 5000 EPLDs with the MAX PLUS and MAX PLUS II development systems These complete CAE systems offer hierarchical design entry tools automatic design compilation and fitting timing simulation and device programming The MAX PLUS and MAX PLUS II Compilers feature advanced logic synthesis algorithms allowing designs to be entered in a variety of high level formats while ensu
35. d ceramic PGA packages oo General The Altera EPM5128 EPLD is a user configurable high performance eae Multiple Array MatriX MAX 5000 family EPLD that provides a high Description density replacement for 7400 series SSI and MSI TTL and CMOS logic For example a 74161 counter uses only 3 of the EPM5128 EPLD The 5128 EPLD can replace over 60 TTL MSI and SSI components and integrate multiple 20 and 24 pin low density PLDs Figure 18 shows the J lead and PGA package diagrams for the EPM5128 EPLD 3 Figure 18 EPM5128 Package Pin Out Diagrams 501 0005 XVI See Table 2 in this data sheet for PGA package pin outs Package outlines not drawn to scale L C0000000 k QOOOOOOOOO GG HOO 6 EPM5128 Ss o9 Q9 S 20 6 5 5 2 sD QQOQOOQOE J Lead PGA Altera Corporation Page 155 ALTERA CORP 47E 0595372 0002173 033 MALT EPM5128 EPLD 7 Yb m 9 2 2 Data Sheet Figure 19 shows output drive characteristics of EPM5128 I O pins and typical supply current versus frequency for the 5128 EPLD Figure 19 EPM5128 Output Drive Characteristics and Ipc vs Frequency 400 Voc 5 0 V Room Temp 5 0 V Room Temp Active mA Typ 8 loH 20 lo Output Current mA Typ 045 2 3 4 5 100Hz 1KHz 10KHz 100KHz 1 MHz 10 MHz 50 MHz Vo Output Voltage V Maximum Frequency The
36. es as well as plastic OTP 300 mil SOIC packages oo oo General The Altera EPM5032 EPLD is a Multiple Array MatriX MAX 5000 family SR CMOS EPLD optimized for speed It can integrate multiple SSI and MSI Description TTL and 74HC devices In addition it can replace multiple 20 pin PAL or PLA devices with logic left over for further integration See Figure 12 Figure 12 EPM5032 Package Pin Out Diagrams gt gt lt o Package outlines not drawn to scale 5603 2603 0 SOIC J Lead DIP Altera Corporation Page 143 ALTERA CORP 47E D 1545372 00021 2 312 WALT 5032 EPLD 7 y 2 2 Data Sheet Figure 13 shows output drive characteristics of EPM5032 I O pins and typical supply current versus frequency for the EPM5032 EPLD Figure 13 EPM5032 Output Drive Characteristics and vs Frequency 240 100 amp 200 X a 10 Vec 5 0 V 5 60 Voc 5 0 V t Room Temp 5 Room Temp 5 120 2 40 T go 8 lon 9 x 40 045 4 2 3 4 5 100Hz 1 KHz 10KHz 100 2 1 MHz 10 MHz 100 MHz Vg Output Voltage V Maximum Frequency The EPM5032 EPLD contains 32 macrocells see Figure 14 The EPM5032 expander product term array contains 64 expanders The I O control block contains 16 bidirectional I O pins that can be configured for dedicated input dedicated output or bidirectional operation All I O pins feature dual feedback for ma
37. ic left over for further integration See Figure 9 Figure 9 EPM5016 Package Pin Out Diagrams Package outlines not drawn to scale INPUT a INPUT CLK 99980 vo 1 n rn 3 2 1 vo INPUT 4 180 O vec GND INPUT o 5 17 INPUT vo m INPUT C16 16 INPUT m vo 2 INPUT CLK O 7 15 INPUT id o vo rj8 14 INPUT Q INPUT RAS a a LI LI LI LI egeoee gt 0 SOIC J Lead DIP l Altera Corporation Page 137 gt gt lt c ALTERA CORP 7 D 0595372 0002155 015 MALT EPMSOT6EPLD 0 T 46 19 201 Data Sheet Figure 10 shows output drive characteristics of EPM5016 I O pins and typical supply current versus frequency for the EPM5016 EPLD Figure 10 EPM5016 Output Drive Characteristics and vs Frequency 180 200 150 160 a F 120 Vcc 5 0 V t 120 Veo 5 0 V Room Temp Room Temp s 90 2 80 2 8 EA 60 8 loH ES 6 40 i 05 4 2 3 4 5 100Hz 1KHz 10KHz 100 KHz 1MHz 10 MHz 100 MHz Vo Output Voltage V Maximum Frequency The EPM5016 EPLD contains 16 macrocells see Figure 11 The expander product term array for the EPM5016 EPLD contains 32 expanders TheI O control block contains 8 bidirectional I O pins that can be configured for dedicated input dedicated output or bidirectional operation All I O pins feature dual feedback for maximum pin flexibility Page 138 Altera Corporatio
38. in each LAB 6 This parameter is measured with a positive edge triggered clock at the register For negative edge clocking the t4 cg and tac parameters must be swapped 7 fmax values represent the highest frequency for pipelined data 8 For information on internal timing parameters refer to Application Brief 75 Product Availability Operating Temperature Availability Commercial 0 C to 70 C 5064 1 EPM5064 2 EPM5064 Industrial 40 C to 85 C EPM5064 Military 55 C to 125 C EPM5064 Note Only military temperature range EPLDs are listed above MIL STD 883 compliant product specifications are provided in Military Product Drawings MPDs available by calling Altera Marketing at 408 984 2800 These MPDs should be used to prepare Source Control Drawings SCDs See Military Products in this data book Page 154 Altera Corporation ALTERA CORP 47E 0595372 0002172 MALT 5128 EPLD TH Features High density 128 macrocell general purpose MAX 5000 EPLD 256 shareable expander product terms that allow over 32 product terms in a single macrocell High speed multi LAB architecture as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62 5 MHz Programmable I O architecture allowing up to 60 inputs or 52 outputs Available in 68 pin windowed ceramic or plastic one time programmable J lead packages and in 68 pin windowe
39. is also available with MAX PLUS II software Logic synthesis and minimization optimize the logic of a design Automatic design partitioning into multiple EPLDs is also available with MAX PLUS II software Errors in a design are automatically located and highlighted in the original design file Design verification and timing analysis are performed with built in timing simulators timing analyzers and delay prediction Page 134 Altera Corporation ALTERA CORP 47E D 0595372 0002152 30 MALT Data Sheet EPM5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices T 90 01 Table 1 MAX 5000 EPLD Design Entry Design Compilation amp Verification Development Systems amp Software Packages MAX PLUS PLDS HPS PLS WS SN MAX PLUS Hosted on IBM PS 2 PC AT or compatible machines and workstations e g HP Apollo and Sun MAX PLUS and MAX PLUS II give designers the tools to quickly and efficiently create complex logic designs Further details about the MAX PLUS and MAX PLUS II development systems are available in the PLDS MAX amp PLS MAX PLS WS HP PLS WS SN and PLDS HPS PLS HPS PLS OS amp PLS ES data sheets in this data book 50783 0009 XVIN Device MAX 5000 EPLDs can be programmed on an IBM PS 2 PC AT or compatible computer with an Altera Logic Programmer the Master Programming Programming Unit MPU and an appropriate device adapter These items are included in the complete PLDS MAX
40. mbinatorial logic expansion Multi LAB architecture that ensures high speeds tpp as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62 5 MHz Programmable I O architecture allowing up to 72 inputs or 64 outputs and I O tri state buffers that facilitate connections to system buses Available in 84 pin windowed ceramic and plastic one time programmable OTP J lead packages 84 pin windowed ceramic PGA packages and 100 pin windowed ceramic and plastic packages General Altera s EPM5192 EPLD is a user configurable high performance Multiple 42 24 Array MatriX 5000 family EPLD that provides high density Description replacement for 7400 series SSI and MSI TTL and CMOS logic Package pin out diagrams for the 5192 are shown in Figure 24 Figure 24 EPM5192 Package Pin Out Diagrams See Table 5 in this data sheet for QFP pin outs and Table 6 for PGA pin outs Package outlines not drawn to scale gt e e e o 9 5192 OO 99 Goo J Lead PGA Altera Corporation Page 169 ALTERA CORP 47E 0595372 000218 b28 WALT EPM5192 EPLD Data Sheet erms _ _7 The EPM5192 EPLD can replace over 100 TTL SSI and MSI components and integrate the logic contained in over 20 22V10 devices In addition it accommodates other low density PLDs of all sizes These features allow the EPM5192 EPLD to easily integrate complete sy
41. ments Simultaneous transitions of multiple outputs should be avoided for 464 accurate measurement Threshold tests 150 Q must not be performed under AC Device to Test conditions Large amplitude fast ground Output System current transients normally occur as the device outputs discharge the load capacitances When these transients flow through the parasitic inductance between the device ground pin and the test system ground it can create significant reductions in observable input noise immunity 2500 82 C1 includes capacitance Device input rise and fall times 3 ns Note Numbers in parentheses are for the 5016 EPLD Test programs can be used and then erased during early stages of the production flow This facility to use application independent general purpose tests called generic testing is unique among user configurable logic devices EPLDs also contain on board logic test circuitry to allow verification of function and AC specifications of devices in windowless packages The MAX PLUS and MAX PLUS II development systems are unified CAE systems for integrating designs into MAX 5000 EPLDs Table 1 summarizes the features available in each MAX PLUS and MAX PLUS II package Designs can be entered as logic schematics with the Graphic Editor or as state machines truth tables and Boolean equations with the Altera Hardware Description Language AHDL waveform design entry
42. n ALTERA CORP 47E D 0595372 0002156 T54 MALT Data Sheet 5016 EPLD 7 y Figure 11 EPM5016 Block Diagram 1 07 The EPM5016 has 16 macrocells and 32 expanders Numbers in parentheses are for the PLCC package 11 16 INPUT gt lt INPUT 1 6 12 17 INPUT gt INPUT CLK 2 7 c 19 INPUT gt CC INPUT 9 14 c 1 20 8 INPUT gt N INPUT 10 15 R MACROCELL 2 MACROCELL 1 1 Eus MACROCELL 4 basis N MACROCELL 3 s KI 4 9 MACROCELL 6 N MACROCELL 5 Ku 0 MACROCELL 8 MACROCELL 7 Eus MACROCELL 10 T MACROCELL 9 K vo 13 18 MACROCELL 12 gt MACROCELL 11 E vo 14 19 MACROCELL 14 MACROCELL 13 4 2 vO 17 2 MACROCELL 16 MACROCELL 15 vo 18 3 Expander Product Term Array 32 gt gt lt e 139 ALTERA CORP 47E D 0595372 0002157 990 MALT 5016 EPLD 7 42 A 2 5 2 Data Sheet Absolute Maximum Ratings Note See Operating Requirements for EPLDs in this data book Parameter Conditions Min Unit Programming supply voltage 1 Programming supply voltage See Note 1 DC input voltage Storage temperature 6 ouneton temperature 12 Recommended Operating Conditions See Note 2 Voc M meme LX
43. ovided by cross coupled expanders J Multi LAB MAX architecture with tpp 25 ns counter frequencies up to 50 MHz and pipelined data rates up to 62 5 MHz Programmable I O architecture allowing up to 36 inputs and 28 outputs 44 pin J lead package that easily integrates 10 standard PALs in 1 2square inch of board space windowed ceramic or plastic one time programmable packages for volume production The Altera EPM5064 EPLD is a user configurable high performance Multiple Array MatriX MAX 5000 family EPLD that serves as a high density replacement for 7400 series SSI and MSI TTL and CMOS logic In addition it can integrate multiple 20 and 24 pin low density PLDs For example the EPM5064 EPLD can integrate the logic contained in over 10 standard 20 pin PALs Figure 15 shows the package pin out for the EPM5064 J lead package This package occupies only 1 2 square inch of board space Figure 15 EPM5064 Package Pin Out Diagram Package outline not drawn to scale INPUT INPUT CLK INPUT GND INPUT Vo EPM5064 18 19 20 21 22 23 24 25 26 27 28 eeogecoeogoeoe gt J Lead Page 149 gt X e 5 ALTERA CORP 47E 0595372 0002167 83T 5064 EPLD 7 y 6 9 27 Data Sheet Figure 16 shows output drive characteristics of EPM5064 I O pins and typical supply current versus frequency for the EPM5064 EPLD The high integration density of the EPM5064 EPLD often grea
44. problems Advanced macrocell array provides registered combinatorial or flow through latch operation Expander product term array automatically provides additional combinatorial or registered logic Decoupled I O block with dual feedback on I O pins allows flexible pin utilization Programmable Interconnect Array PIA provides automatic 100 routing in devices with multiple LABs Eachmacrocell supports combinatorial and registered operation using single or multiple clocks within a single EPLD MAX 5000 Performance Pipelined data rates up to 100 MHz Counters as fast as 100 MHz tpp performance from 15 ns to 25 ns A Advanced 0 8 micron CMOS EPROM technology MAX 5000 Logic Density 16 to 192 macrocell devices 20 to 100 pin packages 32 to 384 flip flops and latches than 32 product terms on a single macrocell Product term expansion on any data or control path MAX PLUS amp MAX PLUS II Design Tools Design entry via unified hierarchical schematic capture Altera Hardware Description Language AHDL and waveform design entry waveform entry in MAX PLUS only Fast automatic design processing with logic synthesis Automatic design partitioning into multiple EPLDs MAX PLUS II only Automatic device fitting no hand editing needed Hardware and software design verification tools EDIF interface to MAX PLUS amp MAX PLUS II provides paths to Viewlogic Systems Valid
45. quency for pipelined data For information on internal timing parameters refer to Application Brief 75 Product Availability Operating Temperature Availability Commercial 0 C to 70 C EPM5130 1 EPM5130 2 EPM5130 Industrial 40 C to 85 C Consult factory Military 55 C to 125 C Consult factory Page 166 Altera Corporation ALTERA CORP 7 D WE 0595372 0002184 919 MALT Data Sheet EPM5130 EPLD Table 3 shows the pin outs for 5130 QFP package 7 27 Table 3 5130 Pin Outs Ooh N 2 N lt lt INPUT CLK INPUT VCC INPUT INPUT INPUT yo yo yo NNN HY a a as 0 O O O 000S XVIN Altera Corporation Page 167 ALTERA CORP 47E D 1545372 0002185 855 EPMSISOEPLD T 46 19 09 Data Sheet Table 4 shows the pin outs for the EPM5130 PGA package Table 4 EPM5130 PGA Pin Outs INPUT CLK GND yo yo yo yo vO VO VO vO VO yo yo GND GND yo VCC VCC vO yo vO Page 168 Altera Corporation ALTERA CORP 7 0595372 0002186 791 MALT EPM5192 EPLD T 40 19 09 Features J 192 macrocells for easy replacement of over 100 TTL devices and for integration of complete logic boards into a single package 384 shareable expander product terms that offer flexibility for register and co
46. ring the most efficient use of EPLD resources The combination of a flexible architecture and advanced CAE tools ensures rapid design cycles so that a design may go from conception to completion in single day Interfaces to third party tools are also available to allow design entry and logic simulation on a variety of workstation platforms Functional MAX 5000 EPLDs use CMOS EPROM cells to configure logic functions AED within the devices The device architecture is user configurable to Descri ption accommodate a variety of independent logic functions and the EPLDs can be erased for quick and efficient iterations during design development and debug cycles Altera Corporation Page 127 Logic Array Block Figure 2 Logic Array Block The LAB consists of a macrocell array an expander product term array and a decoupled block The flexibility of the LAB ensures high speeds and efficient device utilization Macrocells T 90 01 MAX 5000 EPLDs contain from 1 to 12 Logic Array Blocks LABs Each LAB shown in Figure 2 consists of a macrocell array an expander product term array and an I O control block The number of macrocells and expanders in the arrays varies with each device Macrocells are the primary resource for logic implementation but if needed expanders can be used to supplement the capabilities of any macrocell The expander product term array consists of a group of unallocated inverted product terms Fle
47. rol Delay Input fac tore Delay fw cid tsu VO Pin ka PIA T Delay t VO Delay fo Single LAB EPLDs Expander Delay Logic Array Control Delay fac tone Li Su ic Array t elay The timing models shown in Figure 6 can be used together with the internal timing parameters for a particular EPLD to derive timing information External timing parameters are derived from a sum of internal parameters and represent pin to pin timing delays Figure 7 shows the internal timing waveforms for these devices Refer to Application Brief 75 for further information on MAX 5000 EPLD timing Desi gn MAX 5000 EPLDs contain a programmable Security bit that controls access 2 to the data programmed into the device If this feature is used a proprietary Secu rity design implemented in the device cannot be copied or retrieved This feature provides a high level of design security since programmed data within EPROM cells is invisible The Security Bit that controls this function as well as all other program data is reset by erasing the EPLD Page 132 Altera Corporation ALTERA CORP 47E 0595372 0002150 53b MALT Data Sheet EPM5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices 2 2 01 Figure 7 Switching Input Mode 1 90 Waveforms je oye In multi LAB EPLDs O Input Pin pins used as inputs can lho traverse the PIA VO Pin x i fg amp ig 3 ns Expander Array d 1 Inputs
48. stems into a single device Figure 25 shows output drive characteristics of EPM5192 I O pins and typical supply current versus frequency for the EPM5192 EPLD Figure 25 EPM5192 Output Drive Characteristics and Ipc vs Frequency 100 80 Voc 5 0V Room Temp 60 Vcc 5 0 V Room Temp 40 Active mA Typ loH lo Output Current mA Typ 0 45 1 2 3 4 5 1KHz 10KHz 100 KHz 1 MHz 10 MHz 50 MHz Vo Output Voltage V Maximum Frequency The EPM5192 EPLD consists of 192 macrocells equally divided into 12 Logic Array Blocks LABs that each contain 16 macrocells and 32 expander product terms see Figure 26 Because each LAB is very compact high performance is maintained and device resources are used efficiently The EPM5192 EPLD has 8 dedicated input pins one of which can be used as a global synchronous clock The EPM5192 EPLD can mix global and array asynchronous clocking ina single device facilitating easy integration of multiple subsystems It also has 64 I O pins that can be configured for input output or bidirectional data flow providing an interface to high speed bus oriented applications Page 170 Altera Corporation ALTERA CORP 7 D BE 0595372 0002188 3 WALT Data Sheet EPM5192 EPLD Figure 26 5192 Block Diagram 7 9 2 Numbers in parentheses are for PGA packages numbers in brackets are for packages 1 A6 91 INPUT CLK gt
49. tly reduces system power requirements Figure 16 EPM5064 Output Drive Characteristics and vs Frequency 200 150 Voc 5 0 V Room Temp Vcc 5 0 V Room Temp 40 loc Active mA Typ 3 lox 50 20 lo Output Current mA Typ 045 4 2 3 4 5 100Hz 1KHz 10KHz 100KHz 1 MHz 10MHz 100 MHz Vo Output Voltage V Maximum Frequenc The EPM5064 consists of 64 macrocells equally divided into 4 Logic Array Blocks LABs that each contain 16 macrocells see Figure 17 Each LAB also contains 32 expander product terms The flexibility of the LABs allows easy integration of any common PLD The EPM5064 EPLD has 8 dedicated input pins one of which can be used as a global system clock that provides enhanced clock to output delays The device has 28 I O pins that can be configured for input output or bidirectional data flow The I O pins feature dual feedback to allow any macrocell to be buried Two of the LABs have 8 I O pins ensuring high speed for 8 bit bus functions and the other two LABs have 6 I O pins Page 150 Altera Corporation ALTERA CORP 47E 0595372 0002168 77b WALT Data Sheet EPM5064 EPLD Figure 17 EPM5064 Block Diagram 7 Yo J A 2 The 5064 has 64 macrocells divided into 4 Logic Array Blocks 9 INPUT gt lt 1 INPUT 35 11 INPUT gt lt _1 INPUT CLK 34 12 INPUT D gt KL INPUT 33 13 INPUT E gt 31 Dedicated Inputs
50. ucts in this data book Table 2 shows the pin outs for the EPM5128 PGA package INPUT CLK GND VO Page 160 Altera Corporation ALTERA CORP 5130 EPLD Features General Description Figure 21 EPM5130 Package Pin Out Diagrams EPM5130 Altera Corporation 7 D MB 0545372 0002178 615 WALT 0 11 09 High density 128 macrocell general purpose MAX 5000 EPLD 128 macrocells optimized for pin intensive applications easily integrating over 60 TTL MSI and SSI components High pin count for 16 or 32 bit data paths 256 shareable expander product terms More than 32 product terms in a single macrocell 128additional latches provided by cross coupling expanders Allinputs can be latched without using macrocells 20 high speed dedicated inputs for fast latching of 16 bit functions Multi LAB architecture ensuring high speeds tpp as fast as 25 ns Counter frequencies up to 50 MHz Pipelined data rates up to 62 5 MHz Fast clock to output delays for bus oriented functions Programmable I O architecture that allows up to 84 inputs or 64 outputs in windowed ceramic PGA and windowed ceramic and one time programmable OTP plastic QFP packages Programmable I O architecture that allows up to 68 inputs or 48 outputs in windowed ceramic and plastic OTP J lead packages coo DC 3 The 5130 EPLD see Figure 21 is a user configurable high performance Multiple Array Matrix MAX 5000 family
51. ured as dedicated input output or bidirectional pins In multi LAB devices I O pins feed the PIA The higher density MAX 5000 devices EPM5064 EPM5128 EPM5130 and EPM5192 use a Programmable Interconnect Array PIA to route signals between the various LABs The PIA routes only the signals required for implementing logic in an LAB and is fed by all macrocell feedbacks and all I O pin feedbacks Unlike channel routing in masked or programmable gate arrays where routing delays are variable and path dependent the PIA has a fixed delay Because the PIA eliminates skew between signals timing performance is easy to predict Timing within MAX 5000 EPLDs is easily determined with MAX PLUS and MAX PLUS II software or with the models shown in Figure 6 MAX 5000 EPLDs have fixed internal delays which allow the user to determine the worst case timing for any design For complete timing information both MAX PLUS and MAX PLUS II software provide point to point delay prediction full timing simulation and detailed timing analysis Altera Corporation Page 131 501 0009 XVI ALTERA CORP 47E D 1545372 0002149 814 MALT EPM5016 to EPM5192 EPLDs High Speed High Density MAX 5000 Devices Data Shee Figure 6 Timing Models Multi LAB EPLDs T 90 01 Design performance can be predicted with these Expander timing models and the low device performance NE Logic Array specifications Cont
52. xible macrocells and allocable expanders facilitate variable product term designs without the waste associated with fixed product term architectures Thus PAL or PLA devices are easily integrated into MAX 5000 EPLDs The outputs of the macrocells feed the decoupled I O block which consists of a group of programmable tri state buffers and I O pins In the EPM5064 EPM5128 EPM5130 and EPM5192 EPLDs multiple LABs are connected by a Programmable Interconnect Array PIA The MAX 5000 macrocell shown in Figure 3 consists of a programmable logic array and an independently configurable register This register may be programmed for D T JK or SR operation as a flow through latch or bypassed for purely combinatorial operation Combinatorial logic is implemented in the programmable logic array which consists of three product terms ORed together that feed one input of an XOR gate The second input to the XOR gate is also controlled by a product term that makes it possible to implement active high or active low logic The XOR gate is also used for complex XOR arithmetic logic functions and for De Morgan s inversion to reduce the number of product terms The output of the XOR gate feeds the programmable register or bypasses it for purely combinatorial operation The logic array ensures high speed while Page 128 Altera Corporation Figure 3 MAX 5000 Macrocell T 90 01 Global Clock Programmable Register Macrocell and I O
53. ximum pin flexibility Page 144 Altera Corporation ALTERA CORP 7 WE 0595372 0002162 258 MALT Data Sheet EPM5032 EPLD Figure 14 EPM5032 Block Diagram T Yo 9 2 2 The EPM5032 has 32 macrocells and 64 expanders Numbers in parentheses are for J lead packages 15 22 INPUT gt lt INPUT 1 8 16 23 INPUT gt C INPUT CLK 2 9 27 6 INPUT gt lt I INPUT 13 20 28 7 INPUT gt lt LI INPUT 14 21 MACROCELL 2 gt MACROCELL 1 4 vo 3 10 N MACROCELL 3 K vos T eS MACROCELL 6 gt MACROCELL 5 ec E vo 5 12 monoceue _ pa R 7 MACROCELL 7 KA vo 6 a MACROCELL 10 gt gt MACROCELL 9 gt KO vo 6 MACROCELL 12 N MACROCELL 11 K vo 10 17 N Lacu 25 MACROCELL 14 MACROCELL 13 1 vo 11 18 MACROCELL 16 MACROCELL 15 KA vo 12 19 piat qp 25 MACROCELL 18 me MACROCELL 17 E vo 17 24 MACROCELL 20 e gt MACROCELL 19 ON vo 18 25 MACROCELL 22 I vo 19 e MACROCELL 24 MACROCELL 23 vo 20 27 pai 25 MACROCELL 26 gt MACROCELL 25 pid KA vos 2 MACROCELL 28 gt MACROCELL 27 pad vO 24 3 MACROCELL 30 gt MACROCELL 29 Pa K vo 25 4 MACROC

ALTERA EPM5016 to EPM5192 EPLDS handbook

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