ST AN2272 handbook
Contents
1. 18 No Load Start up Waveforms at 265V 18 No Load Start up Waveforms at 115V 19 No Load Start up Waveforms at 230V 19 Step Load Change Stability Tests 88 21 Step Load Change Stability Tests at265V 21 Step Load Change Stability Tests at 115 22 Step Load Change Stability Tests at230V 22 Steady state Full Load 88Vac 24 Steady state Full Load 265V4c 24 Steady state Full Load 115V4c 25 Steady state Full Load 230V4c 25 Steady state No Load 88V4c Waveforms 26 Steady state No Load 265V4c Waveforms 26 Steady state No Load 115V4c Waveforms 27 Steady state No Load 230V4c Waveforms 27 115Vag Line Voltage ee RR te PER RE Eee EES RE Weed 28 115V4c Line Neutral u sn oan oee s asada s aga su h umaman gom a gases RR sa 28 230V Line2. 29 290V o Line Ne tral uuu u bd E ERU eek al besos mao 29 STEVAL ISA011V1 30 Rev 1 3 33 List of Tables AN2272 Application Note List of Tables Table 1 Electrical Characteristics 15 Table 2 Start up Measures 15 Table 3 Component Critical Temperature 5 20 Table 4 Steady state Full Load Condition Measurements 23 Table 5 Steady state Output Voltage 23 Table 6 Bill Of 5 31 Table 7 Document revision history 32 4 33 Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Design 1 1 1 STEVAL ISA011V1 Board Design In order to improve regulation the feedback loop is designed to have enough bandwidth so the converter can react on time to load changes As is shown in the Section 2 3 Dynamic Load Regulation Tests on page 20 the board is able to handle high load step changes with very low variations in the output voltage The flyback converter is designed to work in Discontinuous Conduction Mode DCM in all operating conditions i
3. AN2272 Application Note VIPer12A based Low Power AC DC Adapter Introduction This application note describes a low power output power of 4 1W general purpose adapter which is able to handle a wide range input voltages 88VAc to 265Vac The adapter Order Code STEVAL ISA011V1 is based on the Viper12A monolithic device that has the power switch as well as the basic control function needed to implement a current mode flyback converter February 2006 Rev 1 1 33 www st com Table of Contents AN2272 Application Note Table of Contents 1 STEVAL ISA011V1 Board Design 5 1 1 Primary Side sessir pud a du yd yeh eed we EG RESGOIR 3 weese 5 1 1 1 Step 1 Input Capacitor Selection 5 1 1 2 Step 2 Transformer Selection 6 1 2 Secondary Side 8 1 2 1 D44 Current and Power Dissipation 9 1 2 2 Transformer Turns Ratio and D44 Peak 10 1 2 3 C44 Output Capacitor Selection 11 1 3 Completed Transformer Design 12 1 4 Feedback 12 2 STEVAL ISA011V1 Board Tests 15 2 1 Start up 5 15 2 1 1 Full Load Start up Wavef
4. Notes Magenta Red Ch3 output voltage Yellow Ch1 2 feedback pin voltage and Cyan Blue Ch2 output current Rev 1 21 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 22 33 Figure 11 Step Load Change Stability Tests at 115V Tek Run Average 298 Acqs 09 Jun 05 12 49 31 I ee Chi 200nV Ch2 Soom Q M 400ys 125MS s um Ch3 50 0mV Bw A Ch2 750 Notes Magenta Red Ch3 output voltage Yellow Ch1 feedback pin voltage and Cyan Blue Ch2 output current Figure 12 Step Load Change Stability Tests at 230V Tek Run Awrag 9905125001 Ns J 1 T l Chi 200 Ch2 500m Q M 400ys 125MS s 80nspt Ch3 500 Bw A Ch2 750 Notes Magenta Red Ch3 output voltage Yellow Ch1 feedback pin voltage and Cyan Blue Ch2 output current Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Tests 2 4 Steady State Tests These tests evaluate the converter s behavior see Table 4 The measurements include e converter efficiency for the minimum 88Vac maximum 265V4c and nominal input voltages 115V4c and 230V4c e output voltage quality Static Load regulation where voltage output is measured in both full load and no load conditions and e voltage ripple which is superimposed on the output voltage at the switching frequency see Table 5 Note Th
5. Table 6 Bill Of Materials Item Qty Reference Value 1 1 C1 0 1uF CX2 cap 2 2 C2a C2b 10uF 400V 3 1 C3 150pF 400V 4 1 C4 10uF 5 1 C5 33nF 6 1 C6 47pF 400V 7 1 C7 1 8nF Y1 8 1 C8 100nF 9 1 C11 1 5mF 10V MBZ 10X16 Rubycon Low ESR Capacitor 10 1 D3 1N4148 11 1 D4 1A 600V Bridge 12 1 D5 STTH1RO06 STMicroelectronics Part 13 1 D11 STPS340U SMB Package STMicroelectronics Part 14 1 F1 250mA 15 1 L12 1 5mH 0 25A 16 1 NTC1 330 17 1 R1 12K 1 4W 18 2 R2 10k 19 1 R3 1 5k 20 1 R4 10E 21 1 R5 1k 22 1 R6 560 23 1 R7 12 5k 196 Precision Resistor 24 1 R8 10k 1 Precision Resistor 25 1 R9 56k 26 1 T1 TDK SRW16ES E44H013 27 1 U2 VIPer12A ST Part 28 1 U3 TL1431 ST Part 29 1 U4 PC817 Rev 1 31 33 Revision History AN2272 Application Note 3 32 33 Revision History Table 7 Document revision history Date 2 February 2006 Revision 1 First edition Changes Rev 1 AN2272 Application Note Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces a
6. 0 Jun 05 18 18 52 I TTT T TT r i TL Chi 200v Ch2 200m Q M 400ys 25 psi 40 0nsipt Oh3 50 20 Ch4 20 Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Figure 6 No Load Start up Waveforms at 265V Tek z Stopped Single Se 207 d 05 18 21 08 I MD x L 24 mmm MM Tees E f ee eee ee eee B Chi 200 Ch2 Z00m Q M 4000 254 ONSIS 40 0ns pt Ch3 50 Ch4 20v ACh4 7 20V Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Tests Figure 7 Load Start up Waveforms at 1 15V Tek Preview Single z 1 Acgs E AM m OF Jun 05 18 19 44 ene Q2 200 Q cha 20V Ug 15 La rere rpg La 400ps 25 0MS s 40 0ns pt A Ch4 20V Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for th Yellow Ch1 drain voltage Figure 8 e VIPer12A self supply on Vpp pin and No Load Start up Waveforms at 230V Tek Stopped Single si 1
7. 05 10 24 35 Hi is F F 1 1 T di e L r L lc it im iT Li l gel Ch2 100 Q M 200ps 250MS s 4 0nsipt Oh3 10V Bw Oh4 100 Ch4 152 Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Figure 20 Steady state No Load 230V4c Waveforms Tek Run _ Hi Res i PEPEN EE A Ch2 100mA Q Ch3 10V Bw Ch4 2004 M 200 250N5 s A Ch 7 152 i Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Rev 1 27 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 2 5 28 33 EMI Tests Pre compliant tests with European Normative EN55022 for electromagnetic interference EMI were performed Figure 21 and Figure 22 and Figure 23 and Figure 24 on page 29 illustrate that the conducted EMI induced by the converter to the main are below the normative limits Note Figure 21 through Figure 24 show the Input current spectrum to be inside the 150kHz to 30MHz frequency range Figure 21 112 Line Voltage Start 150 kHz Stop 30 MHz Res BW 9 kHz VBW 30 kHz Sweep 881 3 ms 1905 pts Figure 22 LAG Line Neutral Stop 30 M Res BW 9 kHz VBW 30 kHz Sweep 881 3 ms 1905 pts Rev 1 AN2272 App
8. 09 Jun 05 10 21 53 m 73 Num Averages 8 2 lu 49 233309 47 69 50 841 o 1236m n 700 4 552 Ch2 100 Q 10 0ps 1 25055 IT 100psipt O3 10 Bw 200V A 152V Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current 24 33 Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Tests Figure 15 Steady state Full Load 115 Waveforms Tek Run Average 176 Acgs 09 Jun 05 10 19 08 i I een Position 720 0mdiv Scale 100 0 IMan c4 34750 rn 215 232 6 lo 7599 2340 RMS C2 74 89mA 79 950501m 74 89r 87 56n 4818m n 1940 4553 4 5530565 M4 554 5725 n 1810 L j 25 2 amd f ie pr l i 4 Ch2 100mA Q M 10 0ps 125GS s IT 100ps pt 10V Bw Ch4 100V A Ch4 7 380V Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Figure 16 Steady state Full Load 230V c Waveforms Tek Run Average 78 Acgs 09 Jun 05 10 21 18 a Num Averages 8 230 4 7m M 2362n 3 914m 370 RMS C2 50 55 50 602095 m 50 24m M 50 84n 1208 370 Mean 3 4554V
9. load No load 88 352 353 0 460 0 458 115 393 401 0 472 0 470 230 581 581 0 507 0 505 265 638 633 0 515 0 515 Rev 1 15 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 2 1 1 16 33 Full Load Start up Waveforms Figure 1 Figure 2 Figure 3 and Figure 4 on page 17 show the most pertinent waveforms that occur during the circuit start up phase when it is in Full Load condition for the minimum 88V4c maximum 265V4c and nominal voltages 115V4c and 230VAc Figure 1 Full Load Start up Waveforms at 88V Tek X Stopped Single 2 1 Acqs 0 Jun 05 18 13 04 I T T LR T T YAY Ta I 1 chi 250 5 5 400nspt Ch3 50 cha 20 20V Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Figure 2 Full Load Start up Waveforms at 265V Tek Stopped Single Seq Stopp 7 Acgs 07 Jun 05 18 14 33 f II IL PETN nh de bb a Chi 200v M 400ps 25 0MS s 400nsipt Ch3 50 2 Ch4 20 Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Rev 1 A
10. Acqs rT BS Ill x 1 07 Jun 05 18 20 31 I Da k y D DEE Loca L LELES Lia l L Chi 2004 Ch2 200m Q M400yus25 0MS s 400nsipt Ch3 50 Ch4 2 A Ch4 20V Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Rev 1 19 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 2 2 Temperature Tests These tests verify the board s device and component temperatures Table 3 shows critical temperatures the most stress measured in terms of power dissipation for the board s main components Note The tests were performed at 25 C ambient temperature in Full Load conditions Table 3 Component Critical Temperature Measurements Vinac Vnus VIPer12A Transformer Clamp Resistor Output Diode Units 88V 38 37 36 45 C 115V 39 36 37 45 C 230V 42 38 38 45 C 265V 45 35 39 45 C 2 3 Dynamic Load Regulation Tests These tests monitor and verify the stability and quality of the system response to load changes in terms of speed and overshoot Figure 9 and Figure 10 on page 21 and Figure 11 and Figure 12 on page 22 show the waveforms as they occur during the circuit load changes for the minimum 88V c maximum 265 and nominal voltages 115Va
11. N2272 Application Note STEVAL ISA011V1 Board Tests Figure 3 Full Load Start up Waveforms at 115V Tek Stopped Single Seq Q Jun05 18 13 35 T TAM 1 zs T ES E Chi 200 Ch2 200 Q 400 25 0MS s 40 015 Ch3 50V 20V A Ch4 7 20V Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Figure 4 Full Load Start up Waveforms at 230V Tek Stopped Single Seq 1 Acs 0 Jun 05 18 14 05 prm I III I 400ps 25 ONS s 400nsipt Ch1 2004 Ch2 200m A Ch4 7 20V Ch3 50V Ch4 20V Notes Cyan Blue Ch2 drain current Green Ch4 output voltage Magenta Red Ch3 auxiliary output voltage for the VIPer12A self supply on Vpp pin and Yellow Ch1 drain voltage Rev 1 17 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 2 1 2 18 33 No Load Start up Waveforms Figure 5 Figure 6 Figure 7 and Figure 8 on page 19 show the same waveforms Section 2 1 1 as they occur during the circuit start up phase when no load is applied for the minimum 88V4c maximum 265V4c and nominal voltages 115 230VAc Figure 5 No Load Start up Waveforms at 88V Tek Stopped Single 2 1 Acgs
12. Ri inductor resistance and ESRout equivalent series resistor output e Theflyback zero value for two poles one zero compensation network is expressed as Equation 22 WM Cour ESRour Where flyback zero One pole is located at zero frequency in order to maximize the precision of the regulation Compensation zero was used in order to compensate the and typically it has to be located between one half and double the pg frequency The last pole of the compensation network is used to compensate flyback zero due to the ESR Rev 1 13 33 STEVAL ISA011V1 Board Design AN2272 Application Note 14 33 Loop Gain crossover frequency is the last calculation required to define the compensation network In this design the crossover frequency selected is as high as 2 5kHz to provide the converter with good bandwidth The Transfer Function output control is expressed as Equation 23 5 1 8 Rg Cg Where Algg VIPer12A feedback pin current AVo output voltage ripple CTR optocoupler Current Transfer Ratio Rep VIPer12A feedback pin input impedance Note Using these resistance and capacitance values as guidelines will provide the user with a stable loop as well as the required converter bandwidth Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Tests 2 2 1 STEVAL ISA011V1 Board Tests The tests performed with the STEVAL ISA011V1 demo
13. and the correct values for and are in the diode datasheets Rev 1 9 33 STEVAL ISA011V1 Board Design AN2272 Application Note 1 2 2 Transformer Turns Ratio and D4 Peak Current e The turns ratio that is selected for the transformer depends on the output voltage the chosen reflected voltage and the average voltage drop across the output diode Keeping in mind the voltage drop across its dynamic resistance VDROP avg iS expressed as Equation 13 Voropcavg t lo Where VpRoP avg average voltage drop across the output diode drop voltage when the diode is forward biased rap dynamic resistance lo diode output current and e Using the calculated Vpgop ayg value the turns ratio is expressed as Equation 14 L NS _ Ns VpnoP avg Where Np Primary Turns Ns Secondary Turns Vg reflected voltage and Vo output voltage e Using the calculated turns ratio Ips is then expressed as Equation 15 Np leks Ng lekp Where Ipks peak current at secondary winding and peak power current Note The worst case maximum power dissipation will be in full load condition e The D conduction duty cycle is expressed as Equation 16 D _ Ipkp bp fsw s cond y R Where Ds cond Secondary Diode conduction duty cycle Lp primary inductance and fsw switching frequency 10 33 Rev 1 AN2272 Application Note STEVAL ISA011V1 Board D
14. board are used to evaluate the converter behavior in terms of e efficiency e sale operating area of the devices e lineregulation and load regulation Start up Tests The diagnostic board will handle a wide range of AC input voltage 88V4c to 265V4c and its maximum output power is 4 1W with one output of 4 5V Its maximum output current is 900mA see Table 1 For flyback converters the most critical conditions for the main switch in terms of Maximum Drain Current and of Maximum Drain Voltage when no abnormal event occurs are those that exist during the start up phase The maximum values for drain voltage and current are measured in both full load and no load conditions the two extreme points in terms of load and for minimum maximum and nominal input voltages see Table All the measured values are within the rated maximum values of the VIPer12A so they are not critical for device operation Table 1 Electrical Characteristics Symbol Description Limits or Value Units VAC max Maximum AC Input Voltage 265VRMS V VAC min Minimum AC Input Voltage 88V rus V Vo Output Voltage 4 5 V AVo Maximum Output Voltage Ripple 300 mV lo Maximum Output Current 900 mV n230 Efficiency at full Load and 230Vac 70 11115 Efficiency at full Load and 115 70 Table 2 Start up Measures VpRAIN max V IDRAIN max MA Vinac Vnus Full load No load Full
15. c and 230V pc During these tests load changes from a minimum of 180mA to a maximum of 900mA are applied to the circuit as squarewaves with 3ms periods and a duty cycle of 50 e The output voltage Ch3 has a variation of some tenths of a mV about 40mV with some mV overshoots These results indicate very good dynamic behavior on the part of the system e The V VIPer12A feedback pin voltage Ch1 in Figure 10 on page 21 shows that when the input voltage is 265V4c the load is 180mV its minimum value while the output and feedback pin voltages show some oscillation This oscillation is not related to a low phase margin of the Loop Gain but is related to the VIPer12A Burst mode operation Note Even with the oscillation the output voltages are still regulated well 20 33 Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Tests Figure 9 Step Load Change Stability Tests at 88V Tek Run Average E 09 Jun 05 12 49 06 J 24 TT Lal Chi 200mv Ch2 500m Q M 400 T25MS s 80nsipt Ch3 500mV Bw A Ch2 750 Notes Magenta Red Ch3 output voltage set to 50mV division Yellow Ch1 VIPer12A feedback pin voltage and Cyan Blue Ch2 output load current Figure 10 Step Load Change Stability Tests at 265V Tek Run 09 Jun 05 12 80 26 Chi 200m 02 500m Q NM400ps 125 55 _ 8 Onsht Dh3 500 Ew A Ch2 750mA
16. e Minimum Input Voltage Maximum Load because it provides better dynamic performance Primary Side Step 1 Input Capacitor Selection The first design step is to calculate the input capacitor value C2a C2b see STEVAL ISA011V Demo Board Schematic on page 30 Equation 1 is useful for this purpose Equation 1 Cin 2 2 V AC min pk V DC min Where input capacitor value input power AT the time between the two conduction cycles of the input bridge diodes Vac min pk Sinusoidal input waveform peaks when AC voltage is at its minimum and Vpc min selected minimum input voltage required for the flyback converter stage In this case the Py value used is calculated as Po n where is the maximum output power and n is the overall expected efficiency 70 in this example Rev 1 5 33 STEVAL ISA011V1 Board Design AN2272 Application Note 6 33 An acceptable value for Vpc min is 80 of Equation 2 Vpemin 0 8 V accmin pk J2V accmin AT is expressed as Equation 3 V AT _ 1 x arccos 2 Yo fine V AC min p Where AT the time between the two conduction cycles of the input bridge diodes and fline line frequency The calculated value of C IN using Equation 1 is 16uF For the board two capacitors C2a and C2b see STEVAL ISA011V Demo Board Schematic on page 30 of 10uF were used This means that C N 20uF This value was selected b
17. e tests were performed in Full Load conditions Table 4 Steady state Full Load Condition Measurements Vinac Vnus Pin W Pour W Vo V n 88V 5 9 4 13 4 59 70 115V 5 9 4 13 4 59 70 230V 5 9 4 13 4 59 70 265V 6 1 4 13 4 59 68 Table 5 Steady state Output Voltage Ripple Input Voltage Vans AVo at Full Load 88V 210mV 115V 214mV 230V 215mV 265V 220mV Rev 1 23 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 2 4 1 Steady State Full Load Waveforms Figure 13 and Figure 14 and Figure 15 and Figure 16 on page 25 show the waveforms that occur during converter steady state testing when it is in Full Load condition for the minimum 88V4c maximum 265V4c and nominal voltages 115Vac and 230VAc Figure 13 Steady state Full Load 88V4c Waveforms Tek Run wap _ 92A O O O AOI E o Ch4 Position 120 0mdiv Ch4 Scale 100 0Y 04 3097V i lo n 330 u 653 Hi E bises m 18207 192 3 84 i 8756 r 3 4554Y lu 45527049 m 4547 4554 l lo 1005m n 1380 2 Ch2 100mA Q M 10 0ps 125GS s IT 100psipt Ch3 10V Bw Ch4 100 Ch4 380V Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Figure 14 Steady state Full Load 265 Waveforms Tek Run Average 142 Acqs
18. ecause the tolerance for an electrolytic capacitor is usually around 20 Step 2 Transformer Selection The next step is selecting a transformer with a Primary Inductance Lp that allows the system to work at the boundary between Continuous Conduction Mode CCM and Discontinuous Conduction Mode DCM The worst case is minimum input voltage and full load This value is expressed as Equation 4 2 Vpc min gt L 3 5mH 2 Pin fsw mee LMAX Where Lmax Maximum inductance for discontinuous mode operation Vpc min selected minimum input voltage required for the flyback converter stage Dmax maximum duty cycle input power fsw switching frequency internally fixed in the Vlper12A to 60kHz and Vg reflected voltage fixed to 90V Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Design The Dmax at the boundary between CCM and DCM is expressed as Equation 5 VR D n OD 0 47 MAX Vpo mig Vg MAX The transformer selected for this application provides an Lp of 3mH which is a little less than the maximum inductance Lmax calculated in the first equation 3 5mH This ensures that the system is not working at boundary and will always function in DCM Using the transformer s Lp the designer can calculate the e Peak Primary Current expressed as Equation 6 few Lp IPEAK lpgak 258mA Where peak primary current Pin input power fsw swi
19. esign 1 2 3 Output Capacitor Selection The output capacitor selection C44 see STEVAL ISA011V1 Schematic page 30 depends on the output voltage ripple specification 300mV and the ripple current rate of the capacitor itself The output voltage ripple is mainly due to the Equivalent Series Resistor ESR so we have to select a capacitor with an ESR lower than the maximum allowed ESR value Equation 17 ESfluax PKS Where ESR max maximum allowed ESR rating AVo output voltage ripple and peak current at secondary winding The AC component of the current flowing through the output diode is also that of the current flowing through the capacitor The C11 capacitor current rate has to be higher than the calculated current which is expressed as Equation 18 CAPRMS 7 DRMS O Where Icaprus Capacitor current root mean square diode current root mean square and lo output current The MBZ Type 1500 uF 10V by RUBYCON capacitor was selected for this application Rev 1 11 33 STEVAL ISA011V1 Board Design AN2272 Application Note 1 3 1 4 12 33 Completed Transformer Design All of the calculations for the transformer design are complete They include e Primary Inductance e Turns Ratio and e Winding Current Values RMS Average and Peak Notes 1 In order to prevent transformer saturation during the start up phase the cu
20. lication Note STEVAL ISA011V1 Board Tests Figure 23 230V4c Line vonage Ref 75 dB CE s OTE ee al TTT KEBAB NIST LT Lauda dk aL WG Ha PN C FTD TT im wi 52 53 Start 150 kHz Stop 30 MHz Res BW 9 kHz VBW 30 kHz Sweep 881 3 ms 1905 pts Figure 24 2 Line Neutral inc LLL AL LUI M maii UTTAR u 7 bii NU MCA Lad i VBW 30 kHz Sweep 881 dius teak RD ky Rev 1 29 33 AN2272 Application Note STEVAL ISA011V Demo Board Schematic Appendix STEVAL ISA011V Demo Board Schematic Figure 25 STEVAL ISA011V1 Schematic 20151599 ASSL lt 8 2 961 ZY 24001 89 49S 6H 218 4 sn 20151599 UOISIOOJd L 09S 9d 01 84 3 uooKqng ZEW AOL JWG L L T LI I B V6 0 AS Y NOPESALS 90HIHLIS sa LA 496 O h A A00r 44051 o oor amor SOL ezo VUIS LA Joo AGL EH Sc 0 HWG L 211 p _ A009 VI 112225 Rev 1 30 33 AN2272 Application Note STEVAL ISA011V1 Bill of Materials Appendix B STEVAL ISA011V1 Bill of Materials
21. ll information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2006 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Rev 1 33 33
22. n by the calculation when a Schottky diode is used or a safety margin of 20 to 30 if a standard fast diode is used The safety margin prevents diode breakdown from oscillation caused by circuit parasitic elements e g transformer secondary inductance leakage or parasitic diode capacitance when the MOSFET is turned ON If the calculated VR max is 23V and a Schottky diode is used adding a 50 safety margin the D44 value is about 34V This makes the STPS340U with 40V breakdown voltage an excellent choice for this application Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Design 1 2 1 D Current and Power Dissipation The average current flowing through D44 is the output current while the value is expressed as Equation 11 D lonMs Ipks A Where IpnMs current root mean square lps peak current at secondary winding and Ds cond conduction duty cycle of the secondary diode For one output flyback peak current at the secondary winding be calculated as the primary peak current multiplied by the turns ratio Note This formula applies only to DCM operation D44 power dissipation is calculated as follows Equation 12 2 Piossp Vap p avg ap DRMS Where Piossp diode power dissipation drop voltage when the diode is forward biased Ip avg diode average current and dynamic resistance Note The formula
23. orms 16 2 1 2 No Load Start up Waveforms 18 2 2 Temperature Tests 20 2 3 Dynamic Load Regulation 5 5 20 2 4 Steady State Tests 23 2 4 1 Steady State Full Load Waveforms 24 2 4 2 Steady State No Load Waveforms 26 2 5 EMI TeSI8 eee EERDER S Ra a EAA A 28 Appendix STEVAL ISA011V Demo Board Schematic 30 Appendix STEVAL ISA011V1 Bill of Materials 31 3 Revision History 32 2 33 Rev 1 AN2272 Application Note List of Figures List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Full Load Start up Waveforms at 88 16 Full Load Start up Waveforms at 265 16 Full Load Start up Waveforms at 115V 17 Full Load Start up Waveforms at 2 17 No Load Start up Waveforms at 88V
24. rrent limit of the VIPer12A 480mA see datasheet for details must be considered as the peak current 2 For thermal limits power dissipated in the magnetic core the peak current calculated in Equation 6 on page 7 must be used 3 The RMS value of the current flowing through the windings is used first for calculating the power dissipated in the windings then for winding size selection The transformer reference number SRW16ES 44 013 was designed and manufactured by TDK using aforementioned the data Feedback Loop The transfer function control to output for a flyback converter operating in DCM is given by the following formula Equation 19 S ty 1 Where AVo output voltage ripple VIPer12A feedback pin current Giy flyback gain Zriy flyback zero compensation reference Pry flyback pole reference and Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Design Using the VlPer12A input current to the feedback pin and values Equation 20 V Gip Gine fl y lpk Where Gry flyback gain Vo voltage output primary peak current and feedback current to drain current gain see VIPer12A datasheet for details e The flyback pole value is expressed as Equation 21 i our BL 2 ESBgyp Where Pry flyback pole reference Court output capacitor see C44 STEVAL ISA011V1 Schematic on page 30
25. tching frequency and Lp primary inductance e actual Maximum Duty Cycle Dmax expressed as 2 Pin fgyw Lp SW P and e the primary side Root Mean Square RMS current value IpRMS max Which is the current that flows through the main switch and primary winding It is expressed as Equation 7 Equation 8 Dmax 97mA PRMS max PEAK 3 gt PRMS max m Where IPRMS max Primary Current root mean square Rev 1 7 33 STEVAL ISA011V1 Board Design AN2272 Application Note 1 2 8 33 The conduction losses in the main switch depend on the VIPer12A Iprus max and ON resistance and are expressed as Equation 9 P VIPer12A l ds on PRMS max Where VIPer12A conduction losses and VIPer12A ON resistance Secondary Side In order to select the output rectifier secondary diode D44 the designer needs to know the maximum reverse voltage that the diode has to sustain as well as the average and root mean square of the current flowing through it see STEVAL ISA011V1 Schematic on page 30 VR max is calculated as follows Equation 10 V OUT VR max Voutt VR Where VR max Maximum reverse voltage Vout output voltage Vg reflected voltage and Selected maximum input voltage A commonly used selection method is to choose a diode with a 4096 to 5096 safety margin from the value give
26. u 4 5535453 Im 4 553 4 554 Jo 2138 38 0 Ch2 Q 10 0ps 1 25GS s IT 100psipt Ch3 1 0 Bw Ch4 200V A Ch 7 152V Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Rev 1 25 33 STEVAL ISA011V1 Board Tests AN2272 Application Note 2 4 2 26 33 Steady State No Load Waveforms Figure 17 and Figure 18 and Figure 19 and Figure 20 on page 27 show the waveforms that occur during converter steady state testing when it is in No Load condition for the minimum 88V4c maximum 265V4c and nominal voltages 115Vac and 230V4c Figure 17 Steady state No Load 88V4c Waveforms Tek Run HiRes _ __ 08 Jun 05 10 28 55 Ch2 100 M 200 250MS s 4 Onst Ch3 1 0 Bw Ch4 100 A Ch4 1527 Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Figure 18 Steady state No Load 265V4c Waveforms Tek _ Run Hi Res 88 4605 09 Jun 05 10 25 31 I Ch2 100mA Q M 200ys 250M5 s 4 0nsipt Ch3 10V Bw Ch4 200 A Ch4 152v Notes Magenta Red Ch3 output voltage Green Ch4 drain voltage and Cyan Blue Ch2 drain current Rev 1 AN2272 Application Note STEVAL ISA011V1 Board Tests Figure 19 Steady state No Load 115Vac Waveforms Tek Run Hi Res 145 Acqs T 09
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