FAIRCHILD FAN7888 3 Half-Bridge Gate-Drive IC handbook
Contents
1. 1300 2 12 60 Lk 11 43 2 1 d JIHBBBBRBR 9 50 10 65 7 60 10 00 7 40 c 2 25 0 65 427 aa Td INDICATOR 0 25 c B A LAND PATTERN RECOMMENDATION 2 65 MAX P oi DETAIL A 4 0 33 c 1 0 20 0 30 E C o 10 E V 0 75 0 10 SEATING PLANE gp 25 gt 45 NOTES UNLESS OTHERWISE SPECIFIED R0 10 A THIS PACKAGE CONFORMS TO JEDEC MS 013 VARIATION AC ISSUE E 0 25 B ALL DIMENSIONS ARE IN MILLIMETERS C DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS GAGE PLANE R0 10 127 D CONFORMS ASME 14 5 1994 bs SEATING PLANE E LANDPATTERN STANDARD SOIC127P1030X265 20L 1 40 2 pETAILA F DRAWING FILENAME MKT M20BREV3 SCALE 2 1 MKT M20BREV3 Figure 31 20 Lead Small Outline Package SOIC Package drawings are provided as a service to customers considering Fairchild components Drawings may change in any manner without notice Please note the revision and or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision Package specifications do not expand the terms of Fairchild s worldwide terms and conditions specifically the warranty therein which covers Fairchild products Always visit Fairchild Semiconductor s online packaging area for the most recent package drawings http www fairchildsemi com packag2. Pin Name Description 1 HIN1 Logic input 1 for high side gate 1 driver 2 LIN1 Logic input 1 for low side gate 1 driver 3 HIN2 Logic input 2 for high side gate 2 driver 4 LIN2 Logic input 2 for low side gate 2 driver 5 Logic input 3 for high side gate 3 driver 6 LIN3 Logic input 3 for low side gate 3 driver 7 LO3 Low side gate driver 3 output 8 High side driver 3 floating supply offset voltage 9 High side driver 3 gate driver output 10 VB3 High side driver 3 floating supply voltage 11 GND Ground 12 Vpp Logic and all low side gate drivers power supply voltage 13 LO2 Low side gate driver 2 output 14 Vs2 High side driver 2 floating supply offset voltage 15 HO2 High side driver 2 gate driver output 16 VB2 High side driver 2 floating supply voltage 17 LO1 Low side gate driver 1 output 18 Vsi High side driver 1 floating supply offset voltage 19 HO1 High side driver 1 gate driver output 20 High side driver 1 floating supply voltage 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com 9I 888 Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device The device may not function or be opera ble above the recommended operating conditions and stressing the parts to these levels is not recommended In addi tion extended exposure to stresses above the recomm
3. UniFET VCXTM VisualMax EZSWITCH and FlashWriter are trademarks of System General Corporation used under license by Fairchild Semiconductor DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD S WORLDWIDE TERMS AND CONDITIONS SPECIFICALLY THE WARRANTY THEREIN WHICH COVERS THESE PRODUCTS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which are intended for surgical implant into the body or b support or sustain life whose failure to perform when propery used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury of the user PRODUCT STATUS DEFINITIONS Definition of Terms 2 A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the li
4. x c gt 25939 xL LLLLELIORERULTT 0 2 0 0 pop t ep ee 24 l 0 00 Ld doa dou doa doa dou 21 l 40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120 Temperature C Temperature C Figure 20 High Level Output Voltage vs Temp Figure 21 Low Level Output Voltage vs Temp 2008 Fairchild Semiconductor Corporation www fairchildsemi com FAN7888 Rev 1 0 0 9 9I eBpug JJeH 888 Typical Characteristics Continued Va IV Qno pes opel rcp dp yl 40 20 0 20 40 60 80 100 120 Temperature C Figure 22 Logic High Input Voltage vs Temp In uA 40 20 0 20 40 60 80 100 120 Temperature C Figure 24 Logic Input High Bias Current vs Temp R ko 40 20 0 20 40 60 80 100 120 Temperature C Figure 26 Input Pull down Resistance vs Temp V V 00 e ke 0 40 20 0 20 40 60 80 100 120 Temperature C Figure 23 Logic Low Input Voltage vs Temp V V 40 20 0 20 40 60 80 100 120 Temperature C Figure 25 Allowable Negative Vs Voltage vs Temp 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com 9I eBpug JJeH 888 Application Information 1 Protec
5. 20 40 60 80 100 120 Temperature C Figure 13 Quiescent Vgs Supply Current vs Temp 9I eDpug jJIeH 888 1000 1000 800 800 E 600L lt 600 lt 1 a i J J J 0 o Fr 8 f 400 400L 200L 200 0 1 1 1 1 1 1 1 1 1 1 1 0 1 ji 1 1 1 1 1 1 ji 1 1 1 40 20 0 20 40 60 80 100 120 40 20 0 20 40 60 80 100 120 Temperature C Temperature C Figure 14 Operating Vpp Supply Current vs Temp Figure 15 Operating Vgs Supply Current vs Temp 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 8 www fairchildsemi com Typical Characteristics Continued 9 0 T T T T T 9 0 T T 8 5 8 5 gt 80 8 8 0L gt gt 7 5L 7 5 70 _ Tu 0 5202 0 220 40 gt 60 280 100 120 40 20 20 40 60 80 100 120 Temperature C Temperature C Figure 16 UVLO vs Temp Figure 17 Vpp UVLO vs Temp 9 0 T T T 9 0 8 5L 8 5L E E 8 0 280 gt gt L L 701414181414 1414 ca 1 Yl up battu 40 20 20 40 60 80 100 120 40 20 20 40 60 80 100 120 Temperature C Temperature C Figure 18 Vgs UVLO vs Temp Figure 19 Vgs UVLO vs Temp 1 0 T T T T 0 60 T T T T T T 0 8 0 45 gt osl
6. Absolute Maximum Ratings Symbol Parameter Min Max Unit VB1 23 High side Floating Supply Voltage 5123 10 23 20 V Vs123 High side Floating Supply Offset Voltage 6 200 V Vpp Supply Voltage 10 20 V VHo1 2 3 High side Output Voltage Vs1 2 3 Vp1 2 3 V Viot 2 3 Low side Output Voltage GND Vpp V Vin Logic Input Voltage HIN1 2 3 and LIN1 2 3 GND Vpp V TA Ambient Temperature 40 125 C 2008 Fairchild Semiconductor Corporation www fairchildsemi com FAN7888 Rev 1 0 0 4 9I 888 Electrical Characteristics VBiAs Vps1 2 3 15 0V TA 25 C unless otherwise specified The Viy and parameters are referenced to GND The Vo and l parameters are referenced to GND and Vg 2 and are applicable to the respective outputs LO1 2 3 and 1 2 3 Symbol Characteristics Condition Min Typ Max Unit LOW SIDE POWER SUPPLY SECTION lapp Quiescent Vpp Supply Current ViIN1 2 3 0V or 5V 160 350 Busana Operating Vpp Supply Current for each 2 3 20kHz rms Value 500 900 pA 2 Channel 5 Vpp Supply Under Voltage Positive goin 9 going Vpp Sweep Vgg 15V 72 82 90 V Vpp Supply Under Voltage Negative going t Vppuv Threshold Vpp Sweep Vgs 15V 6 8 7 8 8 5
7. 0 20 0 20 40 60 80 100 120 Temperature C Figure 5 Turn off Propagation Delay vs Temp 100 80 60 t ns OS Si s gt 40 20 0 20 40 60 80 100 120 Temperature C Figure 7 Turn off Fall Time vs Temp e 40L 30 2 ns 20 40 20 0 20 40 60 80 100 120 Temperature C Figure 9 Delay Matching vs Temp 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com Typical Characteristics Continued 500 40 20 0 20 40 60 80 100 120 Temperature C Figure 12 Quiescent Vpp Supply Current vs Temp 6 gt 0 gt gt gt gt gt gt 5 5 50 400 E 40L F 300 30L Q 30 200L 100 pe E E m phe MERE DN UNS NE ent neg 190 200720 40 20 O 20 40 60 80 100 120 Temperature C Temperature C Figure 10 Dead Time vs Temp Figure 11 Dead Time Matching vs Temp 350 120 I I 300 100L 250 lt E lt e m 8 150L 100 50 20L ol 1 1 1 1 1 1 1 1 0 1 1 1 li 1 1 1 1 1 40 20 0
8. 0 0 5 9I 888 Dynamic Electrical Characteristics 25 VBlAS VBs1 2 3 15 0 23 GND 1000pF unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit ton Turn on Propagation Delay Vs12 3 0V 130 220 ns torr Turn off Propagation Delay 51 23 0 150 240 ns tn Turn on Rise Time 50 120 ns t Turn off Fall Time 30 80 ns MT1 Turn on Delay Matching ton H LoFF L 50 ns MT2 Turn off Delay Matching l toeg LoN L 50 ns DT Dead Time 100 270 440 ns MDT Dead time Matching tpr4 tpr2 60 ns 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com 9I ebpiig jeH 888 Typical Characteristics 250 3 OE e hp gs ef S 40 20 0 20 40 60 80 100 120 Temperature C Figure 4 Turn on Propagation Delay vs Temp t4 ns 4 24 du SI pe os sa A 40 20 0 20 40 60 80 100 120 Temperature C Figure 6 Turn on Rise Time vs Temp PP 40L 30 MT1 ns 20 40 20 0 20 40 60 80 100 120 Temperature C Figure 8 Turn on Delay Matching vs Temp tore ns 9I 888 g l j 1 pd poq de hs 4
9. Click here for this datasheet translated into Chinese uwa FAIRCHILD SEMICONDUCTOR FAN7888 3 Half Bridge Gate Drive IC Features m Floating Channel for Bootstrap Operation to 200V m Typically 350mA 650mA Sourcing Sinking Current Driving Capability for All Channels m 3 Half Bridge Gate Driver m Extended Allowable Negative Vs Swing to 9 8V for Signal Propagation at Vgs 15V m Matched Propagation Delay Time Maximum 50ns m 3 3V and 5V Input Logic Compatible m Built in Shoot Through Prevention Circuit for All Channels with Typically 270ns Dead Time m Built in Common Mode dv dt Noise Canceling Circuit m Built in UVLO Functions for All Channels Applications m 3 Phase Motor Inverter Driver May 2008 Description The FAN7888 is a monolithic three half bridge gate drive IC designed for high voltage high speed driving MOS FETs and IGBTs operating up to 200V Fairchild s high voltage process and common mode noise canceling technique provide stable operation of high side drivers under high dv dt noise circumstances An advanced level shift circuit allows high side gate driver operation up to 9 8V typical for Vgs 15V The UVLO circuits prevent malfunction when Vpp and lt are lower than the specified threshold voltage Output drivers typically source sink 350mA 650mA respectively which is suitable for three phase half bridge applications in motor drive systems Ordering In
10. V Vpp Supply Under Voltage Lockout E Vppuvs Hysteresis Vpp Sweep Ves 1 5V 0 4 V BOOTSTRAPPED POWER SUPPLY SECTION Quiescent Vgs Supply Current for each J loBs1 23 Channel VHIN1 2 3 0V or 5V 50 120 HA Operating Vgs Supply Current for each fuv 23 20kHz rms Value 400 800 pA Channel 2 Vps Supply Under Voltage Positive goin NE RUM 9 going Vpp 15V Vas Sweep VOSSIUS v Vgs Supply Under Voltage Negative going Vesuv Threshold Vpp 1 5V Vpgg Sweep 6 8 7 8 8 5 V Vgs Supply Under Voltage Lockout E Hysteresis Vpp 1 5V 0 4 V lik Offset Supply Leakage Current Vp1 2 37Vg1 2 3 200V 10 pA GATE DRIVER OUTPUT SECTION Vou High level Output Voltage 20 1 0 V VoL Low level Output Voltage Vo 20 0 6 V lo Output HIGH Short circuit Pulsed Current 0 5 with PW lt 10us 250 350 mA lo Output LOW Short circuit Pulsed Current 15 with PW lt 10us 500 650 mA Vs Allowable Negative Vs Pin Voltage for IN 9 8 7 0 V Signal Propagation to Ho LOGIC INPUT SECTION HIN LIN Vin Logic 1 Input Voltage 2 5 V ViL Logic 0 Input Voltage 1 0 V TING Logic 1 Input Bias Current Vin oV 25 50 lin Logic 0 Input Bias Current 0 20 uA Rin Input Pull down Resistance 100 200 300 Note 4 This parameter is guaranteed by design 2008 Fairchild Semiconductor Corporation www fairchildsemi com FAN7888 Rev 1
11. ended operating conditions may affect device reliability The absolute maximum ratings are stress ratings only 25 unless otherwise specified Symbol Parameter Min Max Unit Vp High side Floating Supply Voltage of 23 0 3 225 0 V Vs High side Floating Supply Offset Voltage of Ve gt VB1 2 3725 2 3 0 3 V Vuot 2 3 High side Floating Output Voltage Vs1 2 3 0 3 VB1 2 3 0 3 V Vpp Low side and Logic fixed Supply Voltage 0 3 25 0 V Vio12 3 Low side Output Voltage 0 3 Vpp 0 3 V Vin Logic Input Voltage HIN1 2 3 and LIN1 2 3 0 3 Vpp40 3 V dVs dt Allowable Offset Voltage Slew Rate 50 V ns Pp Power Dissipation 99 1 8 W OJA Thermal Resistance Junction to ambient 80 C W Junction Temperature 150 C Ts Storage Temperature 55 150 Notes 1 Mounted on 76 2 x 114 3 x 1 6mm PCB FR 4 glass epoxy material 2 Refer to the following standards JESD51 2 Integral circuits thermal test method environmental conditions natural convection JESD51 3 Low effective thermal conductivity test board for leaded surface mount packages 3 Do not exceed Pp under any circumstances Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications Fairchild does not recommend exceeding them or designing to
12. fe support device or system or to affect its safety or effectiveness Datasheet Identification Advance Information Preliminary Product Status Formative In Design Sp First Production This datasheet conta at a later date Fairch any time without notice to improve design Definition This datasheet contains the design specifications for product development ecifications may change in any manner without notice ins preliminary data supplementary data will be published ild Semiconductor reserves the right to make changes at No Identification Needed This datasheet contai ns final specifications Fairchild Semiconductor reserves Obsolete Not In Full Production the right to make changes at any time without notice to improve the design This datasheet contains specifications on a product that is discontinued by Production Fairchild Semiconductor The datasheet is for reference information only Rev 134 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com 9I eDpug jJIeH 898
13. formation Part Number Package Operating Temperature Range Packing Method FAN7888M Tube 20 SOIC 40 C to 125 C FAN7888MX Tape amp Reel All packages are lead free per JEDEC J STD 020B standard 2008 Fairchild Semiconductor Corporation www fairchildsemi com FAN7888 Rev 1 0 0 9I ebpug JjeH 888 Typical Application Circuit 15V Up to 200V 3 Phase BLDC Motor Controller 888 Figure 1 3 Phase BLDC Motor Drive Application Internal Block Diagram FAN7888 Rev 00 NOISE CANCELLER HO1VH3N3S 3sTnd VDD_UVLO SCHMITT TRIGGER INPUT ULIN a VDD U Phase Driver PREVENTION V Phase Driver CONTROL LOGIC W Phase Driver C OWLIN Figure 2 Functional Block Diagram FAN7888 Rev 01 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 2 www fairchildsemi com 9I 9 uq eie9 abpiig HeH 888 Pin Configuration Pin Definitions TI gt lt 7888 Rev 00 Figure 3 Pin Configuration Top View
14. ing 2008 Fairchild Semiconductor Corporation www fairchildsemi com FAN7888 Rev 1 0 0 13 OI 9Aluq ei1e5 eDpug jjeH 888 ES FAIRCHILD SEMICONDUCTOR TRADEMARKS The following includes registered and unregistered trademarks and service marks owned by Fairchild Semiconductor and or its global subsidiaries and is not intended to be an exhaustive list of all such trademarks ACEx Build it Now CorePLUS CorePOWER CROSSVOLT CTETM Current Transfer Lagic EcoSPARK EfficentMax EZSWITCH EZ Fairchild Fairchild Semiconductor FACT Quiet Series TM FACT FAST FastvCore FlashWriter F PFSE M FRFET Global Power Resource Green FRS Green FPS e Series IntelliMAXTM ISOPLANAR MegaBuck MICROCOUPLER MicroFET MicroPak MillerDrive MotionMax Motion SPM OPTOLOGIC OPTOPLANAR PDP SPM PowerSPM PowerT rench Programmable Active Droop QFET Qs Quiet Series RapidConfigure Saving our world 1mW at a time TM SmartMax TM SMART START STEALTH SuperFET SuperSOT 3 SuperSOT 6 SuperSOT 8 SupreMOS TM SyncFET TM E SYSTEM GENERAL The Power Franchise the Paver TinyBoost TinyBuck TinyLogic TINYOPTO TinyPower TinyPVWM M uSerDes es UHC Ultra FRFET
15. tem The waveforms are idealized they assumed that the generated back EMF waveforms are trapezoidal with flat tops of sufficient width to produce constant torque when the line currents are perfectly rectangular 120 electrical degrees with the switching sequence as shown in Figure 29 The operating waveforms of the wey connection reveal that repeat every 60 electrical degrees with each 60 segment being commutated to another phase as shown in Figure 29 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com 9I eDpug jJjeH 888 Input Output HIN HO1 2 3 LIN LO1 2 3 Phase Current 30 Q5 Application Information Continued Q1 HIN1 Phase Voltage VS1 Current Flow Direction o Switching Time Definitions HIN1 2 3 50 LIN1 2 3 HO1 2 3 LO1 2 3 Figure 30 Switching Time Definition 300 330 Elec Q5 HIN3 Figure 29 120 Commutation Operation Waveforms for 3 Phase BLDC Motor Application 2008 Fairchild Semiconductor Corporation FAN7888 Rev 1 0 0 www fairchildsemi com 9I eBpug JJeH 888 Mechanical Dimensions
16. tion Function 1 1 Under Voltage Lockout UVLO The high and low side drivers include under voltage lockout UVLO protection circuitry for each channel that monitors the supply voltage Vpp and bootstrap capaci tor voltage Vgs1 2 3 independently It can be designed prevent malfunction when Vpp and 2 are lower than the specified threshold voltage The UVLO hystere sis prevent chattering during power supply transitions 1 2 Shoot Through Prevention Function The FAN7888 has shoot through prevention circuitry monitoring the high and low side control inputs It can be designed to prevent outputs of high and low side from turning on at same time as shown Figure 27 and 28 HIN1 2 3 LIN1 2 3 LIN1 2 3 HIN1 2 3 M gt hoot Through Prevent HO1 2 3 LO1 2 3 After DT LO1 2 3 HO1 2 3 gt L After DT FAN7888 Rev 00 Figure 27 Waveforms for Shoot Through Prevention HIN1 2 3 LIN1 2 3 LIN1 2 3 HIN1 2 3 26 Shoot Through Prevent HO1 2 3 LO1 2 3 gt _JAtter DT LO1 2 3 HO1 2 3 FAN7888 Rev 00 Figure 28 Waveforms for Shoot Through Prevention 2 Operational Notes The FAN7888 is a three half bridge gate driver with internal typically 120ns dead time for the three phase Brushless DC BLDC motor drive system as shown in Figure 1 Figure 29 shows a switching sequence of 120 electrical commutation for a three phase BLDC motor drive sys
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