ANALOG DEVICES Single-Lead Heart-Rate Monitor Analog Front End AD8232
Contents
1. 50 NO DC OFFSET 1400 300mV OFFSET 40 1200 1000 30 800 S z 4 600 9 10 400 200 9 10 5 20 15 10 05 0 05 10 15 20 1 10 100 1k 10k GAIN ERROR E FREQUENCY Hz 8 Figure 4 Instrumentation Amplifier Gain Error Distribution Figure 7 Instrumentation Amplifier Gain vs Frequency 120 100 INPUT COMMON MODE VOLTAGE V 5 rk a a a a a CMRR dB gt o 2 80 90g 330 oom mmm mmo aan 447 2 20 2 0 0 5 1 0 1 5 2 0 2 5 3 0 35 10 100 1k 10k 100k 5 OUTPUT VOLTAGE V 8 FREQUENCY Hz 8 Figure 5 Instrumentation Amplifier Figure 8 Instrumentation Amplifier CMRR vs Frequency RTI Input Common Mode Range vs Output Voltage Rev A Page 7 of 28 AD8232 120 110 100 PSRR dB A 50 40 0 1 1 10 100 1 10k 100k FREQUENCY Hz Figure 9 Instrumentation Amplifier PSRR vs Frequency2. 10k _ 1 N gt 5 0 2 100 1 0 1 1 10 100 1k 10k 100k FREQUENCY Hz 10866 009 GAIN ERROR 10866 010 Figure 10 Instrumentation Amplifier Voltage Noise Spectral Density RTI 1s DIV Figure 11 Instrumentation Amplifier 0 1 Hz to 10 Hz Noise 10866 011 Rev A Page 8 of 28 10pV DIV 200ms DIV 10866 012 0 50 100 150 200 250 300 DC OFFSET mV Figure 13 Instrumentation Amplifier Gain Error vs DC Offset 22pF 470pF 1nF O0ps DIV 50mV DIV 10866 014 Figure 14 Instrumentation Amplifier Small Signal Pulse Response 10866 013 OUTPUT SWING V DC BLOCKING INPUT OFFSET mV 0 5V DIV 100us DIV 10866 015 Figure 15 Instrumentation Amplifier Large Signal Pulse Response 1 5 1 5 100 1k 10k 100k 1M LOAD 0 Figure 16 Instrumentation Amplifier Output Swing vs Load 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 17 Instrumentation Amplifier DC Blocking Input Offset Drift INPUT BIAS
3. sss 23 Driven Electrode euet itte aie enitn 23 Application Circuits eter eod ete tees pere tte eR eed Heart Rate Measurement Next to the Heart Exercise Application Heart Rate Measured at the Hands 24 Cardiac Monitor Configuration 25 Portable Cardiac Monitor with Elimination of Motion RR 25 Packaging and Ordering Information 27 Outline Dimensions eene 27 Ordering Gilide ii iere etii 27 Changes to Input Referred Offsets 21 Changes to Figure 53 and High Pass Filtering Section 22 Changes to Additional High Pass Filtering Options Section Added 23 Changes to Low Pass Filtering and Gain Section Added Driving Analog to Digital Converters Section and Figure 61 24 Changes to Figure 62 Figure 64 and Heart Rate Measurement Next to the Heart Section 25 Changes to Exercise Application Heart Rate Measured at the Hands and Figure cette eere 26 Changes to Figure teet e Pe RR 27 8 12 Revision 0 Initial Version Rev A Page 2 of 28 SPECIFICATIONS Vs 3 V Vre 1 5 V Vem 1 5 V Ta 25 C FR low SDN high AC DC low unless otherwise noted AD8232 Table 1 Parameter Symbol Test Conditions Comments Min Typ Max Unit INSTRUMENTATION AMPLIFIER Common Mode Rejection Ratio CMRR Vem 0 35 V to 2 85
4. sse 16 Operational Amplifier 16 Right Leg Drive Amplifier sse 17 Reference corse ete ete tee eid 17 Fast Restore Circuit esses 17 Leads Off Detection ettet 18 REVISION HISTORY 2 13 Rev 0 to Rev A Changes to Table Li e eret 4 Changes to Table2 neenon tiere 6 Change to Figure e DH RE EIER 9 Changes to Figure 22 and Figure 25 t Changes to Figure 34 and Figure 36 sss 14 Changes to Figure 45 Architecture Overview Section and Instrumentation Amplifier Section sss 17 Changes to Right Leg Drive Amplifier Section Reference Buffer Section Fast Restore Circuit Section and Figure 48 Added Figure 46 Renumbered Sequentially 18 Changes to FIgure 4d9 uei perpeti terere N etis 19 Changes to AC Leads Off Detection Section and Standby Operation seien eerie tenter 20 RES 19 Input Protection eterne nente 19 Radio Frequency Interference RFI sss 20 Power Supply Regulation and Bypassing 20 Input Referred Offsets 20 Layout Recommendations 20 Applications Information 21 Eliminating Electrode Offsets 21 High Pass Filtering zeit erret nO nd 21 Low Pass Filtering and Gain ses 23 Driving Analog to Digital Converters
5. ORD Figure 50 Circuit Configuration for DC Leads Off Detection 10866 049 Because in dc leads off mode the AD8232 checks each input individually it is possible to indicate which electrode is discon nected The AD8232 indicates which electrode is disconnected by setting the corresponding LOD or LOD pin high To use this mode connect the AC DC pin to ground Rev A Page 18 of 28 AC Leads Off Detection The ac leads off detection mode is useful when using two electrodes only it does not require the use of a driven electrode In this case a conduction path must exist between the two electrodes which is usually formed by two resistors as shown in Figure 51 These resistors also provide a path for bias return on each input Connect each resistor to REFOUT or RLD to maintain the inputs within the common mode range of the instrumentation amplifier 10866 050 Figure 51 Circuit Configuration for AC Leads Off Detection The AD8232 detects when an electrode is disconnected by forcing a small 100 kHz current into the input terminals This current flows through the external resistors from IN to IN and develops a differential voltage across the inputs which is then synchronously detected and compared to an internal threshold The recommended value for these external resistors is 10 MQ Low resistance values make the differential drop too low to be detected and lower the input impedance of the amplifier When the ele
6. 0 1 V Short Circuit Current Limit lour 12 mA Gain Bandwidth Product GBP 100 kHz Slew Rate SR 0 02 V us Voltage Noise Density RTI f 1kHz 60 nV VHz Peak to Peak Voltage Noise RTI f 0 1 10 Hz 6 uV p p 0 5 Hz to 40 Hz 8 uV p p Rev A Page 3 of 28 AD8232 Parameter Symbol Test Conditions Comments Min Typ Max Unit RIGHT LEG DRIVE AMPLIFIER A2 Output Swing 50 0 1 Vs 0 1 V Short Circuit Current lour 11 mA Integrator Input Resistor 120 150 180 Gain Bandwidth Product GDP 100 kHz REFERENCE BUFFER A3 Offset Error Vos Ri gt 50 1 mV Input Bias Current ls 100 pA Short Circuit Current Limit lout 12 mA Voltage Range 50 0 1 Vs 0 7 V DC LEADS OFF COMPARATORS Threshold Voltage TVs 0 5 V Hysteresis 60 mV Propagation Delay 0 5 us AC LEADS OFF DETECTOR Square Wave Frequency Fac 50 100 175 kHz Square Wave Amplitude lac 200 nA p p Impedance Threshold Between IN and IN 10 20 MO Detection Delay 110 us FAST RESTORE CIRCUIT Switches S1 and S2 On Resistance Ron 8 10 12 kQ Off Leakage 100 pA Window Comparator Threshold Voltage From either rail 50 mV Propagation Delay 2 us Switch Timing Characteristics Feedback Recovery Switch On Time tswi 110 ms Filter Recovery Switch On Time tsw2 55 ms Fast Restore Reset test 2 us LOGIC INTERFACE Input Characteristics Input Voltage AC DC and FR Low Vi 1 24 V High Vin 1 35 V Input Voltage SDN L
7. lt 5 10 2 1 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 42 Reference Buffer Bias Current vs Temperature Rev A Page 14 of 28 10866 042 10866 041 AD8232 SYSTEM PERFORMANCE CURVES 240 200 Vs 2V 180 Vs 220 5 3 5V 160 200 T 140 E 5 LE G 180 tc 5 3 100 160 gt B 2 60 a 140 o 40 120 20 100 g 0 i 40 20 0 20 40 60 80 100 5 40 20 20 40 60 80 100 5 TEMPERATURE 8 TEMPERATURE 8 Figure 43 Supply Current vs Temperature Figure 44 Shutdown Current vs Temperature Rev A Page 15 of 28 AD8232 THEORY OF OPERATION Vs HPDRIVE HPSENSE IAOUT Sw OPAMP OPAMP ALL SWITCHES SHOWN IN DC LEADS OFF DETECTION POSITION AND FAST RESTORE DISABLED REFOUT 10866 045 Figure 45 Simplified Schematic Diagram ARCHITECTURE OVERVIEW The AD8232 is an integrated front end for signal conditioning of cardiac biopotentials for heart rate monitoring It consists of a specialized instrumentation amplifier IA an operational amplifier A1 a right leg drive amplifier A2 and a midsupply reference buffer A3 In addition the AD8232 includes leads off detection circuitry and an automatic fast restore circuit that brings back the signal shortly after leads are reconnected The AD8232 contains a specialized instrumentation amplifier that
8. 1 10 100 1k 10k 100k FREQUENCY Hz Figure 30 Operational Amplifier Power Supply Rejection Ratio 20V DIV 10pV DIV 10866 031 Figure 31 Operational Amplifier Load Transient Response 100 uA Load Change 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 32 Operational Amplifier Offset vs Temperature 10866 030 10866 032 AD8232 10 000 1 000 INPUT BIAS CURRENT pA 40 20 0 20 40 60 80 100 TEMPERATURE C 10866 033 Figure 33 Operational Amplifier Bias Current vs Temperature Rev A Page 12 of 28 AD8232 RIGHT LEG DRIVE RLD AMPLIFIER PERFORMANCE CURVES 140 180 120 160 100 140 a 80 120 S 60 100 5 5 a I M 20 60 0 40 20 20 8 i
9. CURRENT nA GAIN ERROR 10866 016 CMRR pV V 10866 017 Rev A Page 9 of 28 AD8232 TEMPERATURE C Figure 18 Instrumentation Amplifier Input Bias Current and Input Offset Current vs Temperature 0 5 0 4 0 3 0 2 0 1 40 20 0 20 40 60 80 100 TEMPERATURE Figure 19 Instrumentation Amplifier Gain Error vs Temperature 50 50 40 20 0 20 40 60 80 100 TEMPERATURE C Figure 20 Instrumentation Amplifier CMRR vs Temperature INPUT OFFSET CURRENT nA 10866 019 10866 020 10866 018 AD8232 OPERATIONAL AMPLIFIER PERFORMANCE CURVES 1000 800 600 o E z 2 400 200 0 5V DIV 100pV DIV 5 0 5 4 2 0 2 4 OFFSET VOLTAGE mV 8 Figure 21 Operational Amplifier Offset Distribution Figure 24 Operational Amplifier Large Signal Transient Response 14 18 0 TAIN 0 10k
10. LFCSP_WQ CP 20 10 AD8232ACPZ WP 40 C to 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 20 10 AD8232 EVALZ 17 RoHS Compliant Part Evaluation Board Rev A Page 27 of 28 AD8232 NOTES 2012 2013 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D10866 0 2 13 A DEVICES www analog com AD8232 Rev A Page 28 of 28
11. gt ANALOG DEVICES single Lead Heart Rate Monitor Front End FEATURES Fully integrated single lead ECG front end Low supply current 170 pA typical Common mode rejection ratio 80 dB dc to 60 Hz Two or three electrode configurations High signal gain G 100 with dc blocking capabilities 2 pole adjustable high pass filter Accepts up to 300 mV of half cell potential Fast restore feature improves filter settling Uncommitted op amp 3 pole adjustable low pass filter with adjustable gain Leads off detection ac or dc options Integrated right leg drive RLD amplifier Single supply operation 2 0 V to 3 5 V Integrated reference buffer generates virtual ground Rail to rail output Internal RFI filter 8 kV HBM ESD rating Shutdown pin 20 lead 4 mm x 4 mm LFCSP package APPLICATIONS Fitness and activity heart rate monitors Portable ECG Remote health monitors Gaming peripherals Biopotential signal acquisition GENERAL DESCRIPTION The AD8232 is an integrated signal conditioning block for ECG and other biopotential measurement applications It is designed to extract amplify and filter small biopotential signals in the presence of noisy conditions such as those created by motion or remote electrode placement This design allows for an ultralow power analog to digital converter ADC or an embedded microcontroller to acquire the output signal easily The AD8232 can implement a two pole high pass filter for eliminati
12. of the connections between high impedance nodes as short as possible to avoid introducing additional noise and errors from corrupting the signal To maintain high CMRR over frequency keep the input traces symmetrical and length matched Place safety and input bias resistors in the same position relative to each input In addition the use ofa ground plane significantly improves the noise rejection of the system Rev A Page 20 of 28 APPLICATIONS INFORMATION ELIMINATING ELECTRODE OFFSETS The instrumentation amplifier in the AD8232 is designed to apply gain and to filter out near dc signals simultaneously This capability allows it to amplify a small ECG signal by a factor of 100 yet reject electrode offsets as large as 300 mV To achieve offset rejection connect an RC network between the output of the instrumentation amplifier HPSENSE and HPDRIVE as shown in Figure 53 _ HPDRIVE HPSENSE IAOUT HPA R 51 L 99R ELECTRODE OFFSETS C1 2 REFOUT 8 Figure 53 Eliminating Electrode Offsets This RC network forms an integrator that feeds any near dc signals back into the instrumentation amplifier thus eliminating the offsets without saturating any node and maintaining high signal gain In addition to blocking offsets present across the inputs of the instrumentation amplifier this integrator also works as a high pass filte
13. on the high pass filters can saturate the instru mentation amplifier and subsequent stages The use of the fast restore feature helps reduce the recovery time and therefore minimize on time in power sensitive applications INPUT PROTECTION All terminals of the AD8232 are protected against ESD In addition the input structure allows for dc overload conditions that are a diode drop above the positive supply and a diode drop below the negative supply Voltages beyond a diode drop of the supplies cause the ESD diodes to conduct and enable current to flow through the diode Therefore use an external resistor in series with each of the inputs to limit current for voltages beyond the supplies In either scenario the AD8232 safely handles a continuous 5 mA current at room temperature For applications where the AD8232 encounters extreme over load voltages such as in cardiac defibrillators use external series resistors and gas discharge tubes GDT Neon lamps are com monly used as an inexpensive alternative to GDTs These devices can handle the application of large voltages but do not maintain the voltage below the absolute maximum ratings for the AD8232 A complete solution includes further clamping to either supply using additional resistors and low leakage diode clamps such as BAV199 or FJH1100 As a safety measure place a resistor between the input pin and the electrode that is connected to the subject to ensure that the current flow
14. shifts the pole to a higher frequency delivering a quicker settling time Note that the fast restore settling time depends on how quickly the internal 10 resistors of the AD8232 can drain the capacitors in the high pass circuit Smaller capacitor values result in a shorter settling time If by the end of the timing the saturation condition persists the cycle repeats Otherwise the AD8232 returns to its normal operation If either of the leads off comparator outputs is indi cating that an electrode has been disconnected the timing circuit is prevented from triggering because it is assumed that no valid signal is present To disable fast restore drive the FR pin low or tie it permanently to GND LEADS OFF DETECTION The AD8232 includes leads off detection It features ac and dc detection modes optimized for either two or three electrode configurations respectively DC Leads Off Detection The dc leads off detection mode is used in three electrode con figurations only It works by sensing when either instrumentation amplifier input voltage is within 0 5 V from the positive rail In this case each input must have a pull up resistor connected to the positive supply During normal operation the subjects potential must be inside the common mode range of the instrumentation amplifier which is only possible if a third electrode is connected to the output of the right leg drive amplifier Vs TO DRIVEN ELECTRODE
15. voltage AD8232 the voltage at the output of the instrumentation amplifier is this reference voltage The reference voltage level is set at the REFIN pin It can be set with a voltage divider or by driving the REFIN pin from some other point in the circuit for example from the ADC reference The voltage is available at the REFOUT pin for the filtering circuits or for an ADC input 10866 046 Figure 47 Setting the Internal Reference To limit the power consumption of the voltage divider the use of large resistors is recommended such as 10 MO The designer must keep in mind that high resistor values make it easier for interfering signals to appear at the input of the reference buffer To minimize noise pickup it is recommended to place the resistors close to each other and as near as possible to the REFIN terminal Furthermore use a capacitor in parallel with the lower resistor on the divider for additional filtering as shown in Figure 47 Keep in mind that a large capacitor results in better noise filtering but it takes longer to settle the reference after power up The total time it takes the reference to settle within 196 can be estimated with the formula 2 1 X 1 2 Note that disabling the AD8232 with the shutdown terminal does not discharge this capacitor FAST RESTORE CIRCUIT Because of the low cutoff frequency used in high pass filters in ECG applications signals may require several se
16. 120 PHASE MARGIN 100 140 T 9 80 120 5 1k N a 60 100 gt lt 5 lt 40 80 lt a o 20 60 o 100 amp 0 40 20 20 40 0 R 10 0 1 1 10 100 1k 10k 100 1M 3 0 1 1 10 100 1k 10k 100k FREQUENCY Hz 8 FREQUENCY Hz 5 Figure 22 Operational Amplifier Open Loop Gain and Phase vs Figure 25 Operational Amplifier Voltage Spectral Noise Density vs Frequency Frequency 10pS DIV 50mV DIV 2 2 8 1s DIV 8 Figure 23 Operational Amplifier Small Signal Response for Figure 26 Operational Amplifier 0 1 Hz to 10 Hz Noise Various Capacitive Loads Rev A Page 10 of 28 INPUT BIAS CURRENT pA OUTPUT SWING V 5yV DIV 200ms DIV 10866 027 Figure 27 Operational Amplifier 0 5 Hz to 40 Hz Noise S 8 8 8 100 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 INPUT COMMON MODE VOLTAGE V Figure 28 Operational Amplifier Bias Current vs Input Common Mode Voltage 1 5 100 LOAD 0 Figure 29 Operational Amplifier Output Voltage Swing vs Output Current PSRR dB 10866 028 OFFSET mV 10866 029 Rev A Page 11 of 28 AD8232 0 1
17. AUTION 7 2 ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality This level or the maximum specified supply voltage whichever is the lesser indicates the superior voltage limit for any terminal If input voltages beyond the specified minimum or maximum voltages are expected place resistors in series with the inputs to limit the current to less than 5 mA 2 Oja is specified for a device in free air on a 4 layer board Rev A Page 5 of 28 AD8232 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ul 2 ua T eo Nr TT 7 18 REFIN HPDRIVE 1 2 C15 IN 2 2 lt 2 14 AC DC ac AD8232 4 77 TOP VIEW RLDFB 4 i i 2712 LOD RLD 5 1 11 LOD e 22545 2020 amp NOTES 1 CONNECT THE EXPOSED PAD TO GND OR LEAVE UNCONNECTED 10866 002 Figure 2 Pin Configuration Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 HPDRIVE High Pass Driver Output Connect HPDRIVE to the capacitor in the first high pass filter The AD8232 drives this pin to keep HPSENSE at the same level as the reference voltage 2 IN I
18. DP150x 2 8 HPDRIVE HPSENSE 4Vg 42 8V 10 10 180kQ VOUT LA O IAOUTO uoo s Vearr RA O REFIN ELECTRODE m 10ma oUF INTERFACE ORLDF ES 360kQ 1NF RL e GNDQ V C Vs wae a i OPAMP ACIDC ADuCM360 ADXL346 100kQ 6 2 1 0 P1 4 MISO P1 SCLK 0 47uF 0 47 47 47 Vs Q 0 AVDD P0 3 CS1 cs pi IOVDD P0 0 MISO1 TX MERE P0 2 MOSH RX m Q Bs GND P0 1 SCLK1 D CLK Figure 68 Low Power Portable Cardiac Monitor Rev A Page 26 of 28 10866 163 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS PIN 1 INDICATOR 4 10 4 00 sa 3 90 TOP VIEW e 4 a A 0 30 0 25 NI FOR PROPER CONNECTION OF THE EXPOSED PAD REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PLANE 0 05 L nonoo r isnon COPLANARITY SEATING 7 0 08 0 20 REF COMPLIANT STANDARDS MO 220 WGGD Figure 69 20 Lead Lead Frame Chip Scale Package LFCSP_WQ 4mm x 4 mm Body Very Very Thin Quad CP 20 10 Dimensions shown in millimeters SECTION OF THIS DATA SHEET 061609 B AD8232 ORDERING GUIDE Model Temperature Range Package Description Package Option AD8232ACPZ R7 40 C 85 C 20 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 20 10 AD8232ACPZ RL 40 C to 85 20 Lead Lead Frame Chip Scale Package
19. SDN Shutdown Control Input Drive SDN low to enter the low power shutdown mode 14 AC DC Leads Off Mode Control Input Drive the AC DC pin low for dc leads off mode Drive the AC DC pin high for ac leads off mode 15 FR Fast Restore Control Input Drive FR high to enable fast recovery mode otherwise drive it low 16 GND Power Supply Ground 17 Vs Power Supply Terminal 18 REFIN Reference Buffer Input Use REFIN a high impedance input terminal to set the level of the reference buffer 19 IAOUT Instrumentation Amplifier Output Terminal 20 HPSENSE High Pass Sense Input for Instrumentation Amplifier Connect HPSENSE to the junction of R and C that sets the corner frequency of the dc blocking circuit EP Exposed Pad Connect the exposed pad to GND or leave it unconnected Rev Page 6 of 28 AD8232 TYPICAL PERFORMANCE CHARACTERISTICS Vs 3 V Vre 1 5 V Vem 1 5 V Ta 25 C unless otherwise noted INSTRUMENTATION AMPLIFIER PERFORMANCE CURVES 1200 1000 800 600 UNITS INPUT BIAS CURRENT amp kh amp 400 200 120 90 60 30 0 30 60 90 120 0 5 1 0 1 5 2 0 2 5 3 0 35 5 CMRR V V 8 INPUT COMMON MODE VOLTAGE V 8 Figure 3 Instrumentation Amplifier CMRR Distribution Figure 6 Instrumentation Amplifier Input Bias Current vs CMV
20. V Voire 80 86 dB DC to 60 Hz Vem 0 35 V to 2 85 V Voire 0 3 V 80 dB Power Supply Rejection Ratio PSRR Vs 2 0 V to 3 5 V 76 90 dB Offset Voltage RTI Vos Instrumentation Amplifier Inputs 3 8 mV DC Blocking Input 5 50 uV Average Offset Drift Instrumentation Amplifier Inputs 10 uV C DC Blocking Input 0 05 uV C Input Bias Current ls 50 200 pA Ta 0 C to 70 C 1 nA Input Offset Current los 25 100 pA Ta 0 C to 70 C 1 nA Input Impedance Differential 10 7 5 GO pF Common Mode 5 15 GQ pF Input Voltage Noise RTI Spectral Noise Density f 1kHz 100 nV 4Hz Peak to Peak Voltage Noise 0 1 Hzto 10 Hz 12 uV p p 0 5 Hz to 40 Hz 14 uV p p Input Voltage Range Ta 0 C to 70 C 0 2 Vs V DC Differential Input Range Voir 300 300 mV Output Output Swing 50 0 1 Vs 0 1 V Short Circuit Current lour 6 3 mA Gain Av 100 V V Gain Error Vor 0 4 Voirr 300 mV to 300 mV 1 3 5 Average Gain Drift 0 C to 70 C 12 ppm C Bandwidth BW 2 kHz RFI Filter Cutoff Each Input 1 MHz OPERATIONAL AMPLIFIER A1 Offset Voltage Vos 1 5 mV Average TC Ta 0 C 70 C 5 uV C Input Bias Current ls 100 pA Ta 0 C to 70 C 1 nA Input Offset Current los 100 pA Ta 0 C to 70 C 1 nA Input Voltage Range 0 1 Vs 0 1 V Common Mode Rejection Ratio CMRR 0 5 V to 2 5 V 100 dB Power Supply Rejection Ratio PSRR 100 dB Large Signal Voltage Gain Avo 110 dB Output Voltage Range R 50 kQ 0 1 Vs
21. amplifies the ECG signal while rejecting the electrode half cell potential on the same stage This is possible with an indirect current feedback architecture which reduces size and power compared with traditional implementations INSTRUMENTATION AMPLIFIER The instrumentation amplifier is shown in Figure 45 as comprised by two well matched transconductance amplifiers GM1 and GM2 the dc blocking amplifier HPA and an integrator formed by C1 and an op amp The transconductance amplifier GM1 generates a current that is proportional to the voltage present at its inputs When the feedback is satisfied an equal voltage appears across the inputs of the transconductance amplifier GM2 thereby matching the current generated by The difference generates an error current that is integrated across Capacitor C1 The resulting voltage appears at the output of the instrumentation amplifier The feedback of the amplifier is applied via GM2 through two separate paths the two resistors divide the output signal to set an overall gain of 100 whereas the dc blocking amplifier integrates any deviation from the reference level Consequently dc offsets as large as 300 mV across the GM1 inputs appear inverted and with the same magnitude across the inputs of GM2 all without saturating the signal of interest To increase the common mode voltage range of the instrumen tation amplifier a charge pump boosts the supply voltage for the two transconducta
22. at rails the amplifier such as a leads off condition the AD8232 automatically adjusts to a higher filter cutoff This feature allows the AD8232 to recover quickly and therefore to take valid measurements soon after connecting the electrodes to the subject The AD8232 is available in a 4 mm x 4 mm 20 lead LFCSP package Performance is specified from 0 C to 70 C and is operational from 40 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 2012 2013 Analog Devices Inc All rights reserved Technical Support www analog com AD8232 TABLE OF CONTENTS Feature Seana LU LE Mer 1 Applications Renes e Ea 1 Functional Block Diagram 1 General Description eec oe a 1 REVISION HistOby sed MEE 2 Sp cifications t eere 3 Absolute Maximum Ratings sentent 5 ESD Cautions 5 Pin Configuration and Function 6 Typical Performance Characteristics 7 Instrumentation Amplifier Performance Curves 7 Operational Amplifier Performance Curves 10 Right Leg Drive RLD Amplifier Performance Curves 13 Reference Buffer Performance Curves System Performance Curves Theory of Operation eate e 16 Architecture Overview 16 Instrumentation Amplifier
23. cies For stability the gain of the integrator should be less than unity at the frequency of any other poles in the loop such as those formed by the patient s capacitance and the safety resistors The suggested application circuits use a 1 nF capacitor which results in a loop gain of about 20 at line frequencies with a crossover frequency of about 1 kHz In a two lead configuration the RLD amplifier can be used to drive the bias current resistors on the inputs Although not as effective as a true driven electrode this configuration can provide some common mode rejection improvement if the sense electrode impedance is small and well matched Rev A Page 23 of 28 AD8232 APPLICATION CIRCUITS HEART RATE MEASUREMENT NEXT TO THE HEART For wearable exercise devices the AD8232 is typically placed in a pod near the heart The two sense electrodes are placed under neath the pectoral muscles no driven electrode is used Because the distance from the heart to the AD8232 is small the heart signal is strong and there is less muscle artifact interference In this configuration space is at a premium By using as few external components as possible the circuit in Figure 62 is optimized for size ELECTRODE INTERFACE TO DIGITAL INTERFACE SIGNAL OUTPUT 10866 161 Figure 62 Circuit for Heart Rate Measurement Next to Heart A shorter distance from the AD8232 to the heart makes this application less vulnerable to common mod
24. conds to settle This settling time can result in a frustrating delay for the user after a step response for example when the electrodes are first connected Esp TTLE REFERENCE This fast restore function is implemented internally as shown in Figure 48 The output of the instrumentation amplifier is connec ted to a window comparator The window comparator detects a saturation condition at the output of the instrumentation amplifier when its voltage approaches 50 mV from either supply rail 51 SWITCH TIMING 52 10866 047 Figure 48 Fast Restore Circuit Rev A Page 17 of 28 AD8232 SATURATION DETECTED NO SATURATION 51 152 52 trst LEADS OFF LEADS ON e 10866 048 Figure 49 Timing Diagram for Fast Restore Switches Time Base Not to Scale If this saturation condition is present when both input electrodes are attached to the subject the comparator triggers a timing circuit that automatically closes Switch S1 and Switch S2 see Figure 49 for a timing diagram These two switches S1 and S2 enable two different 10 resistor paths one between HPSENSE and IAOUT and another between SW and REFOUT During the time Switch 51 and Switch S2 are enabled these internal resistors appear in parallel with their corresponding external resistors forming high pass filters The result is that the equivalent lower resistance
25. ctrodes are attached to the subject the impedance of this path should be less than 3 to maintain the drop below the comparator s threshold As opposed to the dc leads off detection mode the AD8232 is able to determine only that an electrode has lost its connection not which one During such an event the LOD pin goes high In this mode the LOD pin is not used and remains in a logic low state To use the ac leads off mode tie the AC DC pin to the positive supply rail Note that while REFOUT is at a constant voltage value using the RLD output as the input bias may be more effective in rejecting common mode interference STANDBY OPERATION The AD8232 includes a shutdown pin SDN that further enhances the flexibility and ease of use in portable applications AD8232 where power consumption is critical A logic level signal can be applied to this pin to switch to shutdown mode even when the supply is still on Driving the SDN pin low places the AD8232 in shutdown mode and draws less than 200 nA of supply current offering considerable power savings To enter normal operation drive SDN high when not using this feature permanently tie SDN to Vs During shutdown operation the AD8232 is not able to maintain the REFOUT voltage but it does not drain the REFIN voltage thereby maintaining this additional conduction path from the supply to ground When emerging from a shutdown condition the charge stored in the capacitors
26. cutoff frequency with lower R and C values and the resistor can be used to control of the filter to achieve narrow band pass filters for heart rate detection or maximum pass band flatness for cardiac monitoring With this topology the filter attenuation reverts to a single pole roll off at very low frequencies Because the initial roll off was 40 dB per decade this reversion to 20 dB per decade has little impact on the ability of the filter to reject out of band low frequency signals The designer may choose different values to achieve the desired filter performance To simplify the design process use the following recommendations as a starting point for component value selection R1 22 gt 100 1 2 0 14 x The cutoff frequency is located at 10 2 RI C1 R2C2 The selection of Rcow to be 0 14 times the value of the other two resistors optimizes the filter for a maximally flat pass band Reduce its value to increase the Q and consequently the peaking of the filter Keep in mind that a very low value of can result in an unstable circuit The selection of values based on these criteria result in a transfer function similar to the one shown in Figure 58 fc Table 4 Comparison of High Pass Filtering Options When additional low frequency rejection is desired a high order high pass filter can be implemented by adding an ac coupling network at the output of the ins
27. e interference However since RLD is not used to drive an electrode it can be used to improve the common mode rejection by maintaining the midscale voltage through the 10 bias resistors A single pole high pass filter is set at 7 Hz and there is no low pass filter No gain is used on the output op amp thereby reducing the number of resistors for a total system gain of 100 70 60 50 40 30 MAGNITUDE dB 20 10 0 0 1 1 10 100 1k 10k FREQUENCY Hz 10866 057 Figure 63 Frequency Response for HRM Next to Heart Circuit The input terminals in this configuration use two 180 resistors to protect the user from fault conditions Two 10 MO resistors provide input bias Use higher values for electrodes with high output impedance such as cloth electrodes The schematic also shows two 10 resistors to set the midscale reference voltage If there is already a reference voltage available it can be driven into the REFIN input to eliminate these two 10 MO resistors EXERCISE APPLICATION HEART RATE MEASURED AT THE HANDS In this application the heart rate signal is measured at the hands with stainless steel electrodes The user s arm and upper body movement create large motion artifacts and the long lead length makes the system susceptible to common mode inter ference A ve
28. ed to decouple the chip power supplies Place a 0 1 uF capacitor close to the supply pin 1 uF capacitor can be used farther away from the part In most cases the capacitor can be shared by other integrated circuits Keep in mind that excessive decoupling capacitance increases power dissipation during power cycling INPUT REFERRED OFFSETS Because of its internal architecture the instrumentation amplifier should be used always with the DC blocking amplifier shown as HPA in Figure 45 As described in the Theory of Operation section the dc blocking amplifier attenuates the input referred offsets present at the inputs of the instrumentation amplifier However this is true only when the dc blocking amplifier is used as an integrator In this configuration the input offsets from the dc blocking amplifier dominate appear directly at the output of the instrumentation amplifier If the dc blocking amplifier is used as a follower instead of its intended function as an integrator the input referred offsets of the in amp are amplified by a factor of 100 LAYOUT RECOMMENDATIONS It is important to follow good layout practices to optimize system performance In low power applications most resistors are ofa high value to minimize additional supply current The challenge of using high value resistors is that high impedance nodes become even more susceptible to noise pickup and board parasitics such as capacitance and surface leakages Keep all
29. ents on the printed circuit board PCB Two Pole High Pass Filter A two pole architecture can be implemented by adding a simple ac coupling RC at the output of the instrumentation amplifier as shown in Figure 55 TO NEXT STAGE HPDRIVE R2 e L REFOUT 10866 053 Figure 55 Schematic for a Two Pole High Pass Filter Note that the right side of C2 connects to the SW terminal Just like S1 S2 reduces the recovery time for this ac coupling network by placing 10 in parallel with R2 See the Fast Restore Circuit section for additional details on switch timing and trigger conditions Keep in mind that if this passive network is not buffered it exhibits higher output impedance at the input of a subsequent low pass filter such as with Sallen Key filter topologies Careful component selection can yield good results without a buffer See the Low Pass Filtering and Gain section for additional information on component selection Rev A Page 21 of 28 AD8232 Additional High Pass Filtering Options In addition to the topologies explained in the previous sections an additional pole may be added to the dc blocking circuit for additional rejection of low frequency signals This configuration is shown in Figure 56 TO NEXT C1 R1 R2 STAGE HPDRIVE c2 10866 155 REFOUT Figure 56 Schematic for an Alternative Two Pole High Pass Filter An extra benefit of this circuit topology is that it allows lower
30. h a cutoff frequency of 37 Hz The total signal gain in the pass band is 400 The fully conditioned signal is sampled by the sigma delta ADC integrated on the low power microcontroller ADuCM360 The wide dynamic range of this ADC provides flexibility to reduce the signal gain to avoid saturation depending on electrode placement Because the pass band is relatively wide for ambulatory applica tions the ADXL346 accelerometer signal can be used to further minimize the noise introduced by the motion of the patient Moreover the microcontroller can use the motion information to monitor inactivity and to issue a system shutdown to save battery power The low dropout regulator ensures that the maximum of 3 V is not exceeded especially during charge cycles of the battery which can be a lithium ion cell In this application the ADuCM360 uses its Port 0 to perform DMA transfers to the host communication interface or to an on board memory if recording the waveform for later transfer However in any particular application this port should be used for the busiest interface to minimize CPU cycles and maintain low power operation Note that this circuit is shown to demonstrate the capabilities of AD8232 and other system components It is not a complete system design and additional effort must be made to ensure compliance with medical safety guidelines from regulatory agencies Rev A Page 25 of 28 AD8232 Vs A
31. lues for Q are 0 5 to avoid peaking or 0 7 for maximum flatness and sharp cut off A high value of Q can be used in narrow band applications to increase peaking and the selectivity of the band pass filter common design procedure is to set RI R2 Rand C1 C2 C which simplifies the expressions for cutoff frequency and Q to 1 3 Gain Note that can be controlled by setting the gain with R3 and R4 however this limits the gain to be less than 3 For gain values equal to or greater than 3 the circuit becomes unstable A simple modification that allows higher gains is to make the value of C2 at least four times larger than C1 It is important to note that these design equations only hold true in the case that the output impedance of the previous stage is much lower than the input impedance of the Sallen Key filter This is not the case when using an ac coupling network between AD8232 the instrumentation amplifier output and the input of the low pass filter without a buffer To connect these two filtering stages properly without a buffer make the value of R1 at least ten times larger than the resistor of the ac coupling network labeled as R2 in Figure 55 DRIVING ANALOG TO DIGITAL CONVERTERS The ability of AD8232 to drive capacitive loads makes it ideal to drive an ADC without the need for an additional buffer However depending on the input architecture of the ADC a simple low pass RC net
32. nce amplifiers This further prevents saturation of the amplifier in the presence of large common mode signals such as line interference The charge pump runs from an internal oscillator the frequency of which is set around 500 kHz OPERATIONAL AMPLIFIER This general purpose operational amplifier A1 is a rail to rail device that can be used for low pass filtering and to add additional gain The following sections provide details and example circuits that use this amplifier Rev A Page 16 of 28 RIGHT LEG DRIVE AMPLIFIER The right leg drive RLD amplifier inverts the common mode signal that is present at the instrumentation amplifier inputs When the right leg drive output current is injected into the subject it counteracts common mode voltage variations thus improving the common mode rejection of the system The common mode signal that is present across the inputs of the instrumentation amplifier is derived from the transconduct ance amplifier GM1 It is then connected to the inverting input of A2 through 150 resistor An integrator can be built by connecting a capacitor between the RLD FB and RLD terminals A good starting point is a 1 nF capacitor which places the crossover frequency at about 1 kHz the frequency at which the amplifier has an inverting unity gain This configuration results in about 26 dB of loop gain available at a frequency range from 50 Hz to 60 Hz for common mode line rejection Higher capacit
33. never exceeds 10 uA Calculate the value of this resistor to be equal to the supply voltage across the AD8232 divided by 10 pA Rev A Page 19 of 28 AD8232 RADIO FREQUENCY INTERFERENCE RFI Radio frequency RF rectification is often a problem in applications where there are large RF signals The problem appears as a dc offset voltage at the output The AD8232 has a 15 pF gate capacitance and 10 resistors at each input This forms a low pass filter on each input that reduces rectification at high frequency see Figure 53 without the addition of external elements 10866 151 Figure 52 RFI Filter Without External Capacitors For increased filtering additional resistors can be added in series with each input They must be placed as close as possible to the instrumentation amplifier inputs These can be the same resistors used for overload and patient protection POWER SUPPLY REGULATION AND BYPASSING The AD8232 is designed to be powered directly from a single 3 V battery such as CR2032 type It can also operate from rechargeable lithium ion batteries but the designer must take into account that the voltage during a charge cycle may exceed the absolute maximum ratings of the AD8232 To avoid damage to the part use a power switch or a low power low dropout regulator such as ADP150 In addition excessive noise on the supply pins can adversely affect performance As in all linear circuits bypass capacitors must be us
34. ng motion artifacts and the electrode half cell potential This filter is tightly coupled with the instrumentation architec ture of the amplifier to allow both large gain and high pass filtering in a single stage thereby saving space and cost An uncommitted operational amplifier enables the AD8232 to create a three pole low pass filter to remove additional noise The user can select the frequency cutoff of all filters to suit different types of applications Rev A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rightsofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners AD8232 FUNCTIONAL BLOCK DIAGRAM AC DC 44 AD8232 SDN LEADS OFF DETECTION S2 1 10866 001 To improve common mode rejection of the line frequencies in the system and other undesired interferences the AD8232 includes an amplifier for driven lead applications such as right leg drive RLD The AD8232 includes a fast restore function that reduces the duration of otherwise long settling tails of the high pass filters After an abrupt signal change th
35. nstrumentation Amplifier Positive Input IN is typically connected to the left arm LA electrode 3 IN Instrumentation Amplifier Negative Input IN is typically connected to the right arm RA electrode 4 RLDFB Right Leg Drive Feedback Input RLDFB is the feedback terminal for the right leg drive circuit 5 RLD Right Leg Drive Output Connect the driven electrode typically right leg to the RLD pin 6 SW Fast Restore Switch Terminal Connect this terminal to the output of the second high pass filter 7 OPAMP Operational Amplifier Noninverting Input 8 REFOUT Reference Buffer Output The instrumentation amplifier output is referenced to this potential Use REFOUT as a virtual ground for any point in the circuit that needs a signal reference 9 OPAMP Operational Amplifier Inverting Input 10 OUT Operational Amplifier Output The fully conditioned heart rate signal is present at this output OUT can be connected to the input of an ADC 11 LOD Leads Off Comparator Output In dc leads off detection mode LOD is high when the electrode to IN is disconnected and it is low when connected In ac leads off detection mode LOD is always low 12 LOD Leads Off Comparator Output In dc leads off detection mode LOD is high when the IN electrode is disconnected and it is low when connected In ac leads off detection mode LOD is high when either the IN or IN electrode is disconnected and it is low when both electrodes are connected 13
36. nt Count Low Frequency Rejection Figure 53 1 2 Good Figure 55 2 4 Better Figure 56 2 5 Better Figure 57 3 7 Best Large Low Low Large Medium Higher Smaller Medium Low Smaller Highest Higher For equivalent corner frequency location Output impedance refers to the drive capability of the high pass filter before the low pass filter Low output impedance is desirable to allow flexibility in the selection of values for a low pass filter as explained in the Low Pass Filtering and Gain section Rev A Page 22 of 28 LOW PASS FILTERING AND GAIN The AD8232 includes an uncommitted op amp that can be used for extra gain and filtering For applications that do not require a high order filter a simple RC low pass filter should suffice and the op amp can buffer or further amplify the signal FROM IN AMP STAGE FILTERED SIGNAL 10866 158 Figure 59 Schematic for a Single Pole Low Pass Filter and Additional Gain Applications that require a steeper roll off or a sharper cut off a Sallen Key filter topology can be implemented as shown in Figure 60 c1 FROM IN AMP STAGE R1 FILTERED SIGNAL 10866 159 Figure 60 Schematic for a Two Pole Low Pass Filter The following equations describe the low pass cut off frequency gain and Q fc 1 2 1 C1 R2 2 Gain 1 R3 R4 IRIx C1x R2xC2 Q R2x C2 RIXCI Gain Note that changing the gain has an effect on Q and vice versa Common va
37. or values reduce the crossover frequency thereby reducing the gain that is available for rejection and consequently increasing the line noise Lower capacitor values move the crossover frequency to higher frequencies allowing increased gain The tradeoff is that with higher gain the system can become unstable and saturate the output of the right leg amplifier Note that when using this amplifier to drive an electrode there should be a resistor in series with the output to limit the current to be always less than 10uA even in fault conditions For example if the supply used is 3 0V this resistor should be greater than to account for component and supply variations TO DRIVEN R ELECTRODE REFOUT LIMIT CURRENT TO LESS THAN 10pA 10866 146 Figure 46 Typical Configuration of Right Leg Drive Circuit In two electrode configurations RLD can be used to bias the inputs through resistors as described in the Leads Off Detection section If left unused it is recommended to configure A2 as a follower by connecting RLDFB directly to RLD REFERENCE BUFFER The AD8232 operates from a single supply To simplify the design of single supply applications the AD8232 includes a reference buffer to create a virtual ground between the supply voltage and the system ground The signals present at the out put of the instrumentation amplifier are referenced around this voltage For example if there is zero differential input
38. ow Vi 2 1 V High Vin 0 5 V Output Characteristics LOD and LOD terminals Output Voltage Low Vor 0 05 V High Von 2 95 V SYSTEM SPECIFICATIONS Quiescent Supply Current 170 230 uA 0 C to 70 C 210 Shutdown Current 40 500 nA Ta 0 C to 70 C 100 nA Supply Range 2 0 3 5 V Specified Temperature Range 0 70 C Operational Temperature Range 40 85 C 1 Offset referred to the input of the instrumentation amplifier inputs See the Input Referred Offsets section for additional information Rev Page 4 of 28 ABSOLUTE MAXIMUM RATINGS AD8232 Stresses above those listed under Absolute Maximum Ratings Table 2 Parameter Rating Supply Voltage 3 6V Output Short Circuit Current Duration Indefinite Maximum Voltage Any Terminal Vs 0 3 V Minimum Voltage Any Terminal 0 3V Storage Temperature Range 65 C to 125 C Operating Temperature Range 40 C to 85 C Maximum Junction Temperature 140 C Thermal Impedance 48 C W Osc Thermal Impedance 4 4 C W ESD Rating Human Body Model HBM 8 kV Charged Device Model FICDM 1 25 kV Machine Model MM 200V may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD C
39. r that minimizes the effect of slow moving signals such as baseline wander The cutoff frequency of the filter is given by the equation f 100 2 RC where R is in ohms and C is in farads Note that the filter cutoff is 100 times higher than is typically expected from a single pole filter Because of the feedback architecture of the instrumentation amplifier the typical filter cutoff equation is modified by the gain of 100 of the instrumentation amplifier 50 40 30 20dB PER DECADE 20 MAGNITUDE dB 0 01 0 1 1 10 100 FREQUENCY Hz 10866 153 Figure 54 Frequency Response of Single Pole DC Blocking Circuit AD8232 Just like with any high pass filter with low frequency cutoff any fast change in dc offset takes a long time to settle If such change saturates the instrumentation amplifier output the 51 switch briefly enables the 10 resistor path thus moving the cutoff frequency to _ 100 R 10 Jd ni 2z RC 10 1 For values of R greater than 100 the expression in Equation 1 can be approximated by 1 2007C This higher cutoff reduces the settling time and enables faster recovery of the ECG signal For more information see the Fast Restore Circuit section HIGH PASS FILTERING The AD8232 can implement higher order high pass filters A higher filter order yields better artifact rejection but at a cost of increased signal distortion and more passive compon
40. ry narrow band pass characteristic is required to separate the heart signal from the interferers TO DIGITAL INTERFACE SIGNAL OUTPUT Figure 64 Circuit for Heart Rate Measurement at Hands The circuit in Figure 64 uses a two pole high pass filter set at 7 Hz A two pole low pass filter at 24 Hz follows the high pass filters to eliminate any other artifacts and line noise 70 60 50 5 ul 40 a 2 E z 30 20 10 0 0 1 1 10 100 1k 10866 059 FREQUENCY Hz Figure 65 Frequency Response for HRM Circuit Taken at the Hands Rev A Page 24 of 28 10866 262 The overall narrow band nature of this filter combination distorts the ECG waveform significantly Therefore it is only suitable to determine the heart rate and not to analyze the ECG signal characteristics The low pass filter stage also includes a gain of 11 to bring the total system gain close to 1100 note that the filter roll off prevents the maximum gain from reaching this value Because the ECG signal is measured at the hands it is weaker than when measured closer to the heart The RLD circuit drives to the third electrode which can also be located at the hands to cancel common mode interference CARDIAC MONITOR CONFIGURATION This configuration is designed for monitoring the shape of the ECG waveform It assumes that the patient remains rela
41. s DIV 40 0 5 0 01 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz E Figure 34 RLD Amplifier Open Loop Gain and Phase vs Figure 37 RLD Amplifier 0 1 Hz to 10 Hz Noise Frequency 2 o E 2 2 o 200ms DIV LOAD 0 5 Figure 35 RLD Amplifier Output Voltage Swing vs Figure 38 RLD Amplifier 0 5 Hz to 40 Hz Noise Output Current 10k _ ik N gt o 2 100 10 g 0 1 1 10 100 1k 10k 100k 5 FREQUENCY Hz 8 Figure 36 RLD Amplifier Voltage Spectral Noise Density vs Frequency Rev A Page 13 of 28 AD8232 REFERENCE BUFFER PERFORMANCE CURVES OUTPUT ERROR LOAD CURRENT mA Figure 39 Reference Buffer Load Regulation 20mV DIV 1Ops DIV Figure 40 Reference Buffer Load Transient Response 100 uA Load Change 10866 040 10 000 0 1 000 0 2 100 0 2 a ul n z 5 10 0 n E 2 1 0 2 0 1 0 1 1 10 100 1k 10k 100k 3 FREQUENCY Hz Figure 41 Reference Buffer Output Impedance vs Frequency 1000 E 100 2 o o
42. tively still during the measurement and therefore motion artifacts are less of an issue TO DIGITAL INTERFACE 10866 266 SIGNAL OUTPUT Figure 66 Circuit for ECG Waveform Monitoring To obtain an ECG waveform with minimal distortion the AD8232 is configured with a 0 5 Hz two pole high pass filter followed by a two pole 40 Hz low pass filter A third electrode is driven for optimum common mode rejection 70 60 50 40 30 MAGNITUDE dB 20 10 0 01 0 1 1 10 100 1k FREQUENCY Hz 10866 061 Figure 67 Frequency Response of Cardiac Monitor Circuit AD8232 In addition to 40 Hz filtering the op amp stage is configured for a gain of 11 resulting in a total system gain of 1100 To optimize the dynamic range of the system the gain level is adjustable depending on the input signal amplitude which may vary with electrode placement and ADC input range PORTABLE CARDIAC MONITOR WITH ELIMINA TION OF MOTION ARTIFACTS The circuit in Figure 68 shows an implementation ofa battery powered embedded system for monitoring heart rate in applications where the patient engages in moderate activity such as with a Holter monitor The AD8232 uses a three electrode patient interface and implements a two pole high pass filter with a cutoff at 0 3 Hz and a two pole low pass filter wit
43. trumentation amplifier as shown in Figure 57 The SW terminal is connected to the ac coupling network to obtain the best settling time response when fast restore engages TO NEXT c1 R1 R2 STAGE HPDRIVE 10866 156 L REFOUT Figure 57 Schematic for a Three Pole High Pass Filter 60 40 40dB PER DECADE 20dB PER 60dB PER 20 DECADE DECADE u S o E 2 lt 20 40 40dB PER DECADE THREE POLE FILTER TWO POLE FILTER 60 0 01 0 1 1 10 100 10866 157 FREQUENCY Hz Figure 58 Frequency Response of Circuits in Figure 56 and Figure 57 Careful analysis and adjustment of all of the component values in practice is recommended to optimize the filter characteristics A useful hint is to reduce the value of Rcow to increase the peaking of the active filter to overcome the additional roll off introduced by the ac coupling network Proper adjustment can yield the best pass band flatness The design of the high pass filter involves tradeoffs between signal distortion component count low frequency rejection and component sizes For example a single pole high pass filter results in the least distortion to the signal but its rejection of low frequency artifacts is the lowest Table 4 compares the recommended filtering options Capacitor Sizes Values Signal Distortion Output Impedance Filter Order Compone
44. work may be required to decouple the transients from the switched capacitor input typical of modern ADCs This RC network also acts as an additional filter that can help reduce noise and aliasing Follow the recommended guidelines from the ADC data sheet for the selection of proper R and C values AD8232 10866 261 Figure 61 Driving an ADC DRIVEN ELECTRODE A driven lead or reference electrode is often used to minimize the effects of common mode voltages induced by the power line and other interfering sources The AD8232 extracts the common mode voltage from the instrumentation amplifier inputs and makes it available through the RLD amplifier to drive an opposing signal into the patient This functionality maintains the voltage between the patient and the AD8232 at a near constant greatly improving the common mode rejection ratio As a safety measure place a resistor between the RLD pin and the electrode connected to the subject to ensure that current flow never exceeds 10 pA Calculate the value of this resistor to be equal to the supply voltage across the AD8232 divided by 10 uA The AD8232 implements an integrator formed by an internal 150 resistor and an external capacitor to drive this electrode Choice of the integrator capacitor is a tradeoff between line rejec tion capability and stability The capacitor should be small to maintain as much loop gain as possible around 50 Hz and 60 Hz which are typical line frequen
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