ANALOG DEVICES AD8421: 3 nV/√Hz Low Power Instrumentation Amplifier Datasheet
Contents
1. GAIN 10 T 50mV DIV i tusiDiV s mVIDIV E Figure 52 Small Signal Pulse Response G 10 R 600 Q C 100 pF Figure 55 Small Signal Response with Various Capacitive Loads G 1 R Infinity GAIN 100 o a 2 ul a 2 E amp z lt FREQUENCY Hz 8 Figure 53 Small Signal Pulse Response G 100 RL 600 0 CL 100 pF Figure 56 Second Harmonic Distortion vs Frequency G 1 GAIN 1000 I m 2 W fa gt E EI n z a 20mVIDIV i amp FREQUENCY Hz 8 Figure 54 Small Signal Pulse Response G 1000 R 600 O Ci 100 pF Figure 57 Third Harmonic Distortion vs Frequency G 1 Rev 0 Page 18 of 28 AMPLITUDE dBc AMPLITUDE dBc FREQUENCY Hz Figure 58 Second Harmonic Distortion vs Frequency G 1000 Ru 2 6000 0 Figure 59 Third Harmonic Distortion vs Frequency G 1000 1 100 1k 10k FREQUENCY Hz 10123 075 10123 076 AMPLITUDE dBc Rev 0 Page 19 of 28 AD84212. 10 100 1k 10k 100k 1M 10M FREQUENCY Hz Figure 45 Large Signal Frequency Response 10123 045 10123 039 AD8421 5VIDIV 720ns TO 0 01 1 3 8ys TI 1 12us TO 0 001 5 7645 T 0 002 DIV F0 002 DIV 1us DIV 8 E Figure 46 Large Signal Pulse Response and Settling Time G 1 Figure 49 Large Signal Pulse Response and Settling Time G 1000 10 V Step Vs 15 V Ri 2 KQ C 100 pF 10 V Step Vs 15V Ri 2 KO Ci 100 pF 2500 2000 T w 1500 _ 420ns TO 0 01 E 604ns TO 0 001 o z E 1000 SETTLED TO 0 001 0 002 DIV a SETTLED TO 0 01 500 E GAIN 1 0 10123 054 STEP SIZE V Figure 47 Large Signal Pulse Response and Settling Time G 10 Figure 50 Settling Time vs Step Size G 1 R 2 kQ C 100 pF 10 V Step Vs 15 V Ri 2kQ C 100 pF 5VIDIV Figure 48 Large Signal Pulse Response and Settling Time G 100 Figure 51 Small Signal Pulse Response G 1 R 600 Q Ci 100 pF 10 V Step Vs 15 V R 2kQ C 100 pF 50mV DIV 1us DIV 10123 043 10123 046 Rev 0 Page 17 of 28 AD8421
3. 160 GAIN 1000 140 GAIN 100 120 GAIN 10 100 GAIN 2 1 80 60 40 20 0 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 19 Positive PSRR vs Frequency 160 GAIN 1000 140 GAIN 100 420 GAIN 10 GAIN 1 100 80 60 40 20 0 0 1 1 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 20 Negative PSRR vs Frequency FREQUENCY Hz Figure 21 Gain vs Frequency 10123 018 10123 019 10123 020 CHANGE IN INPUT OFFSET VOLTAGE uV 160 GAIN 1000 120 m 2 amp 100 z o 80 60 40 0 1 5 FREQUENCY Hz 8 Figure 22 CMRR vs Frequency 160 GAIN 1000 140 GAIN 100 120 m GAIN 10 m 2 t 100 4 i g GAIN 1 o 80 60 40 0 1 1 10 100 1k 10k 100k 10123 022 FREGUENCY Hz Figure 23 CMRR vs Frequency 1 kO Source Imbalance 2 0 1 5 1 0 0 5 0 5 10 15 20 25 30 35 40 45 50 WARM UP TIME Seconds Figure 24 Change in Input Offset Voltage Vos vs Warm Up Time BIAS CURRENT nA GAIN ERROR V V CMRR uV V 10123 023 Rev 0 Page 13 of 28 AD8421
4. FREQUENCY Hz Figure 60 THD vs Frequency 10123 077 AD8421 THEORY OF OPERATION lg COMPENSATION INO ESD AND OVERVOLTAGE PROTECTION Vs GAIN STAGE O OUTPUT ESD AND OVERVOLTAGE O REF PROTECTION DIFFERENCE AMPLIFIER STAGE 10123 057 Figure 61 Simplified Schematic ARCHITECTURE The AD8421 is based on the classic 3 op amp topology This topology has two stages a preamplifier to provide differential amplification followed by a difference amplifier that removes the common mode voltage Figure 61 shows a simplified schematic of the AD8421 Topologically Q1 A1 R1 and Q2 A2 R2 can be viewed as precision current feedback amplifiers Input Transistors Q1 and Q2 are biased at a fixed current so that any input signal forces the output voltages of A1 and A2 to change accordingly The differential signal applied to the inputs is replicated across the Ra pins Any current through Re also flows through RI and R2 creating a gained differential voltage between Node 1 and Node 2 The amplified differential and common mode signals are applied to a difference amplifier that rejects the common mode voltage but preserves the amplified differential voltage The difference amplifier employs innovations that result in very low output errors such as offset voltage and drift distortion at various loads as well as output noise Laser trimmed resistors allow for a highly accurate in amp with gain error
5. 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE Vg Figure 32 Input Voltage Limit vs Supply Voltage 105 C 125C SUPPLY VOLTAGE tVs Figure 33 Output Voltage Swing vs Supply Voltage R 10 kQ 10123 029 10123 030 10123 031 AD8421 Vs 0 5 1 0 zh 1 5 9 20 E o gt 40 C Eg 75 425C E o5 85 C E 20 105 C ul 5O 25 125 C Z ar a Q z 5u 20 o otc z E 15 uw W 14 0 0 5 R 10kQ Ns g 2 0 2 4 6 8 10 12 14 16 18 20 8 10 8 6 4 2 0 2 4 6 8 10 SUPPLY VOLTAGE Vs 8 OUTPUT VOLTAGE V B Figure 34 Output Voltage Swing vs Supply Voltage R 600 Q Figure 37 Gain Nonlinearity G 1 R 10 kQ 2 kQ E Z E z amp a 40 C u 25 C E 85 C E a 105 C u Q 125 C 2 2 E 2 o 100 1k 10k 100k 8 LOAD 0 5 OUTPUT VOLTAGE V 5 Figure 35 Output Voltage Swing vs Load Resistance Figure 38 Gain Nonlinearity G 1 R 2 600 Q 100 GAIN 1000 80 i so 60 SE 25 4 gt amp n gt d 20 we R 600Q lt 5 E o ao 105 C ui go 125 C 20 Bg EE zZz 40 Eo oH m 60 r4
6. 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 25 Input Bias Current vs Temperature 100 REPRESENTATIVE SAMPLES 80 H GAIN 7 1 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 26 Gain vs Temperature G 1 REPRESENTATIVE SAMPLES GAIN 1 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 27 CMRR vs Temperature G 1 10123 024 10123 025 10123 074 AD8421 SUPPLY CURRENT mA SHORT CIRCUIT CURRENT mA SLEW RATE Vius 0 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 28 Supply Current vs Temperature G 1 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 29 Short Circuit Current vs Temperature G 1 TEMPERATURE C Figure 30 Slew Rate vs Temperature Vs 15 V G 1 10123 026 10123 027 OUTPUT VOLTAGE V REFERRED TO SUPPLY VOLTAGES 10123 028 Rev 0 Page 14 of 28 SLEW RATE Vlus INPUT VOLTAGE V REFERRED TO SUPPLY VOLTAGES 25 SR 40 25 10 5 20 35 50 65 80 95 110 125 TEMPERATURE C Figure 31 Slew Rate vs Temperature Vs 5 V G 1 25 C 85 C 105 C 125C
7. Vs 10123 067 CHIP FERRITE BEAD Figure 68 RFI Suppression The choice of resistor and capacitor values depends on the desired trade off between noise input impedance at high frequencies CMRR signal bandwidth and RFI immunity An RC network limits both the differential and common mode bandwidth as shown in the following equations 1 FilterFrequenc quent pie A RC C 1 FilterFrequency cy Mi T C where Cp 10 Cc C affects the differential signal and Cc affects the common mode signal A mismatch between R x Cc at the positive input and R x Cc at the negative input degrades the CMRR of the AD8421 By using a value of Cp that is one order of magnitude larger than Cc the effect of the mismatch is reduced and CMRR performance is improved near the cutoff frequencies AD8421 To achieve low noise and sufficient RFI filtering the use of chip ferrite beads is recommended Ferrite beads increase their impe dance with frequency thus leaving the signal of interest unaffected while preventing RF interference to reach the amplifier They also help to eliminate the need for large resistor values in the filter thus minimizing the systems input referred noise The selection of the appropriate ferrite bead and capacitor values is a function of the interference frequency input lead length and RF power For best results place the RFI filter network as close as possible to the amplifier Layout i
8. 80 100 a 0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 0 09 0 10 10 8 6 4 2 0 2 4 6 8 105 OUTPUT CURRENT A 5 OUTPUT VOLTAGE V E Figure 36 Output Voltage Swing vs Output Current Figure 39 Gain Nonlinearity G 1000 Ri 600 0 Vour 10 V Rev 0 Page 15 of 28 AD8421 NONLINEARITY ppm VOLTAGE NOISE SPECTRAL DENSITY nV VHz GAIN 1000 OUTPUT VOLTAGE V Figure 40 Gain Nonlinearity G 1000 Ri 600 0 Vour 5 V 1k 100 GAIN 1 10 GAIN 10 GAIN 100 GAIN 1000 i 1 10 100 1k 10k 100k FREQUENCY Hz Figure 41 RTI Voltage Noise Spectral Density vs Frequency 40nV DIV 10123 038 Figure 42 0 1 Hz to 10 Hz RTI Voltage Noise G 1 G 1000 CURRENT NOISE fA VHz 10123 073 10123 037 Rev 0 Page 16 of 28 OUTPUT VOLTAGE V p p 10k x e 10 0 1 1 10 100 1k 10k 100k FREQUENCY Hz Figure 43 Current Noise Spectral Density vs Frequency 1s DIV 10123 040 Figure 44 0 1 Hz to 10 Hz Current Noise
9. 2 2 uV p p G 10 0 5 0 5 uV p p G 100 to 1000 0 07 0 07 0 09 uV p p Current Noise Spectral Density f 1 kHz 200 200 fA VHz Peak to Peak RTI f 0 1 Hz to 10 Hz 18 18 pA p p VOLTAGE OFFSET Input Offset Voltage Vos Vs 5Vto 15V 60 25 uV Over Temperature Ta 40 C to 85 C 86 45 uV Average TC 0 4 0 2 yv C Output Offset Voltage Voso 350 250 uV Over Temperature Ta 40 C to 85 C 0 66 0 45 mV Average TC 6 5 uV C Offset RTI vs Supply PSR Vs 2 V to 18 V G 1 90 120 100 120 dB G 10 110 120 120 140 dB G 100 124 130 140 150 dB G 1000 130 140 140 150 dB INPUT CURRENT Input Bias Current 1 2 0 1 0 5 nA Over Temperature Ta 40 C to 85 C 8 6 nA Average TC 50 50 pA C Input Offset Current 0 5 2 0 1 0 5 nA Over Temperature Ta 40 C to 85 C 2 2 0 8 nA Average TC 1 1 pA C Rev 0 Page 3 of 28 AD8421 Test Conditions AR Grade BR Grade Parameter Comments Min Typ Max Min Typ Max Unit DYNAMIC RESPONSE Small Signal Bandwidth 3 dB G 1 10 10 MHz G 10 10 10 MHz G 100 2 2 MHz G 1000 0 2 0 2 MHz Settling Time to 0 01 10V step G 1 0 7 0 7 Us G 10 0 4 0 4 ys G 100 0 6 0 6 Us G 1000 5 5 us Settling Time to 0 001 10V step G 1 1 1 us G 10 0 6 0 6 us G 100 0 8 0 8 us G 1000 6 6 us Slew Rate G 1 to 100 35 35 V us GAIN G 14 9 9 kO Re Gain Range 1 10 000 1 10 000 V V Gain Error Vout 10 V G 1 0 02 0 01 G 10 to 1000 0 2 0 1 Gain Nonlinearity Vou
10. 8 Lead SOIC_N standard grade 13 Tape and Reel R 8 AD8421BRZ 40 C to 85 C 8 Lead SOIC_N high performance grade R 8 AD8421BRZ R7 40 C to 85 C 8 Lead SOIC_N high performance grade 7 Tape and Reel R 8 AD8421BRZ RL 40 C to 85 C 8 Lead SOIC_N high performance grade 13 Tape and Reel R 8 AD8421ARMZ 40 C to 85 C 8 Lead MSOP standard grade RM 8 Y49 AD8421ARMZ R7 40 C to 85 C 8 Lead MSOP standard grade 7 Tape and Reel RM 8 Y49 AD8421ARMZ RL 40 C to 85 C 8 Lead MSOP standard grade 13 Tape and Reel RM 8 Y49 AD8421BRMZ 40 C to 85 C 8 Lead MSOP high performance grade RM 8 Y4A AD8421BRMZ R7 40 C to 85 C 8 Lead MSOP high performance grade 7 Tape and Reel RM 8 Y4A AD8421BRMZ RL 40 C to 85 C 8 Lead MSOP high performance grade 13 Tape and Reel RM 8 Y4A 1 Z RoHS Compliant Part Rev 0 Page 27 of 28 AD8421 NOTES 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D10123 0 5 12 0 DEVICES www analo g com Rev 0 Page 28 of 28
11. Rc Power Dissipation The AD8421 duplicates the differential voltage across its inputs onto the Rc resistor Choose an Re resistor size that is sufficient to handle the expected power dissipation at ambient temperature Rev 0 Page 20 of 28 REFERENCE TERMINAL The output voltage of the AD8421 is developed with respect to the potential on the reference terminal This can be used to sense the ground at the load thereby taking advantage of the CMRR to reject ground noise or to introduce a precise offset to the signal at the output For example a voltage source can be tied to the REF pin to level shift the output allowing the AD8421 to drive a single supply ADC The REF pin is protected with ESD diodes and should not exceed either Vs or Vs by more than 0 3 V For best performance maintain a source impedance to the REF terminal that is below 1 O As shown in Figure 61 the reference terminal REF is at one end ofa 10 kQ resistor Additional impedance at the REF terminal adds to this 10 kQ resistor and results in amplification of the signal connected to the positive input The amplification from the additional Rrer can be calculated as follows 2 10 kO Rrzr 20 kO Razr Only the positive signal path is amplified the negative path is unaffected This uneven amplification degrades CMRR INCORRECT CORRECT AD8421 AD8421 REE v REF V i ae V e Figure 62 Driving the Reference Pin INPUT VOLTAGE RANGE The 3 op amp arch
12. voltages from 35 V to 32 V The remaining AD8421 terminals should be kept within the supplies All terminals of the AD8421 are protected against ESD Input Voltages Beyond the Maximum Ratings For applications where the AD8421 encounters voltages beyond the limits in the Absolute Maximum Ratings table external protection is required This external protection depends on the duration of the overvoltage event and the noise performance that is required For short lived events transient protectors such as metal oxide varistors MOVs may be all that is required Vs Vs RPROTECT PN i I Vine Vini i AD8421 m AD8421 RPROTECT i Vin Vin vs TRANSIENT PROTECTION SIMPLE CONTINUOUS PROTECTION V Hs V RPROTECT gt RPROTECT x O l x Vine Vine Vv LOW NOISE CONTINUOUS OPTION 1 OPTION 2 LOW NOISE CONTINUOUS 10123 063 Figure 67 Input Protection Options for Input Voltages Beyond Absolute Maximum Ratings For longer events use resistors in series with the inputs combined with diodes To avoid degrading bias current performance low leakage diodes such as the BAV199 or FJH1100 are recommended The diodes prevent the voltage at the input of the amplifier from exceeding the maximum ratings and the resistors limit the current into the diodes Because most external diodes can easily handle 100 mA or more resistor values do not need to be large and therefore have a minimal impact on noise performan
13. ANALOG DEVICES 3 nV Hz Low Power Instrumentation Amplifier AD8421 FEATURES Low power 2 3 mA maximum supply current Low noise 3 2 nV 4Hz maximum input voltage noise at 1 kHz 200 fA VHz current noise at 1 kHz Excellent ac specifications 10 MHz bandwidth G 1 2 MHz bandwidth G 100 0 6 ps settling time to 0 001 G 10 80 dB CMRRat 20 kHz G 1 35 V us slew rate High precision dc performance AD8421BRZ 94 dB CMRR minimum G 1 0 2 pV C maximum input offset voltage drift 1 ppm C maximum gain drift G 1 500 pA maximum input bias current Inputs protected to 40 V from opposite supply 2 5 V to 18 V dual supply 5 V to 36 V single supply Gain set with a single resistor G 1 to 10 000 APPLICATIONS Medical instrumentation Precision data acquisition Microphone preamplification Vibration analysis Multiplexed input applications ADC driver GENERAL DESCRIPTION The AD8421 is a low cost low power extremely low noise ultralow bias current high speed instrumentation amplifier that is ideally suited for a broad spectrum of signal conditioning and data acquisition applications This product features extremely high CMRR allowing it to extract low level signals in the presence of high frequency common mode noise over a wide temperature range The 10 MHz bandwidth 35 V us slew rate and 0 6 us settling time to 0 001 G 10 allow the AD8421 to amplify high speed signals and excel in applications that requir
14. Figure 72 Typical Spectrum of the AD8421 G 10 Driving the AD7685 Rev 0 Page 26 of 28 AD8421 OUTLINE DIMENSIONS 5 00 0 1968 4 80 0 1890 4 00 0 1574 6 20 0 2441 3 80 0 1497 5 80 0 2284 0 50 0 0196 ye B 1 75 0 0688 lt 0 25 0 0099 0 25 0 0098 1 35 0 0532 o 0 10 0 0040 Y EYY COPLANARITY 4 0 51 0 0201 gt ke 0 10 X JA Tes v 009a 1 27 0 0500 SEATING 0 29 0 0098 5 40 0 0157 PLANE 0 17 0 0067 COMPLIANT TO JEDEC STANDARDS MS 012 AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 73 8 Lead Standard Small Outline Package SOIC_N Narrow Body R 8 Dimensions shown in millimeters and inches 012407 A PI IDENTIFIER 0 95 15 MAX 0 85 1 10 MAX e ns 075 Fy ri LA HP v t 0 80 0 15 din efil 023 oss 0 05 kiz o 0 09 dan COPLANARITY 0 10 10 07 2009 B COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 74 8 Lead Mini Small Outline Package MSOP RM 8 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8421ARZ 40 C to 85 C 8 Lead SOIC_N standard grade R 8 AD8421ARZ R7 40 C to 85 C 8 Lead SOIC_N standard grade 7 Tape and Reel R 8 AD8421ARZ RL 40 C to 85 C
15. NPUT CURRENT mA 10123 011 Rev 0 Page 11 of 28 AD8421 A 3 2 1 0 1 2 3 4 OUTPUT VOLTAGE V Figure 13 Input Common Mode Voltage vs Output Voltage Vs 2 5 Vand 5 V G 100 35 30 25 20 15 10 5 O 5 10 15 20 25 30 35 40 INPUT VOLTAGE V 25 20 15 10 5 0 5 10 15 20 25 INPUT VOLTAGE V Figure 15 Input Overvoltage Performance G 1 Vs 15 V 10123 012 lt 10123 013 10123 014 AD8421 INPUT CURRENT mA 40 35 30 25 20 15 10 5 O 5 10 15 20 25 30 35 40 INPUT VOLTAGE V POSITIVE PSRR dB 10123 015 Figure 16 Input Overvoltage Performance Vs 5 V Vs 0 V G 100 INPUT CURRENT mA BIAS CURRENT nA INPUT VOLTAGE V Figure 17 Input Overvoltage Performance Vs 15 V G 100 2 5 12 10 8 6 4 2 0 2 4 6 8 10 12 14 COMMON MODE VOLTAGE V Figure 18 Input Bias Current vs Common Mode Voltage NEGATIVE PSRR dB 10123 016 GAIN dB 10123 017 Rev 0 Page 12 of 28
16. Vs4 2 5 Vs 2 0 V Ta 85 C Vs 2 1 TVs 1 8 Ns 2 1 V5 18 V Rev 0 Page 6 of 28 AD8421 Test Conditions ARM Grade BRM Grade Parameter Comments Min Typ Max Min Typ Max Unit OUTPUT Ri 2kQ Output Swing Vs 2 5V to 18 V Vs 1 2 Vs 1 6 Vs 1 2 Vs 16 V Over Temperature Ta 40 C to 85 C Vs 1 2 Vs 1 6 Vs 1 2 4 Vs 1 6 V Short Circuit Current 65 65 mA REFERENCE INPUT Rin 20 20 ko lin Vit Vin 0V 20 24 20 24 uA Voltage Range Vs Vs Vs Vs V Reference Gain to Output 1 1 V V 0 0001 0 0001 POWER SUPPLY Operating Range Dual supply 2 5 18 2 5 18 V Single supply 5 36 5 36 V Quiescent Current 2 2 3 2 2 3 mA Over Temperature Ta 40 C to 85 C 2 6 2 6 mA TEMPERATURE RANGE For Specified Performance 40 85 40 85 C Operational 40 125 40 125 C Total voltage noise V eni en G erc See the Theory of Operation section for more information Total RTI Vos Vosi Voso G 3 These specifications do not include the tolerance of the external gain setting resistor Rc For G gt 1 add Re errors to the specifications given in this table 4 Input voltage range of the AD8421 input stage only The input range can depend on the common mode voltage differential voltage gain and reference voltage See the Input Voltage Range section for more information 5 See the Typical Performance Characteristics section fo
17. ce At the expense of some noise performance another solution is to use series resistors In the case of overvoltage current into the AD8421 inputs is internally limited Although the AD8421 inputs must be kept within the limits defined in the Absolute Maximum Ratings section the I x R drop across the protection resistor increases the maximum voltage that the system can withstand as follows For positive input signals VMAX NEW 40 V Negative Supply Im X Rerorecr For negative input signals Vus new Positive Supply 40 V Iovr X Rprrorecr Rev 0 Page 22 of 28 Overvoltage performance is shown in Figure 14 Figure 15 Figure 16 and Figure 17 The AD8421 inputs can withstand a current of 40 mA at room temperature for at least a day This time is cumulative over the life of the device If long periods of overvoltage are expected the use of an external protection method is recommended Under extreme input conditions the output of the amplifier may invert RADIO FREQUENCY INTERFERENCE RFI RF rectification is often a problem when amplifiers are used in applications that have strong RF signals The problem is intensified if long leads or PCB traces are required to connect the amplifier to the signal source The disturbance can appear as a dc offset voltage or a train of pulses High frequency signals can be filtered with a low pass filter network at the input of the instrumentation amplifier as shown in Figure 68
18. cess technology and design techniques to provide noise performance that is limited only by the sensor The AD8421 uses unique protection methods to ensure robust inputs while still maintaining very low noise This protection allows input voltages up to 40 V from the opposite supply rail without damage to the part A single resistor sets the gain from 1 to 10 000 The reference pin can be used to apply a precise offset to the output voltage The AD8421 is specified from 40 C to 85 C and has typical performance curves to 125 C It is available in 8 lead MSOP and SOIC packages One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2012 Analog Devices Inc All rights reserved AD8421 TABLE OF CONTENTS Features ose eoe LL uer 1 Applications iie tute te malin sp layan ile 1 Pin ConnectionDiagram een 1 General Description oae oo anin o lak an 1 R vision HistOEy ms iel este tats sted esses 2 Sp cifications reete tete E eese 3 AR and BR Grades enses sa e tetendit 3 ARM and BRM Grades senes 5 Absolute Maximum Ratings essent 8 Thermal Resistance seen 8 ESD Caution nenne ttettettettnttntenntnntetnn 8 Pin Configuration and FunctionDescriptions 9 Typical Performance Characteristics ssses 10 Theory of Operation ss 20 Arc
19. cessive loading from the dynamic ADC inputs reduces the noise bandwidth of the amplifier and provides overload protection for the AD7685 analog inputs The filter cutoff can be determined empirically To achieve the best ac performance keep the impe dance magnitude greater than 1 kO at the maximum input signal 250mV REF frequency and set the filter cutoff to settle to LSB in one sampling period for a full scale step For additional considerations refer to the data sheet of the ADC in use Ina gain of 10 configuration the AD8421 has approximately 8 nV VHz voltage noise RTI See the Calculating the Noise of the Input Stage section The front end gain makes the system ten times more sensitive to input signals with only a 7 5 dB reduction of SNR The high current output and load regulation of the ADR435 allow the AD7685 to be powered directly from the reference without the need to provide another analog supply rail The reference pin buffer may be any low power unity gain stable dc precision op amp with less than approximately 25 nV VHz of wideband noise such as the OP1177 Not all proper decoupling is shown in Figure 71 Take care to follow decoupling guidelines for both amplifiers and the ADR435 VDD VIO SI 3 OR 4 WIRE INTERFACE 10123 070 Figure 71 AD8421 Driving an ADC SNR 81 12dB THD 100 91dB SFDR 90 71dB AMPLITUDE dB OF FULL SCALE FREQUENCY kHz 10123 071
20. e 400 300 200 100 INPUT OFFSET VOLTAGE pV gt OUTPUT OFFSET VOLTAGE pV Figure 4 Typical Distribution of Input Offset Voltage Figure 7 Typical Distribution of Output Offset Voltage 1800 1200 1500 1000 1200 800 o Fr o Z 900 5 600 2 600 400 300 26 0 i 0 M M Rd ELE M X 20 15 10 05 0 05 10 15 20 INPUT BIAS CURRENT AA 3 INPUT OFFSET CURRENT nA Figure 5 Typical Distribution of Input Bias Current Figure 8 Typical Distribution of Input Offset Current 1600 1400 1400 1200 1200 1000 1000 2 800 p Z 5 800 2 600 600 400 400 200 200 0 2 EC LC E X i 2 10 19 20 g 120 90 60 30 0 30 60 90 120 uVN CMRR uV V Figure 6 Typical Distribution of PSRR G 1 Rev 0 Page 10 of 28 Figure 9 Typical Distribution of CMRR G 1 10123 006 10123 007 10123 008 COMMON MODE VOLTAGE V COMMON MODE VOLTAGE V COMMON MODE VOLTAGE V G 1 Vs 415V 15 10 5 0 5 10 15 OUTPUT VOLTAGE V Figure 10 Input Common Mode Voltage vs Output Voltage Vs 12Vand 15V G 1 OUTPUT VOLTAGE V Figure 11 Input Common Mode Voltage vs Output Voltage Vs 2 5 Vand 5 V G 1 OUTPUT VOLTAGE V Figure 12 Input Common Mode Voltage vs Output Voltage Vs 12 Vand 15 V G 100 COMMON MODE VOLTAGE V 10123 009 INPUT CURRENT mA 10123 010 Figure 14 Input Overvoltage Performance G 1 Vs 5 V Vs 0 I
21. e high channel count multiplexed systems Even at higher gains the current feedback architecture maintains high performance for example at G 100 the bandwidth is 2 MHz and the settling time is 0 8 us The AD8421 has excellent distortion performance making it suitable for use in demanding applications such as vibration analysis Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners PIN CONNECTION DIAGRAM TOP VIEW Not to Scale 10123 001 Figure 1 10u BEST AVAILABLE 7mA LOW NOISE IN AMP EN T 100n BEST AVAILABLE 1mA LOW POWER IN AMP 10n a AD8421 PEAL ADM2I oz ESI Rg NOISE ONLY TOTAL NOISE DENSITY AT 1kHz VIN Hz 100 1k 10k 100k 1M SOURCE RESISTANCE Rg 0 10123 078 Figure 2 Noise Density vs Source Resistance The AD8421 delivers 3 nV VHz input voltage noise and 200 fA NHz current noise with only 2 mA quiescent current making it an ideal choice for measuring low level signals For applications with high source impedance the AD8421 employs innovative pro
22. he amplifier inputs Because load currents flow from the supplies the load should be connected at the same physical location as the bypass capacitor grounds Rev 0 Page 21 of 28 AD8421 Reference Pin The output voltage of the AD8421 is developed with respect to the potential on the reference terminal Ensure that REF is tied to the appropriate local ground INPUT BIAS CURRENT RETURN PATH The input bias current of the AD8421 must have a return path to ground When using a floating source without a current return path such as a thermocouple create a current return path as shown in Figure 65 INCORRECT CORRECT TVs TVs AD8421 AD8421 REF REF V V vs Vs TRANSFORMER TRANSFORMER Vs Vs gi AD8421 AD8421 REF V Ns Vs THERMOCOUPLE THERMOCOUPLE Vs TVs Cc 4 2 1 AD8421 fuich Pass Fa RC c REF o 4 V a 3 CAPACITIVELY COUPLED CAPACITIVELY COUPLED 5 Figure 65 Creating an Input Bias Current Return Path INPUT VOLTAGES BEYOND THE SUPPLY RAILS The AD8421 has very robust inputs It typically does not need additional input protection as shown in Figure 66 Ns Vin Vv MOST APPLICATIONS 10123 062 Figure 66 Typical Application No Input Protection Required The AD8421 inputs are current limited therefore input voltages can be up to 40 V from the opposite supply rail with no input protection required at all gains For example if Vs 5 V and Vs 8 V the part can safely withstand
23. hitecture pe EORR REIS 20 REVISION HISTORY 5 12 Revision 0 Initial Version Gain Selection aneo a teg 20 Reference Terminal esasa eesi aeaa ette ia eatis 21 Input Voltage Range teeth etae anis 21 y MEL 21 Input Bias Current Return Path sss 22 Input Voltages Beyond the Supply Rails 22 Radio Frequency Interference RFI sss 23 Calculating the NoiseofthelnputStage 23 Applications Information seen 25 Differential Output Configuration sse 25 DruviriganADQ e ETERNI 26 Outline Dimensions sees 27 Ordering Gu ide ERE se ebd 27 Rev 0 Page 2 of 28 SPECIFICATIONS Vs 15 V Vre 0 V Ta 25 C G 1 Ri 2 kO unless otherwise noted AD8421 AR AND BR GRADES Table 1 Test Conditions AR Grade BR Grade Parameter Comments Min Typ Max Min Typ Max Unit COMMON MODE REJECTION RATIO CMRR CMRR DC to 60 Hz with 1 kO Ven 7 10V to 10V Source Imbalance G 1 86 94 dB G 10 106 114 dB G 100 126 134 dB G 1000 136 140 dB Over Temperature G 1 T 40 C to 85 C 80 93 dB CMRR at 20 kHz Vem 10V to 10V G 1 80 80 dB G 10 90 100 dB G 100 100 110 dB G 1000 110 120 dB NOISE Voltage Noise 1 kHz Vint Vin 0V Input Voltage Noise en 3 32 3 32 nV JHz Output Voltage Noise eno 60 60 nV 4Hz Peak to Peak RTI f 0 1 Hz to 10 Hz G 1 2 2
24. itecture of the AD8421 applies gain in the first stage before removing the common mode voltage in the difference amplifier stage Internal nodes between the first and second stages Node 1 and Node 2 in Figure 61 experience a combination of a gained signal a common mode signal and a diode drop The voltage supplies can limit the combined signal even when the individual input and output signals are not limited Figure 10 through Figure 13 show this limitation in detail LAYOUT To ensure optimum performance of the AD8421 at the PCB level care must be taken in the design of the board layout The pins of the AD8421 are arranged in a logical manner to aid in this task m zi TOP VIEW Not to Scale 10123 059 Figure 63 Pin Configuration Diagram AD8421 Common Mode Rejection Ratio over Frequency Poor layout can cause some of the common mode signals to be converted to differential signals before reaching the in amp Such conversions occur when one input path has a frequency response that is different from the other To maintain high CMRR over frequency closely match the input source impedance and capacitance of each path Place additional source resistance in the input path for example input protection resistors close to the in amp inputs to minimize the interaction of the resistance with parasitic capacitance from the PCB traces Parasitic capacitance at the gain setting pins Rc can also affect CMRR over frequency If
25. lerance of the external gain setting resistor Rc For G gt 1 add Re errors to the specifications given in this table 4 Input voltage range of the AD8421 input stage only The input range can depend on the common mode voltage differential voltage gain and reference voltage See the Input Voltage Range section for more details 5 See the Typical Performance Characteristics section for expected operation between 85 C and 125 C ARM AND BRM GRADES Table 2 Test Conditions ARM Grade BRM Grade Parameter Comments Min Typ Max Min Typ Max Unit COMMON MODE REJECTION RATIO CMRR CMRR DC to 60 Hz with 1 kO Ven 10V to 10V Source Imbalance G 1 84 92 dB G 10 104 112 dB G 100 124 132 dB G 1000 134 140 dB Over Temperature G 1 Ta 40 C to 85 C 80 90 dB CMRR at 20 kHz Vem 10V to 10V G 1 80 80 dB G 10 90 90 dB G 100 100 100 dB G 1000 100 100 dB NOISE Voltage Noise 1 kHz Vint Vn 20V Input Voltage Noise en 3 32 3 32 nV VHz Output Voltage Noise eno 60 60 nV VHz Peak to Peak RTI f 0 1 Hz to 10 Hz G 1 2 2 2 2 uV p p G 10 0 5 0 5 uV p p G 100 to 1000 0 07 0 07 0 09 uV p p Current Noise Spectral Density f 1 kHz 200 200 fA VHz Peak to Peak RTI f 0 1 Hz to 10 Hz 18 18 pA p p VOLTAGE OFFSET Input Offset Voltage Vos Vs 5Vto 15V 70 50 uV Over Temperature Ta 40 C to 85 C 135 135 uV Average TC 0 9 0 9 uV C Output Offset Voltage Voso 600 400 uV Over Temperature Ta 40 C to 85 C 1 1
26. less than 0 0196 and CMRR that exceeds 94 dB G 1 The high performance pinout and special attention given to design and layout allow for high CMRR performance across a wide frequency and temperature range Using superbeta input transistors and bias current compensation the AD8421 offers extremely high input impedance low bias cur rent low offset current low current noise and extremely low voltage noise of 3 nV VHz The current limiting and overvoltage protection scheme allow the input to go 40 V from the opposite rail at all gains without compromising the noise performance The transfer function of the AD8421 is Vour GX Vin V m Vrer where G 1 9 9kQ Rg Users can easily and accurately set the gain using a single standard resistor GAIN SELECTION Placing a resistor across the Rc terminals sets the gain of the AD8421 The gain can be calculated by referring to Table 6 or by using the following gain equation Rg 99kQ G l The AD8421 defaults to G 1 when no gain resistor is used To determine the total gain accuracy of the system add the tolerance and gain drift of the Rc resistor to the specifications of the AD8421 When the gain resistor is not used gain error and gain drift are minimal Table 6 Gains Achieved Using 1 Resistors 1 Standard Table Value of Rc Calculated Gain 10 kQ 1 99 2 49 kQ 4 98 1 1 kQ 10 00 5230 19 93 2000 50 50 1000 100 0 49 90 199 4 200 496 0 100 991 0 4 990 1985
27. mV Average TC 9 9 uV C Rev 0 Page 5 of 28 AD8421 Test Conditions ARM Grade BRM Grade Parameter Comments Min Typ Max Min Typ Max Unit Offset RTI vs Supply PSR Vs 2 5 V to 18 V G 1 90 120 100 120 dB G 10 110 120 120 140 dB G 100 124 130 140 150 dB G 1000 130 140 140 150 dB INPUT CURRENT Input Bias Current 1 2 0 1 1 nA Over Temperature Ta 40 C to 85 C 8 6 nA Average TC 50 50 pA C Input Offset Current 0 5 2 0 1 1 nA Over Temperature Ta 40 C to 85 C 3 1 5 nA Average TC 1 1 pA C DYNAMIC RESPONSE Small Signal Bandwidth 3 dB G 1 10 10 MHz G 10 10 10 MHz G 100 2 2 MHz G 1000 0 2 0 2 MHz Settling Time 0 01 10V step G 1 0 7 0 7 Us G 10 0 4 0 4 ys G 100 0 6 0 6 ys G 1000 5 5 ys Settling Time 0 00196 10V step G 1 1 1 us G 10 0 6 0 6 ys G 100 0 8 0 8 ys G 1000 6 6 ys Slew Rate G 1to 100 35 35 V us GAIN G 1 9 9 kQ Re Gain Range 1 10 000 1 10 000 V A Gain Error Vout 10V G 1 0 05 0 02 G 10to 1000 0 3 0 2 Gain Nonlinearity Vour 10 V to 10 V G 1 RL 2kO 1 1 ppm Ri 6000 1 3 1 3 ppm G 10to 1000 R 2 6000 30 50 30 50 ppm Vour 5 V to 45V 5 10 5 10 ppm Gain vs Temperature G 1 5 0 1 1 ppm C G gt 1 50 50 ppm C INPUT Input Impedance Differential 30 3 30 3 GO pF Common Mode 30 3 30 3 GO pF Input Operating Voltage Vs 25 V to 18 V Vs 2 3 TVs 1 8 Vs 23 1Vs 18 V Range Over Temperature TA 40 C Vs 2 5 Vs 2 0
28. mple if the R1 source resistance in Figure 69 is 4 kO the R2 source resistance is 1 kO and the gain of the in amp is 100 the total noise referred to input is 489 135 40 8 9 6nV VHz Rev 0 Page 24 of 28 APPLICATIONS INFORMATION DIFFERENTIAL OUTPUT CONFIGURATION Figure 70 shows an example of how to configure the AD8421 for differential output IN AD8421 OUT 10123 066 OUT Figure 70 Differential Output Configuration with Op Amp The differential output voltage is set by the following equation Vpirr our V our V ovr Gain x Vix V m The common mode output is set by the following equation Vcu ovr V our V our 2 Vsus The advantage of this circuit is that the dc differential accuracy depends on the AD8421 not on the op amp or the resistors In addition this circuit takes advantage of the precise control that the AD8421 has of its output voltage relative to the reference voltage AD8421 Although the dc performance and resistor matching of the op amp affect the dc common mode output accuracy such errors are likely to be rejected by the next device in the signal chain and therefore typically have little effect on overall system accuracy Because this circuit is susceptible to instability a capacitor is included to limit the effective op amp bandwidth This capacitor can be omitted if the amplifier pairing is stable The open loop gain and phase of any amplifier may vary wi
29. r 10 V to 10 V G 1 R22kQ 1 1 ppm Ri 26000 1 3 1 3 ppm G 10 to 1000 Ri 26000 30 50 30 50 ppm Vour 5 V to 45V 5 10 5 10 ppm Gain vs Temperature G 1 5 0 1 1 ppm C G gt 1 50 50 ppm C INPUT Input Impedance Differential 30 3 30 3 GQ pF Common Mode 30 3 30 3 GQ pF Input Operating Voltage Range Vs 2 5Vto 18V Vs 2 3 Vs 1 8 Vs 2 3 V 18 V Over Temperature Ta 40 C Vst 2 5 TVs 2 0 Vst 2 5 4 Vs 2 0 V Ta 85 C Vs 2 1 TVs 1 8 Vs 2 1 V5 18 V OUTPUT R 22kQ Output Swing Vs 2 5V to 18 V Vs 1 2 1Vs 16 Vs 1 2 1Vs 16 V Over Temperature Ta 40 C to 85 C Vs 1 2 Vs 1 6 Vs 1 2 Vs 1 6 V Short Circuit Current 65 65 mA REFERENCE INPUT Rin 20 20 ko lin Vit Vin 0V 20 24 20 24 pA Voltage Range Vs TVs Vs Vs V Reference Gain to Output 1 T VN 0 0001 0 0001 Rev 0 Page 4 of 28 AD8421 Test Conditions AR Grade BR Grade Parameter Comments Min Typ Max Min Typ Max Unit POWER SUPPLY Operating Range Dual supply t2 5 18 25 18 V Single supply 5 36 5 36 V Quiescent Current 2 2 3 2 2 3 mA Over Temperature Ta 40 C to 85 C 2 6 2 6 mA TEMPERATURE RANGE For Specified Performance 40 85 40 85 C Operational 40 125 40 125 ie Total voltage noise V eni no G erc See the Theory of Operation section for more information 2 Total RTI Vos Vos Voso G These specifications do not include the to
30. r expected operation between 85 C and 125 C Rev 0 Page 7 of 28 AD8421 ABSOLUTE MAXIMUM RATINGS Table 3 Parameter Rating Supply Voltage 18V Output Short Circuit Current Duration Indefinite Maximum Voltage at IN or IN Vs 40V Minimum Voltage at IN or IN Vs 40V Maximum Voltage at REF Vs 0 3 V Minimum Voltage at REF Vs 0 3 V Storage Temperature Range 65 C to 150 C Operating Temperature Range 40 C to 125 C Maximum Junction Temperature 150 C ESD Human Body Model 2kV Charged Device Model 1 25 kV Machine Model 0 2 kV THERMAL RESISTANCE Oya is specified for a device in free air using a 4 layer JEDEC printed circuit board PCB Table 4 Package Osa Unit 8 Lead SOIC 107 8 C W 8 Lead MSOP 138 6 C W ESD CAUTION For voltages beyond these limits use input protection resistors See the Theory of Operation section for more information There are ESD protection diodes from the reference input to each supply so REF cannot be driven beyond the supplies in the same way that IN and IN can See the Reference Terminal section for more information Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maxim
31. s critical to ensure that RF signals are not picked up on the traces after the filter If RF interference is too strong to be filtered sufficiently shielding is recommended The resistors used for the RFI filter can be the same as those used for input protection CALCULATING THE NOISE OF THE INPUT STAGE The total noise of the amplifier front end depends on much more than the 3 2 nV VHz specification of this data sheet The three main contributors to noise are the source resistance the voltage noise of the instrumentation amplifier and the current noise of the instrumentation amplifier In the following calculations noise is referred to the input RTI In other words all sources of noise are calculated as if the source appeared at the amplifier input To calculate the noise referred to the amplifier output RTO multiply the RTI noise by the gain of the instru mentation amplifier Source Resistance Noise Any sensor connected to the AD8421 has some output resistance There may also be resistance placed in series with inputs for pro tection from either overvoltage or radio frequency interference This combined resistance is labeled R1 and R2 in Figure 69 Any resistor no matter how well made has an intrinsic level of noise This noise is proportional to the square root of the resistor value At room temperature the value is approximately equal to 4 nV NHz x V resistor value in kQ SENSOR 10123 065 Figure 69 Source Re
32. sistance from Sensor and Protection Resistors For example assume that the combined sensor and protection resistance is 4 KQ on the positive input and 1 kO on the negative input Then the total noise from the input resistance is Ja Ja ax VI Je216 8 9 nV VHz Rev 0 Page 23 of 28 AD8421 Voltage Noise of the Instrumentation Amplifier The voltage noise of the instrumentation amplifier is calculated using three parameters the device output noise the input noise and the Rc resistor noise It is calculated as follows Total Voltage Noise V output Noise 1G J Input Noise Noise of Rg Resistor For example for a gain of 100 the gain resistor is 100 Q Therefore the voltage noise of the in amp is 60 100 4327 n x vo 3 5 nV NHz Current Noise of the Instrumentation Amplifier Current noise is converted to a voltage by the source resistance The effect of current noise can be calculated by multiplying the specified current noise of the in amp by the value of the source resistance For example if the RI source resistance in Figure 69 is 4 KQ and the R2 source resistance is 1 kO the total effect from the current noise is calculated as follows J axo2Y 1x02 0 8 nv Bz Total Noise Density Calculation To determine the total noise of the in amp referred to input combine the source resistance noise voltage noise and current noise contribution by the sum of squares method For exa
33. th process variation and temperature Additional phase lag can be introduced by resistive or capacitive loading To guarantee stability the value of the capacitor in Figure 70 should be determined with a sample of circuits by evaluating the small signal pulse response of the circuit with load at the extremes of the output dynamic range The ambient temperature should also be varied over the expected range to evaluate its effect on stability The voltage at OUT may still have some overshoot after the circuit is tuned because the AD8421 output amplifier responds faster than the op amp A 12 pF capacitor is a good starting point For best large signal ac performance use an op amp with a high slew rate to match the AD8421 performance of 35 V us High bandwidth is not essential because the system bandwidth is limited by the RC feedback Some good choices for op amps are the AD8610 ADA4627 1 AD8510 and the ADA4898 1 Rev 0 Page 25 of 28 AD8421 DRIVING AN ADC The Class AB output stage low noise and distortion and high bandwidth and slew rate make the AD8421 a good choice for driving an ADC in a data acquisition system that requires front end gain high CMRR and dc precision Figure 71 shows the AD8421 in a gain of 10 configuration driving the AD7685 a 16 bit 250 kSPS pseudodifferential SAR ADC The RC low pass filter that is shown between the AD8421 and the AD7685 has several purposes It isolates the amplifier output from ex
34. the board design has a component at the gain setting pins for example a switch or jumper choose a component such that the parasitic capacitance is as small as possible Power Supplies and Grounding Use a stable dc voltage to power the instrumentation amplifier Noise on the supply pins can adversely affect performance Place a 0 1 uF capacitor as close as possible to each supply pin Because the length of the bypass capacitor leads is critical at high frequency surface mount capacitors are recommended Any parasitic inductance in the bypass ground trace works against the low impedance that is created by the bypass capacitor As shown in Figure 64 a 10 uF capacitor can be used farther away from the device For these larger value capacitors which are intended to be effective at lower frequencies the current return path distance is less critical In most cases the 10 uF capacitor can be shared by other local precision integrated circuits Vs 10123 060 Figure 64 Supply Decoupling REF and Output Referred to Local Ground A ground plane layer helps to reduce parasitic inductances which minimizes voltage drops with changes in current The area of the current path is directly proportional to the magnitude of parasitic inductances and therefore the impedance of the path at high frequency Large changes in currents in an inductive decoupling path or ground return create unwanted effects due to the coupling of such changes into t
35. um rating conditions for extended periods may affect device reliability A AZN ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 8 of 28 AD8421 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TOP VIEW Not to Scale 10123 002 Figure 3 Pin Configuration Table 5 Pin Function Descriptions Pin No Mnemonic Description 1 IN Negative Input Terminal 2 3 Rc Gain Setting Terminals Place resistor across the Re pins to set the gain G 1 9 9 kO Re 4 IN Positive Input Terminal 5 Vs Negative Power Supply Terminal 6 REF Reference Voltage Terminal Drive this terminal with a low impedance voltage source to level shift the output 7 Vour Output Terminal 8 TVs Positive Power Supply Terminal Rev 0 Page 9 of 28 AD8421 TYPICAL PERFORMANCE CHARACTERISTICS Ta 25 C Vs 15 V Vre 0 V Ri 2 kO unless otherwise noted 600 500 400 p 2 Z 300 z 2 2 200 i il 0 er h 0 60 40 20 0 20 40
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