ANALOG DEVICES ADCMP608: Rail-to-Rail Fast Low Power 2.5 V to 5.5 V Single-Supply TTL/CMOS Comparator Data Sheet (Rev 0 2007-04-01-)
Contents
1. ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features A patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD A Therefore proper ESD precautions should be taken to Aio avoid performance degradation or loss of functionality Rev 0 Page 4 of 12 ADCMP608 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 06769 002 Figure 2 Pin Configuration Table 4 ADCMP608 Pin Function Descriptions Pin No Mnemonic Description 1 Q Noninverting Output Q is at logic high if the analog voltage at the noninverting input Vp is greater than the analog voltage at the inverting input Vw 2 Vee Negative Supply Voltage 3 Vp Noninverting Analog Input 4 VN Inverting Analog Input 5 Son Shutdown Drive this pin low to shut down the device 6 Voc Vcc Supply Rev 0 Page 5 of 12 ADCMP608 TYPICAL PERFORMANCE CHARACTERISTICS Vcc 22 5 V Ta 25 C unless otherwise noted 5 38 0 4 37 8 3 37 6 PROPAGATION DELAY FALL vo 2 37 4 3 1 i 37 2 T a o 37 0 a E PROPAGATION DELAY RISE 1 36 8 i 2 36 6 125 C x 3 36 4 25 C 4 8 36 2 40 c 5 32. sss 7 General Description cescecssessesssesesseesessesssessessesstesessessesseesees 1 Optimizing Performance seen 7 REVISION Hist ORY ara ice cesta teeter teste ei De 2 Comparator Propagation Delay Dispersion 7 Specifications eese res cene s ere led aie vata ead 3 Crossover Bias Point essent 8 Electrical Characteristics seen 3 Minimum Input Slew Rate Requirement sss 8 Absolute Maximum Ratings essent 4 Typical Application Circuits seen 9 Thermal Resistance uei mitt erae 4 O tline Dimensions entere EH Rete 10 ESD Cautions asinis 4 Ordering Guid ssena nei ted i etn 10 Pin Configuration and Function Descriptions 5 Typical Performance Characteristics sse 6 REVISION HISTORY NTENTS 4 07 Revision 0 Initial Version Rev 0 Page 2 of 12 ADCMP608 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Voc 2 5 V Ta 40 C to 125 C Typical values are Ta 25 C unless otherwise noted Table 1 Parameter Symbol Conditions Min Typ Max Unit DC INPUT CHARACTERISTICS Voltage Range Ve VN Vcc 2 5 V to 5 5 V 0 2 Vcc V Common Mode Range Vcc 2 5 V to 5 5 V 0 2 Vcc V Differential Voltage Vcc 2 5 V to 5 5 V Vcc V Offset Voltage Vos 5 0 3 5 0 mV Bias Current lp In 0 4 410 4 uA Offset Current 1 0 1 0 uA Capacitance Cp Cn 1 pF Resistance
3. Differential Mode 0 5 V to Vcc 0 5 V 200 7000 kQ Resistance Common Mode 0 5 V to Vcc 0 5 V 100 4000 kQ Active Gain Av 80 dB Common Mode Rejection CMRR Vcc 2 5 V Vem 0 2 V to 2 7 V 45 dB Vcc 5 5 V 45 dB SHUTDOWN PIN CHARACTERISTICS Vin Comparator is operating 2 0 Vec V Vit Shutdown guaranteed 0 2 10 4 410 4 V lin Vin Vcc 6 6 uA Sleep Time tsp lec lt 100 pA 300 ns Wake Up Time tH Vep 10 mV output valid 150 ns DC OUTPUT CHARACTERISTICS Vcc 2 5 V to 5 5 V Output Voltage High Level Von lou 0 8 mA Vcc 2 5 V Vcc 0 4 V Output Voltage Low Level Vo lo 0 8 mA Vcc 2 5 V 0 4 V AC PERFORMANCE Vcc 2 5 V to 5 5 V Rise Time Fall Time tr tF 10 to 90 Vcc 2 5 V 25 to 50 ns 10 to 90 Vcc 5 5 V 45 to 75 ns Propagation Delay ted Vop 10 mV Vcc 2 5 V 30 to 50 ns Vop 50 mV Vcc 5 5 V 35 to 60 ns Propagation Delay Skew Rising to Vec 2 5 V 4 5 ns Falling Transition Vcc 5 5 V 8 ns Overdrive Dispersion 10 mV lt Von lt 125 mV 12 ns Common Mode Dispersion 0 2 V lt Vem lt Vcc 0 2 V 1 5 ns POWER SUPPLY Supply Voltage Range Vcc 2 5 5 5 V Positive Supply Current lvcc Vec 2 5 V 550 800 pA Vcc 5 5 V 800 1300 uA Power Dissipation Po Vec 2 5 V 1 375 2 0 mW Vcc 5 5 V 4 95 7 15 mW Power Supply Rejection Ratio PSRR Vcc 2 5 V to 5 5 V 50 dB Shutdown Current Iso Vcc 2 5 V to 5 5 V 250 350 uA 1 The output will be in a high impedance mode when the device is in shutdown mode Note
4. observed with the Vcc supply at 2 5 V and larger values are observed when driving loads that switch at other levels Overdrive and input slew rate dispersions are not significantly affected by output loading and Vcc variations The TTL CMOS compatible output stage is shown in the simplified schematic diagram see Figure 9 Because of its inherent symmetry and generally good behavior this output stage is readily adaptable for driving various filters and other unusual loads Viocic O OUTPUT 06769 009 GAIN STAGE OUTPUT STAGE Figure 9 Simplified Schematic Diagram of TTL CMOS Compatible Output Stage OPTIMIZING PERFORMANCE As with any high speed comparator proper design and layout techniques are essential for obtaining the specified performance Stray capacitance inductance common power and ground impedances or other layout issues can severely limit performance and can often cause oscillation The source impedance should be minimized as much as is practicable High source impedance in combination with the parasitic input capacitance of the comparator causes an undesirable degradation in bandwidth at the input thus degrading the overall response Higher impedances encourage undesired coupling COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP608 comparator is designed to reduce propagation delay dispersion over a wide input overdrive range of 10 mV to Vcc 1 V Propagation delay dispersion is the variation in
5. propagation delay that results from a change in the degree of overdrive or slew rate how far or how fast the input signal exceeds the switching threshold Propagation delay dispersion is a specification that becomes important in high speed time critical applications such as data communication automatic test and measurement and instru mentation It is also important in event driven applications such as pulse spectroscopy nuclear instrumentation and medical imaging Dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed Figure 10 and Figure 11 ADCMP608 dispersion is typically lt 12 ns as the overdrive varies from 10 mV to 125 mV This specification applies to both positive and negative signals because the device has very closely matched delays for both positive going and negative going inputs and very low output skews Remember to add the actual device offset to the overdrive for repeatable dispersion measurements Rev 0 Page 7 of 12 ADCMP608 500mV OVERDRIVE INPUT VOLTAGE D 10mV OVERDRIVE Q OUTPUT 06769 010 INPUT VOLTAGE VN Vos 06769 011 Q OUTPUT Figure 11 Propagation Delay Slew Rate Dispersion CROSSOVER BIAS POINT Rail to rail inputs of this type in both op amps and comparators have a dual front end design Certain devices are active near the Vcc rail and others are active near the Vis rail At some predeter mined
6. 6 0 1 0 05 0 05 10 15 20 25 30 35 0 5 1 0 1 5 2 0 2 5 3 Vom AT Vcc 2 5V Vom AT Vec 2 5V Figure 3 Input Bias Current vs Input Common Mode Voltage Figure 6 Propagation Delay vs Input Common Mode Voltage Q 1 T Voc 5 5V 1 j RISE DELAY 1 7 G zs Bess E a Vcc 5 5V FALL DELAY j Vcc 2 5V 7 i E FALL DELAY j Vec 2 5V 4 E i E RISE DELAY 3 18 3 0 5V DIV 10ns DIV1 0 50 100 150 OD mV Figure 4 Propagation Delay vs Input Overdrive at Vcc 2 5 V and 5 5 V Figure 7 1 MHz Output Voltage Waveform Vcc 2 5 V 1 5 SOURCE 1 0 t SINK T E E 0 5 z W in 2 3 a 9 lt fo E 0 5 E 1V DIV 8 1 0 8 s 1 0 05 0 05 10 15 20 25 30 35 40 Vout V Figure 5 Load Current mA vs Vou Vo Figure 8 1 MHz Output Voltage Waveform Vcc 5 5 V Rev 0 Page 6 of 12 06769 006 ADCMP608 APPLICATION INFORMATION POWER GROUND LAYOUT AND BYPASSING The ADCMP608 comparator is a high speed device Despite the low noise output stage it is essential to use proper high speed design techniques to achieve the specified performance Because comparators are uncompensated amplifiers feedback in any phase relationship is likely to cause oscillations or undesired hysteresis Of critical importance is the use of low impedance supply planes particularly the output supply plane Vcc and the ground plane GND Individual supply planes are recommended as part of a multilayer board Providing the lowest inductance ret
7. ANALOG Rail to Rail Fast Low Power 2 5 V to 5 5 V DEVICES Single Supply TTL CMOS Comparator ADCMP608 FEATURES Fully specified rail to rail at Vcc 2 5 V to 5 5 V Input common mode voltage from 0 2 V to Vcc 0 2 V Low glitch CMOS TTL compatible output stage 40 ns propagation delay Low power 1 mW at 2 5 V Shutdown pin Power supply rejection gt 60 dB 40 C to 125 C operation APPLICATIONS High speed instrumentation Clock and data signal restoration Logic level shifting or translation High speed line receivers Threshold detection Peak and zero crossing detectors High speed trigger circuitry Pulse width modulators Current voltage controlled oscillators GENERAL DESCRIPTION The ADCMP608 is a fast comparator fabricated on XFCB2 an Analog Devices Inc proprietary process This comparator is exceptionally versatile and easy to use Features include an input range from Vs 0 2 V to Vcc 0 2 V low noise TTL CMOS compatible output drivers and shutdown inputs The device offers 40 ns propagation delays driving a 15 pF load with 10 mV overdrive on 500 uA typical supply current A flexible power supply scheme allows the device to operate with a single 2 5 V positive supply and a 0 2 V to 2 7 V input signal range up to a 5 5 V positive supply with a 0 2 V to 5 7 V input signal range Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no res
8. ink Small Outline Transistor Package SC70 KS 6 Dimensions shown in millimeters ORDERING GUIDE Temperature Package Model Range Package Description Option Branding ADCMP608BKSZ R2 40 C to 125 C 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 GOU ADCMP608BKSZ RL 40 C to 125 C 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 GOU ADCMP608BKSZ REEL7 40 C to 125 C 6 Lead Thin Shrink Small Outline Transistor Package SC70 KS 6 GOU 1 Z RoHS Compliant Part Rev 0 Page 10 of 12 ADCMP608 NOTES Rev 0 Page 11 of 12 ADCMP608 NOTES 2007 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D06769 0 4 07 0 DEVICES www analo g com Rev 0 Page 12 of 12
9. point in the common mode range a crossover occurs At this point normally Vcc 2 the direction of the bias current reverses and there are changes in measured offset voltages and currents The ADCMP608 slightly elaborates on this scheme Crossover points can be found at approximately 0 8 V and 1 6 V MINIMUM INPUT SLEW RATE REQUIREMENT With the rated load capacitance and normal good PC board design practice as discussed in the Optimizing Performance section these comparators should be stable at any input slew rate with no hysteresis Broadband noise from the input stage is observed in place of the violent chattering seen with most other high speed comparators With additional capacitive loading or poor bypassing oscillation may be encountered These oscilla tions are due to the high gain bandwidth of the comparator in combination with feedback through parasitics in the package and PC board In many applications chattering is not harmful Rev 0 Page 8 of 12 ADCMP608 TYPICAL APPLICATION CIRCUITS 2 5V TO 5V O 06769 012 Figure 12 Self Biased 50 Slicer CMOS O Vec 2 5V TO 5V ADCMP608 O OUTPUT 06769 013 Figure 13 LVDS to CMOS Receiver Rev 0 Page 9 of 12 ADCMP608 OUTLINE DIMENSIONS 1 35 6 5 4 2 40 125 2 10 1 15 e 2 3 1 80 PIN 4B g URBE nea 0 65 BSC 1 30 BSC 0 10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO 203 AB Figure 14 6 Lead Thin Shr
10. ponsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM NONINVERTING 69 INPUT ADCMP608 O Q OUTPUT INVERTING INPUT 06769 001 Figure 1 The TTL CMOS compatible output stage is designed to drive up to 15 pF with full rated timing specifications and to degrade in a graceful and linear fashion as additional capacitance is added The input stage of the comparator offers robust protec tion against large input overdrive and the outputs do not phase reverse when the valid input signal range is exceeded The ADCMP608 is available in a tiny 6 lead SC70 package with a single ended output and a shutdown pin One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2007 Analog Devices Inc All rights reserved ADCMP608 TABLE OF CO iun P 1 Application Information eeeeeennteentnteentnnns 7 Applications ito en e e HR UR RED 1 Power Ground Layout and Bypassing sees 7 Functional Block Diagram eere 1 TTL CMOS Compatible Output Stage
11. that this feature should be used with care since the enable disable time is much longer than with a true tristate output 2 Vn 100 mV square input at 1 MHz Vem O V CL 15 pF Vca 2 5 V unless otherwise noted Rev 0 Page 3 of 12 ADCMP608 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Supply Voltages Supply Voltage 0 5 V to 6 0 V Vcc to GND Supply Differential 6 0V to 6 0V Input Voltages Input Voltage 0 5 V to Vcc 0 5 V Differential Input Voltage Vcc 0 5 V Maximum Input Output Current 50 mA Shutdown Control Pin Applied Voltage So to GND 0 5 V to Vcc 0 5 V Maximum Input Output Current 50 mA Output Current 50 mA Temperature Operating Temperature Ambient 40 C to 125 C Operating Temperature Junction 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE Oya is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 3 Thermal Resistance Package Type Osa Unit ADCMP608 6 Lead SC70 426 C W 1 Measurement in still air ESD CAUTION
12. urn path for switching currents ensures the best possible performance in the target application It is also important to adequately bypass the input and output supplies A 0 1 uF bypass capacitor should be placed as close as possible to the Vcc supply pin The capacitor should be connected to the GND plane with redundant vias placed to provide a physically short return path for output currents flowing back from ground to the Vcc pin High frequency bypass capacitors should be carefully selected for minimum inductance and ESR Parasitic layout inductance should also be strictly controlled to maximize the effectiveness of the bypass at high frequencies TTL CMOS COMPATIBLE OUTPUT STAGE Specified propagation delay performance can be achieved only by keeping the capacitive load at or below the specified minimums The output of the ADCMP608 is designed to directly drive one Schottky TTL or three low power Schottky TTL loads or the equivalent For large fan outs buses or transmission lines use an appropriate buffer to maintain the excellent speed and stability of the comparator With the rated 15 pF load capacitance applied more than half of the total device propagation delay is output stage slew time Because of this the total propagation delay decreases as Vcc decreases and instability in the power supply may appear as excess delay dispersion Delay is measured to the 50 point for whatever supply is in use thus the fastest times are
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ANALOG DEVICES ADCMP608: Rail to Rail Fast Low Power 2.5 V to 5.5 V Single Supply TTL/CMOS Comparato