ANALOG DEVICES ADCMP565 handbook
Contents
1. TIME ns 02820 0 018 Figure 20 Rise and Fall of Outputs vs Time PROPAGATION DELAY ps PROPOGATION DELAY ERROR ps Rev 0 Page 13 of 16 ADCMP565 2 0 1 2 3 INPUT COMMON MODE VOLTAGE V 02820 0 015 Figure 21 Propagation Delay vs Common Mode Voltage 0 15 2 15 4 15 6 15 8 15 PULSEWIDTH ns 02820 0 023 Figure 22 Propagation Delay Error vs Pulsewidth ADCMP565 OUTLINE DIMENSIONS 0 048 1 21 FT 0 180 4 57 0 048 1 21 0 165 4 19 0 042 1 07 0 056 1 42 poai 0 20 0 51 0 020 0 50 a 0 042 1 07 pes TAA A pee P 0 021 0 53 j H T 0 013 0 33 0 042 1 07 Ht Cen 0 330 8 38 ORA PFBSc 0 032 0 81 0 290 7 37 _ aan BAL T p 0 026 0 66 _ 0 020 CA r 0504 0356 04 gt I 0 025 0 64 MIN 0 350 8 89 S 0 120 3 04 0 395 10 02 0 090 2 29 0 385 9 78 COMPLIANT TO JEDEC STANDARDS MO 047AA CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 23 20 Lead Plastic Leaded Chip Carrier PLCC P 20 Dimensions shown in inches and millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADCMP565BP 40 C to 85 C 20 Lead PLCC P 20 Rev 0 Page 14 of 16 ADCMP565 Notes Rev 0 Page 15 of 162. 40 20 0 20 40 60 80 TEMPERATURE C 02820 0 022 Figure 13 Input Offset Voltage vs Temperature 210 205 200 195 190 185 180 175 170 165 160 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C 02820 0 016 Figure 14 Rise Time vs Temperature Rev 0 Page 12 of 16 HYSTERESIS mV INPUT BIAS CURRENT pA TIME ps 25 0 24 5 24 0 23 5 23 0 22 5 40 20 0 20 40 60 80 TEMPERATURE C 02820 0 021 Figure 15 Input Bias Current vs Temperature 60 50 40 30 20 10 0 J 20 15 10 5 0 5 10 15 20 A LATCH LE LEB mV 02820 0 017 Figure 16 Hysteresis vs ALatch 210 205 200 195 190 185 180 175 170 165 160 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C 02820 0 019 Figure 17 Fall Time vs Temperature PROPAGATION DELAY ps PROPAGATION DELAY ERROR ps OUTPUT RISE AND FALL V 280 40 30 20 10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE C 02820 0 014 Figure 18 Propagation Delay vs Temperature 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 OVERDRIVE VOLTAGE 02820 0 013 Figure 19 Propagation Delay Error vs Overdrive Voltage
3. ADCMP565 Notes 2003 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www ana l 0 g om daneo fal DEVICES Rev 0 Page 16 of 16
4. parator should not be allowed to float The high internal gain may cause the output to oscillate possibly affecting the comparator that is being used unless the output is forced into a fixed state This is easily accomplished by ensuring that the two inputs are at least one diode drop apart while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described above The best performance is achieved with the use of proper ECL terminations The open emitter outputs of the ADCMP565 are designed to be terminated through 50 Q resistors to 2 0 V or any other equivalent ECL termination If a 2 0 V supply is not available an 82 Q resistor to ground and a 130 Q resistor to 5 2 V provide a suitable equivalent If high speed ECL signals must be routed more than a centimeter microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing ADCMP565 CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals High speed square waves transmitted over a distance even tens of centimeters can become distorted due to stray capacitance and inductance Poor layout or improper termination can also cause reflections on the transmission line further distorting the signal waveform A high speed com parator can be used to recover the distorted waveform while maintaining a minimum of delay OPTIMIZING HIGH SPEED PERFORMANCE As with any hi
5. be driven in conjunction with the noninverting A input 10 INA Noninverting analog input of the differential input stage for Channel A The noninverting A input must be driven in conjunction with the inverting A input 11 NC No Connect Leave pin unconnected 12 INB Noninverting analog input of the differential input stage for Channel B The noninverting B input must be driven in conjunction with the inverting B input 13 INB Inverting analog input of the differential input stage for Channel B The inverting B input must be driven in conjunction with the noninverting B input 14 Vcc Positive Supply Terminal 15 LEB One of two complementary inputs for Channel B Latch Enable In the compare mode logic low the output will track changes at the input of the comparator In the latch mode logic high the output will reflect the input state just prior to the comparator s being placed in the latch mode LEB must be driven in conjunction with LEB 16 NC No Connect Leave pin unconnected or attach to GND internally connected to GND 17 LEB One of two complementary inputs for Channel B Latch Enable In the compare mode logic high the output will track changes at the input of the comparator In the latch mode logic low the output will reflect the input state just prior to the comparator s being placed in the latch mode LEB must be driven in conjunction with LEB Rev 0 Page 6 of 16 ADCMP565 Pin No Mnemoni
6. change in the degree of overdrive how far the switching point is exceeded by the input The overall result is a higher degree of timing accuracy since the ADCMP565 is far less sensitive to input variations than most comparator designs Propagation delay dispersion is a specification that is important in critical timing applications such as ATE bench instruments and nuclear instrumentation Overdrive dispersion is defined Rev 0 Page 9 of 16 ADCMP565 as the variation in propagation delay as the input overdrive conditions are changed Figure 4 For the ADCMP565 overdrive dispersion is typically 50 ps as the overdrive is changed from 100 mV to 1 V This specification applies for both positive and negative overdrive since the ADCMP565 has equal delays for positive and negative going inputs The 50 ps propagation delay dispersion of the ADCMP565 offers considerable improvement of the 100 ps dispersion of other similar series comparators 1 5V OVERDRIVE INPUT VOLTAGE 20mV OVERDRIVE Vrer Vos Q OUTPUT 02820 0 004 Figure 4 Propagation Delay Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the com parator to toggle between states when the input signal is at the switching threshold The transfer function for a comparator with hysteresis is shown in Figure 5 If the input voltage approaches the threshold fr
7. ANALOG DEVICES Dual Ultrafast Voltage Comparator ADCMP565 FEATURES 300 ps propagation delay input to output 50 ps propagation delay dispersion Differential ECL compatible outputs Differential latch control Robust input protection Input common mode range 2 0 V to 3 0 V Input differential range 5 V Power supply sensitivity greater than 65 dB 200 ps minimum pulsewidth 5 GHz equivalent input rise time bandwidth Typical output rise fall of 160 ps SPT 9689 replacement APPLICATIONS High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers and signal restoration Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand held test instruments Zero crossing detectors Clock drivers Automatic test equipment Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT O Q OUTPUT INVERTING INPUT O Q OUTPUT LATCH ENABLE O OLATCH ENABL
8. DCMP565 design is the use of a low impedance ground plane A ground plane as part of a multilayer board is recommended for proper high speed performance Using a continuous con ductive plane over the surface of the circuit board can create this allowing breaks in the plane only for necessary signal paths The ground plane provides a low inductance ground eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce A proper ground plane also minimizes the effects of stray capacitance on the circuit board It is also important to provide bypass capacitors for the power supply in a high speed application A 1 pF electrolytic bypass capacitor should be placed within 0 5 inches of each power supply pin to ground These capacitors will reduce any potential voltage ripples from the power supply In addition a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP565 to ground These capacitors act as a charge reservoir for the device during high frequency switching The LATCH ENABLE input is active low latched If the latching function is not used the LATCH ENABLE input should be grounded ground is an ECL logic high and the complementary input LATCH ENABLE should be tied to 2 0 V This will disable the latching function Occasionally one of the two comparator stages within the ADCMP565 will not be used The inputs of the unused com
9. E INPUT INPUT 02820 0 001 Figure 1 GENERAL DESCRIPTION The ADCMP565 is an ultrafast voltage comparator fabricated on Analog Devices proprietary XFCB process The device features 300 ps propagation delay with less than 50 ps overdrive dispersion Overdrive dispersion a particularly important characteristic of high speed comparators is a measure of the difference in propagation delay under differing overdrive conditions A fast high precision differential input stage permits consis tent propagation delay with a wide variety of signals in the common mode range from 2 0 V to 3 0 V Outputs are complementary digital signals fully compatible with ECL 10 K and 10 KH logic families The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Q to 2 V A latch input is included which permits tracking track and hold or sample and hold modes of operation The ADCMP565 is available in a 20 lead PLCC package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc All rights reserved ADCMP565 TABLE OF CONTENTS Specifications aori a R a E E ERE 3 Optimizing High Speed Performance cesesessseseeeseestesseene 9 Absolute Maximum RatingS ccccessessesesseessessesseesessessneseeseens 5 Comparator Propagation Delay Dispersion csseseseeees 9 Thermal Considerations ccc
10. Output Output Current 30 mA Temperature Operating Temperature 40 C to 85 C Ambient Operating Temperature 125 C Junction Storage Temperature Range 55 C to 125 C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features WARNING S proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy Rint 4 electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev 0 Page 5 of 16 ADCMP565 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADCMP565 TOP VIEW Not to Scale NC NO CONNECT 02820 0 002 Figure 2 ADCMP565 Pin Configuration Table 3 ADCMP565 Pin Descriptions Pin No Mnemonic Function 1 NC No Connect Leave pin unconnected 2 QA One of two complemen
11. c Function 18 GND Analog Ground 19 QB One of two complementary outputs for Channel B QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEB description Pin 17 for more information 20 QB One of two complementary outputs for Channel B QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEB description Pin 17 for more information Rev 0 Page 7 of 16 ADCMP565 TIMING INFORMATION The timing diagram in Figure 3 shows the ADCMP565 compare LATCH ENABLE LATCH ENABLE DIFFERENTIAL INPUT VOLTAGE Q OUTPUT Q OUTPUT Figure 3 System Timing Diagram and latch features Table 4 describes the terms in the diagram Table 4 Timing Descriptions Symbol Timing Description tron Input to output Propagation delay measured from high delay the time the input signal crosses the reference the input offset voltage to the 50 point of an output low to high transition teoi Input to output Propagation delay measured from low delay the time the input signal crosses the reference the input offset voltage to the 50 point of an output high to low transition tPLoH Latch enable Propagation delay measured from to out
12. essesssssessesssesesseesesseesseessesseenes 5 Comparator Hysteresis scessssssseeeeeesessessessesseseesessesesesees 10 ESD Ca ation vce sessed pr E E E ER 5 Minimum Input Slew Rate Requirement 10 Pin Configuration and Function Descriptions 6 Typical Application Circuits oc ceeesesseesessessessesseesseeseenes 11 Timing Information 0 esseesessesssessessessesssessesseessessessesseeseess 8 Typical Performance Characteristics 0 12 Application Information cscsesessesssesesseessessesseessessesseessesseens 9 Outline Dimensions snin a E E KET 14 Clock Timing RECOVELY sesesiisecsessassissseccscsssnoasesessecseesioeassvosesscdunbes 9 Ordering GUE sissies ccs scsssassvesnscidessusaderaicoasen ssschacedocascvcseastatenes 14 REVISION HISTORY Revision 0 Initial Version Rev 0 Page 2 of 16 SPECIFICATIONS Table 1 ADCMP565 ELECTRICAL CHARACTERISTICS Vcc 5 0 V Ve 5 2 V Ta 25 C unless otherwise noted ADCMP565 Parameter Symbol Condition Min Typ Max Unit DC INPUT CHARACTERISTICS See Note Input Common Mode Range Vem 2 0 3 0 V Input Differential Voltage 5 5 V Input Offset Voltage Vos 6 0 1 5 6 0 mV Input Offset Voltage Channel Matching 8 1 8 mV Offset Voltage Tempco DVos dr 5 0 uV C Input Bias Current lsc 10 0 24 40 0 uA Input Bias Current Tempco 17 nA C Input Offset Current 5 0 0 5 5 0 uA Input Capacitance Cin 1 75 pF Input Resistance Differential Mode 100 kQ I
13. gh speed comparator amplifier proper design and layout techniques should be used to ensure optimal perform ance from the ADCMP565 The performance limits of high speed circuitry can easily be a result of stray capacitance improper ground impedance or other layout issues Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP565 Source resistance in combination with equivalent input capacitance could cause a lagged response at the input thus delaying the output The input capacitance of the ADCMP565 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance A combination of 3 kQ source resistance and 5 pF of input capacitance yields a time constant of 15 ns which is significantly slower than the sub 500 ps capability of the ADCMP565 Source impedances should be significantly less than 100 Q for best performance Sockets should be avoided due to stray capacitance and induc tance If proper high speed techniques are used the ADCMP565 should be free from oscillation when the comparator input signal passes through the switching threshold COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP565 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V Propagation delay overdrive dispersion is the change in propagation delay that results from a
14. h BW OV to 1V swing 5000 MHz 20 to 80 50 ps tr tr Rev 0 Page 3 of 16 ADCMP565 Parameter Symbol Condition Min Typ Max Unit AC PERFORMANCE continued Toggle Rate gt 50 output swing 5 Gbps Minimum Pulse Width PW Atro from 10 ns to 200 ps 200 ps lt 50 ps Unit to Unit Propagation Delay Skew 10 ps POWER SUPPLY Positive Supply Current Vee 5 0V 10 13 18 mA Negative Supply Current Wee 5 2V 60 70 80 mA Positive Supply Voltage Vcc Dual 4 75 5 0 5 25 V Negative Supply Voltage Vee Dual 4 96 5 2 5 45 V Power Dissipation Dual without load 370 435 490 mW Power Dissipation Dual with load 550 mW Power Supply Sensitivity Vcc PSSv c 67 dB Power Supply Sensitivity Vee PSSv 83 dB NOTE Under no circumstances should the input voltages exceed the supply voltages Rev 0 Page 4 of 16 ADCMP565 ABSOLUTE MAXIMUM RATINGS Table 2 ADCMP565 Absolute Maximum Ratings THERMAL CONSIDERATIONS Rarameter Rating The ADCMP565 20 lead PLCC package option has a ja Supply Positive Supply Voltage 0 5 V to 6 0 V junction to ambient thermal resistance of 89 4 C W in Voltages Vcc to GND Aias still air Negative Supply Voltage 6 0 V to 0 5 V Ve to GND Ground Voltage Differential 0 5 V to 0 5 V Input Input Common Mode 3 0 V to 4 0 V Voltages Voltage Differential Input Voltage 7 0 V to 7 0 V Input Voltage Ve to 0 5 V Latch Controls
15. nput Resistance Common Mode 600 kQ Open Loop Gain 60 dB Common Mode Rejection Ratio CMRR Vcm 2 0 V to 3 0 V 69 dB Hysteresis 1 0 mV LATCH ENABLE CHARACTERISTICS Latch Enable Common Mode Range Vicm 2 0 0 V Latch Enable Differential Input Voltage Vio 0 4 2 0 V Input High Current 0 0 V 10 6 10 uA Input Low Current 2 0 V 10 6 10 uA Latch Setup Time ts 250 mV overdrive 50 ps Latch to Output Delay teLon tPLoL 250 mV overdrive 280 ps Latch Pulse Width teL 250 mV overdrive 150 ps Latch Hold Time tH 250 mV overdrive 10 ps OUTPUT CHARACTERISTICS Output Voltage High Level Vou ECL 50 Q to 2 0 V 1 08 0 81 V Output Voltage Low Level VoL ECL 50 Q to 2 0 V 1 95 1 61 V Rise Time tr 20 to 80 160 ps Fall Time tF 20 to 80 145 ps AC PERFORMANCE Propagation Delay ted 1 V overdrive 310 ps Propagation Delay ted 20 mV overdrive 375 ps Propagation Delay Tempco 0 5 ps C Prop Delay Skew Rising Transition to 10 ps Falling Transition Within Device Propagation Delay Skew 10 ps Channel to Channel Propagation Delay Dispersion vs 1 MHz 1 ns te tr 10 ps Duty Cycle Propagation Delay Dispersion vs Overdrive 50 mV to 1 5V 50 ps Propagation Delay Dispersion vs Overdrive 20 mV to 1 5 V 50 ps Propagation Delay Dispersion vs 0V to 1 V swing 50 ps Slew Rate 20 to 80 50 ps and 600 ps tr tF Propagation Delay Dispersion vs 1 V swing 5 ps Common Mode Voltage 1 5 V to 2 5 Vem Equivalent Input Rise Time Bandwidt
16. om the negative direction the comparator will switch from a 0 to a 1 when the input crosses Vu 2 The new switching threshold becomes Vu 2 The comparator will remain in a 1 state until the threshold Vu 2 is crossed coming from the positive direction In this manner noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by Vu 2 Positive feedback from the output to the input is often used to produce hysteresis in a comparator Figure 9 The major problem with this approach is that the amount of hysteresis varies with the output logic levels resulting in a hysteresis that is not symmetrical around zero Another method to implement hysteresis is generated by introducing a differential voltage between the LATCH ENABLE and LATCH ENABLE inputs Figure 10 Hysteresis generated in this manner is independent of output swing and is symmetri cal around zero The variation of hysteresis with input voltage is shown in Figure 6 OUTPUT 02820 0 005 Figure 5 Comparator Hysteresis Transfer Function 30 HYSTERESIS mV 20 10 20 15 10 5 0 5 10 15 20 A LATCH LE LEB mV 02820 0 006 Figure 6 Comparator Hysteresis Transfer Function Using Latch Enable Input MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the
17. put high the 50 point of the Latch Enable delay signal low to high transition to the 50 point of an output low to high transition teLoL Latch enable Propagation delay measured from to output low delay the 50 point of the Latch Enable signal low to high transition to the 50 point of an output high to low transition Vrer Vos 50 50 02820 0 003 Symbol Timing Description tH Minimum Minimum time after the negative hold time transition of the Latch Enable signal that the input signal must remain unchanged to be acquired and held at the outputs te Minimum Minimum time that the Latch latch enable Enable signal must be high to pulse width acquire an input signal change ts Minimum Minimum time before the setup time negative transition of the Latch Enable signal that an input signal change must be present to be acquired and held at the outputs tr Output rise Amount of time required to time transition from a low to a high output as measured at the 20 and 80 points tF Output fall Amount of time required to time transition from a high to a low output as measured at the 20 and 80 points Vop Voltage Difference between the overdrive differential input and reference input voltages Rev 0 Page 8 of 16 APPLICATION INFORMATION The ADCMP565 comparators are very high speed devices Consequently high speed design techniques must be employed to achieve the best performance The most critical aspect of any A
18. tary outputs for Channel A QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEA description Pin 5 for more information 3 QA One of two complementary outputs for Channel A QA will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input provided the comparator is in the compare mode See the LEA description Pin 5 for more information 4 GND Analog Ground 5 LEA One of two complementary inputs for Channel A Latch Enable In the compare mode logic high the output will track changes at the input of the comparator In the latch mode logic low the output will reflect the input state just prior to the comparator s being placed in the latch mode LEA must be driven in conjunction with LEA 6 NC No Connect Leave pin unconnected or attach to GND internally connected to GND 7 LEA One of two complementary inputs for Channel A Latch Enable In the compare mode logic low the output will track changes at the input of the comparator In the latch mode logic high the output will reflect the input state just prior to the comparator s being placed in the latch mode LEA must be driven in conjunction with LEA 8 Vee Negative Supply Terminal 9 INA Inverting analog input of the differential input stage for Channel A The inverting A input must
19. threshold This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package Analog Devices recommends a slew rate of 5 V s or faster to ensure a clean output transition If slew rates less than 5 V us are used then hysteresis should be added to reduce the oscillation Rev 0 Page 10 of 16 TYPICAL APPLICATION CIRCUITS OUTPUTS O O LATCH ENABLE INPUTS ALL RESISTORS 509 02820 0 007 Figure 7 High Speed Sampling Circuits VREF ViN q l A VREF O O LATCH 20v ENABLE INPUTS ALL RESISTORS 509 02820 0 008 Figure 8 High Speed Window Comparator Vin ADCMP565 OUTPUTS Vrer O 2 0V ALL RESISTORS 509 02820 0 009 Figure 9 Hysteresis Using Positive Feedback Rev 0 Page 11 of 16 ADCMP565 OUTPUTS O HYSTERESIS VOLTAGE ALL RESISTORS 509 UNLESS OTHERWISE NOTED 02820 0 010 Figure 10 Hysteresis Using Latch Enable Input 5 2V 02820 0 011 Figure 11 How to Interface an ECL Output to an Instrument with a 50 Q to Ground Input ADCMP565 TYPICAL PERFORMANCE CHARACTERISTICS Vcc 5 0 V V 5 2 V Ta 25 C unless otherwise noted OFFSET VOLTAGE mV INPUT BIAS CURRENT uA TIME ps 25 20 15 10 0 2 5 1 5 0 5 0 5 1 5 2 5 3 5 NONINVERTING INPUT VOLTAGE INVERTING VOLTAGE 0 5V 02820 0 020 Figure 12 Input Bias Current vs Input Voltage
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