ANALOG DEVICES AD8318-EP: 1 MHz to 8 GHz 70 dB Logarithmic Detector/Controller Data Sheet (Rev 0 2012-07-25-)
Contents
1. 6 6 5 5 4 4 3 3 2 i 2 o 1 ao 1 z kJ x 0 ct 0 o o Eo WW uu 2 2 3 3 4 E 5 5 6 a 6 2 65 55 45 35 25 15 5 5 15 5 65 55 45 35 25 15 5 5 15 3 Pin dBm 5 Pin dBm Figure 10 Distribution of Error over Temperature After Ambient Figure 13 Distribution of Error at Temperature After Ambient Normalization vs Input Amplitude at 900 MHz for at Least 70 Devices Normalization vs Input Amplitude at 3 6 GHz for at Least 70 Devices Rraps 510 6 6 5 5 4 4 3 3 1 2 2 oa 1 m A 2 z tc 0 tc 0 g 1 e 1 m ui 2 2 3 3 4 4 5 5 6 6 4 65 55 45 35 25 15 5 5 15 5 65 55 45 35 235 15 5 5 15 5 Pin dBm Pix dBm 5 Figure 11 Distribution of Error at Temperature After Ambient Figure 14 Distribution of Error at Temperature After Ambient Normalization vs Input Amplitude at 1900 MHz for at Least 70 Devices Normalization vs Input Amplitude at 5 8 GHz for at Least 70 Devices Rrap 1000 Q 6 6 5 5 4 4 3 3 2 2 oa 1 mo kJ kJ cr o0 c2. CLPF 0 1 uF 200mV VERTICAL DIVISION ANA AAA AAP Vout V ERROR dB PULSED RF INPUT 0 1GHz 10dBm T e 4 65 55 45 35 25 15 5 5 15 10783 017 20ns PER HORIZONTAL DIVISION Pix dBm Figure 18 VOUT Pulse Response Time Pulsed RF Input 0 1 GHz 10 dBm Figure 21 Output Voltage Stability vs Supply Voltage at 1 9 GHz CLPF Open When VP Varies by 10 Multiple Devices Rev 0 Page 10 of 12 10783 020 AD8318 EP OUTLINE DIMENSIONS 4 10 4 00 SQ 23 PIN 1 3 90 INDICATOR AR ATOR 0 80 FOR PROPER CONNECTION OF 075 THE EXPOSED PAD REFER TO m RM Ce a aerate arity SECTION OF THIS DATA SHEET SEATING a i PLANE 0 20 REF i COMPLIANT TO JEDEC STANDARDS MO 220 WGGC E Figure 22 16 Lead Lead Frame Chip Scale Package LFCSP_WQ 4mm x 4 mm Body Very Very Thin Quad CP 16 23 Dimensions shown in millimeters ORDERING GUIDE Temperature Ordering Model Range Package Description Package Option Quantity AD8318SCPZ EP RL7 55 C to 105 C 16 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 16 23 1 500 AD8318SCPZ EP R2 55 C to 105 C 16 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 16 23 250 AD8318SCPZ EP WP 55 C to 105 C 16 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 16 23 64 AD8318 EP EVALZ Evaluation Board Z RoHS Compliant Part WP waffle pack Rev 0 Page 11 of 12
3. 33 0 59 Q pF 3 dB Dynamic Range T 25 C 70 dB 55 C lt T lt 105 C 62 dB 1 dB Dynamic Range T 25 C 57 dB Maximum Input Level 1 dB error 1 dBm Minimum Input Level 1 dB error 58 dBm Slope 24 3 mV dB Intercept 25 dBm Output Voltage High Power In Pn 10 dBm 0 86 V Output Voltage Low Power In Pn 40 dBm 1 59 V Temperature Sensitivity Pn 7 10 dBm 25 C lt T lt 105 C 0 019 dB C 55 C lt T lt 25 C 0 0096 dB C f 8 0 GHz Rap 5000 3 dB Dynamic Range T 25 C 60 dB 55 C lt T lt 105 C 58 dB Maximum Input Level 3 dB error 3 dBm Minimum Input Level 3 dB error 55 dBm Slope 23 mV dB Intercept 37 dBm Output Voltage High Power In Pn 10 dBm 1 06 V Output Voltage Low Power In Pn 40 dBm 1 78 V Temperature Sensitivity Pn 10 dBm 25 C lt T lt 105 C 0 032 dB C 55 C lt T lt 25 C 0 0078 dB C OUTPUT INTERFACE VOUT Pin 6 Voltage Swing Vser OV P4 10 dBm no load 4 9 V Vs 2 1 V Pn 10 dBm no load 25 mV Output Current Drive Veer 1 5 V P4 50 dBm 60 mA Small Signal Bandwidth Pn 10 dBm from CLPF to VOUT 60 MHz Video Bandwidth or Envelope Bandwidth 45 MHz Output Noise Pn 2 2 GHz 10 dBm fyose 100 kHz C 220 pF 90 nV VHz Fall Time Pin Off to 10 dBm 90 to 10 10 ns Rise Time Pn 10 dBm to off 10 to 90 12 ns Rev 0 Page 4 of 12 AD8318 EP Parameter Test Conditions Comments
4. 8 65 55 45 35 25 15 5 5 15 Pin dBm B Pin dBm Figure 4 VOUT and Log Conformance vs Input Amplitude at 900 MHz Figure 7 Voy and Log Conformance vs Input Amplitude at 3 6 GHz Typical Device Typical Device Rj 5 51 Q 2 4 6 24 6 22 5 22 5 2 0 4 2 0 4 1 8 3 1 8 3 1 6 2 1 6 2 gt 14 18 g 14 18 5 12 o5 5 1 2 o5 S 1 gt 10 18 0 43g 4a 0 8 2 0 8 2 0 6 3 0 6 3 0 4 4 0 4 E 0 2 5 0 2 5 0 6 0 6 65 55 45 35 25 15 5 5 15 8 65 55 45 35 2 15 5 5 15 Pix dBm 5 Pin dBm Figure 5 VOUT and Log Conformance vs Input Amplitude at 1 9 GHz Figure 8 VOUT and Log Conformance vs Input Amplitude at 5 8 GHz Typical Device Typical Device Ran 1000 Q 24 6 24 6 22 5 2 2 5 2 0 4 2 0 4 1 8 3 18 3 1 6 2 1 6 2 s14 18 s14 18 5 1 2 0 5 E 1 2 o gt 10 1 gt 1 0 15 B 4a d A 0 8 2 0 8 2 0 6 3 0 6 3 0 4 E 0 4 E 0 2 5 0 2 5 0 6 m 0 6 65 55 45 35 235 15 5 5 15 3 65 55 45 35 2 15 5 5 15 Piy dBm 5 Pi dBm Figure 6 Voy and Log Conformance vs Input Amplitude at 2 2 GHz Figure 9 Voy and Log Conformance vs Input Amplitude at 8 GHz Typical Device Typical Device Rev 0 Page 8 of 12 10783 007 10783 008 10783 009 AD8318 EP Vio 5 Vi T 25 C 55 C 105 C Cipp 220 pF Rr 500 Q unless otherwise noted Colors 25 C gt Black 55 C gt Blue 105 C Red
5. AD8318 EP NOTES 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D10783 0 7 12 0 DEVICES www analo g com Rev 0 Page 12 of 12
6. Min Typ Max Unit VSET INTERFACE VSET Pin 7 Nominal Input Range Pin 0 dBm measurement mode 0 5 Pin 65 dBm measurement mode 2 1 V Logarithmic Scale Factor 0 04 dB mV Bias Current Source Py 7 10dBm V44 2 1 V 2 5 pA TEMPERATURE REFERENCE TEMP Pin 13 Output Voltage T4 25 C Rigjp 10 KQ 057 06 063 V Temperature Slope 55 C lt T 105 C Rojo 10 KQ 2 mvV C Current Source Sink T 25 C 10 0 1 mA POWER DOWN INTERFACE ENBL Pin 16 Logic Level to Enable Device 1 7 V ENBL Current When Enabled ENBL 5V 1 yA ENBL Current When Disabled ENBL 0 V sourcing 15 pA POWER INTERFACE VPSI Pin 3 and Pin 4 VPSO Pin 9 Supply Voltage 4 5 5 5 5 V Quiescent Current ENBL 5V 50 68 82 mA vs Temperature 55 C lt T lt 105 C 150 pA C Supply Current when Disabled ENBL OV total currents for VPSI and VPSO 260 pA vs Temperature 55 C lt T 105 C 350 uA 1 Controller mode Gain 1 For other gains see the AD8318 data sheet Rev 0 Page 5 of 12 AD8318 EP ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings Table 2 Parameter Rating Supply Voltage Pin VPSO Pin VPSI 57V ENBL Ver Voltage 0 to V os Input Power Single Ended re 50 Q 12 dBm Internal Power Dissipation 0 73 W Oa 55 C W Maximum Junction Temperature 130 C Operating Temperature Range 55 C to 105 C Storage Temperature Range 65 C to 150 C may cause pe
7. 8 mA Power consumption decreases to 1 5 mW when the device is disabled The AD8318 EP can be configured to provide a control voltage to a VGA such as a power amplifier or a measurement output from Pin VOUT Because the output can be used for controller applications wideband noise is minimal In this mode the setpoint control voltage is applied to VSET The feedback loop through an RF amplifier is closed via VOUT the output of which regulates the amplifier output to a magnitude corresponding to VSET The AD8318 EP provides 0 V to 4 9 V output capability at the VOUT pin suitable for controller Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 1 MHz to 8 GHz 70 dB Logarithmic Detector Controller AD8318 EP FUNCTIONAL BLOCK DIAGRAM VPSI ENBL TADJ VPSO 10783 001 Figure 1 Vour V ERROR dB 0 65 60 55 50 45 40 35 30 25 20 15 10 5 0 5 1 Pin dBm 10783 052 Figure 2 Typical Logarithm
8. ANALOG DEVICES FEATURES Wide bandwidth 1 MHz to 8 GHz High accuracy 1 0 dB over 55 dB range f 5 8 GHz Stability over temperature 0 5 dB Low noise measurement controller output VOUT Pulse response time 10 ns 12 ns fall rise Integrated temperature sensor Small footprint LFCSP Power down feature 1 5 mW at 5 V Single supply operation 5 V 68 mA Fabricated using high speed SiGe process APPLICATIONS RF transmitter PA setpoint control and level monitoring RSSI measurement in base stations WLAN WiMAX and radars GENERAL DESCRIPTION The AD8318 EP is a demodulating logarithmic amplifier capable of accurately converting an RF input signal to a corresponding decibel scaled output voltage It employs the progressive compression technique over a cascaded amplifier chain each stage of which is equipped with a detector cell The device is used in measurement or controller mode The AD8318 EP maintains accurate log conformance for signals of 1 MHz to 6 GHz and provides useful operation to 8 GHz The input range is typically 60 dB re 50 Q with error less than 1 dB The AD8318 EP has a 10 ns response time that enables RF burst detection to beyond 45 MHz The device provides unprecedented logarithmic intercept stability vs ambient temperature conditions A 2 mV C slope temperature sensor output is also provided for additional system monitoring A single supply of 5 V is required Current consumption is typically 6
9. al Performance Characteristics sss 1 Outline Dimensions eene LL 2 Ordering Guide ete teet Ll Paepe R Kek 3 raS 6 SPECIFICATIONS Vros 5 V Cipr 220 pF T 25 C 52 3 Q termination resistor at INHI unless otherwise noted AD8318 EP Table 1 Parameter Test Conditions Comments Min Typ Max Unit SIGNAL INPUT INTERFACE INHI Pin 14 and INLO Pin 15 Specified Frequency Range 0 001 8 GHz DC Common Mode Voltage Vpos 1 8 V MEASUREMENT MODE VOUT Pin 6 shorted to VSET Pin 7 sinusoidal input signal f 900 MHz Rian 5000 Input Impedance 957 0 71 Q pF 3 dB Dynamic Range T 25 C 65 dB 55 C lt T lt 105 C 63 dB 1 dB Dynamic Range T 25 C 57 dB Maximum Input Level 1 dB error 1 dBm Minimum Input Level 1 dB error 58 dBm Slope 26 24 5 23 mV dB Intercept 19 5 22 24 dBm Output Voltage High Power In Pn 10 dBm 0 7 0 78 086 V Output Voltage Low Power In Pn 40 dBm 1 42 1 52 162 V Temperature Sensitivity Pn 10 dBm 25 C T lt 105 C 0 0071 dB C 55 C T lt 425 C 0 0031 dB C f 1 9 GHz Rap 500 Q Input Impedance 523 0 68 Q pF 3 dB Dynamic Range Ty 25 C 65 dB 55 C lt T lt 105 C 63 dB 1 dB Dynamic Range T 25 C 57 dB Maximum Input Level 1 dB error 2 dBm Minimum Input Level 1 dB error 59 dBm Slope 27 24 4 22 mV dB Intercept 17 20 4 24 dBm Output Vo
10. ic Response and Error vs Input Amplitude at 5 8 GHz applications As a measurement device Pin VOUT is externally connected to VSET to produce an output voltage Voyr which is a decreasing linear in dB function of the RF input signal amplitude The logarithmic slope is nominally 25 mV dB but can be adjusted by scaling the feedback voltage from VOUT to the VSET interface The intercept is 20 dBm re 50 O CW input using the INHI input These parameters are very stable against supply and temperature variations The AD8318 EP is fabricated on a SiGe bipolar IC process and is available in a 4 mm x 4 mm 16 lead LFCSP Performance is specified over a temperature range of 55 C to 105 C Additional application and technical information can be found in the AD8318 data sheet One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2012 Analog Devices Inc All rights reserved AD8318 EP TABLE OF CONTENTS USC 1 00 1 ot nae RSIS nore Applications eoe ter reete General Description see Functional Block Diagram sss REVISION HistOEy eee Sp cifications eee p te ee bee Absolute Maximum Ratings sees REVISION HISTORY 7 12 Revision 0 Initial Version Rev 0 Page 2 of 12 SEA 1 ESD Caution oett tette erc ERRE 1 Pin Configuration and Function Descriptions 7 T 1 Typic
11. ltage High Power In Pn 10 dBm 0 63 0 73 0 83 V Output Voltage Low Power In Pn 35 dBm 1 2 1 35 1 5 V Temperature Sensitivity Pn 10 dBm 25 C lt T lt 105 C 0 0056 dB C 55 C lt T lt 25 C 0 0004 dB C f 2 2 GHz Rap 5000 Input Impedance 391 0 66 Q pF 3 dB Dynamic Range T 25 C 65 dB 55 C lt T lt 105 C 62 dB 1 dB Dynamic Range T 25 C 58 dB Maximum Input Level 1 dB error 2 dBm Minimum Input Level 1 dB error 60 dBm Slope 28 24 4 21 5 mV dB Intercept 15 19 6 25 dBm Output Voltage High Power In Pn 10 dBm 0 68 0 73 084 V Output Voltage Low Power In Pn 35 dBm 1 2 1 34 1 5 V Temperature Sensitivity Pn 7 10 dBm 25 C lt T lt 105 C 0 0052 dB C 55 C lt T lt 25 C 0 0034 dB C Rev 0 Page 3 of 12 AD8318 EP Parameter Test Conditions Comments Min Typ Max Unit f 3 6 GHz Ran 51 0 Input Impedance 119 0 7 Q pF 3 dB Dynamic Range Ty 25 C 70 dB 55 C lt T lt 105 C 61 dB 1 dB Dynamic Range T 25 C 58 dB Maximum Input Level 1 dB error 2 dBm Minimum Input Level 1 dB error 60 dBm Slope 24 3 mV dB Intercept 19 8 dBm Output Voltage High Power In Pn 10 dBm 0 717 V Output Voltage Low Power In Pn 40 dBm 1 46 V Temperature Sensitivity Pn 10 dBm 25 C lt T lt 105 C 0 0012 dB C 55 C lt T lt 25 C 0 009 dB C f 5 8 GHz Rag 1000 Q Input Impedance
12. rmanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD CAUTION With package die paddle soldered to thermal pads with vias connecting to inner and bottom layers A ta ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 6 of 12 AD8318 EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CMIP CMIP TADJ VPSO CMIP CMIP VPSI VPSI NOTES 1 THE EXPOSED PADDLE IS INTERNALLY CONNECTED TO CMIP SOLDER TO GROUND 10783 002 Figure 3 Pin Configuration Table 3 Pin Function Descriptions Pin No Mnemonic Description 1 2 11 12 CMIP Device Common Input System Ground 3 4 VPSI Positive Supply Voltage Input System 4 5 V to 5 5 V Voltage on Pin 3 Pin 4 and Pin 9 should be equal 5 CLPF Loop Filter Capacitor 6 VOUT Measurement and Controller Output 7 VSET Setpoint Input for Controller Mode or Feedback Input for Meas
13. t 0 g ZER g c i E a4 TT m 2 2 3 3 A 4 E 5 5 6 a 6 o 65 55 45 35 25 15 5 5 15 5 65 55 45 35 25 15 5 5 15 Pin dBm 5 Pix dBm Figure 12 Distribution of Error at Temperature After Ambient Figure 15 Distribution of Error at Temperature After Ambient Normalization vs Input Amplitude at 2 2 GHz for at Least 70 Devices Normalization vs Input Amplitude at 8 GHz for at Least 70 Devices Rev 0 Page 9 of 12 AD8318 EP Vros 5 V Ta 25 C 55 C 105 C Crer 220 pF Rray 500 Q unless otherwise noted Colors 25 C gt Black 55 C Blue 1105 C gt Red x e eo NOISE SPECTRAL DENSITY nV VHz START FREQUENCY 0 1GHz 10783 015 10783 018 j1 STOP FREQUENCY 8GHz j FREQUENCY kHz Figure 16 Input Impedance vs Frequency No Termination Resistor on Figure 19 Noise Spectral Density of Output CLPF Open INHI Zo 50 0 07 1k 0 06 E I z gt 0 05 x gt E E i o 2 E a a8 E 100 o E a o a E o 0 7 W o 0 01 9 10 2 3 1 3 10 30 100 300 1k 3k 10k S Vener V B FREQUENCY kHz B Figure 17 Supply Current vs Enable Voltage Figure 20 Noise Spectral Density of Output Buffer from CLPF to VOUT
14. urement Mode 8 CMOP Device Common Output System Ground 9 VPSO Positive Supply Voltage Output System 4 5 V to 5 5 V Voltage on Pin 3 Pin 4 and Pin 9 should be equal 10 TADJ Temperature Compensation Adjustment 13 TEMP Temperature Sensor Output 14 INHI RF Input Nominal input range 60 dBm to 0 dBm re 50 Q ac coupled 15 INLO RF Common for INHI AC coupled RF common 16 ENBL Device Enable Connect to VPSI for normal operation Connect pin to ground for disable mode Paddle The Exposed Paddle is Internally Connected to CMIP Solder to Ground Rev 0 Page 7 of 12 AD8318 EP TYPICAL PERFORMANCE CHARACTERISTICS Voos 5 Vi T 25 C 55 C 105 C C 220 pF Ry 500 Q unless otherwise noted Colors 25 C gt Black 55 C gt Blue 105 C Red 24 6 24 6 2 2 5 2 2 5 2 0 4 2 0 4 1 8 3 1 8 3 1 6 2 1 6 2 gt 14 18 gt 14 18 5 12 oc 512 o5 ia 2 E 1 0 416 1 0 EE 0 8 2 0 8 2 0 6 3 0 6 3 0 4 4 0 4 4 0 2 5 0 2 5 0 6 z 0 6 65 55 45 35 25 15 5 5 15
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ANALOG DEVICES AD8318 EP: 1 MHz to 8 GHz 70 dB Logarithmic Detector/Controller Data Sheet (Rev 0 201