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MOTOROLA MPC850EC/D handbook

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1. D 0 31 DP 0 3 Figure 15 External Bus Write Timing GPCM Controlled TRLX 1 CSNT 1 Figure 16 provides the timing for the external bus controlled by the UPM MOTOROLA MPC850 Rev A B C Hardware Specifications 27 Layout Practices CLKOUT mou e _ CSx oy B34 gt My a B34q gt at B D gt etl a BS_A 0 3 BS_B 0 3 X KX X _ GPL _A 0 5 GPL_B 0 5 __ Figure 16 External Bus Timing UPM Controlled Signals Figure 17 provides the timing for the asynchronous asserted UPWAIT signal controlled by the UPM CLKOUT 3 UPWAIT AE f RAN BS_A 0 3 GPL_A 0 5 X X x GPL_B 0 5 Figure 17 Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing 28 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Figure 18 provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM CLKOUT UPWAIT BS_A 0 3 GPL A 0 5 X X GPL_B 0 5 Figure 18 Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing Figure 19 provides the timing for the synchronous external master access controlled by the GPCM CLKOUT TS A 6 31 _TSIZ 0 1 _______ R W BURST CSx Figure 19 Synchronous External Master Access Timing GPCM Handled ACS 00 MOTOROLA MPC850 Rev A B C Hardware Specification
2. Num Characteristic Unit Min Max 100 RCLKx and TCLKx frequency x 2 3 for all specs in this 1 SYNCCLK jns table 101 RCLKx and TCLKx width low 1 SYNCCLK 5 jns 102 RCLKx and TCLKx rise fall time 15 00 ns 103 TXDx active delay from TCLKx falling edge 0 00 50 00 ns 104 RTSx active inactive delay from TCLKx falling edge 0 00 50 00 ns 105 CTSx setup time to TCLKx rising edge 5 00 jns 106 RXDx setup time to RCLKx rising edge 5 00 jns 107 RXDx hold time from RCLKx rising edge 5 00 jns 108 CDx setup time to RCLKx rising edge 5 00 jns The ratios SyncCLK RCLKx and SyncCLK TCLKx must be greater than or equal to 2 25 1 2 Also applies to CD and CTS hold time when they are used as an external sync signal Table 19 provides the NMSI internal clock timing Table 19 NMSI Internal Clock Timing All Frequencies Num Characteristic Unit Min Max 100 RCLKx and TCLKx frequency x 2 3 for all specs in this table 0 00 SYNCCLK 3 MHz 102 RCLKx and TCLKx rise fall time E ns 103 TXDx active delay from TCLKx falling edge 0 00 30 00 ns 104 RTSx active inactive delay from TCLKx falling edge 0 00 30 00 ns 105 CTSx setup time to TCLKx rising edge 40 00 ns 106 RXDx setup time to RCLKx rising edge 40 00 ns 107 RXDx hold time from RCLKx rising edge 0 00 ns 108 CDx setup time to RCLKx rising edge 40 00 ns 1 The ratios SyncCLK
3. All Frequencies Num Characteristic Unit Min Max 61 TIN TGATE rise and fall time 10 00 ns 62 TIN ATGATE low time 1 00 clk 63 TIN ATGATE high time 2 00 clk 64 TIN TGATE cycle time 3 00 clk 65 CLKO high to TOUT valid 3 00 25 00 ns TIN TGATE Input TOUT Output 63 65 Figure 44 CPM General Purpose Timers Timing Diagram 8 5 Serial Interface AC Electrical Specifications Table 17 provides the serial interface timings as shown in Figure 45 to Figure 49 Table 17 SI Timing All Frequencies Num Characteristic Unit Min Max 70 L1RCLK L1TCLK frequency DSC 0 2 SYNCCLK 2 MHz 5 71 L1RCLK L1TCLK width low DSC 0 P 10 ns 71a L1RCLK L1TCLK width high DSC 0 3 P 10 ns 72 L1TXD L1STn LTRQ L1xCLKO rise fall time 15 00 ns 73 L1RSYNC L1TSYNC valid to L1xCLK edge Edge 20 00 ns SYNC setup time MOTOROLA MPC850 Rev A B C Hardware Specifications 43 Serial Interface AC Electrical Specifications 44 Table 17 SI Timing continued All Frequencies Num Characteristic Unit Min Max 74 L1xCLK edge to L1RSYNC LITSYNC invalid 35 00 ns SYNC hold time 75 L1RSYNC L1TSYNC rise fall time 15 00 ns 76 L1RXD valid to L1xCLK edge L1RXD setup time 17 00 ns 77 L1xCLK edge to L1RXD invalid L1RXD hold time 13 00 ns
4. MOTOROLA MPC850 Rev A B C Hardware Specifications 31 Layout Practices Table 8 PCMCIA Timing continued 50MHz 66MHz 80 MHz Num Characteristic FFACTOR Unit Min Max Min Max Min Max P53 CLKOUT to ALE negate time 13 00 16 00 14 00 0 250 ns PCWE IOWR negated to D 0 31 3 00 6 00 4 00 0 250 ns P54 con invalid P55 WAIT B valid to CLKOUT rising edge 8 00 8 00 8 00 ns P56 CLKOUT rising edge to WAIT _B invalid 2 00 2 00 2 00 ns PSST 1 Otherwise add PSST times cycle time PSHT 0 Otherwise add PSHT times cycle time These synchronous timings define when the WAIT_B signal is detected in order to freeze or relieve the PCMCIA current cycle The WAIT_B assertion will be effective only if it is detected 2 cycles before the PSL timer expiration See PCMCIA Interface in the MPC850 PowerQUICC User s Manual Figure 24 provides the PCMCIA access cycle timing for the external bus read z 3 PCOE IORD o 32 ALE D 0 31 Q Figure 24 PCMCIA Access Cycles Timing External Bus Read MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Figure 25 provides the PCMCIA access cycle timing for the external bus write pap PCOE IOWR ALE Figure 25 PCMCIA Access Cycles Timing External Bus Write Figure
5. Figure 39 IDMA External Requests Timing Diagram 40 MPC850 Rev A B C Hardware Specifications MOTOROLA IDMA Controller AC Electrical Specifications CLKOUT Output TS Output R W Output TA Output SDACK Figure 40 SDACK Timing Diagram Peripheral Write TA Sampled Low at the Falling Edge of the Clock CLKOUT Output TS Output R W Output TA Output SDACK f Figure 41 SDACK Timing Diagram Peripheral Write TA Sampled High at the Falling Edge of the Clock MOTOROLA MPC850 Rev A B C Hardware Specifications 41 Baud Rate Generator AC Electrical Specifications Output TS Output R W Output DATA TA Output SDACK Figure 42 SDACK Timing Diagram Peripheral Read 8 3 Baud Rate Generator AC Electrical Specifications Table 15 provides the baud rate generator timings as shown in Figure 43 BRGOn 42 Table 15 Baud Rate Generator Timing All Frequencies Num Characteristic Unit Min Max 50 BRGOrise and fall time 10 00 ns 51 BRGO duty cycle 40 00 60 00 52 BRGO cycle 40 00 ns Figure 43 Baud Rate Generator Timing Diagram MPC850 Rev A B C Hardware Specifications MOTOROLA Timer AC Electrical Specifications 8 4 Timer AC Electrical Specifications Table 16 provides the baud rate generator timings as shown in Figure 44 Table 16 Timer Timing
6. Figure 61 I C Bus Timing Diagram Information Table 26 provides information on the MPC850 derivative devices Table 26 MPC850 Derivatives Device Ethernet Support Number of SCCs santa aia Ser a MPC850 N A One N A N A MPC850DE Yes Two N A N A MPC850SAR Yes Two N A Yes 1 MOTOROLA Serial Communication Controller SCC 50 MHz version supports 64 time slots on a time division multiplexed line using one SCC MPC850 Rev A B C Hardware Specifications 61 Pin Assignments and Mechanical Dimensions of the PBGA Table 27 identifies the packages and operating frequencies available for the MPC850 Table 27 MPC850 Package Frequency Availability Package Type Frequency MHz Temperature Tj Order Number 256 Lead Plastic Ball Grid Array 50 0 C to 95 C XPC850ZT50B ZT suffix XPC850DEZT50B XPC850SRZT50B 66 0 C to 95 C XPC850ZT66B XPC850DEZT66B XPC850SRZT66B 80 0 C to 95 C XPC850ZT80B XPC850DEZT80B XPC850SRZT80B 256 Lead Plastic Ball Grid Array 50 40 C to 95 C XPC850CZT50B CZT suffix XPC850DECZT50B XPC850SRCZT50B 66 XPC850CZT66B XPC850DECZT66B XPC850SRCZT66B 80 XPC850CZT80B XPC850DECZT80B XPC850SRCZT80B 9 1 Pin Assignments and Mechanical Dimensions of the PBGA The original pin numbering of the MPC850 conformed to a Motorola proprietary pin numbering scheme that has since been replaced by the JEDEC pin numbering standard for this package
7. 7X PC 850C ZT 66Bf hy A Advance Information i o 67 B Rev 0 2 04 2002 MPC850 Rev A B C Communications Controlle Hardware Specifications ale L Nd MOTOROLA er w OT OROFA e digitaldna r This document contains detailed information on power considerations AC DC electrical characteristics and AC timing specifications for revision A B and C of the MPC850 This document contains the following topics Topic Page Part I Overview 1 Part II Features Part III Electrical and Thermal Characteristics 7 Part IV Thermal Characteristics 8 Part V Power Considerations 9 Part VI Bus Signal Timing 10 Part VII IEEE 1149 1 Electrical Specifications 37 Part VIII CPM Electrical Characteristics 39 Part IX Mechanical Data and Ordering Information 61 Part X Document Revision History 67 Part Overview The MPC850 is a versatile one chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications excelling particularly in communications and networking products The MPC850 which includes support for Ethernet is specifically designed for cost sensitive remote access and telecommunications applications It is provides functions similar to the MPC860 with system enhancements such as universal serial bus USB support and a larger 8 Kbyte dual port RAM In addition to a high performance embedded MPC8xx core t
8. ns J85 TMS TDI data setup time 5 00 5 00 5 00 ns MOTOROLA MPC850 Rev A B C Hardware Specifications 37 Layout Practices Table 12 JTAG Timing continued 50 MHz 66MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max J86 TMS TDI data hold time 25 00 25 00 25 00 ns J87 TCK low to TDO data valid 27 00 27 00 27 00 ns J88 TCK low to TDO data invalid 0 00 0 00 0 00 ns J89 TCK low to TDO high impedance 20 00 20 00 20 00 ns J90 TRST assert time 100 00 100 00 100 00 ns J91 TRST setup time to TCK low 40 00 40 00 40 00 ns J92 TCK falling edge to output valid 50 00 50 00 50 00 ns J93 TCK falling edge to output valid out of high 50 00 50 00 50 00 ns impedance J94 TCK falling edge to output high impedance 50 00 50 00 50 00 ns J95 Boundary scan input valid to TCK rising edge 50 00 50 00 50 00 ns J96 TCK rising edge to boundary scan input invalid 50 00 50 00 50 00 ns TCK TCK TMS TDI TDO Figure 35 JTAG Test Access Port Timing Diagram 38 MPC850 Rev A B C Hardware Specifications MOTOROLA TCK EA TRST Figure 36 JTAG TRST Timing Diagram TCK 494 J94 me 2 Output Signals Output Signals Input Signals Part VIII CPM Electrical Characteristics PIO AC Electrical Specifications Figure
9. 181 Rise time input 15 00 ns 182 Fall time input 15 00 ns MOTOROLA MPC850 Rev A B C Hardware Specifications 57 SPI Slave AC Electrical Specifications SPISEL Input SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input Figure 59 SPI Slave CP 0 Timing Diagram 58 MPC850 Rev A B C Hardware Specifications MOTOROLA SPISEL Input SPICLK Cl 0 Input SPICLK Cl 1 Input SPIMISO Output SPIMOSI Input I2C AC Electrical Specifications Figure 60 SPI Slave CP 1 Timing Diagram 8 11 lC AC Electrical Specifications Table 24 provides the PC SCL lt 100 KHz timings Table 24 I2C Timing SCL lt 100 KHz All Frequencies Num Characteristic Unit Min Max 200 SCL clock frequency slave 0 00 100 00 KHz 200 SCL clock frequency master 1 50 100 00 KHz 202 Bus free time between transmissions 4 70 us 203 Low period of SCL 4 70 us 204 High period of SCL 4 00 us 205 Start condition setup time 4 70 E us 206 Start condition hold time 4 00 us 207 Data hold time 0 00 us MOTOROLA MPC850 Rev A B C Hardware Specifications 59 I2C AC Electrical Specifications Table 24 1 C Timing SCL lt 100 KHZ CONTINUED All Frequencies Num Characteristic Unit Min Max
10. 2 00 9 00 2 00 9 00 50 00 ns negated B27 A 6 31 to CS asserted GPCM 23 00 36 00 29 00 1 250 50 00 ns ACS 10 TRLX 1 B27a A 6 31 to CS asserted GPCM 28 00 43 00 36 00 1 500 50 00 ns ACS 11 TRLX 1 B28 CLKOUT rising edge to WE 0 3 9 00 9 00 9 00 50 00 ns negated GPCM write access CSNT 0 B28a CLKOUT falling edge to WE 0 3 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns negated GPCM write access TRLX 0 1 CSNT 1 EBDF 0 B28b CLKOUT falling edge to CS 12 00 14 00 13 00 0 250 50 00 ns negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 B28c CLKOUT falling edge to WE 0 3 7 00 14 00 11 00 18 00 9 00 16 00 0 375 50 00 ns negated GPCM write access TRLX 0 1 CSNT 1 write access TRLX 0 CSNT 1 EBDF 1 B28d CLKOUT falling edge to CS 1400 18 00 16 00 0 375 50 00 ns negated GPCM write access TRLX 0 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 B29 WE 0 3 negated to D O 31 3 00 6 00 4 00 0 250 50 00 ns DP 0 3 high Z GPCM write access CSNT 0 B29a WE 0 3 negated to D O 31 8 00 13 00 11 00 0 500 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 EBDF 0 MOTOROLA MPC850 Rev A B C Hardware Specifications 13 Layout Practices Table 6 Bus Ope
11. 208 Data setup time 250 00 ns 209 SDL SCL rise time 1 00 us 210 SDL SCL fall time 300 00 ns 211 Stop condition setup time 4 70 us Table 25 provides the PC SCL gt 100 KHz timings Table 25 1 C Timing SCL gt 100 KHz SCL frequency is given by SCL BRGCLK_frequency BRG register 3 pre_scaler 2 The ratio SyncClk BRGCLK pre_scaler must be greater or equal to 4 1 All Frequencies Num Characteristic Expression Unit Min Max 200 SCL clock frequency slave fSCL 0 BRGCLK 48 Hz 200 SCL clock frequency master 1 fSCL BRGCLK 16512 BRGCLK 48 Hz 202 Bus free time between transmissions 1 2 2 fSCL s 203 Low period of SCL 1 2 2 fSCL s 204 High period of SCL 1 2 2 fSCL Ss 205 Start condition setup time 1 2 2 fSCL s 206 Start condition hold time 1 2 2 fSCL s 207 Data hold time 0 s 208 Data setup time 1 40 fSCL s 209 SDL SCL rise time 1 10 fSCL s 210 SDL SCL fall time 1 33 fSCL s 211 Stop condition setup time 1 2 2 2 fSCL s 1 SCL frequency is given by SCL BrgClk_frequency BRG register 3 pre_scaler 2 The ratio SyncClk Brg_Clk pre_scaler must be greater or equal to 4 1 60 MPC850 Rev A B C Hardware Specifications MOTOROLA Figure 61 shows the PC bus timing Part IX Mechanical Data and Ordering I2C AC Electrical Specifications
12. 4 00 4 00 50 00 ns CLKOUT falling edge setup time 8 B21 CLKOUT falling edge to D O 31 2 00 2 00 2 00 DP 0 3 valid hold time 8 B22 CLKOUT rising edge to CS 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns asserted GPCM ACS 00 B22a CLKOUT falling edge to CS 8 00 8 00 8 00 50 00 ns asserted GPCM ACS 10 TRLX 0 1 B22b CLKOUT falling edge to CS 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns asserted GPCM ACS 11 TRLX 0 EBDF 0 12 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Table 6 Bus Operation Timing 1 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B22c CLKOUT falling edge to CS 7 00 14 00 11 00 18 00 9 00 16 00 0 375 50 00 ns asserted GPCM ACS 11 TRLX 0 EBDF 1 B23 CLKOUT rising edge to CS 2 00 8 00 2 00 8 00 2 00 8 00 50 00 ns negated GPCM read access GPCM write access ACS 00 TRLX 0 amp CSNT 0 B24 A 6 31 to CS asserted GPCM 3 00 6 00 4 00 0 250 50 00 ns ACS 10 TRLX 0 B24a A 6 31 to CS asserted GPCM 8 00 13 00 11 00 0 500 50 00 ns ACS 11 TRLX 0 B25 CLKOUT rising edge to OE 9 00 9 00 9 00 50 00 ns WE 0 3 asserted B26 CLKOUT rising edge to OE 2 00 9 00
13. 9 25 2 50 9 25 50 00 ns When driven by the memory controller or PCMCIA interface B12 CLKOUT to TS BB negation 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns B12a CLKOUT to TA BI negation 2 50 11 00 2 50 11 00 2 50 11 00 50 00 ns when driven by the memory controller or PCMCIA interface B13 CLKOUT to TS BB high Z 5 00 19 00 7 58 21 58 6 25 20 25 0 250 50 00 ns B13a CLKOUT to TA BI high Z when 2 50 15 00 2 50 15 00 2 50 15 00 50 00 ns driven by the memory controller or PCMCIA interface B14 CLKOUT to TEA assertion 2 50 10 00 2 50 10 00 2 50 10 00 50 00 ns B15 CLKOUT to TEA high Z 2 50 15 00 2 50 15 00 2 50 15 00 50 00 ns B16 TA BI valid to CLKOUT setup 9 75 9 75 9 75 50 00 ns time B16a TEA KR RETRY valid to 10 00 10 00 10 00 50 00 ns CLKOUT setup time B16b BB BG BR valid to CLKOUT 8 50 8 50 8 50 50 00 ns setup time B17 CLKOUT to TA TEA BI BB BG 1 00 1 00 1 00 50 00 ns BR valid Hold time B17a CLKOUT to KR RETRY except 2 00 2 00 2 00 50 00 ns TEA valid hold time B18 D 0 31 DP 0 3 valid to 6 00 6 00 6 00 50 00 ns CLKOUT rising edge setup time 7 B19 CLKOUT rising edge to D O 31 1 00 1 00 1 00 50 00 ns DP 0 3 valid hold time B20 D 0 31 DP 0 3 valid to 4 00
14. A B C Hardware Specifications 21 Layout Practices Figure 9 through Figure 12 provide the timing for the external bus read controlled by various GPCM factors en Figure 9 External Bus Read Timing GPCM Controlled ACS 00 22 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices OE B19 Co pga as D 0 31 DP 0 3 Figure 10 External Bus Read Timing GPCM Controlled TRLX 0 ACS 10 D 0 31 DP 0 3 Figure 11 External Bus Read Timing GPCM Controlled TRLX 0 ACS 11 MOTOROLA MPC850 Rev A B C Hardware Specifications 23 Layout Practices CLKOUT gt D 0 31 DP 0 3 Figure 12 External Bus Read Timing GPCM Controlled TRLX 1 ACS 10 ACS 11 24 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Figure 13 through Figure 15 provide the timing for the external bus write controlled by various GPCM factors D 0 31 DP 0 3 Figure 13 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 0 MOTOROLA MPC850 Rev A B C Hardware Specifications 25 Layout Practices 26 D 0 31 DP 0 3 Figure 14 External Bus Write Timing GPCM Controlled TRLX 0 CSNT 1 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices A 6 31
15. as requested by control bit CST1 in the corresponding word in the UPM 5 00 12 00 8 00 14 00 13 00 0 250 50 00 ns B31b CLKOUT rising edge to CS valid as requested by control bit CST2 in the corresponding word in the UPM 1 50 8 00 8 00 50 00 ns B31c CLKOUT rising edge to CS valid as requested by control bit CST3 in the corresponding word in the UPM 5 00 12 00 8 00 14 00 13 00 0 250 50 00 ns B31d CLKOUT falling edge to CS valid as requested by control bit CST1 in the corresponding word in the UPM EBDF 1 9 00 14 00 13 00 18 00 11 00 16 00 0 375 50 00 ns B32 CLKOUT falling edge to BS valid as requested by control bit BST4 in the corresponding word in the UPM 1 50 6 00 1 50 50 00 ns B32a CLKOUT falling edge to BS valid as requested by control bit BST1 in the corresponding word in the UPM EBDF 0 5 00 12 00 8 00 14 00 13 00 0 250 50 00 ns MOTOROLA MPC850 Rev A B C Hardware Specifications 15 Layout Practices Table 6 Bus Operation Timing 1 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B32b CLKOUT rising edge to BS valid 1 50 8 00 1 50 8 00 1 50 8 00 50 00 ns as requested by control bit BST2 in the corresponding wor
16. 00 2 00 2 00 ns Figure 29 provides the input timing for the debug port clock DSCK Figure 29 Debug Port Clock Input Timing Figure 30 provides the timing for the debug port DSCK DSDI DSDO Figure 30 Debug Port Timings MOTOROLA MPC850 Rev A B C Hardware Specifications 35 Layout Practices Table 11 shows the reset timing for the MPC850 Table 11 Reset Timing 50 MHz 66MHz 80 MHz Num Characteristic pp FFACTOR Unit Min Max Min Max Min Max R69 CLKOUT to HRESET high impedance 20 00 20 00 _ 20 00 ns R70 CLKOUT to SRESET high impedance 20 00 20 00 20 00 ns R71 RSTCONF pulse width 340 00 515 00 425 00 17 000 jns R72 R73 Configuration data to HRESET rising 350 00 505 00 425 00 15 000 edge set up time R74 Configuration data to RSTCOMF rising 350 00 350 00 350 00 edge set up time R75 Configuration data hold time after 0 00 0 00 0 00 RSTCONF negation R76 Configuration data hold time after 0 00 0 00 0 00 HRESET negation HRESET and RSTCONF asserted to 25 00 25 00 25 00 R77 data out drive R78 RSTCONF negated to data out high 25 00 25 00 25 00 impedance CLKOUT of last rising edge before chip 25 00 25 00 25 00 R79 tristates HRESET to dat
17. 164 Master data valid after SCK edge 20 00 ns 165 Master data hold time outputs 0 00 ns 166 Rise time output 15 00 ns 167 Fall time output 15 00 ns MOTOROLA MPC850 Rev A B C Hardware Specifications 55 SPI Master AC Electrical Specifications SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output SPICLK Cl 0 Output SPICLK Cl 1 Output SPIMISO Input SPIMOSI Output Figure 58 SPI Master CP 1 Timing Diagram 56 MPC850 Rev A B C Hardware Specifications MOTOROLA SPI Slave AC Electrical Specifications 8 10 SPI Slave AC Electrical Specifications Table 23 provides the SPI slave timings as shown in Figure 59 and Figure 60 Table 23 SPI Slave Timing All Frequencies Num Characteristic Unit Min Max 170 Slave cycle time 2 teyc 171 Slave enable lead time 15 00 ns 172 Slave enable lag time 15 00 ns 173 Slave clock SPICLK high or low time 1 teyc 174 Slave sequential transfer delay does not require deselect 1 toyc 175 Slave data setup time inputs 20 00 ns 176 Slave data hold time inputs 20 00 ns 177 Slave access time 50 00 ns 178 Slave SPI MISO disable time 50 00 ns 179 Slave data valid after SPICLK edge 50 00 ns 180 Slave data hold time outputs 0 00 ns
18. 78 L1xCLK edge to L1STn valid 4 10 00 45 00 ns 78A L1SYNC valid to L1STn valid 10 00 45 00 ns 79 L1xCLK edge to L1STn invalid 10 00 45 00 ns 80 L1xCLK edge to L1TXD valid 10 00 55 00 ns 80A L1TSYNC valid to L1TXD valid 4 10 00 55 00 ns 81 L1xCLK edge to L1TXD high impedance 0 00 42 00 ns 82 L1RCLK L1TCLK frequency DSC 1 16 00 or MHz SYNCCLK 2 83 L1RCLK L1TCLK width low DSC 1 P 10 ns 83A L1RCLK L1TCLK width high DSC 1 P 10 ns 84 L1CLK edge to L1CLKO valid DSC 1 30 00 ns 85 LTRQ valid before falling edge of L1TSYNC4 1 00 L1TCLK 86 L1GR setup time 42 00 ns 87 L1GR hold time 42 00 ns 88 L1xCLK edge to L1SYNC valid FSD 00 CNT 0 00 ns 0000 BYT 0 DSC 0 Ron The ratio SyncCLK L1RCLK must be greater than 2 5 1 These specs are valid for IDL mode only Where P 1 CLKOUT Thus for a 25 MHz CLKO1 rate P 40 ns These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC whichever is later MPC850 Rev A B C Hardware Specifications MOTOROLA Serial Interface AC Electrical Specifications LIRCLK FE 0 CE 0 Input LIRCLK FE 1 CE 1 Input LIRSYNC Input L1RxD Input L1STn Output Figure 45 SI Receive Timing Diagram with Normal Clocking DSC 0 MOTOROLA MPC850 Rev A B C Hardware Specifications 45 Serial Interface AC Electrical Specifications L1RCLK FE 1 CE 1 In
19. RCLKx and SyncCLK TCLK1x must be greater or equal to 3 1 2 Also applies to CD and CTS hold time when they are used as an external sync signals 50 MPC850 Rev A B C Hardware Specifications MOTOROLA SCC in NMSI Mode Electrical Specifications Figure 50 through Figure 52 show the NMSI timings CDx SYNC Input Figure 50 SCC NMSI Receive Timing Diagram TCLKx TXDx Output RTSx Output CTSx Input CTSx SYNC Input Figure 51 SCC NMSI Transmit Timing Diagram MOTOROLA MPC850 Rev A B C Hardware Specifications 51 Ethernet Electrical Specifications TCLKx TXDx Output RTSx Output Cee tae er lt CTSx Echo Input Figure 52 HDLC Bus Timing Diagram 8 7 Ethernet Electrical Specifications Table 20 provides the Ethernet timings as shown in Figure 53 to Figure 55 Table 20 Ethernet Timing All Frequencies Num Characteristic Unit Min Max 120 CLSNwidthhigh S Tao ls 121 RCLKx rise fall time x 2 3 for all specs in this table 15 00 ns 122 RCLKx width low 40 00 ns 123 RCLKx clock period 80 00 120 00 ns 124 RXDx setup time 20 00 ns 125 RXDx hold time 5 00 ns 126 RENA active delay from RCLKx rising edge of the last data bit 10 00 ns 127 RENA width low 100 00 ns 128 TCLKx rise fall time 15 00 ns 129 TCLKx widt
20. 26 provides the PCMCIA WAIT signals detection timing CLKOUT oe WAIT B Figure 26 PCMCIA WAIT Signal Detection Timing MOTOROLA MPC850 Rev A B C Hardware Specifications 33 Layout Practices Table 9 shows the PCMCIA port timing for the MPC850 Table 9 PCMCIA Port Timing Num Characteristic Unit P57 CLKOUT to OPx valid P58 HRESET negated to OPx drive P59 IP_Xx valid to CLKOUT rising edge ns P60 CLKOUT rising edge to IP_Xx invalid 1 00 1 00 E 1 00 ns ns ns 1 OP2 and OP3 only Figure 27 provides the PCMCIA output port timing for the MPC850 CLKOUT es Output Signals HRESET gt OP2 OP3 Figure 27 PCMCIA Output Port Timing Figure 28 provides the PCMCIA output port timing for the MPC850 CLKOUT Input Signals Figure 28 PCMCIA Input Port Timing 34 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Table 10 shows the debug port timing for the MPC850 Table 10 Debug Port Timing 50 MHz 66 MHz 80 MHz Num Characteristic Unit Min Max Min Max D61 DSCK cycle time 60 00 91 00 ns D62 DSCK clock pulse width 25 00 38 00 ns D63 DSCK rise and fall times 0 00 3 00 0 00 3 00 ns D64 DSDI input data setup time 8 00 8 00 ns D65 DSDI data hold time 5 00 5 00 ns D66 DSCK low to DSDO data valid 0 00 15 00 0 00 15 00 15 00 ns D67 DSCK low to DSDO invalid 0 00 2 00 0
21. 37 Boundary Scan JTAG Timing Diagram This section provides the AC and DC electrical specifications for the communications processor module CPM of the MPC850 8 1 PIO AC Electrical Specifications Table 13 provides the parallel I O timings for the MPC850 as shown in Figure 38 Table 13 Parallel I O Timing All Frequencies Num Characteristic Unit Min Max 29 Data in setup time to clock high 15 ns 30 Data in hold time from clock high 7 5 ns 31 Clock low to data out valid CPU writes data control or direction 25 ns MOTOROLA MPC850 Rev A B C Hardware Specifications 39 IDMA Controller AC Electrical Specifications CLKOUT DATA IN DATA OUT Figure 38 Parallel I O Data In Data Out Timing Diagram 8 2 IDMA Controller AC Electrical Specifications Table 14 provides the IDMA controller timings as shown in Figure 39 to Figure 42 Table 14 IDMA Controller Timing All Frequencies Num Characteristic Unit Min Max 40 DREQ setup time to clock high 7 00 ns 41 DREQ hold time from clock high 3 00 ns 42 SDACK assertion delay from clock high 12 00 ns 43 SDACK negation delay from clock low 12 00 ns 44 SDACK negation delay from TA low 20 00 ns 45 SDACK negation delay from clock high 15 00 ns 46 ITA assertion to falling edge of the clock setup time applies to external TA 7 00 ns CLKOUT Output 41
22. 4 5M 1994 D2 2 DIMENSIONS IN MILLIMETERS 3 DIMENSION b IS MEASURED AT THE MAXIMUM l SOLDER BALL DIAMETER PARALLEL TO PRIMARY 0 35 7 DATUM C 4 PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS as 256X ol 0 20 C MILLIMETERS DIM MIN MAX A 191 2 35 E E2 A1 0 50 070 A2 TOP VIEW e 1 27 BSC A1 A Cc A2 112 122 A3 0 29 043 b 0 60 0 90 D 23 00BSC Di 19 05 REF D2 19 00 20 00 4x E 23 00BSC o 0 20 E1 19 05 REF E2 19 00 20 00 D1 15x e SEATING PLANE SIDE VIEW ooooooo0o00000000 ooooo0oo0o000000000 ooooooo0o000000000 ooooo0oo0000000000 ooooo0oo0oo000000000 ooooo0o0000000000 oooooooo0oo0oo000000 ooooo0oo0000000000 ooooo0oo0o000000000 oooo0o0000000000 ooooo0o00o0000000 oooooo0oo0o0000000 oooo0oo0o000000000 o o o o o o o o o 0 0 0 o o o 200000900000000 000000d l00000000 o000 woomnNng re ArszZz0y AC oooo0oo0o000 2 345 6 7 8 9 10111213141516 17 256X Ob 0 30 W C A B 0150C BOTTOM VIEW CASE 1130 01 ISSUE B Figure 65 Package Dimensions for the Plastic Ball Grid Array PBGA JEDEC Standard 66 MPC850 Rev A B C Hardware Specifications MOTOROLA Pin Assignments and Mechanical Dimensions of the PBGA Part X Document Revisio
23. 50 bus shown assumes a 50 pF load This timing can be derated by 1 ns per 10 pF Derating calculations can also be performed using the MPC850 Electrical Specifications Spreadsheet 10 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Table 6 Bus Operation Timing 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B1 CLKOUT period 20 30 30 25 ns Bla EXTCLK to CLKOUT phase 0 90 0 90 0 90 0 90 0 90 0 90 50 00 ns skew EXTCLK gt 15 MHz and MF lt 2 Bib EXTCLK to CLKOUT phase 2 30 2 30 2 30 2 30 2 30 2 30 50 00 ns skew EXTCLK gt 10 MHz and MF lt 10 Bic CLKOUT phase jitter EXTCLK gt 0 60 0 60 0 60 0 60 0 60 0 60 50 00 ns 15 MHz and MF lt 2 Bid CLKOUT phase jitter 2 00 2 00 2 00 2 00 2 00 2 00 50 00 ns Ble CEKOUT frequency jitter MF lt 0 50 0 50 0 50 50 00 10 B1f CLKOUT frequency jitter 10 lt 2 00 200 2 00 50 00 MF lt 500 Big CLKOUT frequency jitter MF gt 3 00 3 00 3 00 50 00 500 Bih Frequency jitter on EXTCLK 0 50 0 50 0 50 50 00 B2 CLKOUT pulse width low 8 00 12 12 10 00 50 00 ns B3 CLKOUT width high 8 00 12 12 10 00 50 00 n
24. D Cache gt Load Store Data Real Time Clock Bus MMU Bus Interface Unit System Functions PCMCIA Interface Communications Baud Rate Four Interrupt Dual Port Processor Generators Timers Controller RAM EEN Module Channels aos VO 32 Bit RISC Communications and ors Processor CP and Program ROM 2 Virtual UTOPIA IDMA 850SAR Timer Channels Peripheral Bus a SCC3 SMC1 lt N Time Slot Assigner Non Multiplexed Serial Interface Figure 1 MPC850 Microprocessor Block Diagram The following list summarizes the main features of the MPC850 e Embedded single issue 32 bit MPC8xx core implementing the PowerPC architecture with thirty two 32 bit general purpose registers GPRs Performs branch folding and branch prediction with conditional prefetch but without conditional execution MOTOROLA MPC850 Rev A B C Hardware Specifications 3 2 Kbyte instruction cache and 1 Kbyte data cache Harvard architecture Caches are two way set associative Physically addressed Cache blocks can be updated with a 4 word line burst Least recently used LRU replacement algorithm Lockable one line granularity Memory management units MMUs with 8 entry translation lookaside buffers TLBs and fully associative instruction and data TLBs MMwUs support multiple page size
25. Minimum input setup time specification 0 Minimum input hold time specification Figure 2 Control Timing 18 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Figure 3 provides the timing for the external clock CLKOUT Figure 4 provide Figure 3 External Clock Timing s the timing for the synchronous output signals CLKOUT ee ee eee ee ee Output Signals Output Signals Output Signals MOTOROLA Pi D Figure 4 Synchronous Output Signals Timing MPC850 Rev A B C Hardware Specifications 19 Layout Practices Figure 5 provides the timing for the synchronous active pull up and open drain output signals CLKOUT TEA Figure 5 Synchronous Active Pullup and Open Drain Outputs Signals Timing Figure 6 provides the timing for the synchronous input signals oor fff i Figure 6 Synchronous Input Signals Timing 20 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Figure 7 provides normal case timing for input data CLKOUT Ff SF RF e wwa OO O O ONKO OAN DP 0 3 Figure 7 Input Data Timing in Normal Case Figure 8 provides the timing for the input data controlled by the UPM in the memory controller CLKOUT O F w o o o ee D 0 31 DP 0 3 Figure 8 Input Data Timing when Controlled by UPM in the Memory Controller MOTOROLA MPC850 Rev
26. Q D D a O O w N N PA4 PB16 PD15 PD12 PD7 PD6 O O O w N D Q gt o PD9 PD4 O p 4 g O 2 N ue Q 0 wD Le f O O O O is fa i iw me O O OO O OOQ O O O Q Z E w O 50O O iw 00000000 O O TSIZO OO0000 0 0 O iw s N is O 5O D N is ie a olo O O TSIZ1 N C O O Q WEO WE2 GPLA3 CS5 CSO GPLA4 0000000 0 0 0 0000000 0 O O O O O O O O O O O O O O O O O O 00000 o0000 O 4 n ae w x H ae w N T Fas s e s Q tt x O G 4 O GPLA1 GPLA2 CS6 WR GPLA5 TEA oo0o0o 0 cs4 cs7 CcS2 GPLB4 BI BR OO0O000 0 N C Cs3 CS1 BDIP TA BB las las w H S Q RSTCONF W AITB s U 00 O O O w q D n 4 H in w ES D ps H S 0 D H lis w Ww as D B 5 is Figure 63 Pin Assignments for the PBGA Top View JEDEC Standard For more information on the printed circuit board layout of the PBGA package including thermal via design and suggested pad layout please refer to AN 1231 D Plastic Ball Grid Array Application Note available from your local Motorola sales office 64 MPC850 Rev A B C Hardware Specifications MOTOROLA Pin Assignments and Mechanical Dimensions of the PBGA Figure 64 shows the non JEDEC package dimensions of the PBGA A D NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y14 5M 1994 D2 2 DIMENSION
27. S IN MILLIMETERS 3 DIMENSION b IS MEASURED AT THE MAXIMUM l SOLDER BALL DIAMETER PARALLEL TO PRIMARY 0 35 7 DATUM C 4 PRIMARY DATUM C AND THE SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS a 256X ol 0 20 C MILLIMETERS DIM MIN MAX A 191 2 35 E E2 A1 0 50 070 A2 112 122 A3 0 29 043 b 0 60 0 90 D 23 00BSC Di 19 05 REF D2 19 00 20 00 4x E 23 00BSC E1 19 05 REF E2 19 00 20 00 A2 TOP VIEW e 1 27 BSC A3 B A1 A D1 C 15X e SEATING PLANE SIDE VIEW 200000900000000 000000d 00000000 0000000 i00000000 000000000000000 0000000000000000 000000000000000 000000000000000 0000000 I00000000 000000000000000 000000000000000 000000000000000 OC0000000000000 000000 l00000000 000000jl00000000 000000jl00000000 o o o o o o o o o 0 0 0 o o o o000 rPIamoomnNng re ArszZz0uy 4 oooo0oo0o000 12345 6 7 8 9 101112131415 16 256X Ob 0 30 M C A B 0150C BOTTOM VIEW Figure 64 Package Dimensions for the Plastic Ball Grid Array PBGA non JEDEC Standard MOTOROLA MPC850 Rev A B C Hardware Specifications 65 Pin Assignments and Mechanical Dimensions of the PBGA Figure 65 shows the JEDEC package dimensions of the PBGA A D NOTES 1 DIMENSIONING AND TOLERANCING PER ASME Y1
28. SDO Part V Power Considerations The average chip junction temperature Ty in C can be obtained from the equation Ty T Pp 9 1 where T A Ambient temperature C 9 A Package thermal resistance junction to ambient C W Py PinrtPyo Pwr Ipp X Vpp Watts chip internal power Pig Power dissipation on input and output pins user determined MOTOROLA MPC850 Rev A B C Hardware Specifications 9 Layout Practices For most applications P o lt 0 3 e Pyr and can be neglected If P is neglected an approximate relationship between P and T is Pp K T 273 C 2 Solving equations 1 and 2 for K gives 2 K Pp T 273 C 04 Pp 3 where K is a constant pertaining to the particular part K can be determined from equation 3 by measuring P_ at equilibrium for a known T Using this value of K the values of P and T can be obtained by solving equations 1 and 2 iteratively for any value of T R 5 1 Layout Practices Each Vcc pin on the MPC850 should be provided with a low impedance path to the board s supply Each GND pin should likewise be provided with a low impedance path to ground The power supply pins drive distinct groups of logic on chip The Vcc power supply should be bypassed to ground using at least four 0 1 uF by pass capacitors located as close as possible to the four sides of the package The capacitor leads and associated printed circuit traces connecting t
29. a out high impedance R80 DSDI DSCK set up 60 00 90 00 75 00 3 000 R81 DSDI DSCK hold time 0 00 0 00 0 00 R82 SRESET negated to CLKOUT rising 160 00 242 00 200 00 8 000 edge for DSDI and DSCK sample Figure 31 shows the reset timing for the data bus configuration 36 HRESET ee Ges is R71 RSTCONF e R73 2 NEJ Figure 31 Reset Timing Configuration from Data Bus MPC850 Rev A B C Hardware Specifications MOTOROLA Figure 32 provides the reset timing for the data bus weak drive during configuration CLKOUT fa i ar RSTCONF HRESET Z D 0 31 OUT Figure 33 provides the reset timing for the debug port configuration SRESET y R80 R80 gt E DSCK DSDI Weak o fF 0 Layout Practices Figure 32 Reset Timing Data Bus Weak Drive during Configuration Figure 33 Reset Timing Debug Port Configuration Part VII IEEE 1149 1 Electrical Specifications Table 12 provides the JTAG timings for the MPC850 as shown in Figure 34 to Figure 37 Table 12 JTAG Timing 50 MHz 66MHz 80 MHz Num Characteristic Unit Min Max Min Max Min Max J82 TCK cycle time 100 00 100 00 100 00 ns J83 TCK clock pulse width measured at 1 5 V 40 00 40 00 40 00 ns J84 TCK rise and fall times 0 00 10 00 0 00 10 00 0 00 10 00
30. aken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level for example either GND or Vcc Table 3 provides the package thermal characteristics for the MPC850 MOTOROLA MPC850 Rev A B C Hardware Specifications Part IV Thermal Characteristics Table 3 shows the thermal characteristics for the MPC850 Table 3 Thermal Characteristics 1 Characteristic Symbol Value Unit Thermal resistance for BGA 1 OJA 402 C W OJA 313 C W OJA 244 C W Thermal Resistance for BGA junction to case Nos 8 C W For more information on the design of thermal vias on multilayer boards and BGA layout considerations in general refer to AN 1231 D Plastic Ball Grid Array Application Note available from your local Motorola sales office 2 Assumes natural convection and a single layer board no thermal vias 3 Assumes natural convection a multilayer board with thermal vias 1 watt MPC850 dissipation and a board temperature rise of 20 C above ambient 4 Assumes natural convection a multilayer board with thermal vias 1 watt MPC850 dissipation and a board temperature rise of 13 C above ambient Ty Tat Pp e a Pp Vpp e lbp Pio where Pro is the power dissipation on pins Table 4 provides power dissipation information Table 4 Power Dissipati
31. cs clocking Allows dynamic changes Can be internally connected to four serial channels two SCCs and two SMCs Low power support Full high all units fully powered at high clock frequency Full low all units fully powered at low clock frequency Doze core functional units disabled except time base decrementer PLL memory controller real time clock and CPM in low power standby Sleep all units disabled except real time clock and periodic interrupt timer PLL is active for fast wake up Deep sleep all units disabled including PLL except the real time clock and periodic interrupt timer Low power stop to provide lower power dissipation Separate power supply input to operate internal logic at 2 2 V when operating at or below 25 MHz Can be dynamically shifted between high frequency 3 3 V internal and low frequency 2 2 V internal operation Debug interface Eight comparators four operate on instruction address two operate on data address and two operate on data MPC850 Rev A B C Hardware Specifications MOTOROLA The MPC850 can compare using the lt and gt conditions to generate watchpoints Each watchpoint can generate a breakpoint internally e 3 3 V operation with 5 V TTL compatibility on all general purpose I O pins Part Ill Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics
32. d in the UPM B32c CLKOUT rising edge to BS valid 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns as requested by control bit BST3 in the corresponding word in the UPM B32d CLKOUT falling edge to BS valid 9 00 14 00 13 00 18 00 11 00 16 00 0 375 50 00 ns as requested by control bit BST1 in the corresponding word in the UPM EBDF 1 B33 CLKOUT falling edge to GPL 1 50 6 00 1 50 6 00 1 50 6 00 50 00 ns valid as requested by control bit GxT4 in the corresponding word in the UPM B33a CLKOUT rising edge to GPL 5 00 12 00 8 00 14 00 6 00 13 00 0 250 50 00 ns valid as requested by control bit GxT3 in the corresponding word in the UPM B34 A 6 31 and D 0 31 to CS valid 3 00 6 00 4 00 0 250 50 00 ns as requested by control bit CST4 in the corresponding word in the UPM B34a A 6 31 and D 0 31 to CS valid 8 00 13 00 11 00 0 500 50 00 ns as requested by control bit CST1 in the corresponding word in the UPM B34b A 6 31 and D 0 31 to CS valid 13 00 21 00 17 00 0 750 50 00 ns as requested by CST2 in the corresponding word in UPM B35 A 6 31 to CS valid as 3 00 6 00 4 00 0 250 50 00 ns requested by control bit BST4 in the corresponding word in UPM B35a A 6 31 and D 0 31 to BS valid 8 00 13 00 11 00 0 500 50 00 ns as requested by BST1 in the correspo
33. d on reference match and event capture e Interrupts Eight external interrupt request IRQ lines Twelve port pins with interrupt capability Fifteen internal interrupt sources Programmable priority among SCCs and USB Programmable highest priority request e Single socket PCMCIA ATA interface Master socket interface release 2 1 compliant Single PCMCIA socket Supports eight memory or I O windows e Communications processor module CPM 32 bit Harvard architecture scalar RISC communications processor CP Protocol specific command sets for example GRACEFUL STOP TRANSMIT stops transmission after the current frame is finished or immediately if no frame is being sent and CLOSE RXBD closes the receive buffer descriptor Supports continuous mode transmission and reception on all serial channels Upto 8 Kbytes of dual port RAM Twenty serial DMA SDMA channels for the serial controllers including eight for the four USB endpoints Three parallel I O registers with open drain capability e our independent baud rate generators BRGs Can be connected to any SCC SMC or USB Allow changes during operation Autobaud support option e Two SCCs serial communications controllers Ethernet IEEE 802 3 supporting full 10 Mbps operation HDLC SDLC all channels supported at 2 Mbps HDLC bus implements an HDLC based local area network LAN Asynchronous HDLC to su
34. ed to A 6 31 3 00 6 00 4 00 0 250 50 00 ns invalid GPCM write access 9 B30a WE 0 3 negated to A 6 31 8 00 13 00 11 00 0 500 50 00 ns invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 14 MPC850 Rev A B C Hardware Specifications MOTOROLA Num Table 6 Bus Operation Timing 1 continued Characteristic Min Min FFACT Layout Practices Cap Load default 50 pF Unit B30b B30c WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 6 31 Invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 CS negated to A 6 31 invalid GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 28 00 5 00 43 00 8 00 1 500 0 375 50 00 50 00 ns ns B30d WE 0 3 negated to A 6 31 invalid GPCM write access TRLX 1 CSNT 1 CS negated to A 6 31 invalid GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 25 00 39 00 31 00 1 375 50 00 ns B31 CLKOUT falling edge to CS valid as requested by control bit CST4 in the corresponding word in the UPM 1 50 6 00 1 50 1 50 50 00 ns B31a CLKOUT falling edge to CS valid
35. er descriptor at the end of the frame transmission Figure 55 Ethernet Transmit Timing Diagram 8 8 SMC Transparent AC Electrical Specifications Figure 21 provides the SMC transparent timings as shown in Figure 56 Table 21 Serial Management Controller Timing All Frequencies Num Characteristic Unit Min Max 150 SMCLKx clock period 100 00 ns 151 SMCLKx width low 50 00 E ns 151a SMCLKx width high 50 00 ns 152 SMCLKx rise fall time 15 00 ns 153 SMTXDx active delay from SMCLKx falling edge 10 00 50 00 ns 154 SMRXDx SMSYNx setup time 20 00 ns 155 SMRXDx SMSYNx hold time 5 00 ns 1 The ratio SyncCLK SMCLKx must be greater or equal to 2 1 54 MPC850 Rev A B C Hardware Specifications MOTOROLA SPI Master AC Electrical Specifications SMCLKx SMTXDx Output NOTE nae Re 59 lt ___ SMSYNx ae SMRXDx Input NOTE 1 This delay is equal to an integer number of character length clocks Figure 56 SMC Transparent Timing Diagram 8 9 SPI Master AC Electrical Specifications Table 22 provides the SPI master timings as shown in Figure 57 and Figure 58 Table 22 SPI Master Timing All Frequencies Num Characteristic Unit Min Max 160 MASTER cycle time 4 1024 teyc 161 MASTER clock SCK high or low time 2 512 toyc 162 MASTER data setup time inputs 50 00 ns 163 Master data hold time inputs 0 00 ns
36. for the MPC850 Table 2 provides the maximum ratings Table 2 Maximum Ratings GND OV Rating Symbol Value Unit Supply voltage VDDH 0 3 to 4 0 VDDL 0 3 to 4 0 V KAPWR 0 3 to 4 0 V VDDSYN 0 3 to 4 0 V Input voltage Vin GND 0 3 to VDDH 2 5 V V Junction temperature 2 T 0 to 95 standard C 40 to 95 extended Storage temperature range Tstg 55 to 150 C 1 Functional operating conditions are provided with the DC electrical specifications in Table 5 Absolute maximum ratings are stress ratings only functional operation at the maxima is not guaranteed Stress beyond those listed may affect device reliability or cause permanent damage to the device CAUTION All inputs that tolerate 5 V cannot be more than 2 5 V greater than the supply voltage This restriction applies to power up and normal operation that is if the MPC850 is unpowered voltage greater than 2 5 V must not be applied to its inputs The MPC850 a high frequency device in a BGA package does not provide a guaranteed maximum ambient temperature Only maximum junction temperature is guaranteed It is the responsibility of the user to consider power dissipation and thermal management Junction temperature ratings are the same regardless of frequency rating of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however it is advised that normal precautions be t
37. h low 40 00 ns 130 TCLKx clock period 99 00 101 00 ns 131 TXDx active delay from TCLKx rising edge 10 00 50 00 ns 132 TXDx inactive delay from TCLKx rising edge 10 00 50 00 ns 52 MPC850 Rev A B C Hardware Specifications MOTOROLA Ethernet Electrical Specifications Table 20 Ethernet Timing continued All Frequencies Num Characteristic Unit Min Max 133 TENA active delay from TCLKx rising edge 10 00 50 00 ns 134 TENA inactive delay from TCLKx rising edge 10 00 50 00 ns 138 CLKOUT low to SDACK asserted 20 00 ns 139 CLKOUT low to SDACK negated 2 20 00 ns The ratios SyncCLK RCLKx and SyncCLK TCLKx must be greater or equal to 2 1 1 2 SDACK is asserted whenever the SDMA writes the incoming frame destination address into memory CLSN CTSx Input 420 ae Figure 53 Ethernet Collision Timing Diagram RCLKx EOGI PEC a RXDx VA VJVVVVVVWVVVW Input OVANA lt RENA CDx Input Figure 54 Ethernet Receive Timing Diagram MOTOROLA MPC850 Rev A B C Hardware Specifications 53 SMC Transparent AC Electrical Specifications TCLKx TxDx Output TENA RTSx Input RENA CDx Input NOTE 2 ______ NOTES 1 Transmit clock invert TCI bit in GSMR is set 2 If RENA is deasserted before TENA or RENA is not asserted at all during transmit then the CSL bit is set in the buff
38. he MPC850 integrates system functions such as a versatile memory controller and a communications processor module CPM that incorporates a specialized independent RISC communications processor referred to as the CP This separate processor off loads peripheral tasks from the embedded MPC8xx core The CPM of the MPC850 supports up to seven serial channels as follows e One or two serial communications controllers SCCs The SCCs support Ethernet ATM MPC850SAR HDLC and a number of other protocols along with a transparent mode of operation e One USB channel e Two serial management controllers SMCs e One IC port e One serial peripheral interface SPI Table 1 shows the functionality supported by the members of the MPC850 family Table 1 MPC850 Functionality Matrix MPC850SAR Yes Yes number et Ethernet Multi channel puteper et Part SCCs Support ATM Support USB Support HDLC Support PCMCIA Slots Supported PP PP Supported MPC850 1 Yes Yes 1 MPC850DE 2 Yes Yes 1 Additional documentation may be provided for parts listed in Table 1 MPC850 Rev A B C Hardware Specifications MOTOROLA Part ll Features Figure 1 is a block diagram of the MPC850 showing its major components and the relationships among those components 2 Kbyte System Interface Unit I Cache Embedded Instruction Instruction Memory Controller MPC8xx Bus MMU Unified Bus Core 1 Kbyte
39. lculated for all frequency dependent AC parameters Frequency dependent AC parameters are those with an entry in the FFactor column AC parameters without an FFactor entry do not need to be calculated and can be taken directly from the frequency column corresponding to the frequency marked on the part The following equations should be used in these calculations For a frequency F the following equations should be applied to each one of the above parameters For minima FFACTOR x 1000 Dso 20 x FFACTOR 7 F For maxima FFACTOR x 1000 D5 20 x FFACTOR 1ns CAP LOAD 50 10 7 F where D is the parameter value to the frequency required in ns F is the operation frequency in MHz Dsg is the parameter value defined for 50 MHz CAP LOAD is the capacitance load on the signal in question Ea is the one defined for each of the parameters in the table Phase and frequency jitter performance results are valid only if the input jitter is less than the prescribed value If the rate of change of the frequency of EXTAL is slow i e it does not jump between the minimum and maximum values in one cycle or the frequency of the jitter is fast i e it does not stay at an extreme value for a long time then the maximum allowed jitter on EXTAL can be up to 2 The timing for BR output is relevant when the MPC850 is selected to work with external bus arbiter The timing for BG output is relevant when the MPC850 is selected to work with inter
40. n History Table 28 lists significant changes between revisions of this document 67 Table 28 Document Revision History Revision Date Change 0 1 11 2001 Removed reference to 5 Volt tolerance capability on peripheral interface pins Replaced SI and IDL timing diagrams with better images Put into new template added this revision table 0 2 04 2002 Put in the new power numbers and added Rev C MPC850 Rev A B C Hardware Specifications MOTOROLA HOW TO REACH US USA EUROPE LOCATIONS NOT LISTED Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 TECHNICAL INFORMATION CENTER 1 800 521 6274 HOME PAGE http Awww motorola com semiconductors DOCUMENT COMMENTS FAX 512 933 2625 Attn RISC Applications Engineering Information in this document is provided solely to enable system and software implementers to use Motorola products There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Motorola reserves the right to make changes withou
41. nal bus arbiter The setup times required for TA TEA and BI are relevant only when they are supplied by an external device and not when the memory controller or the PCMCIA interface drives them The timing required for BR input is relevant when the MPC850 is selected to work with the internal bus arbiter The timing for BG input is relevant when the MPC850 is selected to work with the external bus arbiter 7 The D 0 31 and DP 0 3 input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted 3 MOTOROLA MPC850 Rev A B C Hardware Specifications 17 Layout Practices 8 The D 0 31 and DP 0 3 input timings B20 and B21 refer to the falling edge of CLKOUT This timing is valid only for read accesses controlled by chip selects controlled by the UPM in the memory controller for data beats where DLT3 1 inthe UPM RAM words This is only the case where data is latched on the falling edge of CLKOUT 9 The timing B30 refers to CS when ACS 00 and to WE 0 3 when CSNT 0 10 The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals 11 The AS signal is considered asynchronous to CLKOUT Figure 2 is the control timing diagram CLKOUT Outputs Outputs Inputs Inputs A Maximum output delay specification B Minimum output hold time
42. nding word in the UPM B35b A 6 31 and D 0 31 to BS valid 13 00 21 00 17 00 0 750 50 00 ns as requested by control bit BST2 in the corresponding word in the UPM B36 A 6 31 and D 0 31 to GPL 3 00 6 00 4 00 0 250 50 00 ns valid as requested by control bit GxT4 in the corresponding word in the UPM 16 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Table 6 Bus Operation Timing 1 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B37 UPWAIT valid to CLKOUT falling 6 00 6 00 6 00 50 00 ns edge i B38 CLKOUT falling edge to UPWAIT 1 00 1 00 1 00 50 00 ns valid 1 B39 Foy valid to CLKOUT rising edge 7 00 7 00 7 00 50 00 ns B40 A 6 31 TSIZ O 1 RD WR 7 00 7 00 7 00 50 00 ns BURST valid to CLKOUT rising edge B41 TS valid to CLKOUT rising edge 7 00 7 00 7 00 50 00 ns setup time B42 CLKOUT rising edge to TS valid 2 00 2 00 2 00 50 00 ns hold time B43 AS negation to memory TBD TBD TBD 50 00 ns controller signals negation The minima provided assume a 0 pF load whereas maxima assume a 50pF load For frequencies not marked on the part new bus timing must be ca
43. njury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Motorola and the Stylized M Logo are registered in the U S Patent and Trademark Office digital dna is a trademark of Motorola Inc All other product or service names are the property of their respective owners Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola Inc 2002 MPC850EC D
44. o chip Vcc and GND should be kept to less than half an inch per capacitor lead A four layer board is recommended employing two inner layers as Vcc and GND planes All output pins on the MPC850 have fast rise and fall times Printed circuit PC trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times This recommendation particularly applies to the address and data busses Maximum PC trace lengths of six inches are recommended Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PC traces Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the Vcc and GND circuits Pull up all unused inputs or signals that will be inputs during reset Special care should be taken to minimize the noise levels on the PLL supply pins Part VI Bus Signal Timing Table 6 provides the bus operation timing for the MPC850 at 50 MHz 66 MHz and 80 MHz Timing information for other bus speeds can be interpolated by equation using the MPC850 Electrical Specifications Spreadsheet found at http www mot com netcomm The maximum bus speed supported by the MPC850 is 50 MHz Higher speed parts must be operated in half speed bus mode for example an MPC850 used at 66 MHz must be configured for a 33 MHz bus The timing for the MPC8
45. on Pp Characteristic Frequency MHz Typical Maximum Unit Power Dissipation 33 TBD 515 mW All Revisions 1 1 Mode 40 TBD 590 mW 50 TBD 725 mW 1 Typical power dissipation is measured at 3 3V Maximum power dissipation is measured at 3 65 V Table 5 provides the DC electrical characteristics for the MPC850 Table 5 DC Electrical Specifications Characteristic Symbol Min Max Unit Operating voltage at 40 MHz or less VDDH VDDL 3 0 3 6 V KAPWR VDDSYN Operating voltage at 40 MHz or higher VDDH VDDL 3 135 3 465 V KAPWR VDDSYN Input high voltage address bus data bus EXTAL EXTCLK VIH 2 0 3 6 V and all bus control status signals Input high voltage all general purpose I O and peripheral pins VIH 2 0 5 5 V 8 MPC850 Rev A B C Hardware Specifications MOTOROLA Table 5 DC Electrical Specifications continued Characteristic Symbol Min Max Unit Input low voltage VIL GND 0 8 V EXTAL EXTCLK input high voltage VIHC 0 7 VCC VCC 0 3 V Input leakage current Vin 5 5 V Except TMS TRST DSCK lin 100 uA and DSDI pins Input leakage current Vin 3 6V Except TMS TRST DSCK lin 10 uA and DSDI pins Input leakage current Vin OV Except TMS TRST DSCK and lin 10 uA DSDI pins Input capacitance Cin 20 pF Output high voltage IOH 2 0 mA VDDH 3 0V VOH 2 4 V except XTAL XFC and open drain pins O
46. pport PPP point to point protocol AppleTalk Universal asynchronous receiver transmitter UART Synchronous UART Serial infrared IrDA Totally transparent bit streams Totally transparent frame based with optional cyclic redundancy check CRC e QUICC multichannel controller QMC microcode features Up to 64 independent communication channels on a single SCC Arbitrary mapping of 0 31 channels to any of 0 31 TDM time slots MOTOROLA MPC850 Rev A B C Hardware Specifications Supports either transparent or HDLC protocols for each channel Independent TxBDs Rx and event interrupt reporting for each channel One universal serial bus controller USB Supports host controller and slave modes at 1 5 Mbps and 12 Mbps Two serial management controllers SMCs UART Transparent General circuit interface GCI controller Can be connected to the time division multiplexed TDM channel One serial peripheral interface SPI Supports master and slave modes Supports multimaster operation on the same bus One I C interprocessor integrated circuit port Supports master and slave modes Supports multimaster environment Time slot assigner Allows SCCs and SMCs to run in multiplexed operation Supports T1 CEPT PCM highway ISDN basic rate ISDN primary rate user defined l or 8 bit resolution Allows independent transmit and receive routing frame syn
47. put L1RCLK FE 0 CE 0 Input L1RSYNC Input L1RXD Input L1ST 4 1 Output L1CLKO Output Figure 46 SI Receive Timing with Double Speed Clocking DSC 1 46 MPC850 Rev A B C Hardware Specifications MOTOROLA Serial Interface AC Electrical Specifications LITCLK FE 0 CE 0 Input LITCLK FE 1 CE 1 Input LITSYNC Input L1TxD Output o L1STn Output Figure 47 SI Transmit Timing Diagram MOTOROLA MPC850 Rev A B C Hardware Specifications 47 Serial Interface AC Electrical Specifications L1RCLK FE 0 CE 0 Input L1RCLK FE 1 CE 1 Input L1RSYNC Input L1TXD Output L1ST 4 1 Output L1CLKO Output 48 Figure 48 SI Transmit Timing with Double Speed Clocking DSC 1 MPC850 Rev A B C Hardware Specifications MOTOROLA Serial Interface AC Electrical Specifications lt ndu YO indjno oyt indjno L p LSI ndu axati ndino ax 1 ndu ONASYI1 indu y8 41 Figure 49 IDL Timing 49 MPC850 Rev A B C Hardware Specifications MOTOROLA SCC in NMSI Mode Electrical Specifications 8 6 SCC in NMSI Mode Electrical Specifications Table 18 provides the NMSI external clock timing Table 18 NMSI External Clock Timing All Frequencies
48. ration Timing 1 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B29b CS negated to D O 31 DP 0 3 3 00 6 00 400 0 250 50 00 ns high Z GPCM write access ACS 00 TRLX 0 amp CSNT 0 B29c CS negated to D 0O 31 DP O 3 8 00 13 00 11 00 0 500 50 00 ns high Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 0 B29d WE 0 3 negated to D O 31 28 00 43 00 36 00 1 500 50 00 ns DP 0 3 high Z GPCM write access TRLX 1 CSNT 1 EBDF 0 B29e CS negated to D O 31 DP O 3 28 00 43 00 36 00 1 500 50 00 ns high Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 0 B29f WE 0 3 negated to D O 31 5 00 9 00 7 00 0 375 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 EBDF 1 B29g CS negated to D O 31 DP 0 3 5 00 9 00 7 00 0 375 50 00 ns high Z GPCM write access TRLX 0 CSNT 1 ACS 10 or ACS 11 EBDF 1 B29h WE 0 3 negated to D O 31 25 00 39 00 31 00 1 375 50 00 ns DP 0 3 high Z GPCM write access TRLX 0 CSNT 1 EBDF 1 B29i CS negated to D 0 31 DP 0 3 25 00 39 00 31 00 1 375 50 00 ns high Z GPCM write access TRLX 1 CSNT 1 ACS 10 or ACS 11 EBDF 1 B30 CS WE 0 3 negat
49. s B4 CLKOUT rise time 400 400 4 00 50 00 ns B5 CLKOUT fall time 400 400 4 00 50 00 ns B7 CLKOUT to A 6 31 5 00 7 58 625 0 250 50 00 ns RD WR BURST D 0 31 DP 0 3 invalid B7a CLKOUT to TSIZ 0 1 REG 5 00 7 58 625 0 250 50 00 ns RSV AT 0 3 BDIP PTR invalid B7b CLKOUT to BR BG FRZ 5 00 7 58 625 0 250 50 00 ns VFLS 0 1 VF 0 2 IWP 0 2 LWP 0 1 STS invalid 4 B8 CLKOUT to A 6 31 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns RDR BURST D 0 31 DP 0 3 valid B8a CLKOUT to TSIZ 0 1 REG 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns RSV AT 0 3 BDIP PTR valid B8b CLKOUT to BR BG VFLS 0 1 5 00 11 74 7 58 14 33 6 25 13 00 0 250 50 00 ns VF 0 2 IWP 0 2 FRZ LWP 0 1 STS valid 4 B9 CLKOUT to A 6 31 RD WR 5 00 11 75 7 58 14 33 6 25 13 00 0 250 50 00 ns BURST D 0 31 DP 0 3 TSIZ 0 1 REG RSV AT 0 3 PTR high Z MOTOROLA MPC850 Rev A B C Hardware Specifications 11 Layout Practices Table 6 Bus Operation Timing 1 continued 50 MHz 66 MHz 80 MHz Cap Load Num Characteristic FFACT default Unit Min Max Min Max Min Max 50 pF B11 CLKOUT to TS BB assertion 5 00 11 00 7 58 13 58 6 25 12 25 0 250 50 00 ns Bi1a CLKOUT to TA BI assertion 2 50 9 25 2 50
50. s 29 Layout Practices Figure 20 provides the timing for the asynchronous external master memory access controlled by the GPCM AS A 6 31 TSIZ O 1 R W CSx Figure 20 Asynchronous External Master Memory Access Timing GPCM Controlled ACS 00 Figure 21 provides the timing for the asynchronous external master control signals negation AS _ s CSx WE 0 3 OE GPLx BS 0 3 Figure 21 Asynchronous External Master Control Signals Negation Timing Table 7 provides interrupt timing for the MPC850 Table 7 Interrupt Timing 50 MHz 66MHz 80 MHz Num Characteristic 1 Unit Min Max Min Max Min Max 139 IRQx valid to CLKOUT rising edge set up time 6 00 6 00 6 00 ns 140 IRQx hold time after CLKOUT 2 00 2 00 2 00 ns 141 IRQx pulse width low 3 00 3 00 3 00 ns 142 IRQx pulse width high 3 00 3 00 3 00 ns 143 IRQx edge to edge time 80 00 121 0 100 0 ns 1 The timings 139 and 140 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT The timings 141 142 and 143 are specified to allow the correct function of the IRQ lines detection circuitry and has no direct relation with the total system interrupt latency that the MPC850 is able to
51. s of 4 Kbytes 16 Kbytes 256 Kbytes 512 Kbytes and 8 Mbytes 16 virtual address spaces and eight protection groups Advanced on chip emulation debug mode Data bus dynamic bus sizing for 8 16 and 32 bit buses Supports traditional 68000 big endian traditional x86 little endian and modified little endian memory systems Twenty six external address lines Completely static design 0 80 MHz operation System integration unit SIU Hardware bus monitor Spurious interrupt monitor Software watchdog Periodic interrupt timer Low power stop mode Clock synthesizer Decrementer time base and real time clock RTC from the PowerPC architecture Reset controller IEEE 1149 1 test access port JTAG Memory controller eight banks Glueless interface to DRAM single in line memory modules SIMMs synchronous DRAM SDRAM static random access memory SRAM electrically programmable read only memory EPROM flash EPROM etc Memory controller programmable to support most size and speed memory interfaces Boot chip select available at reset options for 8 16 or 32 bit memory Variable block sizes 32 Kbytes to 256 Mbytes Selectable write protection On chip bus arbiter supports one external bus master Special features for burst mode support General purpose timers Four 16 bit timers or two 32 bit timers Gate mode can enable disable counting MPC850 Rev A B C Hardware Specifications MOTOROLA Interrupt can be maske
52. support 30 MPC850 Rev A B C Hardware Specifications MOTOROLA Layout Practices Figure 22 provides the interrupt detection timing for the external level sensitive lines CLKOUT IRQx Figure 22 Interrupt Detection Timing for External Level Sensitive Lines Figure 23 provides the interrupt detection timing for the external edge sensitive lines CLKOUT IRQx a e 143 gt ey Figure 23 Interrupt Detection Timing for External Edge Sensitive Lines Table 8 shows the PCMCIA timing for the MPC850 Table 8 PCMCIA Timing 50MHz 66MHz 80 MHz Num Characteristic FFACTOR Unit Min Max Min Max Min Max P44 A 6 31 REG valid to PCMCIA strobe 13 00 21 00 17 00 0 750 ns asserted P45 A 6 31 REG valid to ALE negation 18 00 28 00 23 00 1 000 ns P46 CLKOUT to REG valid 5 00 13 00 8 00 16 00 6 00 14 00 0 250 ns P47 CLKOUT to REG Invalid 6 00 9 00 7 00 0 250 ns P48 CLKOUT to CE1 CE2 asserted 5 00 13 00 8 00 16 00 6 00 14 00 0 250 P49 CLKOUT to CE1 CE2 negated 5 00 13 00 8 00 16 00 6 00 14 00 0 250 ns P50 CLKOUT to PCOE IORD PCWE IOWR 11 00 11 00 11 00 ns assert time p54 CLKOUT to PCOE IORD PCWE IOWR 2 00 11 00 2 00 11 00 2 00 11 00 ns negate time P52 CLKOUT to ALE assert time 5 00 13 00 8 00 16 00 6 00 14 00 0 250 ns
53. t further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal i
54. type To support customers that are currently using the non JEDEC pin numbering scheme two sets of pinouts JEDEC and non JEDEC are presented in this document 62 MPC850 Rev A B C Hardware Specifications MOTOROLA Pin Assignments and Mechanical Dimensions of the PBGA Figure 62 shows the non JEDEC pinout of the PBGA package as viewed from the top surface O O O O O O O O 0 OF PB23 PA8 PA7 VDDL PAS PC7 PC4 PD14 PD10 PD8 O le PC11 PB22 PC9 PA4 PB16 PD15 PD12 PD7 PD6 O D a O Q PD11 PD3 IRQ7 IRQ1l IRQO O O O zO 230 is o pa x s 0 a 6 O 00 00 O O OO O O 5O O20 O 80 sO 20 2 0 O N 18 U0 O 000 O O TSIZO s U0 U0 N O 30 D o ol TSIZ1 N C GPLAQ o z ti N ie a C0O0000000 010000 O0000 Oo oO O O O O WE2 GPLA3 CS5 O Q O GPLA2 CS6 WR O OQO cs7 CS2 GPLB4 IP ooo Cs3 Ccs1 BDIP a H s w 4 ie x ic il ie il O O O O O O O O kom O O O c N C RSTCONF W AITB z 4 rel gt w fe O O oO 0 0 O Q w wD p QP w Figure 62 Pin Assignments for the PBGA Top View non JEDEC Standard MOTOROLA MPC850 Rev A B C Hardware Specifications 63 Pin Assignments and Mechanical Dimensions of the PBGA Figure 63 shows the JEDEC pinout of the PBGA package as viewed from the top surface O O O O O 0 Of VDDL PAS PC PC4 PD14 PD10 PD8 amp H
55. utput low voltage VOL 0 5 V IOL 2 0 mA CLKOUT IOL 3 2 mA IOL 5 3 mA IOL 7 0 mA PA 14 USBOE PA 12 TXD2 IOL 8 9 mA TS TA TEA BI BB HRESET SRESET 1 A 6 31 TSIZO REG TSIZ1 D 0 31 DP 0 3 IRQ 3 6 RD WR BURST RSV IRQ2 IP_B 0 1 IWP 0 1 VFLS 0 1 IP_B2 IOIS16_B AT2 IP_B3 IWP2 VF2 IP_B4 LWPO VFO IP_B5 LWP1 VF1 IP_B6 DSDI ATO IP_B7 PTR AT3 PA 15 USBRXD PA 13 RXD2 PA 9 L1TXDA SMRXD2 PA 8 L1 RXDA SMTXD2 PA 7 CLK1 TIN1 L1RCLKA BRGO1 PA 6 CLK2 TOUTT TINS PA 5 CLK3 TIN2 L1TCLKA BRGO2 PA 4 CLK4 TOUT2 TIN4 PB 31 SPISEL PB 30 SPICLK TXD3 PB 29 SPIMOSI RXD3 PB 28 SPIMISO BRGOS PB 27 I2CSDA BRGO1 PB 26 I2CSCL BRGO2 PB 25 SMTXD1 TXD3 PB 24 SMRXD1 RXD3 PB 23 SMSYN1 SDACK1 PB 22 SMSYN2 SDACK2 PB 19 L1ST1 PB 18 RTS2 L1ST2 PB 17 L1ST3 PB 16 L1RQa L1ST4 PC 15 DREQO L1ST5 PC 14 DREQT RTS2 L1ST6 PC 13 L1ST7 RTS3 PC 12 L1RQa L1ST8 PC 1 1 USBRXP PC 10 TGATET USBRXN PC 9 CTS2 PC 8 CD2 TGATET PC 7 USBTXP PC 6USBTXN PC 5 CTS3 L1TSYNCA SDACKT PC 4 CD3 L1RSYNCA PD 15 PD 14 PD 13 PD 12 PD 11 PD 10 PD 9 PD 8 PD 7 PD 6 PD 5 PD 4 PD 3 2 BDIP GPL_B5 BR BG FRZ IRQ6 CS 0 5 CS6 CE1_B CS7 CE2_B WE0 BS_ABO IORD WET BS_ABT IOWR WE2 BS_AB2 PCOE WE3 BS_AB3 PCWE GPL_A0 GPL_BO OE GPL_A1 GPL_B1 GPL_A 2 3 GPL_B 2 3 CS 2 3 UPWAITA GPL_A4 AS UPWAITB GPL_B4 GPL_A5 ALE_B DSCK AT1 OP2 MODCK1 STS OP3 MODCK2 D

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