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MOTOROLA XPC850 (Rev 0.3) XPC860 XPC860T handbook

1. considered as a reject criterion PRE CONDITIONING VAPOR PHASE VPR AND INFRARED REFLOW IR Pre conditioning is a process which simulates the manufacturing steps involved in mounting and rework of a surface mount device on to the customer s application printed circuit board Different methodologies can be employed for this purpose Infrared Reflow uses heaters instead of hot fluorocarbon vapor for the reflow Vapor Phase Reflow VPR is known to be the most contingent stress to the surface mount devices per JEDEC Standard 22 Method A112 3 In vapor phase pre conditioning different presoak conditions are defined such as 85C 85 Relative Humidity RH Class I 85C 60 RH Class II 30C 60 RH Class III IV amp V to simulate different environmental conditions Devices are exposed to VPR within 4 hours after the completion of the pre soaking process Three cycles of VPR are performed to the parts 8 to 10 minutes cool down time is allowed between VPR immersions Devices are visually inspected for package cracks after the final immersion The pre conditioning test is conducted prior to the normal reliability test SOLDERABILITY TEST The purpose of this test is to determine the solderability of device package termination that are intended to be joined to another surface using solder for the attachment This test provides optional conditions for aging and solder the purpose of allowing simulation of the soldering process to use in the device a
2. 256 leaded plastic ball grid array The XPC860 is assembled in a 357 lead plastic ball grid array PBGA Both packages have been shown to meet level 3 moisture sensitivity as classified by JEDEC A113 Our volume production is manufactured in Motorola s Kuala Lumpur Malaysia facility however we have also qualified Citizen Watch Co in Japan as an alternate assembly site 3 0 Family Qualification Strategy Motorola uses a family qualification strategy which allows sharing of certain reliability data across a common design rule fabrication geometries and packaging types Reliability data from other Motorola devices which are designed using the same design rules and wafer fabrication processes are included with this report All of the devices in this report have been in production manufacturing for at least 3 years The data presented in this report is both data from current production material and historical data used to qualify devices processes and wafer fab and assembly sites This report will be updated periodically typically twice year with new reliability data from subsequent qualifications and reliability monitors 4 0 Qualification Data Motorola 42u Process Qualification Summary The following data shows results of our 42u qualifications Life Test 125 C 4 5V Device Mask Set 168 Hrs 504 Hrs 1008 Hrs 2016 Hrs Failure Details 1008 Hr 4 parts missing balls 1 part damaged discounted EE discou
3. 3 3 V 3 5 V 5 4E 4 2 6E 4 1 6E 4 1 8E 4 8 4E 3 5 1E 3 6 6E 3 3 1E 3 1 9E 3 40 60 80 100 120 Junction Temperature C Temp Cycle 65 C 150 C Die Rev Mask Set PC MSL3 100 Cyc 500 Cyc 1000 Cyc Failure Details XPC860 0 77 0 77 0 77 1 77 1000 Cyc 1 fail EE 1000 Cyc missing ball discounted XPC860 0 77 0 77 0 77 0 77 XPC860 J23A rev A 3 0 77 0 77 0 77 0 76 XPC860 723A rev A3 77 0 77 o7 077 Om XPC860 723A revA3 77 0 77 o7 om om LO XPC860 723A rev A3 77 0 77 o7 w7 Om XPC860 723A revA3 77 077 o7 om om XPC860 723A rev A3 77 0 77 o7 077 Om oo XPC860 J23A rev A3 77 077 o7 om Om Total Lal 0693 0 693 0 693 wees Table 2 Temperature Cycle Data MSL3 Autoclave 121 C 15PSIG XPC860 0 77 0 77 0 77 XPC860 J23A rev A 3 0 77 0 77 0 77 XPC860 J23A rev A 3 XPC860 J23A rev A 3 XPC860 J23A rev A 3 0 77 0 77 0 77 0 77 0 77 0 76 XPC860 J23A rev A 3 XPC860 J23A rev A 3 0 60 0 60 0 60 XPC860 J23A rev A 3 Table 3 Autoclave Data MSL3 MEE 60 144 Hrs 0 77 0 77 0 77 0 77 0 76 1 853 Failure Details Terminated die attach problem 48 hr Mishandled discounted MSL3 functional EN THB 85 C 85 RH Die Rev M
4. AX PC 8501 hy Fi Reliability Report for Networking Communication Microprocessors XPC850 Rev 0 3 XPC860 XPC860T 0 42u Single Poly Wafer Fabrication Process M MOTOROLA Revision 5 99 1 0 Purpose and Description This report summarizes the reliability data for Motorola communication microprocessors fabricated on the 0 42u single polysilicon process in our wafer fabrication facility Mos 11 in Austin Texas The current devices fabricated using this process are given in the table below Device Mask Set Design Die Size Process Revision mils Geometry XPC850 309 x 335 XPC860 338 x 329 338 x 329 XPC860T 338 x 347 Table 1 Device properties All of these devices are currently in their XC phase of product life which is the time when design errata are discovered and corrected Although the 850 and 860 are still classified as XC devices they are built using production equipment and processes and have completed their reliability qualifications There are some functional errata on these devices which may impact some customers These errata are expected to be corrected in revision D of the 860 which we expect to grant MC status to For a list of current design errata on these devices please contact your local Motorola sales person To locate the nearest sales office you can find them on our website at http mot sps com sales sales web html 2 0 Assembly Package Information The XPC850 is assembled in a
5. ask Set PC MSL3 168 Hrs 504 Hrs 1008 Hrs Failure Details rev A 3 Ker eI d d UR D n rev A 3 rev A3 discounted Me SALA Bo odii Io NN rev A3 Total 308 0307 0230 0230 029 Table 4 THB Data MSL3 Electrostatic Discharge Data The following ESD data is device specific 860 ESD Human Body Model I O 1 5 kV 2 0kV 2 5 kV Failure Details J24A 860revB 1 3 23 2 functional in analysis H96G 860revC 1 9 02 02 oo 02 Le RE OMBUD EECH 08 eee Toa GI as o2 03 on 3 Table 5 Human Body Model I O ESD data for the 860 860 ESD Human Body Model PWR Failure Details J24A 860 revB 1 3 03 2 functional in analysis H96G 860evCl 2 qe s wr ESME ES EE Table 6 Human Body Model PWR ESD data for the 860 860 ESD Machine Model Vmax 200 V DAA 860revB l 3 03 Pe DAA 860 rev BO 3 03 Pe 33IM 860T 3 ov e O Jop L3l 03 v gt E Table 7 Machine Model ESD data for the 860 860 ESD CDM Vmax 1000 V corner balls 500V inner balls 500V 1000V Failure Details HOGG eo Rev CD RI OB ae EE RE omm RE 0 0 8 1j Table 8 Charged device model ESD data for the 860 850 ESD Human Body Model VO Vmax 1kV Failure Details F98S REV 0 3 16 36 Functional fails ee Toa P
6. ds or cosmetic package defects 12 TEMPERATURE CYCLE T C Temperature Cycle accelerates the effects of thermal expansion mismatch between different components of the packaging system a condition which can cause wire bond problems and seal leakage Temperature Cycle is typically performed per Mil Std 750 or Mil Std 883 Method 1010 Condition D Devices are inserted into cycling system and held at 65C for at least ten minutes devices are then transferred to a second chamber and held at 150C for at least 10 minutes The system employs a circulating air environment to assure rapid stabilization at the specified temperature The dwell at each extreme plus two transition times of five minutes each constitute one cycle The duration of this testing is typically 500 or 1000 cycles A device shall be considered as a reject if hermeticity cannot be demonstrated parametric limits are exceeded or if functionality cannot be demonstrated as per the data sheet limits Mechanical damage such as cracking chipping or breaking of package will also be considered as a reject provided such damage was not caused by fixturing or handling Verified EOS and ESD failures shall not be considered as legitimate rejects TEMPERATURE HUMIDITY BIAS THB This is an environmental test performed at a temperature of 85 C and a relative humidity of 85 per JEDEC Standard 22 Method A101 The test is designed to measure the moisture resistance of plastic encapsu
7. el o2 SS Table 9 Human Body Model I O ESD data for the 850 850 ESD Human Body Model PWR Vmax 1kV POSS REVOS ECH B 0 ee SO F98S REVOS 3 B Pe Teal el we 05 o O Table 10 Human Body PWR ESD data for the 850 850 ESD Machine Model Vmax 200V Failure Details FOSS REVOS El FOSS REV 0 3 1 3 OR Pe F98S REV 03 J3 03 JN J A y y O F98S REV 03 3 03 D 9 Total JULI DE Table 11 Machine Model ESD data for the 850 Latchup Data For 42u Devices The following latchup data is specific for each device type 200mA Failure Details ee ee di Table 12 Latchup Data for each device type REESEN Device XPC860T 10 AVERAGE OUTGOING QUALITY In Parts per Million 4th Quarter 3rd 2nd Quarter 1st Quarter Quarter Device Type Category 1998 1998 1998 1998 XPC850 Electrical 872 3 0 106 0 Vis Mech 0 0 509 6 0 XPC 860 XPC860T Electrical 96 7 69 3 68 4 189 1 Vis Mech 0 180 6 185 1 0 Networking Microprocessors 100 90 80 70 60 3 o e Electrical 9 Vis Mech 40 30 20 10 0 1Q98 2Q98 3Q98 4Q98 1Q99 Quarter 11 5 0 Qualification Stress Descriptions The following summary briefly describes the various reliability tests included in the Motorola reliability monitor program DYNAMIC EARLY FAIL STUDY EFR This stress is performed to accelerate infant
8. lated circuits A nominal 5V static bias is applied to the device to create the electrolytic cells necessary to accelerate corrosion of the metallization Typical stress duration is 1008 hours A device will be considered to have failed the static temperature humidity bias test if parametric limits are exceeded or functionality cannot be demonstrated under normal and worst case conditions as specified in the data sheet Device which recovers after baking shall be considered as a reject Verified ESD or EOS failures shall not be considered legitimate rejects 13 AUTOCLAVE ACVPRESSURE TEMPERATURE HUMIDITY PTH Autoclave is an environmental test that measures device resistance to moisture penetration and the resultant effects of galvanic corrosion It is a highly accelerated and destructive test performed per JEDEC Standard 22B Method A110 Code C Conditions employed during the test include 121 C 100 relative humidity and 15 psig Corrosion of the die is the expected failure mechanism Typical test duration is 144 hours A device will be considered to have failed the autoclave test if parametric limits are exceeded or if functionality cannot be demonstrated under normal and worst case conditions specified in the data sheet Verified EOS and ESD failures shall not be considered as legitimate failures nor will mechanical damage such as cracking of the package Cosmetic package defects and degradation of lead finish and solderability are not
9. mortality failure mechanisms which are defects that occur within the first year of normal device operation The typical stress condition is a temperature of 125 C a voltage of 6V for SV products and 4 5V for 3 3V products and a duration of 168 hours Devices used in this test are sampled directly after the standard production final test flow with no prescreening unless called out in the normal production flow HIGH TEMPERATURE OPERATING LIFE HTOL TEST High Temperature Operating Life HTOL test is performed to accelerate failure mechanism which are thermally activated through the application of extreme temperatures and the use of dynamic operating conditions All devices performing the HTOL test are sampled directly after final electrical test with no prior burn in or other pre screening Testing is performed per Mil Std 883 Method 1005 with dynamic signaling applied to the devices for a minimum duration of 168 hours Some sample groups are extended to 2016 hours A device will be considered to have failed the life test if parametric limits are exceeded or if functionality cannot be demonstrated under nominal and worst case conditions specified in the data sheet Forms of mechanical damage such as cracking of the package will be considered as a reject Device which recovers after baking will also be considered as a reject Verified ESD and EOS failures shall not be considered legitimate nor will failures caused by handling such as bent lea
10. nted XPC850 F98S rev 0 3 77 0 77 0 77 0 72 1008Hr Units discounted XPC850 F98S rev 0 3 77 0 77 0 75 0 69 168 504 Hr Units discounted XPC860 123A rev A 3 77 0 77 077 7 Tut XPC860 J23A rev A3 77 077 0 77 om Tut 0 XPC860 J23A rev A 3 77 0 77 0 77 7 TI XPC860 H96G rev C 1 77 0 77 o7 ant XPCS60 H96G rev C 1 77 0 77 1 77 0 77 Functional Failure destroyed in FA XPCS60 H96G rev C 1 77 0 77 o7 om CC MCI ITIN EN damaged at test discounted 68LCO60 G59Y 77 0 76 0 76 0 63 168 1008 Hr Parts discounted EE eee 68LC060 G59Y 0 77 0 77 OTT EEN 68LC060 G59Y 0 77 o7 7 68LC060 G59Y orm sd E 68LC060 G59Y ee 1 77 04076 168 Hr 1 functional fail 0 1040 0 231 Table 1 Life Test Data Fit Rate Failuresh Ho 9deews Hoane MTEF wears 1 1 1 1 1 1 1 1 000 00 100 00 10 00 1 00 0 10 00E 06 00E 05 00E 04 00E 03 00E 02 00E 01 00E 00 0 M woronoLa 20 20 FITs vs Junction Temperature 42u FIT MTBF Data Thermal and Voltage Acceleration eA 0 5 eV Beta 2 5 90 Confidence 40 60 80 100 120 Junction Temperature C MTBF vs Junction Temperature 42u FIT MTBF Data Thermal and Voltage Acceleration eA 0 5 eV Beta 2 5 90 Confidence 3 V
11. pplication It provides procedures for through hole axial and surface mount devices Leads should be dipped at a solder temperature of 245 5C for a duration of 5 10 seconds per JEDEC Standard 22 Method A102 14 HIGH TEMPERATURE BAKE HTB The purpose of High Temperature Bake HTB is to bake the device for a specified length of time to determine the stability of the device transistors per Mil Std 883 Method 1008 ELECTROSTATIC DISCHARGE ESD This series of stresses included Human Body Model HBM Machine Model MM per JEDEC Standard 22 Method 2007 to determine if the devices cab be handled in a normal production environment without being damaged by the various sources of static that are present 15

MOTOROLA XPC850 (Rev 0.3) XPC860 XPC860T handbook

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