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ANALOG DEVICES VisualDSP 5.0 Loader Utilities Manual (Revision 2.1 October 2008)

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1. DMA Setting Processor Model ADSP 21060 61 62 ADSP 21065L BMSspace Mkz8sbi o f8Mz8bi O DMA channel DMAC6 0x2A1 DMACO 0x2A1 116 IIEPO 0x20000 0x8000 IM6 IMEPO 0x1 implied 0x1 implied C6 CEPO 0x100 0x100 EI6 EIEPO 0x80 0000 0x40 0000 EM6 EMEPO 0x1 implied 0x1 implied EC6 ECEPO 0x600 0x600 IRQ vector 0x20040 0x8040 Table 4 9 DMA Settings for ADSP 21160 EPROM Booting DMA Setting ADSP 21160 Processor BMS space 8M x 8 bit DMA channel DMAC10 0x4A1 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors Table 4 9 DMA Settings for ADSP 21160 EPROM Booting Cont d DMA Setting ADSP 21160 Processor II 0x40000 IM 0x1 implied C10 0x100 EI 0x800000 EM 0x1 implied EC 0x600 IRQ vector 0x40050 After the processor s RESET pin goes inactive on start up a SHARC system configured for EPROM boot undergoes the following boot loading sequence 1 The processor BMS pin becomes the boot EPROM chip select 2 The processor goes into an idle state identical to that caused by the IDLE instruction The program counter PC is set to the processor reset vector address refer to Table 4 2 on page 4 4 The DMA controller reads 8 bit EPROM words packs them into 48 bit instruction words and transfers them into internal memory low to high byt
2. Bit Setting Comment SPIEN Set 1 SPI enabled MS Set 1 Master device MSBF Cleared 0 LSB first WL 10 32 bit SPI receive shift register word length 6 10 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 21469 SHARC Processors Table 6 7 SPI Master Boot Mode Bit Settings Contd Bit Setting Comment DMISO Cleared 0 MISO enabled SENDZ Set 1 Send zeros SPIRCV Set 1 Receive DMA enabled CLKPL Set 1 Active low SPI clock CPHASE Set 1 Toggle SPICLK at the beginning of the first bit The SPI DMA channel is used when downloading the boot kernel infor mation to the processor At reset the DMA parameter registers are initialized to the values listed in Table 6 8 Table 6 8 Parameter Registers Settings for SPI Master Boot Parameter Register Initialization Value Comment SPICTL 0x0000 5D06 SPIBAUD 0x0064 CCLK 400 500 KHz 200 MHz SPIFLG Oxfedl FLAGO ADSP 2126x and ADSP 21362 21363 21364 21365 2136 or SPI_FLAGO_0 ADSP 21367 21368 21369 2137x and ADSP 21469 used as slave select SPIDMAC 0x0000 0007 Enable receive interrupt on completion IISPI 0x0008 0000 Start of block 0 normal word memory IMSPI 0x0000 0001 32 bit data transfers CSPI 0x0000 0180 0x100 instructions 0x180 32 bit words From the perspective of the processor there is no difference between boo
3. Off chip Instruction ROM in Async Bank 0 MEM_PROGRAM_ROM TYPE ROM START 0x20000000 END Ox2009FFFF WIDTH 8 Off chip constant data in Async Bank 0 EM_DATA_ROM TYPECROM START Ox200A0000 END OX200FFFFF WIDTH 8 On chip SRAM data is not booted automatically EM_DATA_RAM TYPECRAM START COXFF903000 END OXFF907FFF WIDTH 8 Listing 3 7 ROM Segment Definitions LDF File Example PROCESSOR pO OUTPUT COMMAND_LINE_OUTPUT_FILE SECTIONS program_rom VisualDSP 5 0 Loader and Utilities Manual 3 79 ADSP BF53x BF561 Proc essor Loader Guide INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS rom_code gt MEM_PROGRAM_ROM data_ro INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS rom_data gt MEM_DATA_ROM data_sram INPUT_SECTION_ALIGN 4 INPUT_SECTIONS OBJECTS ram_data gt MEM_DATA_RAM With the LDF file modified this way the source files can now take advan tage of the newly introduced sections as in Listing 3 8 Listing 3 8 Section Handling Source File Example SECTION rom_code _reset_vector 10 0 1 0 12 0 Se continue with setup and application code fe ie ge COL SECTION rom_data VAR myconst x Oxdeadbeef GR fas aa oe A SECTION ram_data VAR myvar y note that y cannot be initialized automatically 3 80 VisualDSP 5 0 Loader and Utilities Manual 4 LOADER F
4. As the loader utility converts the code from an input dxe file into blocks comprising the output loader file each block receives a 10 byte header Figure 3 3 followed by a block body if it is a non zero block or no block body if it is a zero block A description of the header structure can be found in Table 3 3 3 10 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors Table 3 3 ADSP BF531 BF532 BF533 Block Header Structure Bit Field Description Address 4 byte address at which the block resides in memory Count 4 byte number of bytes to boot Flag 2 byte flag containing information about the block the following text describes the flag structure HEADER OF DXE 1 DXE 1 BYTE COUNT BLOCK 1 HEADER 10 BYTE HEADER 4 BYTE ADDRESS BOOT SAREAN BLOCK 1 BODY 1St EXECUTABLE DXE 1 BLOCK 2 HEADER 4 BYTE COUNT 2 BYTE FLAG ay SEE FLAG INFORMATION BLOCK 2 BODY HEADER OF DXE 2 OF THE DXE 2 BYTE COUNT 2nd EXECUTABLE DXE 2 BOOT STREAM Figure 3 3 ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Processors Boot Stream Structure VisualDSP 5 0 Loader and Utilities Manual 3 11 ADSP BF53x BF561 Proc essor Booting Refer to Figure 3 4 and Table 3 4 for the flag s bit descriptions Table 3 4 Flag Structure Bit Field Description Zero fill block Indicates that the block is for a buf
5. Currently the loader utility generates single processor loader files for host link and SPI port boot The loader utility supports multiprocessor EPROM boot only The application code must be modified to properly set up multiprocessor booting in host link and SPI port boot modes There are two methods by which a multiprocessor system can be booted e Boot From a Single EPROM e Sequential EPROM Boot Regardless of the method the processors perform the following steps 1 Arbitrate for the bus 2 Upon becoming bus master DMA the 256 word boot stream VisualDSP 5 0 Loader and Utilities Manual 5 21 ADSP 21161 Proc essor Booting 3 Release the bus 4 Execute the loaded instructions Boot From a Single EPROM The loader utility can produce boot loadable files that permit SHARC processors in a multiprocessor system to boot from a single EPROM The BMS signals from each processor may be wire ORed together to drive the EPROM s chip select pin Each processor can boot in turn according to its priority When the last processor has finished booting it must inform the other processors which may be in the idle state that program execu tion can begin if all processors are to begin executing instructions simultaneously When multiple processors boot from a single EPROM the processors can boot identical code or different code from the EPROM If the processors load differing code use a jump table in the loader file
6. EVT1 vector 0010 BCODE_QUICKBOOT 0100 BCODE_ALLBOOTt 0110 BCODE_FULLBOOT 1xxx reserved Figure 2 2 ADSP BF526 BF527 BF548 BF548M Processors SYSCR Register Loader utility operations depend on the loader options which control how the utility processes executable files You select features such as boot modes boot kernels and output file formats via the options The options are specified on the loader utility s command line or via the Load page of VisualDSP 5 0 Loader and Utilities Manual 2 5 ADSP BF518 BF526 BF527 BF548 BF548M Processor Loader Guide the Project Options dialog box in the VisualDSP environment The Load page consists of multiple panes When you open the Load page the default loader settings for the selected processor are set already Option settings on the Load page correspond to switches displayed on the command line These sections describe how to produce a bootable or non bootable loader file sing Blackfin Loader Command Line on page 2 6 sing VisualDSP Loader on page 2 17 U U Using VisualDSP Second Stage Loader on page 2 19 U sing VisualDSP ROM Splitter on page 2 20 Using Blackfin Loader Command Line The ADSP BF518 BF526 BF527 BF548 BF548M Blackfin loader utility uses the following command line syntax For a single input file elfloader inputfile proc processor switch For multiple input files elfloader inputfilel i
7. Specifies the processor This is a mandatory switch 5 30 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors Table 5 10 ADSP 21161 Loader Command Line Switches Cont d Switch Description si revision none any The si revision none any switch provides a silicon revi sion of the specified processor The switch parameter represents a silicon revision of the processor specified by the proc processor switch The parameter takes one of three forms e The none value indicates that the VisualDSP ignores silicon errata e The value indicates one or more decimal digits fol lowed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the point specify the chip tape out number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an output file that can be run at any silicon revision The switch generates either a warning about any potential anoma lous conditions or an error if any anomalous conditions occur In the absence of the silicon revision switch the loader utility selects the greatest silicon revision it is aware of if any S In the absence of the switch parameter a valid revi sion
8. To put two 32 bit hex messages in the final block header optional e Not to include the initial word in the loader file For more information see Internal Boot Mode on page 6 17 o filename Directs the loader utility to use the specified fi 7ename as the name for the loader s output file If the o f77ename is absent the default name is the root name of the input file with an 1dr extension VisualDSP 5 0 Loader and Utilities Manual 6 45 ADSP 2126x 2136x 2137x 21469 Processor Loader Guide Table 6 18 ADSP 2126x 2136x 2137x 21469 Loader Command Line Switches Cont d Switch Description noZeroBlock The noZeroBlock switch directs the loader utility not to build zero blocks paddress Specifies the PROM start address This EPROM address corresponds to 0x80000 ADSP 2126x processors or to 0x90000 ADSP 2136x 2137x 21469 processors The p switch starts the boot loadable file at the specified address in the EPROM If the p switch does not appear on the command line the loader utility starts the EPROM file at address 0x0 proc processor Specifies the processor This is a mandatory switch The processor argument is one of the following ADSP 21261 ADSP 21262 ADSP 21266 ADSP 21267 ADSP 21362 ADSP 21363 ADSP 21264 ADSP 21365 ADSP 21366 ADSP 21267 ADSP 21368 ADSP 21369 ADSP 21371 ADSP 21375 ADSP 21469 retainSecondStagek ernel Directs the loade
9. 6 47 7 11 8 8 simulators for boot simulation 1 10 single processor systems 4 24 5 23 7 6 7 9 8 2 VisualDSP 5 0 Loader and Utilities Manual si revision none any loader switch for Blackfin 2 16 3 67 loader switch for SHARC 4 31 5 31 6 47 loader switch for TigerSHARC 7 11 splitter switch 8 8 slave processors 1 10 1 14 6 10 s_ Motorola S record files 8 4 A 10 sm shared memory files 2 8 3 59 4 28 5 28 7 8 A 5 A 15 software reset 1 13 3 7 3 24 3 25 3 38 source file formats assembly text asm A 2 C C text c cpp cxx A 2 SPIBAUD register 6 11 SPI boot modes SHARC processors ADSP 21161 processors 5 2 5 4 5 14 ADSP 2126x 36x 37x 46x processors 6 7 6 13 6 21 6 28 SPICLK register 6 8 6 10 6 13 6 17 SPICTL register 5 15 6 9 6 11 SPIDMAC register 6 9 6 11 SPIDS signal 6 8 SPI EEPROM boot mode Blackfin processors ADSP BF535 processors 3 22 3 26 3 29 3 30 ADSP BF561 processors 3 44 SPIEN bit 6 9 6 10 SPI_FLAGO_O signal 6 10 6 11 SPI flash boot mode ADSP 2126x 2136x 2137x 21469 processors 6 16 SPIFLG register 6 11 SPI host boot mode ADSP 2126x 36x 37x 46x processors 6 17 INDEX SPI master boot modes ADSP 2126x 36x 37x 46x processors 6 7 6 10 6 14 ADSP 2126x 36x 37x processors 6 18 ADSP BF5 1x processors 2 3 ADSP BF52x 54x processors 2 4 ADSP BF531 2 3 8 9 processors 3 4 ADSP BF534 6 7 processors 2 4 3 4 See also SPI flash SPI RO
10. Figure 3 17 Global Header A global header s bit assignments for eight and 16 bit Flash PROM boot are illustrated in Figure 3 18 a a Ld CT Number of hold time cycles 3 default Number of wait states 15 default 1 16 bit Admix 0 8 bit flash PROM 0 default Figure 3 18 Flash PROM Boot Global Header Bit Assignments 3 32 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors A global header s bit assignments for eight and 16 bit addressable SPI boot are illustrated in Figure 3 19 eae 9 gt a en Ld Baud rate 0 500 kHz default 1 1 MHz 2 2 MHz Figure 3 19 SPI Boot Global Header Bit Assignments Block Headers and Flags For application code a block is the basic structure of the output 1dr file when the second stage loader is used All application code is grouped into blocks A block always has a header and a body if it is a non zero block A block does not have a body if it is a zero block A block structure is illus trated in Figure 3 20 OUTPUT LOR FILE SIZE OF APPLICATION CODE N1 4 BYTES BYTE COUNT N N1 START ADDRESS N BYTES 2nd STAGE LOADER tf q BYTE COUNT apytes 8 d OF BLOCK 1 3 Ni oY ADDRESS macronmocki e FOR BLOCK 1 2 BYTES z 4 BYTES GLOBAL HEADER BODY OF BLOCK 1 SIZE OF APPLICATION CODE N1 wE ADDRESS wE BLOCK 2 APPLICATION CODE BYTE COUNT OF BLOCK
11. Initial Word Option for SPI Master Boot Modes on page 6 14 for details Figure 6 1 shows the initial 32 bit word sent out from the processor As shown in the figure the processor initiates the SPI master boot process by writing an 8 bit opcode LSB first to the slave device to specify a read operation This read opcode is fixed to 0xC0 0x03 in MSB first format Following that a 24 bit address all zeros is always driven by the proces 6 12 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 21469 SHARC Processors sor On the following SPICLK cycle cycle 32 the processor expects the first bit of the first word of the boot stream This transfer continues until the boot kernel has finished loading the user program into the processor SPICLK J Driven by MASTER 1 _ lt G lt READ A15 A8 X AT A0 MASTER OUT SLAVE IN A8 y K Cmn XA15 A8 X AT A0 T MOSI j SPI SLAVE gt si o 2 Processor 0x00 X 0x00 ox0o0 Y oxas 3 Ist KNL y MASTER IN SLAVE OUT BYTE MISO MISO B o Slave Processor TX s I i anytime SPICLK driven J SPI SLAVE oi PROM fst KNL MASTER IN SLAVE OUT _BYTE MISO i l I SFLEROM doesnt i DATA clocked into DSP during this recieves a read cycle MUST be OxAS5 If slave device command and address is an SPI PROM then the FIRST byte must be 0xA5 1 I i Ifthe SPI slave device is a processor 1 the FOU
12. The boot kernel uses three copies of SYSCON one that contains the original value of SYSCON a second that contains SYSCON with the BSO bit set allowing the processor to gain access to the boot EPROM and a third with the 850 bit cleared When 8S0 1 the EPROM packing mode bits in the DMACx control register are ignored and 8 to 48 bit packing is forced 8 bit pack ing is available only during EPROM booting or when BS0 is set When an external port DMA channel is being used in conjunction with the BSO bit none of the other three channels may be used In this mode BMS is not asserted by a core processor access but only by a DMA transfer This allows the boot kernel to perform other external accesses to non boot memory VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2106x 21160 SHARC Processors The EPROM is automatically selected by the BMS pin after reset and other memory select pins are disabled The processor s DMA controller reads the 8 bit EPROM words packs them into 48 bit instruction words and transfers them to internal memory until 256 words have been loaded The master DMA internal and external count registers Cx and ECx decrement after each EPROM transfer When both counters reach zero DMA trans fer has stopped and RTI returns the program counter to the address where the kernel starts To EPROM boot a single processor system include the executable on the command line without a switch Do not use
13. W SUN DSP 5 0 Loader and Utilities Manual Analog Devices Inc One Technology Way Norwood Mass 02062 9106 Revision 2 1 October 2008 Part Number 82 000450 01 ANALOG DEVICES Copynght Information 2008 Analog Devices Inc ALL RIGHTS RESERVED This docu ment may not be reproduced in any form without prior express written consent from Analog Devices Inc Printed in the USA Disclaimer Analog Devices Inc reserves the right to change this product without prior notice Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by impli cation or otherwise under the patent rights of Analog Devices Inc Trademark and Service Mark Notice The Analog Devices icon bar and logo VisualDSP the VisualDSP logo Blackfin the Blackfin logo SHARC the SHARC logo Tiger SHARC the TigerSHARC logo CROSSCORE and the CROSSCORE logo are registered trademarks of Analog Devices Inc All other brand and product names are trademarks or service marks of their respective owners CONTENTS PREFACE Parpose ot This Manual ssccniceaaasumienbiuasdenaneibeatanseieaiines xiii Tapes Oe a SAE a A eeneees xiii Maa OTE E EEEO xiv Thats Mewin Thir Manusi sorndponsipnniiiina an xiv Technical or Customer S
14. b prom ter TWIslave FIFO OTP NAND switch directs the loader utility b spimaster to prepare a boot loadable file for the specified boot mode Valid b spislave boot modes include flash PROM SPI master SPI slave UART b TWImaster TWI master TWI slave FIFO OTP NAND and b TWIslave SDRAM DDR b UART b FIFO If b does not appear on the command line the default is b OTP b flash b NAND 2 8 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors Table 2 5 ADSP BF518 BF526 BF527 BF548 BF548M Loader Command Line Switch Summary Contd Switch Description CRC32 polynomial The CRC32 polynomial coefficient switch directs the loader utility to generate CRC32 checksum Use a polynomial coefficient if specified otherwise use default 0xD8018001 This switch inserts an initcode boot block that calls an initializa tion routine residing in the on chip boot ROM The argument field of the boot block provides the used polynomial The loader utility calculates the CRC checksum for all subsequent data blocks and stores the result in the block header s argument field The CRC32 checksum is not performed by the ADSP BF52x boot kernel callback sym symbol The callback switch takes a sym symbo no spaces assign Larg const32 ment The switch directs the loader utility to isolate the named subrou tine into a separate block set the block
15. bspiprom bspimaster 10 EPROM boot via the parallel port bprom 11 Internal boot not available on all Does not use the loader utility ADSP 2126x processors 6 4 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 21469 SHARC Processors Table 6 2 ADSP 21469 Boot Mode Pins BOOT_CFG 2 0 Boot Mode Boot Mode Selection 000 SPI slave bspislave 001 SPI master SPI flash SPI PROM ora bspiflash host processor via SPI master mode bspiprom bspimaster 010 AMI user boot for 8 bit flash memory bprom boot 011 Reserved N A 100 Link port 0 boot blink 101 Reserved N A ADSP 2126x 2136x 2137x 21469 Processors Boot Modes The following sections describe the ADSP 2126x 2136x 2137x 21469 processor boot types e PROM Boot Mode on page 6 5 e SPI Port Boot Modes on page 6 7 e Internal Boot Mode on page 6 17 PROM Boot Mode The ADSP 2126x 2136x 2137x 21469 processors support an 8 bit boot mode through the parallel port This mode is used to boot from external 8 bit wide memory devices The processor is configured for 8 bit boot mode when the BOOT_CFG1 0 pins 10 orB00T_CFG2 0 pins 010 When configured for parallel booting the parallel port transfers occur with the default bit settings for the PPCTL register shown in Table 6 3 VisualDSP 5 0 Loader and Utilities Manual 6 5 ADSP 2126x 2136x 2137x 21469 Proc essor Bootin
16. 2M 11 27 Reserved for future use 28 31 Signature that indicates valid boot stream VisualDSP 5 0 Loader and Utilities Manual 3 39 ADSP BF53x BF561 Proc essor Booting Following the global header is a dxe count block which contains a 32 bit byte count for the first dxe file in the boot stream Though this block contains only a byte count it is encapsulated by a 10 byte block header just like the other blocks The 10 byte header instructs the boot ROM where in memory to place each block how many bytes to copy and whether the block needs any special processing The block header structure is the same as that of the ADSP BF531 BF532 BF533 processors described in ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 Each header contains a 4 byte start address for the data block a 4 byte count for the data block and a 2 byte flag word indicating whether the data block is a zero fill block or a final block the last block in the boot stream For the dxe count block the address field is irrelevant since the block is not going to be copied to memory The ignore bit is set in the flag word of this header so the boot loader utility does not try to load the dxe count but skips the count For more details see ADSP BF531 BF532 BF533 BF534 BF536 BF537 BF538 BF539 Block Headers and Flags on page 3 10 Following the dxe count block are the rest of the
17. BF527 BF548 BF548M Processor Loader Guide The loader utility post processes VisualDSP executable dxe files and generates loader 1dr files A loader file can be formatted as binary ASCII or Intel hex style An 1dr file contains the boot stream in a format expected by the on chip boot kernel 2 4 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF51x BF52x BF54x Blac kfin Proc essors ADSP BF518 Processors System Reset Configuration Register SYSCR X state is initialized from BMODE pins during hardware reset 15 14 13 12 11 oeecooos o To Te Jo POO PPT TTT DT eet tendent on nin BCODE 3 0 BMODE 2 0 Boot Mode RO Boot Code RW ee baer NORMAL The BMODE bit field represents the 0001 BCODE_NOBOOT Do not boot directly jump to BMODE pin settings see Table 2 2 EVT1 vector L Reserved 0010 BCODE_QUICKBOOT 0100 BCODE_ALLBOOTt 0110 BCODE_FULLBOOT 1xxx reserved Figure 2 1 ADSP BF518 Processors SYSCR Register ADSP BF526 BF527 BF548 BF548M Processors System Reset Configuration Register SYSCR X state is initialized from BMODE pins during hardware reset 15 14 13 12 11 10 OxFFCO 0104 fo Jo fo fo TAAA dada PET Reset dependent on pin values BCODE 3 0 L Boot Code RW BMODE 3 0 Boot Mode RO 0000 BCODE_NORMAL The BMODE bit field represents the 0001 BCODE_NOBOOT Do not boot directly jump to BMODE pin settings see Table 2 3
18. DMACx control setting in R2 for later restore clears DMACx for new setting and sets the BUSLCK bit in the MODE2 register to lock out the host 2 Stores the SYSCON register value in R12 for restore 3 Enables interrupts and nesting for DMA transfer sets up the IMASK register to allow DMA interrupts and sets up the MODE1 register to enable interrupts and allow nesting VisualDSP 5 0 Loader and Utilities Manual 4 13 ADSP 2106x 21160 Proc essor Booting 4 Loads the DMA control register with 0x00A1 and sets up its param eters to read the data word by word from external buffer 0 Each word is read into the reset vector address refer to Table 4 2 on page 4 4 for dispatching The data through this buffer has a structure of boot section which could include more than one ini tialization block 5 Clears the BUSLCK bit in the MODE2 register to let the host write in the external buffer 0 right after the appropriate DMA channel is activated For information on the data structure of the boot section and ini tialization see ADSP 2106x 21160 Processor Boot Steams on page 4 17 6 Loads the first 256 words of target the executable file during the final initialization stage and then the kernel overwrites itself The final initialization works the same way as with EPROM booting except that the BUSLCK bit in the MODE2 register is cleared to allow the host to write to the external port buffer The default boot kernel for
19. Loader for ADSP 2106x 21160 SHARC Processors Table 4 15 ADSP 2106x 21160 Loader Command Line Switches Switch Description si revision The si revision none any switch provides a silicon revision dF none any of the specified processor The switch parameter represents a silicon revision of the processor spec ified by the proc processor switch The parameter takes one of three forms e The none value indicates that the VisualDSP ignores sili con errata e The value indicates one or more decimal digits followed by a point followed by one or two decimal digits Examples of revisions are 0 0 1 12 23 1 Revision 0 1 is distinct from and lower than revision 0 10 The digits to the left of the point specify the chip tapeout number the digits to the right of the point identify the metal mask revision number The number to the right of the point cannot exceed decimal 255 e The any value indicates that VisualDSP produces an out put file that can be run at any silicon revision The switch generates either a warning about any potential anomalous conditions or an error if any anomalous conditions occur In the absence of the switch parameter a valid revision value si revision alone or with an invalid value the loader utility generates an error ti Host boot only Specifies timeout cycles for example t100 Limits the number of cycles that the processor spends initializing external memory with zero
20. Purpose 10D00043C4034343426142226084C Example record 51 Record type OD Byte count of this record 0004 Address of the first data byte 3C First data byte 08 Last data byte AC Checksum The S2 data record has the same format except that the start character is s2 and the address field is six characters wide The 3 data record is the same as the S1 data record except that the start character is 3 and the address field is eight characters wide Termination records have an address field that is 16 24 or 32 bits wide whichever matches the format of the preceding records Table A 7 shows the organization of an S1 termination record Table A 7 S1 Termination Record Example Field Purpose S903000DEF Example record s9 Start character 03 Byte count of this record 000D Address EF Checksum The S2 termination record has the same format except that the start char acter is S8 and the address field is six characters wide VisualDSP 5 0 Loader and Utilities Manual A 11 Build Files The S3 termination record is the same as the S1 format except the start character is S7 and the address field is eight characters wide For more information see hexutil Hex 32 to S Record File Converter on page B 2 Splitter Output Files in Intel Hex 32 Format The splitter utility can output Intel hex 32 format h_ files Thes
21. R9 0xb16b0000 Load opcode for PM 0 I8 PX into R9 PX pm 0x80002 User instruction destined for 0x80030 is passed in the section header for FINAL_INIT That instr is initialized upon completion of this DMA see comments below using the PX register R11 BSET R11 BY 9 Set IMDW to 1 for inst write xI DM SYSCTL R11 Set IMDW to 1 for inst write a VisualDSP 5 0 Loader and Utilities Manual 6 29 ADSP 2126x 2136x 2137x 21469 Proc essor Booting ORs eae Setup loop 14 0x80004 R9 pass R9 R11 R12 DO 0x80004 UNTIL EQ for self modifying instruction Point to 0x080004 for self modifying code inserted by the loader at 0x80004 in bootstream K Clear AZ copy power o of SYSCTL to R11 Set bottom of loop address loopstack to 0x80004 and top of loop PC Stack value to the address of the next instruction K PCSTK 0x80004 Change top of loop value from the address of this instruction to 0x80004 Ky LE Teuer Setup final DMA parameters R R1 0x80000 DM IISX R1 Setup DMA to load over ldr ay R2 0x180 DM CSX R2 Load internal count Ef DM IMSX M6 Set to increment internal ptr af RRA SOR Se Sos He Enable SPI interrupt ees ss sie nero aii Ei bit clr IRPTL SPIHI Clear any pending SPI interr latch bit set IMASK SPIHI Enable SPI receive interrupt K bit set MODE1 IRPTEN Enable global interrupts X FLUSH
22. The loader util ity supports relative and absolute directory names and default directories File searches occur as follows e Specified path If relative or absolute path information is included in a file name the loader utility searches only in that location for the file e Default directory If path information is not included in the file name the loader utility searches for the file in the current working directory e Overlay and shared memory files The loader utility recognizes overlay and shared memory files but does not expect these files on the command line Place the files in the directory that contains the executable file that refers to them or place them in the current working directory The loader utility can locate them when pro cessing the executable file When providing an input or output file name as a loader splitter com mand line parameter use these guidelines e Enclose long file names within straight quotes long file name Append the appropriate file extension to each file VisualDSP 5 0 Loader and Utilities Manual 1 17 File Searches 1 18 VisualDSP 5 0 Loader and Utilities Manual 2 LOADER SPLITTER FOR ADSP BF51X BF52X BF54X BLAC KFIN PRO C ESSO RS This chapter explains how the loader splitter utility e1f1oader exe is used to convert executable dxe files into boot loadable or non bootable files for the ADSP BF518 ADSP BF526 ADSP BF527 ADSP BF548 and ADSP BF548M
23. bflt B 3 B 4 binary format files ldr 2 9 3 61 7 9 A 9 bit reverse option SHARC processors 6 13 block of application code introduction to 1 16 byte counts Blackfin processors 2 13 3 64 flags See flag words packing See data packing tags 4 18 5 17 6 18 6 23 6 24 block headers Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 9 3 11 ADSP BF535 processors 3 34 ADSP BF561 processors 3 40 3 44 block headers SHARC processors ADSP 2106x 160 processors 4 17 ADSP 21161 processors 5 17 ADSP 2126x 36x 37x processors 6 18 6 22 blocks of application code Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 9 ADSP BF535 processors 3 33 ADSP BF561 processors 3 38 blocks of application code SHARC processors ADSP 2106x 160 processors 4 17 ADSP 21161 processors 5 17 ADSP 2126x 36x 37x processors 6 22 BMODE1 0 pins ADSP BF531 2 3 8 9 processors 3 4 3 17 3 78 BMODE2 0 pins ADSP BF5 1x processors 2 3 ADSP BF531 2 3 8 9 processors 3 8 ADSP BF534 6 7 processors 3 4 ADSP BF535 processors 3 17 3 22 3 78 baud rate Blackfin processors 3 26 3 39 3 73 BMODE3 0 pins BFLAG_CALLBACK block flag 2 9 BFLAG_QUICKBOT block flag 2 15 ADSP BF52x 54x processors 2 4 2 VisualDSP 5 0 Loader and Utilities Manual BMS pins ADSP 2106x 160 processors 4 5 4 7 4 10 4 11 4 15 4 23 ADSP 21161 processors 5 4 5 6 5 9 5 13 5 15 5 22 TigerSHARC processors 7 2 7 3
24. boot stream compression from the command line VisualDSP also offers a dedicated loader property page see Figure 3 29 to manage the compression from the IDDE The loader utility takes two steps to compress a boot stream First the utility generates the boot stream in the conventional way builds data blocks then applies the compression to the boot stream The decompres 3 50 VisualDSP 5 0 Loader and Utilities Manual Loader Splitter for ADSP BF53x BF561 Blac kfin Processors sion initialization is the reversed process the loader utility decompresses the compressed stream first then loads code and data into memory seg ments in the conventional way The loader utility compresses the boot stream on the dxe by dxe basis For each input dxe file the utility compresses the code and data together including all code and data from any associated overlay ov1 and shared memory sm files Compressed Streams Figure 3 23 illustrates the basic structure of a loader file with compressed streams INITIALIZATION CODE KERNEL WITH DECOMPRESSION ENGINE 15T xe COMPRESSED STREAM 1ST dxe UNCOMPRESSED STREAM 2ND dxe COMPRESSED STREAM 2ND dxe UNCOMPRESSED STREAM Figure 3 23 Loader File with Compressed Streams The initialization code is on the top of the loader file The initialization code is loaded into the processor first and is executed first when a boot process starts Once the initialization code is executed the
25. modifying 5 18 5 19 rebuilding 5 18 5 19 kernels ADSP 2126x 36x 37x 46x processors boot sequence 6 3 6 19 compression decompression 6 34 6 35 6 39 default source files 6 19 loading to processor 6 8 6 13 modifying 6 20 omitting in output 6 17 rebuilding 6 20 kernels Blackfin processors See also second stage loader compression decompression 3 51 3 56 graphical user interface 2 19 3 75 omitting in output 3 65 specifying boot mode 2 12 2 18 3 62 3 72 specifying file format 2 12 2 13 3 63 specifying file width 2 18 3 63 3 72 specifying hex address 2 12 3 63 specifying hold time 3 73 specifying kernel and app files 2 20 3 76 specifying user kernel 2 13 3 64 kernels TigerSHARC processors modifying 7 5 omitting in output 7 4 7 10 source files 7 4 specifying user kernel 7 10 VisualDSP 5 0 Loader and Utilities Manual I 9 INDEX kf hex ascii binarylinclude loader switch for Blackfin 2 12 3 63 knl kernel code files 2 7 3 59 kp loader switch for Blackfin 2 12 2 14 3 63 3 66 kWidth loader switch for Blackfin 2 13 3 63 L L1 memory Blackfin processors ADSP BF531 2 3 4 6 7 8 9 processors 3 7 3 13 3 20 ADSP BF535 processors 3 26 3 34 3 35 ADSP BF561 processors 3 38 3 46 L2 memory Blackfin processors ADSP BF535 processors 3 24 3 25 3 26 3 34 3 35 ADSP BF561 processors 3 45 3 46 last blocks Blackfin processors ADSP BF
26. only one initialization tag per width because there is no need to draw dis tinction between pm and dm sections during initialization The same tag is used for 16 bit short word 32 bit normal word and 64 bit long word blocks that contain only zeros The 0x1 tag is used for ZERO_INIT blocks of 16 bit 32 bit and 64 bit words The 0x2 tag is used for ZERO_INIT blocks of 40 bit data and 48 bit instructions 6 24 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 2126x 2136x 2137x 21469 SHARC Processors For clarity the letter L has been added to the names of the internal block tags L indicates that the associated section header uses the logical word count and Jogical address Previous SHARC boot kernels do not use logi cal values For example the count for a 16 bit block may be the number of 32 bit words rather than the actual number of 16 bit words Only four tags are required to handle an external memory two for each packing mode see Packing Options for External Memory on page 6 7 because parallel port DMA is the only way to access the external memory The external memory can be accessed only via the physical address of the memory This means that each 32 bit word corresponds to either four for 8 bit or two for 16 bit external addresses The EXT appended to the name of the block tag indicates that the address is a physical external address For the ADSP 21367 21368 21369 2137x and ADSP 21469 processors tag
27. proc ADSP 21161 Specifies ADSP 21161 as the target processor Multiprocessor Systems The following command line elfloader proc ADSP 21161 bprom idlexe Inputl dxe id2exe Input2 dxe runs the loader utility with e proc ADSP 21161 Specifies ADSP 21161 as the target processor e bprom Specifies EPROM booting as the boot type for the boot loadable file e jdlexe Input1 dxe lIdentifies Input1 dxe as the executable file to process into a boot loadable file for a processor with ID of 1 see Processor ID Numbers on page 5 23 e d2exe Input2 dxe Identifies Input2 dxe as the executable file to process into a boot loadable file for a processor with ID of 2 see Processor ID Numbers on page 5 23 5 26 VisualDSP 5 0 Loader and Utilities Manual Loader for ADSP 21161 SHARC Processors File Searches File searches are important in loader processing The loader utility sup ports relative and absolute directory names default directories and user selected directories for file search paths File searches occur as described on page 1 17 File Extensions Some loader switches take a file name as an optional parameter Table 5 9 lists the expected file types names and extensions Table 5 9 File Extensions Extension File Description dxe Executable files and boot kernel files The loader utility recognizes overlay memory files ov1 and shared memory files sm but does no
28. si revision alone or with an invalid value the loader utility generates an error v Outputs verbose loader messages and status information as the loader utility processes files version Directs the loader utility to show its version information Type elfloader version to display the version of the loader drive Add the proc switch for example elfloader proc ADSP 21262 version to display version information of both loader drive and SHARC loader VisualDSP 5 0 Loader and Utilities Manual 6 47 ADSP 2126x 2136x 2137x 21469 Processor Loader Guide Using VisualDSP Interface Load Page After selecting a Loader file as the target type on the Project page in Visu alDSP Project Options dialog box modify the default options on the Load pages also called loader property page Click OK to save the selec tions Selecting Build Project from the Project menu generates a loader file For information relative to a specific processor refer to the Visu alDSP online help for that processor VisualDSP invokes the elfloader utility to build the output file Dia log box buttons and fields correspond to command line switches and parameters see Table 6 18 on page 6 43 Use the Additional Options box to enter options that have no dialog box equivalent 6 48 VisualDSP 5 0 Loader and Utilities Manual 7 LOADER FOR TIGERSHARC PROC ESSO RS This chapter explains how the loader utility e floader exe
29. symbol Caution Incorrect device operation may result if Caution Device damage may result if A Caution identifies conditions or inappropriate usage of the product that could lead to undesirable results or product damage In the online version of this book the word Caution appears instead of this symbol Warning Injury to device users may result if A Warning identifies conditions or inappropriate usage of the product that could lead to conditions that are potentially hazardous for the devices users In the online version of this book the word Warning appears instead of this symbol VisualDSP 5 0 Loader and Utilities Manual xix Notation Conventions XX VisualDSP 5 0 Loader and Utilities Manual 1 INTRODUCTION The majority of this manual describes the loader utility or loader pro gram as well as the process of loading and splitting the final phase of the application development flow Most of this chapter applies to all 8 16 and 32 bit processors Informa tion specific to a particular processor or to a particular processor family is provided in the following chapter Chapter 2 Loader Splitter for ADSP BF51x BF52x BF54x Blackfin Processors Chapter 3 Loader Splitter for ADSP BF53x BF561 Blackfin Processors Chapter 4 Loader for ADSP 2106x 21160 SHARC Processors Chapter 5 Loader for ADSP 21161 SHARC Processors Chapter 6 Loader for ADSP 2126x 21
30. the loader output in include format have some basic parts in the following order 1 Initialization code some Blackfin processors 2 Boot kernel some Blackfin SHARC and TigerSsHARC processors 3 User application code A 8 VisualDSP 5 0 Loader and Utilities Manual File Formats 4 Saved user code in conflict with the initialization code some Blackfin processors 5 Saved user code in conflict with the kernel code some Blackfin SHARC and TigerSHARC processors The initialization code is an optional first part for some Blackfin proces sors while the kernel code is the