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ANALOG DEVICES ADSP-2136x SHARC Processor Hardware Reference (includes the ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 processors) Revision 2.0 June 2009 Manual

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Contents

1. Register Mnemonic Address Description Reset IISPOA 0xC40 Internal memory DMA address Undefined IMSPOA 0xC41 Internal memory DMA access modifier Undefined CSPOA 0xC42 Contains number of DMA transfers remaining Undefined CPSPOA 0xC43 Points to next DMA parameters Undefined IISPOB 0xC44 Internal memory DMA address Undefined IMSPOB 0xC45 Internal memory DMA access modifier Undefined CSPOB 0xC46 Contains number of DMA transfers remaining Undefined CPSPOB 0xC47 Points to next DMA parameters Undefined IISP1A 0xC48 Internal memory DMA address Undefined IMSP1A 0xC49 Internal memory DMA access modifier Undefined CSP1A 0xC4A Contains number of DMA transfers remaining Undefined CPSP1A 0xC4B Points to next DMA parameters Undefined IISP1B 0xC4C Internal memory DMA address Undefined IMSP1B 0xC4D Internal memory DMA access modifier Undefined CSP1B OxC4E Contains number of DMA transfers remaining Undefined CPSPIB OxC4F Points to next DMA parameters Undefined TXSPOA 0xC60 SPORT 0A transmit data Undefined RXSPOA 0xC61 SPORT 0A receive data Undefined TXSPOB 0xC62 SPORT OB transmit data Undefined RXSPOB 0xC63 SPORT OB receive data Undefined TXSPIA 0xC64 SPORT 1A transmit data Undefined RXSP1A 0xC65 SPORT 1A receive data Undefined TXSP1B 0xC66 SPORT 1B transmit data Undefined RXSP1B 0xC67 SPORT 1B receive data Undefined Serial Port 2 and 3 Registers SPCTL2 0x400 SPORT 2 control 0x0000 0000 SPCTL3
2. Interrupt Vector Programmable Default Default Function Priority Name Address Interrupt Control Select Register PICR Value POI 0x2C PICRO 4 0 0x00 DAIHI interrupt HIGHEST pii 0x30 PICRO 9 5 0x01 SPII high interrupt P2I 0x34 PICRO 14 10 0x02 GP timer 0 interrupt P3I 0x38 PICRO 19 15 0x03 SPORT1 interrupt P4I 0x3C PICR0 24 20 0x04 SPORTS interrupt PSI 0x40 PICR0 29 25 0x05 SPORTS interrupt P6I 0x44 PICR1 4 0 0x06 SPORTO interrupt P7I 0X48 PICR1 9 5 0x07 SPORT 2 interrupt P8I 0X4C PICRI 14 10 0x08 SPORT4 interrupt por 0X50 PICR1 19 15 0x09 Parallel port interrupt P10I 0X54 PICR1 24 20 0x0A GP Timer 1 interrupt P11I 0x58 PICR1 29 25 0x0B Reserved P121I 0x5C PICR2 4 0 0x0C DAILI interrupt P13I 0x60 PICR2 9 5 0x0D PWM interrupt P14I 0x64 PICR2 14 10 OxOE Reserved P15I 0x68 PICR2 19 15 OxOF MTM DTCP interrupt P16I 0x6C PICR2 24 20 0x10 Reserved P171 0x70 PICR2 29 25 0x11 GP timer 2 interrupt P18I 0x74 PICR3 4 0 0x12 SPIB low interrupt LOWEST 1 These interrupts have an option to be unmasked at reset Therefore the peripherals that boot the pro cessor should be allocated these interrupts P11 POI B 2 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Interrupts Programmable Interrupt Control Register 0 PICRO This 32 bit read write register shown in Figure B 1 controls programma ble p
3. Block Start Oversampling ratio DIT_VALIDR DIT SCDF Validity Bit B Single Channel Double Fre DIT VALIDL quency Mode Enable Validity bit A JpIT SCDF LR DIT AUTO Select SCDF Channel Automatically Block Start DIT SMODE IN 8 6 Serial Data Input Format Figure A 35 DITCTL Register A 70 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference Table A 33 DITCTL Register Bit Descriptions Bit Name Description 0 DIT EN Transmitter Enable Enables the transmitter and resets the control registers to their defaults 0 Transmitter disabled 1 Transmitter enabled 1 DIT MUTE Mute Mutes the serial data output 3 2 DIT FREQ Frequency Multiplier Sets the over sampling ratio to the fol lowing 00 256 x frame sync 01 384 x frame sync 10 11 Reserved 4 DIT SCDF Single channel Double frequency Mode Enable 0 2 channel mode 1 SCDF mode 5 DIT SCDF LR Select Single channel Double frequency Mode 0 Left channel 1 Right channel 8 6 DIT_SMODEIN Serial Data Input Format Selects the input format as follows 000 Left justified 001 PS 010 reserved 011 reserved 100 Right justified 24 bits 101 Right justified 20 bits 110 Right justified 18 bits 111 Right justified 16 bits 9 DIT_AUTO Automatically Generate Block Start Automa
4. g 30 29 ze 26 25 2s 22 21 20 19 18 17 16 Lll DIR 1 29 25 SPDIF Receiver Biphase Encoded Data Input 15 14 13 2 1 10 9 87 6 5 JE 2 1 o IDP6_FS_l 19 15 Lp IDP5 FS 1 14 10 Input Data Port Channel 5 FS Input IDPA FS I 9 5 Input Data Port Channel 4 FS Input Figure A 54 SRU_FS3 Register l IDPO FS lor PDAP HOLD 1l 19 15 con t Input Data Port Channel 0 FS Input IDP1 FS 24 20 Input Data Port Channel 1 FS Input SRC3 FS IP I 4 0 Sample Rate Converter 3 FS Input Input SRC3 FS OP I 9 5 Sample Rate Converter 3 FS Output Input IDP6 FS 1 19 15 con t Input Data Port Channel 6 FS Input IDP7 FS 1 24 20 Input Data Port Channel 7 FS Input E ee ey Input Data Port Channel 3 FS Input ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 91 DAI Signal Routing Unit Registers Table A 44 Group C Sources Frame Sync Selection Code Source Signal Description Source Selection 00000 0x0 DAI PB01 O Pin buffer 1 00001 0x1 DAI PB02 O Pin buffer 2 00010 0x2 DAI PB03 O Pin buffer 3 00011 0x3 DAI PB04 O Pin buffer 4 00100 0x4 DAI PB05 O Pin buffer 5 00101 0x5 DAI PB06 O Pin buffer 6 00110 0x6 DAI PB07 O Pin buffer 7 00111 0x7 DAI PB08 O Pin buffer 8 010
5. P18l 4 0 SPI Low Interrupt Programmable Interrupt 18 Figure B 4 PICR3 Register ADSP 2136x SHARC Processor Hardware Reference B 5 for the ADSP 21362 3 4 5 6 Processors Programmable Interrupt Control Registers B 6 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors C AUDIO FRAME FORMATS This appendix introduces all the serial timing protocols used for audio inter chip communications These formats are listed and their availability in the various peripherals noted in Table C 1 Table C 1 Audio Format Availability Frame Format SPORTs IDP SIP ASRC ASRC S PDIF S PDIF PCG Input Output Tx Rx Serial Yes Yes IS Yes Yes Yes Yes Yes Yes Yes Left justified Yes Yes Yes Yes Yes Yes Right justified Yes Yes Yes Yes Yes 24 bit Right justified Yes Yes Yes Yes Yes 20 bit Right justified Yes Yes Yes Yes Yes 18 bit Right justified Yes Yes Yes Yes Yes 16 bit TDM 128 Yes Yes Yes Yes channel ADSP 2136x SHARC Processor Hardware Reference C 1 for the ADSP 21362 3 4 5 6 Processors Overview Overview The following protocols are available in the SHARC processor and are briefly described in this appendix For complete information on the indus try standard protocols see the specification listings in each section Standard Serial Mode e Left justified Mode Sony format I Mode Sony Philips
6. sf 13 AE 10 9 JE 6 5 HE 2 1 o CLKA SYNC Sync CLKA with external LRCLK ____FSB_SYNC Sync FSA with external LRCLK Figure A 34 PCG_SYNC Register Table A 32 PCG_SYNC Register Bit Descriptions in Normal Mode Bit Name Description 0 FSA_SYNC Enable trigger of frame sync A with external LRCLK 1 CLKA SYNC Enable trigger of CLKA with external LRCLK 16 FSB_SYNC Enable trigger of frame sync B with external LRCLK 17 CLKB_SYNC Enable trigger of CLKB with external LRCLK ADSP 2136x SHARC Processor Hardware Reference A 69 for the ADSP 21362 3 4 5 6 Processors Peripherals Routed Through the DAI Sony Philips Digital Interface Registers The following sections describe the registers that are used to configure enable and report status information for the S PDIF transceiver Transmitter Registers Transmit Control Register DITCTL This 32 bit read write register s bits are shown in Figure A 35 and described in Table A 33 e 30 29 28 27 26 25 24 zs 22 21 20 io 18 17 16 DIT_BOCHANR Ba T e DIT_BOCHANL 23 16 Channel Status Byte 0 for Subframe B Channel Status Byte 0 for Subframe A Ps tis lo v ve o e F 8 5 e T2 7 o S Lo EXT_SYNC_EN B DIT_EN External Sync Enable Transmitter Enable USER_BITS_PEND DIT_MUTE Status Bit Mute serial data output DIT_BLKSTART DIT_FREQ 3 2
7. Selection Code Source Signal Description Source Selection 0000000 0x0 DAI PB01 O Pin buffer 1 0000001 0x1 DAI PB02 O Pin buffer 2 0000010 0x2 DAI PB03 O Pin buffer 3 0000011 0x3 DAI PB04 O Pin buffer 4 0000100 0x4 DAI PB05 O Pin buffer 5 0000101 0x5 DAI PBOG O Pin buffer 6 0000110 0x6 DAI PB07 O Pin buffer 7 0000111 0x7 DAI PB08 O Pin buffer 8 0001000 0x8 DAI PB09 O Pin buffer 9 0001001 0x9 DAI PB10 O Pin buffer 10 0001010 0xA DAI PB11 O Pin buffer 11 0001011 OxB DAI PB12 O Pin buffer 12 0001100 0xC DAI PB13 O Pin buffer 13 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 95 DAI Signal Routing Unit Registers Table A 45 Group D Sources Pin Signal Assignments Cont d Selection Code Source Signal Description Source Selection 0001101 0xD DAI PB14 O Pin buffer 14 0001110 OxE DAI PB15 O Pin buffer 15 0001111 OxF DAI PB16 O Pin buffer 16 0010000 0x10 DAI PB17 O Pin buffer 17 0010001 0x11 DAI PB18 O Pin buffer 18 0010010 0x12 DAI PB19 O Pin buffer 19 0010011 0x13 DAI PB20 O Pin buffer 20 0010100 0x14 SPORTO DA O SPORT 0A data 0010101 0x15 SPORTO DB O SPORT OB data 0010110 0x16 SPORT1_DA_O SPORT 1A data 0010111 0x17 SPORTI DB O SPORT 1B data 0011000 0x18 SPORT2 DA O SPORT 2A data 0011001 0x19 SPORT2 DB O SPORT 2B data 0011010 0x1A SPORT3 DA O SPORT
8. PWM PHASE Phase Status Figure A 12 PWMSTATX Register Table A 11 PWMSTAT x Register Bit Descriptions Bit Name Description 0 PWM PHASE PWM Phase Status Set during operation in the second half of each PWM period Allows programs to determine the particular half cycle first or second during implementation of the PWM SYNC interrupt service routine if required 0 First half 1 Second half 1 Reserved 2 PWM_PAIRSTAT PWM Paired Mode Status 0 Inactive paired mode 1 Active paired mode 15 3 Reserved A 26 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference PWM Period Registers PWMPERIODx These 16 bit read write registers control the unsigned period of the four PWM groups PWM Output Disable Registers PWMSEGx These 16 bit read write registers shown in Figure A 13 and described in Table A 12 control the output signals of the four PWM groups sT 13 i 10 9 gE EN 5 4s 2 1 0 PWM AXOV PWM BH Crossover Mode PWM BL PWM BXOV PWM AH Crossover Mode ES PWM AL Figure A 13 PWMSEG x Register Table A 12 PWMSEGx Register Bit Descriptions Bit Name Description 0 PWM BH Channel B High Disable Enables or disables the channel B output signal 0 Enable 1 Disable 1 PWM_BL Channel B Low Disable Enables or disa
9. PWM_POLOAH Channel A High Polarity 0 Figure A 14 PWMPOLx Register Table A 13 PWMPOLsx Register Bit Descriptions Bit Name Description 0 PWM POLIAL Write 1 to set channel A low polarity 1 1 PWM_POLOAL Write to set channel A low polarity 0 A 28 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference Table A 13 PWMPOLx Register Bit Descriptions Contd Bit Name Description 2 PWM_POL1AH Write 1 to set channel A high polarity 1 3 PWM_POLOAH Write 1 to set channel A high polarity 0 4 PWM_POLIBL Write 1 to set channel B low polarity 1 5 PWM_POLOBL Write 1 to set channel B low polarity 0 6 PWM_POL1BH Write 1 to set channel B high polarity 1 y PWM_POLOBH Write 1 to set channel B high polarity 0 15 8 Reserved PWM Channel Duty Control Registers PWMAx PWMBx The 16 bit duty cycle control registers directly control the A B two s complement duty cycles of the two pairs of PWM signals PWM Channel Low Duty Control Registers PWMALx PWMBLx The 16 bit duty cycle control registers directly control the AL BL duty cycles two s complement of the non paired PWM signals These can be different from the AH BH cycles PWM Dead Time Registers PWMDTx These 16 bit registers setup a short time delay 10 bit unsigned between turning off one PWM signal and turning on its complementary signal
10. 5 27 ers Misit MEN 5 28 ror 5 29 M edt Me 5 29 Loop Back Routt susci iaoi 5 30 ia ic VOCED S 5 31 SERIAL PORTS PRIDRERS Laisser p ph E en E Manni E LU Ll blast E Look Hoetiett 6 4 QUEE iir c 6 6 SRU OUR 21 o pcs amistad dede aded M dine 6 6 ADSP 2136x SHARC Processor Hardware Reference ix for the ADSP 21362 3 4 5 6 Processors Contents SRU SPORE Reserve Master ooo dons ert ter qek s ei pedi ep ttm une 6 7 SRU SPORT Bipiul DRWERUIDE aseenaan 6 7 Bea Rae DNE suramericano MEN Mu D IN Tk 6 9 Ber ey oai aite WM dedbdq aM ddp M irat E 6 10 Control Registers SPC ae ieisecenp idetk bath bebida pix bed lee tn ad iad 6 12 Multichannel Control Registers SPMCTLxy 6 12 Ds UP Sete eee eae eae emis 6 13 Transmit Buffers TXSPxA B cscsesavccsarsnvsaxcoccesarcieersucaonacses 6 13 Tanpoi Pah ae eee ee 6 14 Receive Buffers RXSPxA B cocccccsscvccccodveseacnscrsevecsdadsvcnscess 6 14 Rete Pati aieuenib aed ainni e E EUH NRI a REDE 6 15 DAE occus eee ee eee 6 15 Mulachannel Biter Stats vcnos 6 17 Seleoring Orit Modot soreta a a UN END PME 6 18 Mode Sabi dercesine usecase 6 19 Data Word FOMA ascent ann eee 6 20 Word Length GLEN oaseisuchmesictiddt da kids tiui aapne ik 6 20 Endian Format LSBF aepo Rmi bip DE Rte rra 6 21 Doca Packing PACK cerniere estar di 6 21 Data Type ETD erisera ror deett ipn piae 6 22 Companding th Dara
11. Bits 27 4 24 Bit Audio Data 3 2 1 0 Validity Bit lt a User Data Channel Status Block Start Figure 11 4 Data Packing for Right Justified Format 24 Bits Bits 27 8 20 Bit Audio Data 7 6 5 Validity Bit User Data Channel Status A BITS 3 0 Block Start Padding zero Figure 11 5 Data Packing for Right Justified Format 20 Bits ADSP 2136x SHARC Processor Hardware Reference 11 7 for the ADSP 21362 3 4 5 6 Processors S PDIF Transmitter Bits 27 10 18 Bit Audio Data 8 7 6 BITS 5 0 9 Validity Bit va User Data Channel Status Block Start Padding zero Figure 11 6 Data Packing for Right Justified Format 18 Bits Bits 27 12 16 Bit Audio Data 11 10 9 8 BITS 7 0 Validity Bit a User Data Channel Status Block Start Padding zero Figure 11 7 Data Packing for Right Justified Format 16 Bits Output Data Mode Two output data formats are supported by the transmitter wo channel mode and single channel double frequency SCDF mode The output for mat is determined by the transmitter control register DITCTL In two channel mode the left channel channel A is transmitted when the DIT FS I is high and the right channel channel B is transmitted when the DIT FS I is low In SCDF mode the transmitter sends successive audio samples of the same signal across both sub frames instead
12. M i M 1 i M 1 M 1 M 1 i Figure 9 9 Timer PWM Enable and Disable Timing Debug Features The following section provides information on debugging features avail able with the timer Note that in emulation space during a core halt that the timer continues to operate ADSP 2136x SHARC Processor Hardware Reference 9 21 for the ADSP 21362 3 4 5 6 Processors Programming Model Loopback Routing The timer support an internal loopback mode by using the SRU For more information see Loop Back Routing on page 5 30 Programming Model The section describes which sequences ofsoftware steps are required to get the peripheral working successfully PWM Ovut Mode Use the following procedure to configure and run the timer in PWM out mode 1 Reset the TIMEN bit and set the configuration mode to 01 to select PWM OUT operation This configures the TIMERx 0 pin as an output pin with its polarity determined by the PULSE bit Measures a positive active pulse width at the TIMERx 0 pin Measures a negative active pulse width at the TIMERx 0 pin 2 Initialize the period and width register values Insure that the period value is greater than the width value 3 Set the TIMEN bit The timer performs boundary exception checks on the period and width values f width 0 or Period lt width or period width both the OVF ERR and TRO bits are set e f there are no exceptions the width value is loaded into the
13. 6 46 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports Receive Selection Registers Setting a particular bit to 1 in theMR1CS0 3 MR3CS0 3 or MR5CS0 3 register causes the serial port to receive the word in that channel s position of the data stream The received word is loaded into the receive buffer Clearing the bit in the register causes the serial port to ignore the data Data Transfer Types Serial port data can be transferred for use by the processor in two different methods e Core driven single word transfers DMA transfers between both internal and external memory DMA transfers can be set up to transfer a configurable number of serial words between the serial port buffers TXSPxA TXSPxB RXSPxA and RXSPxB and internal memory automatically Core driven transfers use SPORT interrupts to signal the processor core to perform single word transfers to from the serial port buffers TXSPxA TXSPxB RXSPxA and RXSPxB Core Transfers The following sections provide information on core driven data transfers Single Word Transfers Individual data words may also be transmitted and received by the serial ports with interrupts occurring as each 32 bit word is transmitted or received When a serial port is enabled and DMA is disabled the SPORT interrupts are generated whenever a complete 32 bit word has been received in the receive buffer or whenever the transmit buffer is no
14. 7 20 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Peripheral Interface Ports BAUD Rate Register SPIBAUDx For master devices the clock rate is determined by the 15 bit value of the baud rate registers SPIBAUDx as shown in Table 7 5 For slave devices the value in the SPIBAUDx register is ignored For more information see SPI Baud Rate Registers SPIBAUD SPIBAUDB on page A 20 Table 7 5 SPI BAUD Rate Settings BAUDR Bit Setting Divider SPICLK PCLK 167 MHz 0 N A N A 1 8 41 7 MHz 2 16 20 8 MHz 3 24 13 9 MHz 4 32 10 4 MHz 32 767 0x7FFF 262136 1 3 KHz DMA Control Register SPIDMACx This register contains the error status bits SPIMME SPIUNF SPIOVF and SPIERRS These bits are set when an error occurs during a DMA transfer The SPIERRS bit is set if any ofthe SPIMME SPIUNF SPIOVF bits is set An interrupt can be generated with the INTERR bit to respond to these errors Data Transfer Types The SPI is capable of transferring data via the core and DMA The follow ing sections describe these transfer types ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors 7 21 Data Transfer Types Core Transfers For core driven SPI transfers the software has to read from or write to the RXSPIx and TXSPIx registers respectively to control the transfer It is important to check
15. 0 MCEA Multichannel Mode Enable Standard and multichannel modes only One of two configuration bits that enable and disable multichannel mode on serial port channels See also OPMODE on page A 26 0 Disable multichannel operation 1 Enable multichannel operation if OPMODE 0 4 1 MFD Multichannel Frame Delay Sets the interval in number of serial clock cycles between the multichannel frame sync pulse and the first data bit These bits provide support for different types of T1 interface devices Valid values range from 0 to 15 with bits SPMCTLO1 4 1 SPMCTL23 4 1 or SPMCTL45 4 1 Values of 1 to15 correspond to the number of intervening serial clock cycles A value of 0 corresponds to no delay The multichannel frame sync pulse is concurrent with first data bit 11 5 NCH Number of Multichannel Slots minus one Selects the number of channel slots maximum of 128 to use for multichannel operation Valid values for actual number of channel slots range from 1 to 128 Use this formula to calculate the value for NCH NCH Actual number of channel slots 1 12 SPL SPORT Loopback Mode Enables if set 1 or disables if cleared 0 the channel loopback mode Loopback mode enables developers to run internal tests and to debug applications Loopback only works under the following SPORT configurations SPORTO configured to receive or transmit together with SPORTI configured to transmit or receive SPO
16. 1001110 Ox4E DIR LRCLK REF O External PLL reference point connec tion 0x52 Ox7F 1001111 Ox4F Reserved 1010000 0x50 LOW Logic level low 0 1010001 0x51 HIGH Logic level high 1 1010010 1111111 Reserved Miscellaneous Signal Routing Registers SRU MISCx Group E The miscellaneous registers see Figure A 60 and Figure A 61 are a very powerful and versatile feature of the DAI These registers allow external pins timers and clocks to serve as interrupt sources or timer inputs and outputs They also allow pins to connect to other pins or to invert the logic of other pins Notice that when the PCG s one shot option PCG PW A 98 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference register is enabled the inputs MISCA2 1 PCG unit A and MISCA3 I1 PCG unit B are used asinput signals Also notice if using the S PDIF Tx block start output it must be routed to the MISCB4_I input for interrupt operation The miscellaneous signal routing registers correspond to the group E mis cellaneous signals listed in Table A 46 31 30 29 28 27 26 25 2a 2s 22 2 20 19 17 eee MISCAS5 INVERT Invert Miscellaneous Channel A 5 MISCA4_INVERT Invert Miscellaneous Channel A 4 MISCA5_l 29 25 B External Miscellaneous Channel A 5 SPIB MOSI I Second
17. 2 26 br cq en Diyen TO cere PPM Polisi DMA Channel SUN oisi erie riii ids endi bap pa GE 2 28 Standard DMA Status M dae anina nA 2 29 Morin Mr e ric errre aeann 2 29 ADSP 2136x SHARC Processor Hardware Reference v for the ADSP 21362 3 4 5 6 Processors Contents TOB Stripe 2 30 vu iN on UGE E EN E EA 2 30 Parallel Port TOD i ctressn arenes do dpi auc RE nEMUE RU 2 30 LEE ooo sessi dimi beim eee 2 31 DU Processor Keriter AGGES uai cibebiiiui Chri Pb nidek 2 32 IOP Access Condition occured vein idipIMP Rp entidad a EE 2 32 Interrupt Latency 24233 TCD Chami Loading Be 2 34 TOP Register Boni Arbitration oa ace Qa edt dba Ue 2 34 Wd c eet 2 35 MEMORY TO MEMORY PORT DMA ic elo MEME RIP 3 2 Peer al Description ooa nu d oatid dde edE a Ms 3 2 p fA co 3 2 i R 3 3 licis e 23 Dare Thoo I M V 3 3 docto rq rl M 3 4 Pee DIO ao eda Ponit p spl tis Risa IRI MR E EE NH 3 4 PARALLEL PORT ioo mW NIIT 4 2 Pin Deseripti ns M 4 3 Mules Pin PIOS sneren 4 4 vi ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Contents Perit ie oxedeeveienitotaboliseeniletidirlmen tiii tppis 4 4 tuiles BW Tar iio MEINE NI ES 4 4 Address Cyle MP 4 4 Et e e A E EA A E E A A E E 4 5
18. Figure A 48 SRU_DAT3 Register A 86 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference 2 29 ze z se 26 25 24 23 22 21 20 19 18 17 rel i L IDP1 DAT 17 12 con t IDP3 DAT 29 24 Input Data Port 1 Data Input Input Data Port 3 Data Input IDP2 DAT 1I 23 18 Input Data Port 2 Data Input 15 14 18 12 11 10 IDP1 DAT 17 12 IM IDPO DAT 1 11 6 DIT DAT 5 0 Input Data Port 0 Data Input SPDIF Transmit Data Input Figure A 49 SRU_DAT4 Register g 30 29 28 E 26 25 24 E 22 21 20 E 18 17 16 Li re DAT_I 17 12 con t IDP7 DAT 23 18 Input Data Port 6 Data Input Input Data Port 7 Data Input 5 12 l 1 JE o IDP6 DAT pote c IDP4 DAT 1 0 5 IDP5 DAT I 11 6 Input Data Port 4 Data Input Data Port 5 Data Input Input Figure A 50 SRU DAT5 Register Table A 43 Group B Sources Serial Data Selection Code Source Signal Description Source Selection 000000 0x0 DAI PB01 O Pin buffer 1 000001 0x1 DAI PB02 O Pin buffer 2 000010 0x2 DAI PB03 O Pin buffer 3 000011 0x3 DAI_PB04_O Pin buffer 4 000100 0x4 DAI_PB05_O Pin buffer 5 000101 0x5 DAI_PB06_O Pin buffer 6 ADSP 2136x SHARC Processor
19. PPEN Parallel Port Enable 0 Disable parallel port Clearing this bit clears the FIFO and the parallel status information If an RD WR or ALE cycle has already started it completes normally before the port is disabled The parallel port is ready to transmit or receive two cycles after it is enabled An ALE cycle always occurs before the first read or write cycle after PPEN is enabled 1 Enable parallel port 5 1 PPDUR Parallel Port Duration The duration of parallel port data cycles is determined by these bits ALE cycles are not affected by this setting and are fixed at 3 PCLK cycles 00010 3 clock cycles 55 5 MHz throughput 00011 4 clock cycles 41 6 MHz throughput 00100 5 clock cycles 33 3 MHz throughput 00101 6 clock cycles 27 75 MHz throughput to 11111 32 clock cycles 5 2 MHz throughput The default setting is for user boot mode only Otherwise bits 1 through 5 are all zeros PPBHC Bus Hold Cycle If set 1 this causes every data cycle to be prolonged for 1 PCLK period If cleared 0 no bus hold cycle occurs and the duration of data cycle is exactly the value specified in PPDUR Bus hold cycles do not apply to ALE cycles which are always 3 PCLK cycles Along with the PPFLMD bit 1 allows user boot mode When cleared 0 default for user boot mode only otherwise 1 PP16 Parallel Port External Data Width 0 External data width is 8 bits 1 External data width is 16 bit
20. For access latency of IOP registers see I O Processor Register Access on page 2 32 Programming Model The section describes some programming procedures that are used to enable and operate the SPORTs Setting Up and Starting Chained DMA To set up and initiate a chain of DMA operations use the following procedure 1 Clear the chain pointer register 2 For internal memory transfers set up all TCBs in intanal memory For external memory transfers TCBs can be set up in internal or external memory 3 Write to the appropriate DMA control register setting the DMA enable bit to one and the chaining enable bit to one 4 Write the address containing the index register value of the first TCB to the chain pointer register which starts the chain 6 56 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports Enter DMA Chain Insertion Mode Chain insertion lets the SPORT insert a single SPORT DMA operation or another DMA chain within an active SPORT DMA chain 1 Enter chain insertion mode by setting SDENx 0 and SCHENx 1 in the channel s DMA control register The DMA interrupt indicates when the current DMA sequence is complete 2 Copy the address currently held in the chain pointer register to the chain pointer position of the last TCB in the chain that is being inserted 3 Write the start address of the first TCB of the new chain into the chain pointer register
21. m PHASE SHIFT 2 l OTHER VALUES CLOCK DIVISOR 4 FRAME SYNC DIVISOR 16 PULSE WIDTH 8 Figure 13 3 Phase Shift Settings 13 12 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Precision Clock Generator Pulse Width Pulse width is the number of inputclock periods for which the frame sync output is high Pulse width should be less than the divisor of the frame sync The pulse width of frame sync A is specified in thePWFSA bits 15 0 of the PCG PW register and the pulse width of frame sync B is specified in the PWFSB bits 31 16 of the PCG PM register If the pulse width is equal to 0 or if the divisor is even then the actual pulse width of the frame sync output is equal to Pulse Width PrameSyneDivisor If the pulse width is equal to 0 or if the divisor is odd then the actual pulse width of the frame sync output is equal to Pulse Width Frames neos 1 Bypass Mode When the divisor for the frame sync hasa value of 0 or 1 the frame sync is in bypass mode and the PCG PW register has different functionality than in normal mode Two bit fields determine the operation in this mode The one shot which is a strobe pulse frame sync A or B STROBEx bit bits 0 and 16 in the PCG_PW register determines if the frame sync has the same width as the input or of a single strobe The active low frame sync select for the frame syncs INVFSx bit bits 1 and 17 of the PCG_PW registe
22. nop nop n op nop nop jump start rti rti PP interrupt service routine at location 0x00090050 section pm seg_pp jump is r L 3 a a Pee a a Pe Enable PP interrupt By default PPI interrupt is mapped to P9 interrup bit elr bit set m bit set lir t ptl P9I odel IRPTEN lir ptl P9IMSK Register used for comparison with the flag value in the ISR r15 0x rO 0x0 dm PPCTL rO 0x0 dm ECPP dmCICPP r d CPPP r0 roe ros 0 tx tcb 6 r0 4 26 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Parallel Port rO PPEN PPDUR20 PPDEN PPTRAN PPCHEN PPBHC dm PPCTL 9 r0 nop ADSP 2136x SHARC Processor Hardware Reference 4 27 for the ADSP 21362 3 4 5 6 Processors Programming Examples 4 28 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors 5 DIGITAL APPLICATION INTERFACE The digital application interface DAI is comprised of a groups of periph erals and its respective signal routing unit SRU The inputs and outputs of the peripherals are not directly connected to external pins Rather the SRUs connect the peripherals to a set ofpins and to eachother based on a set of configuration registers This allows the peripherals to be intercon nected to suit a wide variety of systems It also allows the ADSP 2136x SHARC processo
23. 30 29 ze 2 26 25 2a 2s 22 2 20 19 18 17 16 SRCy Serial Output Format SRCy_DITHER L SRCy_HARD_MUTE SRCy Hard Mute Enable SRCy_AUTO_MUTE SRCy Auto Hard Mute Enable from SPDIF RX SRCy_SMODEIN 20 18 SRCy Serial Input Format SRCy_BYPASS SRCy Bypass Mode SRCy Dither Enable SRCy_SOFTMUTE SRCy_DEEMPHASIS 23 22 SRCy De emphasis Filter SRCy Soft Mute Enable SRCx_RESET ga LL SRCx Reset SRCx_MPHASE SRCx Matched Phase Mode SRCx_LENOUT 13 12 SRCx Output Word Length SRCx_SMODEOUT 11 10 SRCx Serial Output Format SRCx_DITHER 5 14 13 BE 10 9 eT e 5 4 2 2 Jo SRCx Dither Enable SRCx_SOFTMUTE L SRCx_HARD_MUTE SRCx Hard Mute Enable SRCx_AUTO_MUTE SRCx Auto Hard Mute Enable from SPDIF RX SRCx_SMODEIN 4 2 SRCx Serial Input Format SRCx_BYPASS SRCx Bypass Mode SRCx_DEEMPHASIS 20 18 SRCx De emphasis Filter SRCO Soft Mute Enable Figure A 27 SRCCTLn Register Table A 27 SRCCTLn Register Bit Descriptions Bit Name Description 0 SRCx HARD MUTE Hard Mute Hard mutes SRC 0 2 1 Mute default SRCx AUTO MUTE Auto Hard Mute Auto hard mutes SRC 0 2 when non audio is asserted by the SPDIF receiver 0 No mute 1 Mute default A 60 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Pro
24. I 14 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors PDAP continued port mask bits IDP Pxx PDAPMASK A 51 rising or falling clock edge IDP_PDAP_CLKEDGE bit A 52 PDAP control IDP_PDAP_CTL register A 50 peripheral devices I O interface to 6 1 peripheral interrupt priority control PICR registers B 1 peripherals overview 1 7 peripheral timers configuring 9 5 A 56 external event watchdog EXT_CLK mode 9 6 9 17 input output TMRx pin 9 4 interrupts 9 20 invalid conditions 9 11 modes 9 4 period configuring 9 6 period equation 9 13 pulse width count and capture WD TH CAP mode 9 14 pulse width modulation PWMOUT mode 9 9 rectangular signals 9 12 RTI instruction 9 20 single pulse generation 9 13 TIMERx pin 9 5 TMRPDN peripheral timer enable disable bit A 9 watchdog 9 20 word count TMxCNT registers 9 5 peripheral timers registers 9 7 A 56 high word period TMxPRD registers 9 5 high word pulse width TMxW registers 9 5 period TMxPRD registers 9 6 pulse width TMxW registers 9 6 Index peripheral timers registers continued timer control TMxCTL 9 5 A 56 timer count TMxCNT 9 5 9 6 timer global status and control TMSTAT 9 7 timer status TMxSTAT A 57 timer width TMxW 9 6 timer word period TMxPRD 9 6 word count TMxCNT registers 9 6 phase shift of frame sync 13 11 PICR peripheral interrupt priority regi
25. There is a macro that has been created to connect peripherals used in a DAI configuration This code can be used in both assembly and C code See the INCLUDE file SRU H There is also a software plug in called the Expert DAI that greatly simplifies the task of connecting the signals described in this chap ter This plug in is described in Engineer to Engineer Note EE 243 Using the Expert DAI for ADSP 2126x and ADSP 2136x SHARC Processors This EE note is also found on the Analog Devices Web site 5 32 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors 6 SERIAL PORTS The ADSP 2136x processors have six independent synchronous serial ports SPORTS that provide an I O interface to a wide variety of periph eral devices They are called SPORTO SPORTI SPORT2 SPORTS SPORTA and SPORTS Each SPORT has its own set of control registers and data buffers With a range of clock and frame synchronization options the SPORTS allow a variety of serial communication protocols and provide a glueless hardware interface to many industry standard data converters and codecs Serial ports offer the additional features and capabilities shown in Table 6 1 Figure 6 1 and described in the following list Table 6 1 Serial Port Feature Summary Feature SPORTS5 O AB Connectivity Multiplexed Pinout No SRU DAI Required Yes SRU DAI Default Routing Yes Interrup
26. When the BYPASS bit is set 21 the input data bypasses the sample rate converter and is sent directly to the serial output port Dithering of the output data when the word length is set to less than 24 bits is disabled This mode is ideal when the input and output sample rates are the same and SRCx FS IP I and SRCx FS 0P I are synchronous with respect to each other This mode can also be used for passing through non audio data since no processing is performed on the input data in this mode Matched Phase Mode ADSP 21364 Only The matched phase mode of the sample rate converter is enabled by the SRCx MPHASE bit This mode is used to match the phase group delay 12 16 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Asynchronous Sample Rate Converter between two or more adjacent sample rate converters that are operating with the same input and output clocks When the SRCx_MPHASE bit is set 21 the SRC a matched phase mode slave accepts the sample rate ratio transmitted by another SRC the matched phase mode master through its serial output as shown in Figure 12 5 DATA INPUT 2 DATA INPUT 1 Non TDM IP FSout CLKout 32 x FSout Non TDM OP DATA OUTPUT 1 DATA OUTPUT 0 Figure 12 5 Typical Configuration for Matched Phase Mode Operation The phase master SRC device transmits its SRCx FS OP SRCx FS IP ratio through the data output pin SRCx DAT 0P 0 to the slave s SRC s data i
27. division ratios are implemented on the fly without entering bypass mode since the VCO frequency does not change The reset value for the output divisor of the PLLD bit field is 1 This value can be reprogrammed in the boot kernel to take effect immediately after startup Peripheral Clock PCLK The peripheral clock is derived from the core clock with a fixed divisor of 2 This clock feeds all the peripherals including the I O processor IOP Bypass Clock Bypass mode must be used if any runtime VCO clock change is required Setting the PLLBP bit bypasses the entire PLL circuitry In bypass mode the core runs at CLKIN speed Once the PLL has settled into the new VCO frequency which may take 4096 CLKIN cycles the PLLBP bit may be cleared to release the core from bypass mode Only VCO frequency changes require bypass mode This does not apply to the output divider block Power Savings The PMCTL register allows programs to disable the clock source to a partic ular peripheral for example the SPORTS or the SPI to further conserve power By default each peripheral block has its internal clock enabled only after it is initialized Programs can use the PMCTL register to turn the specific peripheral when not needed After reset these clocks are not enabled until the peripheral itself is initialized by the program 14 10 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors System Design Powe
28. e The global 1DP DMA EN bit of the IDP_CTL1 register to enable standard DMA on the selected channel e The global IDP EN bit bit 7 in the IDP CTLO register Starting a Ping Pong DMA Transfer To start a ping pong DMA transfer from the FIFO to memory l Clear the FIFO by setting 1 the IDP_FFCLR bit bit 31 in the IDP_CTL1 register While the global IDP_DMA_EN and IDP EN bits are cleared 0 set the values for the following DMA parameter registers that corre spond to channels 7 0 Keep the clock and the frame sync input of the serial inputs and or the PDAP connected to low by setting proper values in the SRU registers Refer to Setting Miscellaneous Bits above 8 28 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Input Data Port 5 Connect all of the inputs to the IDP by writing to the SRU registers 6 Enable the channel s IDP ENx IDP DMA ENx and IDP PINGx bit settings 7 Start DMA by setting e The IDP PDAP EN bit bit 31 in IDP_PP_ PDAP is required O TL register if the The global IDP_DMA_EN bit of the IDP_CTL1 register to enable the standard DMA of the selected channel e The global IDP EN bit bit 7 in the 1DP_ C TLO register Servicing Interrupts for DMA The following steps describe how to handle an IDP ISR for DMA 1 An interrupt is generated and program control jumps to the ISR when the DMA for a channel
29. l Before initializing DMA chaining clear the ECPP and ICPP registers to zero Set or reset the PPTRAN bit Depending on whether the operation is write or read ensure that the FIFO is empty and that the exter nal interface is idle by reading the status of the PPS and PPBS bits respectively Initialize the CPPP register with the address of the next transfer con trol block Set the PCI bit if the interrupt is needed at the end of each DMA block transfer Set the PPCTL register with all the required controls and enable the PPEN PPDEN and PPCHEN bits Once DMA chaining is enabled the DMA engine fetches the 11PP IMPP ICPP EIPP EMPP and ECPP register values from the memory address specified in the CPPP 4 24 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Parallel Port register Once the DMA descriptors are fetched normal DMA exe cution starts and continues until the CPPP register contains all zeros Configuring the Parallel Port for Core Access The following steps provide the basic procedure for setting up and initiat ing a data transfer using the core 1 Before initializing or modifying any of the parallel port parameter registers such as EIPP and EMPP the parallel port must first be dis abled bit 0 PPEN of the PPCTL register must be cleared Only when PPEN 0 may those registers be modified and the port then re enabled This sequence is most often used to perform
30. ter is set to zero at system reset or subsequently reset by user programs These registers are shown in Figure A 25 A 56 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference is 13 AR 10 eiel Tel IRQEN Interrupt Enable PRDCNT L TIMODE 1 0 Timer Mode PULSE Period Count Pulse Edge Select Figure A 25 TMxCTL Register Table A 25 TMxCTL Register Bit Descriptions Bit Name Definition 1 0 TIMODE Timer Mode 00 Reset 01 PWM_OUT mode TIMODEPWM 10 WDTH_CAP mode TIMODEW 11 EXT_CLK mode TIMODEEXT 2 PULSE Pulse Edge Select 1 Positive active pulse 0 Negative active pulse 3 PRDCNT Period Count 1 Count to end of period 0 Count to end of width 4 IRQEN Interrupt Enable 1 Enable 0 Disable Timer Status Registers TMxSTAT The global status registers TMxSTAT are shown in Figure A 26 Status bits are sticky and require a write one to clear operation During a status regis ter read access all reserved or unused bits return a zero Each timer generates a unique processor interrupt request signal TIMxIRQ A common status register latches these interrupts Interrupt bits are sticky and must be cleared to assure that the interrupt is not reissued ADSP 2136x SHARC Processor Hardware Reference A 57 for the ADSP 21362 3 4 5 6 Processors Peri
31. 28 E 26 25 24 22 22 21 20 19 18 17 tel o IDP DMAO STAT IDP_FIFOSZ IDP_DMA1_STAT Number of Valid Data in IDP FIFO IDP_DMA2_STAT IDP_DMA7_STAT IDP_DMA3_STAT IDP_DMA6_STAT IDP_DMA4_STAT IDP_DMA5_STAT DMA Active Status for IDP Channel s s e Fs ros 8 7 6 JAE 2 1 o SRU_OVF7 EMI L SRU PING0O STAT SRU OVF6 SRU PING1 STAT SRU OVF5 SRU PING2 STAT SRU OVF4 SRU PING3 STAT SRU OVF3 SRU PING4 STAT SRU OVF2 SRU PING5 STAT SRU OVF1 SRU PING6 STAT SRU OVFO SRU PING7 STAT IDP Channel Overflow Sticky Ping pong DMA Channel Status Figure A 39 DAI STAT Register ADSP 2136x SHARC Processor Hardware Reference A 79 for the ADSP 21362 3 4 5 6 Processors DAI Signal Routing Unit Registers Table A 41 DAI STAT Register Bit Descriptions Bit Name Description 7 0 SRU PINGx STAT Ping pong DMA Status Channel Indicates the status of ping pong DMA in each respective channel channel 7 0 0 DMA is not active 1 DMA is active SRU_OVFx Sticky Overflow Status Channel Provides overflow status information for each channel bit 8 for channel 0 through bit 15 for channel 7 0 No overflow 1 Overflow has occurred Reserved IDP_DMAx_STAT Input Data Port DMA Status 0 DMA is not active 1 DMA is active Reserved IDP_FIFOSZ IDP
32. 3 the processor must wait for the RXS bit to be set after SPIF is set before reading the RXSPI buffer For larger SPIBAUD settings SPIBAUD 4 RXS is set before SPIF Interrupts The following section describes SPI operations using both the core and direct memory access DMA Interrupt Sources The SPI ports can generate interrupts in five different situations During core driven transfers an SPI interrupt is triggered 1 When the TXSPI buffer has the capacity to accept another word from the core 2 When the RXSPI buffer contains a valid word to be retrieved by the core The TIMOD transfer initiation and interrupt register determines whether the interrupt is based on the TXSPI or RXSPI buffer status If configured to generate an interrupt when SPIRX is full TIMOD 00 the interrupt will be active 1 PCLK cycle after the RXS bit is set 7 28 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Peripheral Interface Ports During DMA driven transfers an SPI interrupt is triggered 1 At the completion of a single DMA transfer 2 At the completion of a number of DMA sequences if DMA chain ing is enabled 3 When a DMA error has occurred Note that the SPIDMAC register must be initialized properly to enable DMA interrupts Each of these five interrupts are serviced using the interrupt associated with the module being used The primary SPI uses the SPIHI interrupt and
33. 4 Resume chained DMA mode by setting SDENx 1 and SCHENx 1 Programming Examples This section provides three programming examples written for the ADSP 2136x processor The first listing Listing 6 1 transmits a buffer of data from SPORT5 to SPORT4 using DMA and the internal loopback feature of the serial port In this example SPORTS drives the clock and frame sync and the buffer is transferred only one time The second listing Listing 6 2 transmits a buffer of data from SPORT2 to SPORT3 using direct core reads and writes and the internal loopback feature of the serial port In this example SPORT2 drives the clock and frame sync and the buffer is transferred only one time The third listing Listing 6 3 transmits a buffer of data from SPORT1 to SPORTO using DMA chaining and the internal loopback feature of the serial port In this example SPORT5 drives the clock and frame sync and the two TCBs for each SPORT are set up to ping pong back and forth to continually send and receive data ADSP 2136x SHARC Processor Hardware Reference 6 57 for the ADSP 21362 3 4 5 6 Processors Programming Exam Listing 6 1 SPORT ples Transmit Using DMA include lt def21364 h gt include lt sru21364 h gt dFinclude lt SRU h gt Default Buffer define BUFSIZE 10 Length SECTION DM seg dmda TX Buffers var tx bufl1a BUFSIZE 0x11111111 0x22222222 0x33333333 0x44444444 0x55555555 0x66666666
34. AD7 pins in flag mode FLG15 12 26 PWMOEN Pulse Width Modulation0 Mode Select 0 AD11 8 pins in parallel port mode 1 AD11 8 pins in PWM mode ADSP 2136x SHARC Processor Hardware Reference A 5 for the ADSP 21362 3 4 5 6 Processors Power Management Control Register PMCTL Table A 1 SYSCTL Register Contd Bit Name Description 27 PWMIEN Pulse Width Modulation1 Mode Select 0 AD15 12 pins in parallel port mode 1 ADI5 12 pins in PWM mode 28 PWM2EN Pulse Width Modulation2 Mode Select 0 AD3 0 pins in parallel port mode 1 AD3 0 pins in PWM mode 29 PWM3EN Pulse Width Modulation3 Mode Select 0 AD7 4 pins in parallel port mode 1 AD7 4 pins in PWM mode 31 30 Reserved Power Management Control Register PMCTL The following sections describe the regsters associated with the processors power management functions The power management control register shown in Figure A 2 is a 32 bit memory mapped register This register contains bits to control phase lock loop PLL multiplier and divider both input and output values PLL bypass mode and clock enabling control for peripherals see Table A 2 on page A 8 This register also contains status bits which keep track of the status of the CLK_CFG pins read only The reset value of PMCTL is depen dent on the CLK_CFG pins bits 5 0 The core can write to all bits except the read only status bits The DIVEN
35. smit Control Bits Receive Control SPORTO 2 4 Bits SPORTI 3 5 21 SCHEN_B SCHEN_B SCHEN_B SCHEN_B 22FSHO TH Reseved Reserved Reseved _ 23 BHD BHD BHD BHD 24sP EN B SPEN B Reserved Reserved 25 SPTRAN SPTRAN Reserved Reserved 26D ERR B DERR B TUVF B ROVE B 27D Xs B DXS B TXS B RXS B 28D XS B DXS B TXS B RXS B 29D ERRA DERR A TUVE_A ROVE_A 30D XS_A DXS_A TXS_A RXS_A 31D XS_A DXS_A TXS_A RXS_A Control Registers SPCTLx The SPCTLx registers control serial port modes and are part of the SPCTLx transmit and receive control registers Other bits in these registers set up DMA and I O processor related serial port features For information about configuring a specific operation mode refer to Table 6 5 on page 6 19 and Operating Modes on page 6 34 Multichannel Control Registers SPMCTLxy There is one global control and staus register for each SPORT pair 0 and 1 2 and 3 4 and 5 for mutichannel operation These registers define the number of channels provide the status of the current channel enable multichannel operation and set the multichannel frame delay These ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports registers are described in SPORT Multichannel Control Registers SPM CTLxy on page A 43 Data Buffers When programming the serial port channd A or B asa transmitter only the corresponding TXSPxA and TXSPx8 bu
36. 0 and MSBF 1 Figure 7 5 also shows the SPI transfer protocol for CPHASE 1 Note that SPICLK starts toggling at the beginning of the data transfer where the bit settings are WL 0 and MSBF 1 ADSP 2136x SHARC Processor Hardware Reference 7 15 for the ADSP 21362 3 4 5 6 Processors Register Descriptions SPI Transfer Protocol for CPHASE 0 CLOCK CYCLE NUMBER SPICLK l CLKPL 0 l l SPI MODE 0 1 l I I SPICLK T i T CLKPL 1 i l l I I I l SPIMODE 2 l EO 000 d d d od o EO d OE gp d d 3 usi l EO 000 dod dod EO 0d d dod Frommaster KMB A 6 X 5 X 4 X 3 X 2 X 1 X tsp X MISO I Doo d dod dod dod o d 4d gd obo or qp o FROM SLAVE m X e X s X 4 X 9 X X XU X SPIDS I oO od dod dod god i ft d a coo wa ow 23 FROM MASTER Mo obs no own o3 Cd X o3 cost de ui ES d lw de pe de uw W l FO o d dod dod dod EO d d dog go 1 Oo 0d dod dod dog EO 00 d d gd 0g UNDEFINED SPI Transfer Protocol for CPHASE 1 CLOCK CYCLE 1 2 3 4 5 6 7 8 NUMBER I I I I I I I I I SPICLK CLKPL 0 SPI MODE 1 SPICLK CLKPL 1 SPI MODE 3 I I l I l I l I l I l I l I l I l I mowwasrm c XmSB_X 6 Xs X 4 Xo X 2 X3 X X I I l L l I l I l I l I l I I I I I l MISO FROM SLAVE SPIDS TO SLAVE UNDEFINED Figure 7 5 SPI Transfer Protocol for CPHASE 0 7 16 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Peripheral Interface Por
37. 13 19 multiplexing 5 15 output divider 14 8 parallel port duration PPDUR bits A 12 peripheral clock PCLK 2 32 4 4 4 21 6 2 14 10 PLL design 14 4 PLL input clock 14 10 precision clock generator registers 13 9 selecting clock ratios 14 7 software control 14 8 source select MSTR bit A 32 A 37 A 40 SPI clock phase select CPHASE bit A 16 SPORTS 6 25 to 6 28 VCO encodings 14 9 VCO frequency 14 4 compand data in place 6 5 companding compressing expanding 6 5 conditioning input signals 14 2 configuring frame sync signals 6 9 connecting peripherals through DAI 5 13 ADSP 2136x SHARC Processor Hardware Reference I 3 for the ADSP 21362 3 4 5 6 Processors Index connections DAI 5 20 conventions manual xlii converters A D and D A 4 10 core PLL 13 2 core transmit receive operations 7 22 count CSPx DMA registers 2 7 count CSPx registers 2 20 count IDP DMA Cx registers 8 20 8 21 CPSPx chain pointer registers 2 8 CRAT PLL clock ratio bit A 8 crosstalk reducing 14 29 CSPx peripheral DMA counter registers 2 7 2 20 customer support xxxvi D DAI See also SRU cframe sync routing control registers Group C A 89 clock routing control registers Group A A 80 clock routing control regisers group A 5 20 configuration macro 5 32 connecting peripherals with 5 13 DAI interrupt falling edge DAI IRPTL FE register 8 27 DAI interrupt rising e
38. Because the IOP registers are memory mapped the processors have access to program DMA operations A program sets up a DMA channel by writ ing the transfer s parameters to the DMA parameter registers After the index modify and count registers among others are loaded with a start ing source or destination address an address modifier and a word count the processor is ready to start the DMA The peripherals each have a DMA enable xDEN bits in their channel con trol registers Setting this bit fora DMA channel with configured DMA parameters starts the DMA on that channel If the parameters configure the channel to receive the I O processor transfers data words received at the buffer to the destination in internal memory If the parameters config ure the channel to transmit the I O processor transfers a word automatically from the source memory to the channel s buffer register These transfers continue until the I O processor transfers the selected number of words as determined by the count parameter DMA through the IDP ports occurs in internal memory only IOP Registers The IOP registers are memory mapped and can be accessed through an address by the core For the list of parameter registers refer to Registers Reference in Appendix A Registers Reference ADSP 2136x SHARC Processor Hardware Reference 2 5 for the ADSP 21362 3 4 5 6 Processors IOP Registers Standard DMA Parameter Registers The parameter registers des
39. Clearing this bit 0 causes data to latch on the rising edge default Notice that in all four packing modes described data is read on a clock edge but the specific edge used ris ing or falling is not indicated 0 Data is latched on the rising edge 1 Data is latched on the falling edge 30 IDP_PDAP_RESET PDAP Reset A reset clears any data in the packing unit waiting to get latched into the IDP FIFO This bit causes the reset circuit to strobe when asserted and then automatically clears Therefore this bit always returns a value of zero when read 31 IDP_PDAP_EN PDAP Enable 0 Disconnects all PDAP inputs data control from use as parallel input channel 1 Connects all PDAP inputs data control from use as parallel input channel IDP channel 0 cannot be used as a serial input port with this setting A 52 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference Input Data Port FIFO Register IDP FIFO The IDP_FIFO register shown in Figure A 23 and described in Table A 22 provides information about the output of the 8 deep IDP FIFO For more information see Data Buffer on page 8 17 g 30 29 28 E 26 25 24 f 22 21 20 18 17 6 Serial Input Data 31 4 s 14 13 B 10 9 JE 6 5 JE 2 1 e EL c cM ES Serial Input Data 81 4 l IDP Channel Encoding Bi
40. Digital Application Interface 6 6 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Table 6 3 SPORT DAI SRU Signal Connections Serial Ports Internal Node DAI Connection SRU Register SPORT5 0 FS PBEN O SPORT5 0 DA PBEN O SPORT5 0 DB PBEN O Inputs SPORT5 0 CIK I Group A SRU_CLK1 0 SPORT5 0 FS I Group C SRU FSO SPORT5 0 DA I Group B SRU_DAT2 0 SPORT5 0 DB I Outputs SPORT5 0 CLK O Group A D SPORT5 0 FS O Group C D SPORT5 0 DA O Group B D SPORT5 0 DB O SPORTS 0 CLK PBEN O GrupF SRU SPORT Receive Master If the SPORT is operating as receive mater it must feed its master output clock back to its input clock This isrequired to trigger the SPORT s state machine Using SPORT 4 as an example receive master programs should route SPORT4_CLK_0 to SPORTA CLK I This is not required if the SPORT is operating as a transmitter in master mode SRU SPORT Signal Integrity There is some sensitivity to noise on the clock SPORTx CLK and frame sync SPORTx FS signals when the SPORT is configured as a master receiver By correctly programming the signal routing unit SRU clock ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors 6 7 SRU Configuration and frame sync registers the reflection sensitivity in these signals can be avoided Figure 5 10 on page 5 18 sh
41. Enable Channel A SLEN32 32 bit word length FSR Frame Sync Required SPTRAN Transmit on enabled channels IFS Internally Generated Frame Sync ICLK Internally Generated Clock 6 62 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports dm SPCTL2 ustat4 Configure SPORT3 as a receiver externally generating clock and frame sync rO 0x0 dm DIV3 RO ustat3 SPEN_A Enable Channel A SLEN32 32 bit word length FSR Frame Sync Required dm SPCTL3 ustat3 Set up loop to transmit and receive data lcntr LENGTH tx buf2a do pc 4 until lce Retrieve data using DAG and send TX via SPORT2 rO dm i4 m4 dm TXSP2A r0 Receive data via SPORT3 and save via DAG2 rO dm RXSP3A pm il2 m12 r0 main end jump pc 0 Listing 6 3 SPORT Transmit Using DMA Chaining Default Buffer Length define BUFSIZE 10 SECTION DM seg dmda Transmit buffer v r tx buf5a BUFSIZE 0x11111111 0x22222222 0x33333333 0x44444444 0x55555555 0x66666666 ADSP 2136x SHARC Processor Hardware Reference 6 63 for the ADSP 21362 3 4 5 6 Processors Programming Examples Ox77777777 0x88888888 0x99999999 OxAAAAAAAA Receive buffer var rx buf4a BUFSIZE Main code section global main SECTION PM seg pmco main SPORT Loopback Use SP
42. Interrupt Default Routing Yes P11 Yes P18I Protocol Master Capable Yes Yes Slave Capable Yes Yes ADSP 2136x SHARC Processor Hardware Reference 7 1 for the ADSP 21362 3 4 5 6 Processors Features Table 7 1 SPI Port Feature Summary Contd Feature SPI SPIB Transmission Simplex Yes Yes Transmission Half Duplex Yes Yes Transmission Full Duplex Yes Core and DMA Yes Core and DMA Access Type Data Buffer Yes Yes Core Data Access Yes Yes DMA Data Access Yes Yes DMA Channels 1 1 DMA Chaining Yes Yes Interrupt Source Core DMA Core DMA Boot Capable Yes Yes Local Memory No No Clock Operation PCLK 4 PCLK 4 Asimple 4 wire interface consisting of two data pins a device select pin and a clock pin Special data formats to accommodate little and big endian data different word lengths and packing modes Master and multiples slave multi devices in which the ADSP 2136x master processor can be connected to up to four other SPI devices Parallel core and DMA access allow full duplex operation Open drain outputs to avoid data contention and to support multimaster scenarios e Programmable baud rates clock polarities and phases SPI mode 0 3 7 2 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Peripheral Interface Ports e Master or slave booting from a master SPI device See SPI Port Booting o
43. It is not possible to run out of patch points for an output signal Just as group A routes clock signals each of the other groups route a col lection of compatible signals Group B routes serial data streams while group C routes frame sync signals Group D routes signals to pins so that they may be driven off chip Note that all of the groups have an encoding that allows a signal to flow from a pin output to the input being specified by the bit field but group D is required to route a signal to the pin input Group F routes signals to the pin enables and the value of these signals determines if a DAI pin isused as an output oran input These groups are described in more detail in the following sections 5 14 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors tion Interface Ica tal Appli igi D Plaid 199 eS 1319 0180dS pied 199 es X19 I1H0dS pier 4999S 19719 z180dS Plaid 199 95 1319 180dS Plat 3919S i19 v180dS pier 49919S 1319 s180dS I 19 01H0dS TATO 11H0dS TATO z1H0dS I 19 1H0dS I 19 v1H0dS TATO s1H0dS 1 HDIH 21501 0 MO1 31907 O 319 SLYOdS O 108d Iva Figure 5 9 Example DAI SRU Group A Multiplexing SRU CLKx 5 15 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors DAI Peripherals Rules for SRU Connections There are two rules which app
44. Ox77777777 0x88888888 0x99999999 OXAAAAAAAA var tx bufl1b BUFS 0x23456789 0x34567894 0x456789AB 0x56789ABC 0x6789ABCD Ox789ABCDE Ox89ABCDEF Ox9ABCDEFO OxABCDEFO1 RX Buffers var rx bufOa BUFS var rx bufOb BUFS IZE 0x12345678 TAR IZE 6 58 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports TX Transfer Control Blocks var tx tcbl 4 O BUFSIZE 1 tx bufla var tx tcb2 4 O BUFSIZE 1 tx buflb RX Transfer Control Blocks var rx tcbl1 4 O BUFSIZE 1 rx buf0a O BUFSIZE 1 rx bufOb I I var rx tcb2 4 Main code section global main SECTION PM seg pmco ain rO 0 Clear CP registers before enabling chaining dm CPSPOA r0 dm CPSP1A r0 SPORT Loopback Use SPORTO as RX amp SPORTI as TX initially clear SPORT control register ro 0x00000000 dm SPCTLO r0 dm SPCTL1 r0 dm SPMCTLO1 r0 SPORT_DMA_setup set internal loopback bit for SPORTO amp SPORTI bit set ustat3 SPL dm SPMCTLO1 ustat3 Configure SPORTI as a transmitter internally generating clock and frame sync CLKDIV fPCLK 167 MHz AxFSCLK 8 325 MHz 1 0x0004 FSDIV FSCLK 8 325 MHz TFSC260 kHz 1 31 OxOOI1F RO 0x001F0004 dm DIV1 RO ustat4 SPEN_A Enable Channel A SLEN32 32 bit word length FSR Fram
45. Period Value WO Period Value Width WO Width Value RO Width Value Unused Counter RO Only if not enabled RO Only if not enabled RO Only if not enabled Counts down on PCLK Counts up on PCLK Counts down on Event 9 8 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Peripheral Timers Table 9 4 Timer Signal Use Contd TMxCTL PWM OUT Mode WIDTH CAP Mode EXT CLK Mode Register Settings OVF ERR Set if Initialized with Set if the Counter wraps Unused IRQ also set Period Width or Error Condition Period Width or Period IRQ If PERIOD_CNT If PERIOD_CNT Set after Period Expires If enabled 1 Set at end of Period 1 Set at end of Period and PCLK is running 0 Set at end of Width 0 Set at end of Width Pulse Width Modulation Mode PWM_OUT In PWM_OUT mode the timer supports on the fly updates of period and width values of the PWM waveform The period and width values can be updated once every PWM waveform cycle either within or across PWM cycle boundaries To enable PWM_OUT mode set the TIMODE1 0 bits to 01 in the timer s con figuration TMxCTL register This configures the timer s TIMERx signal as an output with its polarity determined by PULSE as follows If PULSE is set 1 an active high width pulse waveform is gener ated at the TIMERx signal e If PULSE is cleared 0 an active low width pulse wave
46. SPORT CLK O PBEN O SPORT FS I SPORT FS O PBEN O Figure 5 12 DAI Default Routing 5 22 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Digital Application Interface SPORT2 DA I SPORT2 DA O SRORTZSESEI SPORTA FS SPORT2 FS O SPORTA FS O PBEN O PBEN O SPORT5 CLK I SPORT5 FS O PBEN O SPORT5 DA I SPORT5 DA O PBEN O SPORT5 DB I SPORT5 DB O PBEN O Figure 5 13 DAI Default Routing con t ADSP 2136x SHARC Processor Hardware Reference 5 23 for the ADSP 21362 3 4 5 6 Processors Interrupt Controller Interrupt Controller The DAI contains a dedicated interrupt controller that signals the core when DAI peripheral events occur System versus Exception Interrupts Generally interrupts are classified as system or exception Exception events include any hardware interrupts for example resets and emula tion interrupts math exceptions and illegal accesses to memory that does not exist Programs can manage responses to signals by configuring registers In a sample audio application for example upon detection of a change of pro tocol the output can be muted This change of output and the resulting behavior causing the sound to be muted results in an alert signal an interrupt being introduced in response if the detection of a protocol change is a high priority interrupt Exception events are treated as high piority events In comparison
47. See also SPORT bits modes registers 128 channel TDM 6 5 active low versus active high frame syncs 6 30 buffer error status 6 16 buffer hang disable BHD bit 6 55 buffers data 6 13 chain insertion mode DMA 6 52 channel number quantity select NCH bit 6 45 clock master 6 25 clock divisor equation 6 25 clock edge selection 6 28 clock frequency equation 6 25 clock SCLKx pins 6 9 clock signal options 6 25 to 6 28 companding and data type bit DTYPE 6 23 companding compressing expanding 6 5 configuring frame sync signals 6 9 configuring standard DSP serial mode 6 34 control bit comparison 6 11 data type sign extend 6 22 data type zero fill 6 22 divisor DIVx register 6 25 6 27 6 30 6 35 6 36 DMA chaining 6 51 DMA channels 6 49 duplex full 6 9 endian format 6 21 equation frame sync frequency 6 26 examples normal vs alternate framing 6 32 features 6 4 flag pins 6 10 FLAGx pins 6 10 Index SPORTs continued framed and unframed data 6 29 framed vs unframed data example 6 32 frame sync and serial word length 6 26 frame sync delay 6 45 full duplex operation 6 9 input output FLAGx pins 6 10 internal clock selection 6 25 internal serial clock setting 6 36 interrupts 6 50 6 53 I O processor bus and 6 21 latency in writes 6 55 left justified mode control bits 6 37 loopback mode 6 54 masking interrupts 6 53 master mo
48. Synchronization Register POG SYNC sesieiesinsisviccieriinecs A 69 Sony Philips Digical Interface Registers eoo ne A 70 Transm tter Kee anaE A 70 Transmit Control Register DITOTL srninisiicniniiniss A 70 Transmit Status Registers for Subframe A iE C92 A otc A 72 Transmit Status Registers for Subframe B DITC HANR I UPPER A 73 Rete 00 ll M A 73 Receive Control Register DIRGTL 2er iieri A 73 xxviii ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Contents Receive Status Register DIRS LAT Laecisecssseertn ihe A 75 Receive Status Registers for Subframe A dE cA ZI NT Ove cease dade A 77 Receive Status Registers for Subframe B JEI LISTO S MORE E OR MERE A 77 DAE Interrupt Controller Registers ciccssccscteasesxeivasecenmeasccccts A 77 RI S dg oo A oun A 78 Digital Applications Interface Status Register 4 R TE UE UU PPP AAE A E Pn A 79 DAI god Routing Unit Rte tere oisinnean A 80 Clock Routing Control Registers ORU LLEX Gropp A nesermen a A 80 Serial Data Routing Registers SRU_DATx Group B A 85 Frame Sync Routing Control Registers SRU Fs Group C M A 89 Pin Signal Assignment Registers DRU PE ieu DI airian A 93 Miscellaneous Signal Routing Registers SRU NISC Group B iduencedisdtb5bkix ue uui du du bn d du pbi A 98 DAI Pin Buffer Enable Registers SRU _PBEN Group FI sone eee ec ae eee A 102 gti o o do o c eens A 106 DAI Pin B
49. System Components on page 14 26 Designing for High Frequency Operation on page 14 28 Processor Booting on page 14 32 Other chapters also discuss system design issues Some other locations for system design information include Pin Descriptions on page 6 6 Pin Descriptions on page 7 3 By following the guidelines described in this chapter you can ease the design process for your ADSP 2136x processor product Development ADSP 2136x SHARC Processor Hardware Reference 14 1 for the ADSP 21362 3 4 5 6 Processors Conditioning Input Signals and testing of your application code and hardware can begin without debugging the JT AG port Before proceeding with this chapter it is recommended that you become familiar with the ADSP 2136x processor core architecture This information is presented in the SHARC Processor Programming Reference Conditioning Input Signals The processor is a CMOS device Ithas input conditioning circuits which simplify system design by filtering or latching input signals to reduce sus ceptibility to glitches or reflections The following sections describe why these circuits are needed and their effect on input signals A typical CMOS input consists of an inverter with specific N and P device sizes that cause a switching point of approximately 1 4 volts This level is selected to be the midpoint of the standard TTL interface specification of Vi 0 8 V and Vg 2 0 V This input inverter un
50. TIMER2 DAI Timer 0 Input DAI Timer 2 Input L DAI_INT_23_l DAI Interrupt 23 TIMER1 I DAI Timer 1 Input Figure A 61 SRU EXT MISCB Register Table A 46 Group E Sources Miscellaneous Signals Selection Code Source Signal Description Source Selection 00000 0x0 DAI_PB01_O Pin buffer 1 output as a source 00001 0x1 DAI PB02 O Pin buffer 2 output as a source 00010 0x2 DAI PB03 O Pin buffer 3 output as a source 00011 0x3 DAI PB04 O Pin buffer 4 output as a source 00100 0x4 DAI PB05 O Pin buffer 5 output as a source 00101 0x5 DAI PB06 O Pin buffer 6 output as a source 00110 0x6 DAI PB07 O Pin buffer 7 output as a source 00111 0x7 DAI PB08 O Pin buffer 8 output as a source 01000 0x8 DAI PB09 O Pin buffer 9 output as a source A 100 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference Table A 46 Group E Sources Miscellaneous Signals Cont d Selection Code Source Signal Description Source Selection 01001 0x9 DAI PB10 O Pin buffer 10 output as a source 01010 0xA DAI PB11 O Pin buffer 11 output as a source 01011 OxB DAI PB12 O Pin buffer 12 output as a source 01100 0xC DAI PB13 O Pin buffer 13 output as a source 01101 OxD DAI PB14 O Pin buffer 14 output as a source 01110 OxE DAI PB15 O Pin buffer 15 output as a source 01111 O
51. TXSPI RCV 0 11 SPIMME Multimaster Error 0 Successful transfer 1 Error during transfer 13 12 SPISx DMA FIFO Status 00 FIFO empty 01 Reserved 10 FIFO partially full 11 FIFO full 14 SPIERRS DMA Error Status 0 Successful DMA transfer 1 Errors during DMA transfer 15 SPIDMAS DMA Transfer Status 0 DMA idle 1 DMA in progress ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 19 Peripheral Registers Table A 5 SPIDMAC SPIDMACB Register Bit Descriptions Contd Bit Name Description 16 SPICHS DMA Chain Loading Status 0 Chain idle 1 Chain loading in progress 31 17 Reserved SPI Baud Rate Registers SPIBAUD SPIBAUDB These SPI registers are 32 bit read write registers that are used to set the bit transfer rate for a master device When configured as slaves the value written to these registers is ignored The SPIBAUDx registers can be read from or written to at any time Bit descriptions are provided in Table A 6 Table A 6 SPIBAUD SPIBAUDB Register Bit descriptions Bit Name Description 0 Reserved 15 1 BAUDR Baud Rate Enable Enables the SPICLK per the equation SPICLK baud rate peripheral clock PCLK 4 x BAUDR Default 0 31 16 Reserved Note that this baud rate equation applies to master mode operation only For slave mode opera
52. The frame sync input is used to hold off latching of the next sample that is ignore the clock edges The data then flows through the FIFO and is transferredby a dedicated DMA channel into the core s memory as with any IDP channel As shown in Figure 8 8 the PDAP can accept input words up to 20 bits wide or can accept input words that are packed as densely as four input words up to eight bits wide Mode 11 No Packing Mode 11 provides for 20 bits coming into the packing unit and 32 bits going out to the FIFO in a single cycle On every clock edge 20 bits of data are moved and placed in a 32 bit register left aligned That is bit 19 maps to bit 31 The lower bits 11 0 are always set to zero as shown in Figure 8 8 This mode sends one 32 bit word to FIFO foreach input clock cycle the DMA transfer rate matches the PDAP input clock rate ADSP 2136x SHARC Processor Hardware Reference 8 13 for the ADSP 21362 3 4 5 6 Processors Parallel Data Acquisition Port PDAP Mode 10 Packing by 2 Mode 10 moves data in two cycles Each input word can be up to 16 bits wide e On clock edge 1 bits 19 4 are moved to bits 15 0 16 bits e On clock edge 2 bits 19 4 are moved to bits 31 16 16 bits This mode sends one packed 32 bit word to FIFO for every two input clock cycles the DMA transfer rate is one half the PDAP input clock rate Mode 01 Packing by 3 Mode 01 packs three acquired samples together Since the resulti
53. after a DMA transmit operation use the following steps 1 Wait for the DMA FIFO to empty This is done when the SPISx bits bits 13 12 in the SPIDMACx registers become zero 2 Wait for the TXSPIx registers to empty This is done when the TXS bit bit 3 in the SPISTATx registers becomes zero Q When stopping receive DMA transfers it is recommended that programs follow the SPI disable steps provided in Switching from Receive to Receive Transmit DMA below 3 Wait for the SPI shift register to finish transferring the last word This is done when the SPIF bit bit 0 of the SPISTATx registers becomes one 4 Disable the SPI ports by setting theSPIEN bit bit 0 of theSPICTLx registers to zero Switching from Transmit To Transmit Receive DMA The following sequence details the steps for switching from transmit to receive DMA With disabled SPI 1 Write 0x00 to the SPICTLx registers to disable SPI Disabling the SPI also clears the RXSPIx TXSPIx registers and the buffer status 2 Disable DMA by writing 0x00 to the SPIDMAxC register ADSP 2136x SHARC Processor Hardware Reference 7 41 for the ADSP 21362 3 4 5 6 Processors Programming Model Clear all errors by writing to the W1C type bits in the SPISTATx registers This ensures that no interrupts occur due to errors from a previous DMA operation 4 Reconfigure the SPICTLx registers and enable the SPI ports 5 Configure DMA by writing to the DMA parameter regis
54. bit is a logical bit that is it can be set but on reads it always responds with zero ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference When the PLL is programmed using a multiplier and a divisor the DIVEN and PLLBP bits should NOT be programmed in the same core clock cycle For more information see Bypass Clock on page 14 10 and Example for Output Divider Management on page 14 13 30 29 28 g 26 25 24 2s 22 21 20 19 18 17 te TMRPDN RW L Peripheral Timer CRAT 17 16 RO Enable Disable PLL Clock Ratio SPIPDN RW SRCPDN RW SPI Enable Disable Clock to SRC Enable SP3PDN RW PPPDN RW SP4 5 Enable Disable PP Enable Disable SP2PDN RW SP1PDN RW SP2 3 Enable Disable SP0 1 Enable Disable 5 14 18 a 10 9 JE els JE 2 1 o LT e PLLBP RW 1 PLLM 5 0 RW PLL Multiplier PLL Bypass Mode Indicator PLLD 7 6 RW DIVEN RW PLL Divider PLL Divider Enable INDIV RW Input Divider Figure A 2 PMCTL Register ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 7 Power Management Control Register PMCTL Table A 2 PMCTL Register Bit Descriptions Bit Name Description 5 0 PLLM PLL Multiplier Read Write PLLM 0 PLL multiplier 64 0 lt PLLM lt 64 P
55. counter and it starts counting 9 22 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Peripheral Timers The timer produces PWM waveform with a period of 2 x period and a width of 2 x width When 2 x width expires the counter is loaded with 2x period width and continues counting When 2 x period expires the counter is loaded with 2 x width value again and the cycle repeats When the width or period expires the TRQ bit if enabled is set depending on the PRDCNT bit When IRQ is sensed read the status register TMxSTAT and perform the appropriate write one to clear WDTH CAP Mode Use the following procedure to configure and run the timer in WDTH CAP out mode 1 Reset the TIMEN bit and set the configuration mode to 10 to select WDTH_CAP operation This configures the TIMERx I pin as an input pin with its polarity determined by the PULSE bit Measures a positive active pulse width at the TIMERx I pin Measures a negative active pulse width at the TIMERx I pin 2 The PRDCNT bit determines when the TRO status bit if enabled is set e If P DCNT 1 TRO is set when the period expires and the value is captured e If PKDCNT 0 TRO is set when the width expires and the value is captured ADSP 2136x SHARC Processor Hardware Reference 9 23 for the ADSP 21362 3 4 5 6 Processors Programming Model 3 Valid period and width values are set in their resp
56. data transfer 8 bit mode 4 8 data transfer core stall driven 4 17 data transfer interrupt driven 4 15 data transfer known duration accesses 4 16 data transfer status driven 4 16 DMA address IMPP register 14 38 DMA enable PPDEN bit 4 11 4 12 4 18 4 24 DMA external address EIPPx registers 4 14 14 38 DMA external address EMPP register 4 14 DMA external address modifier EMPP register 14 38 DMA external word count ECPP register 4 12 14 38 DMA internal word count ICPD register 4 12 14 38 DMA start internal index address 14 38 DMA use in 4 12 external word count ECPP register 4 10 hold cycle 4 8 interrupt PPI signal 4 19 latency in PPCTL register 4 23 multiplexed pin functions 4 4 14 17 14 24 multiplexing with PWM 14 24 packing sequence for 32 bit data 4 6 ADSP 2136x SHARC Processor Hardware Reference I 13 for the ADSP 21362 3 4 5 6 Processors Index parallel port continued pins 4 3 4 9 polarity 4 5 read cycle 4 5 registers 10 A 10 restrictions in use 4 13 signals 4 3 SRAM memory 4 8 stalls in 4 17 system configure and enable A 11 TCB 2 30 throughput 4 19 4 21 A 12 transfer protocol 4 8 write cycle 4 5 parallel port bits ALE polarity level PPALEPL A 13 buffer hang disable PPBHD A 13 bus hold cycle enable PPBHC 4 8 4 17 A 12 bus status PPBS 4 16 A 13 data cycle duration PPDUR 4 8 A 12
57. pai PBo9 1 6 0 DAI PB10 I 13 7 DAI Pin Buffer 9 Input DAI Pin Buffer 10 Input Figure A 57 SRU_PIN2 Register E 30 29 ze 27 26 25 24 23 22 21 20 19 18 e peu PB15 1 20 14 con t DAI PB16 1 27 21 DAI Pin Buffer 15 Input DAI Pin Buffer 16 Input 15 14 13 DE 10 9 JE els JE 2 1 o DAI PB15 I 20 14 eu DAI PB14 1 13 7 DAI Pin Buffer 14 Input DAI PB13 I 6 0 DAI Pin Buffer 13 Input Figure A 58 SRU PIN3 Register A 94 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference 31 30 29 28 f 27 DAI PB20 I INVERT DAI PB19 I INVERT _ DAI PB20 I 27 21 DAI Pin Buffer 20 Input 24 z 22 20 is 18 17 16 l e DAI PB19 I 20 14 con t DAI Pin Buffer 19 Input s 14 13 i jo 9 e 7 e s a o 214 e DAI PB17 I 6 0 DAI Pin Buffer 17 Input DAI PB19 I 20 14 DAI PB18 I 13 7 DAI Pin Buffer 18 Input Figure A 59 SRU_PIN4 Register Setting SRU_PIN4 bit 28 to high inverts the level of DAI PB19 I and setting SRU_PIN4 bit 29 to high inverts the level of DAI P820 I Input Inversion only works if the buffer output is not routed to its input Table A 45 Group D Sources Pin Signal Assignments
58. pin act as SPI slave select IRQxEN x 3 0 TMREXPEN x DSxEN 1 ADSP 2136x SHARC Processor Hardware Reference 14 19 for the ADSP 21362 3 4 5 6 Processors Pin Multiplexing PPFLGS IRQxEN FLGOEN TMREXPEN PINS IRQO FLAGO Figure 14 3 FLG3 0 IRQ2 0 TMREXP Pin Multiplexing Scheme Parallel Port Pin Multiplexing As described Table 14 7 and shown in Figure 14 4 the parallel port can multiplex around the following five interfaces e Parallel port address and data input output PDAP input only FLAGS input output 14 20 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors System Design PWM channels output SPI output slave selects To use the muxed parallel port pins as flags FLAG15 0 set 1 the PPFLGS bit 20 of the SYSCTL register and disable the parallel port by clearing 20 the PPEN bit bit 0 in the PPCTL register For the address pin to FLAG pin mapping refer to the ADSP 21362 3 4 5 6 SHARC Processor Data Sheet In the PDAP control register IDP PP CTL the IDP PP SELECT bit bit 26 is the logical AND of the 1DP PDAP EN bit bit 31 Setting the IDP PP SELECT bit 21 selects the 16 inputsfrom the parallel portAD15 0 clearing this bit 20 selects the 16 inputs from DAI pin buffers DAI P20 5 Table 14 7 Parallel Port Pin Multiplexing Scheme Control F unction of Type Comment AD15 0 IDP PDAP EN 0 Three state Not connected
59. triggered Internal Transfer Completion Each serial port has an interrupt asociated with it For each SPORT both the A and B channel transmit and receive data buffers share the same interrupt vector The interrupts can be used to indicate the completion of the transfer of a block of serial data when the serial ports are configured for DMA They can also be used to perform single word transfers refer to 6 52 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports Single Word Transfers on page 6 47 The priority of the serial port interrupts is shown in Table 2 9 on page 2 11 Multiple interrupts can occur if both SPORTS transmit or receive data in the same cycle Any interrupt can be masked in the IMASK register if the interrupt is later enabled in the LIRPTL register the corresponding inter rupt latch bit in the IRPTL or LIRPTL registers must be cleared in case the interrupt has occurred in the same time period SPORT interrupts occur on the second peripheral clock PCLK after the last bit of the serial word is latched in or driven out When serial port data packing is enabled PACK 1 in the SPCTLx regis ters the transmit and receive interrupts are generated for 32 bit packed words not for each 16 bit word Each DMA channel has a count register CSPxA CSPxB which must be initialized with a word count that specifies the number of words to trans fer The count register decr
60. 0x24C2 0x800 00000 FS B Ph Lo CLK B Div PCG_CTLB1 0x24C3 0 2 0x000 00002 PW FS B PW FS A PCG PW 0x24C4 0 0 0x0000 0000 KAR KKK KK KK KK KK KK KK KK KKK KK KK KK KK KK KK KK KK KKK KK KK KK KK KK KK KK KKK KK KK dFinclude lt def21365 h gt PCGA gt SCLK amp FSYNC Divisors Sample Rate 65 098 kHz define PCGA CLK DIVISOR 0x0008 SCLK output 64xFs i tdefine PCGA FS DIVISOR 0x0200 FSYNC output Fs 1idefine ENCLKA 0x80000000 define ENFSA 0x40000000 define PCGA FS PHASE LO 0x04 Set FSYNC SCLK Phase for digital audio IF mode PCGB gt PCG CLKx O Divisor define PCGB CLK DIVISOR 0x0002 PCG CLKx 0 output 256xFs 1idefine PCGB FS DIVISOR 0x0000 Not used disabled i fdefine PCGB FS PHASE LO 0x00 Don t care section pm seg pmco global Init PCG KIRK KKK KKK KKK KK ck KK KK KK KK KK KKK KK KK KK KK KK KKK KK ke KK KK KK KK KKK Init PCG Set PCGA SCLK amp FSYNC Source first to Xtal Buffer and set SCLK A divisor rO PCGA FS PHASE LO lt lt 20 PCGA CLK DIVISOR dm PCG CTLA1 r0 Enable PCGA SCLK amp FSYNC and set FSYNC A divisor rO ENCLKA ENFSA PCGA FS DIVISOR dm PCG CTLAO r0 Set PCGB SCLK amp FSYNC Source first to Xtal Buffer and set SCLK B divisor rO PCGB FS PHASE LO lt lt 20 PCGB_CLK_DIVISOR dm PCG CTLB1 r0 Enable PCGB SCLK and disable FSYNC B rO ENCLKB ENF
61. 0x401 SPORT 3 control 0x0000 0000 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 109 Register Listing Register Mnemonic Address Description Reset DIV2 0x402 SPORT 2 divisor for TX RX SCLK2 and FS2 0x0 DIV3 0x403 SPORT 3 divisor for TX RX SCLK3 and FS3 0x0 SPMCTL23 0x404 SPORTs 2 amp 3 Multichannel Control 0x0 MT2CSO0 0x405 SPORT 2 multichannel TX select channels 31 0 Undefined MT2CSI 0x406 SPORT 2 multichannel TX select channels 63 32 Undefined MT2CS2 0x407 SPORT 2 multichannel TX select channels 95 64 Undefined MT2CS3 0x408 SPORT 2 multichannel TX select channels 127 96 Undefined MR3CSO 0x409 SPORT 3 multichannel RX select channels 31 0 Undefined MR3CSI 0x40A SPORT 3 multichannel RX select channels 63 32 Undefined MR3CS2 0x40B SPORT 3 multichannel RX select channels 95 64 Undefined MR3CS3 0x40C SPORT 3 multichannel RX select channels 127 96 Undefined MT2CCSO 0x40D SPORT 2 multichannel TX compand select channels 31 0 Undefined MT2CCSI 0x40E SPORT 2 multichannel TX compand select channels 63 32 Undefined MT2CCS2 0x40F SPORT 2 multichannel TX compand select channels 95 64 Undefined MT2CCS3 0x410 SPORT 2 multichannel TX compand select channels 127 96 Undefined MR3CCSO 0x411 SPORT 3 multichannel RX compand select channels 31 0 Undefined MR3CCS1 0x412 SPORT 3 multi
62. 22 21 20 e 18 17 6 RXS A TXS A 31 30 ie Data Buffer Channel A Status ROVF_A TUVF_A Channel A overflow underflow status sticky RXS_B TXS_B 28 27 Data Buffer Channel B Status ROVF_B TUVF_B Channel B overflow underflow status sticky BHD Buffer Hang Disable L LMFS LTDV Active Low Transmit Data Valid SDEN_A Receive DMA Channel A Enable SCHEN_A Receive DMA Channel A Chaining Enable SDEN_B Receive DMA Channel B Enable SCHEN_B Receive DMA Channel B Chaining Enable fa 10 fee ea AERE IMFS Internally Generated Mul tichannel Frame Sync CKRE Active Clock Edge for Data and Frame Sync Sampling OPMODE SPORT Operation Mode ICLK Internally Generated Clock DTYPE 2 1 Data Type LSBF Serial Word Bit Order SLEN 8 4 Serial Word Length 1 PACK 16 32 Packing Figure A 17 SPCTLx Register Multichannel Mode ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 39 Peripherals Routed Through the DAI Table A 17 SPCTLx Register Bit Descriptions Multichannel Name Description Reserved DTYPE Data Type Select Selects the data type formatting for standard serial mode transmissions For Standard serial mode selection of companding mode and MSB format are exclusive Multichannel Data Type Formatting 00 Right justify zero fil
63. 3 00011 0x3 DAI PB04 O Pin buffer 4 00100 0x4 DAI PB05 O Pin buffer 5 00101 0x5 DAI PB06 O Pin buffer 6 00110 0x6 DAI PB07 O Pin buffer 7 00111 0x7 DAI PB08 O Pin buffer 8 01000 0x8 DAI PB09 O Pin buffer 9 01001 0x9 DAI PB10 O Pin buffer 10 01010 0xA DAI PB11 O Pin buffer 11 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 83 DAI Signal Routing Unit Registers Table A 42 Group A Sources Serial Clock Contd Selection Code Source Signal 01011 0xB DAI PBI2 O Pin buffer 12 01100 0xC DAI PB13 O Pin buffer 13 01101 0xD DAI PB14 O Pin buffer 14 01110 OxE DAI PB15 O Pin buffer 15 01111 OxF DAI PB16 O Pin buffer 16 10000 0x10 DAI PB17 O Pin buffer 17 10001 0x11 DAI PB18 O Pin buffer 18 10010 0x12 DAI PB19 O Pin buffer 19 10011 0x13 DAI PB20 O Pin buffer 20 10100 0x14 10101 0x15 SPORTO CLK O SPORTI CLK O SPORT 0 clock SPORT 1 clock 10110 0x16 SPORT2_CLK_O SPORT 2 clock 10111 0x17 SPORT3_CLK_O SPORT 3 clock 11000 0x18 SPORT4_CLK_O SPORT 4 clock 11001 0x19 SPORT5_CLK_O SPORT 5 clock 11010 0x1A DIR_CLK_O SPDIF receive clock output 11011 0x1B DIR_TDMCLK_O SPDIF receive TDM clock output 11100 0x1C PCG_CLKA_O Precision clock A output 11101 0x1D PCG_CLKB_O Precision clock B output 11110 Ox1E LOW Logic level low 0 111
64. 3 4 5 6 Processors Asynchronous Sample Rate Converter data into the 64 bit shift register The input to the shift register is con nected to SRCx TDM 0P I and the output is connected to SRCx DAT 0P 0 By connecting the SRCx DAT 0P 0 to the SRCx TDM 0P I of the next SRC a large shift register is created which is clocked by SRCx CLK 0P I TDM Input Daisy Chain In TDM input port several SRCs can be daisy chained together and con nected to the serial input port of a SHARC processor or other processor Figure 12 4 The SRC IP contains a 64 bit parallel load shift register When the SRCx FS IP I pulse arrives each SRC parallel loads its left and right data into the 64 bit shift register The input to the shift register is connected to SRCx DATA IP I while the output is connected to SRCx TDM IP 0 By connecting the SRCx DATA IP I to the SRCx TDM IP 0 of the next SRC a large shift register is created which is clocked by SRCx IP CLK I The number of SRCs that can be daisy chained together is limited by the maximum frequency of SRCx CLK xx I which is about 25 MHz For example if the output sample rate fs is 48 kHz up to eight SRCs could be connected since 512 f is less than 25 MHz ADSP 2136x SHARC Processor Hardware Reference 12 15 for the ADSP 21362 3 4 5 6 Processors Operation Modes TDM IP Daisy Chain Clock FS Clock FS TDM OP Daisy Chain Figure 12 4 TDM Input Output Modes Bypass Mode
65. 32 Dosis dq oo feret MIT 14 32 Loading the Boot Kernel Using DMA Leere 14 33 Executing the Boor Kernel cecsussunicensuncredees 14 33 Loading the Application oincisenriintenintaensewmens 14 33 Loading the Application s Interrupt Vector Table 14 34 cii Program Beet a ccccncsinomunsneniaineaaas 14 34 Internal Memory Kernel Load 1 ecce rt ris tna t eHS sis 14 35 Parallel Port Booting eidiastisscaietbsdis E HRK MM MILF a PEL Ue iid tiia 14 36 SPI Port Booting 14 38 Nr bane Node eara 14 38 Alaster Header Tater Ot eneo 14 40 Skive f ior TT a eee 14 41 uM E oo rr MM 14 42 32 Bit SPI Packing M 14 44 I lego e NE 14 45 ADSP 2136x SHARC Processor Hardware Reference Xxv for the ADSP 21362 3 4 5 6 Processors Contents SBi SPI Pae cor 14 46 Ferme Boor Tine EE 14 47 Detinition of TERUEL sisdv ex xii pan EQ araa 14 48 REGISTERS REFERENCE 1 0 Processor Teeter quvzusxsecidetoibebiniunidaspip vet betebiufeipeiinipbas iia A 2 Notes on Reading Register Drawings sc aeescenti uper tni ras A 3 Systemi Control Register OY SOT aacecenedeitspbinec d einige ipti A 4 Power Management Control Peer E usin es A 6 ave itor WE tos 2 ener oe ane Ren qan dida a a buen mdi n quide A 10 MTM DMA Control MTMCTL Register 5 utem enitn A 10 Parallel Port Registers coecniatmenarerenininnsnedeidie A 10 Parallel Port DMA Registers ronoimnroassnrsnncneensneniis A 10 Parallel Port Control Register PPC
66. 32 bit period buffer and a 32 bit width buffer are used During the pulse width and period capture WDTH CAP mode both the period and width values are captured at the appropriate time Since both the width and period registers are read only in this mode the exist ing 32 bit period and width buffers are used When the processor is in EXT CLK mode the width register is unused Status and Control Registers The timer global status and control MSTAT register indicates the status d all three timers using a single read The TMSTAT register also contains timer enable bits Within TMSTAT each timer has a pair of sticky status bits that require a write one to set TIMxEN or write one to clear TIMxDIS to enable and disable the timer respectively Writing a one to both bits of a pair disables that timer Each timer also has an overflow error detection bit TIMxOVF When an overflow error occurs this bit is set in the TMSTAT register A program must write one to clear this bit After the timer has been enabled its TIMxEN bit is set 1 The timer then starts counting three peripheral clock cycles PCLK after the TIMxEN bit is set Setting writing one to the timer s TIMxDIS bit stops the timer with out waiting for another event Operation To enable an individual timer set the timer s TIMxEN bit in the TMSTAT reg ister To disable an individual timer set the timer s TIMxDIS bit in the ADSP 2136x SHARC Processor
67. 49 bootstrap loading 14 32 DMA use in 2 2 hardware use 14 32 IVT addresses 14 35 process 14 32 SPI master mode 14 38 SPI packing 14 42 SPI slave mode 14 41 boot memory select pin BMS not used 4 3 buffer addressing 2 18 data 2 9 DMA count 2 4 interrupts 2 27 4 15 parallel port operation 4 11 SPORT data 6 1 stalls core 2 33 4 17 buffer continued TCB allocation 2 21 buffer enable DIT_CHANBUEF bit S PDIF 11 10 buffer hang disable BHD bit 6 55 A 34 A 38 A 41 buses access through I O processor 2 34 ALE cycles and 4 20 contention 7 37 contention in SPORTs 6 43 determining parallel port cycles 4 17 external 4 16 4 25 A 13 external parallel 4 12 granting 7 24 hold cycle enable PPBHC bit 4 17 S and C 3 I O address IOA 2 18 I O data IOD 2 3 2 14 7 37 I O processor IOP 2 3 2 14 6 21 packing sequence 4 6 parallel port 4 1 parallel port bus hold cycle enable PPBHO bit 4 8 parallel port bus hold cycle enable PPBHO bits A 12 parallel port bus status PPBS bit 4 16 A 13 parallel port pins 4 8 unpacking sequence 4 7 bypass as a one shot strobe pulse 13 14 C capacitors bypass decoupling 14 29 center aligned paired PWM double update mode 10 16 single update mode 10 14 chain assignment I O processor 2 22 I 2 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors chained DMA 2 3 2 20 2 24 2 25 chained DM
68. 5 Index A for Ping Pong DMA 0x0 IDP_DMA_I6A 0x240E IDP DMA Channel 6 Index A for Ping Pong DMA 0x0 ADSP 2136x SHARC Processor Hardware Reference A 115 for the ADSP 21362 3 4 5 6 Processors Register Listing Register Mnemonic Address Description Reset IDP DMA I7A 0x240F IDP DMA Channel 7 Index A for Ping Pong DMA 0x0 IDP_DMA_IOB 0x2418 IDP DMA Channel 0 Index B for Ping Pong DMA 0x0 IDP_DMA_I1B 0x2419 IDP DMA Channel 1 Index B for Ping Pong DMA 0x0 IDP_DMA_I2B 0x241A IDP DMA Channel 2 Index B for Ping Pong DMA 0x0 IDP_DMA_I3B 0x241B IDP DMA Channel 3 Index B for Ping Pong DMA 0x0 IDP_DMA_I4B 0x241C IDP DMA Channel 4 Index B for Ping Pong DMA 0x0 IDP_DMA_I5B 0x241D IDP DMA Channel 5 Index B for Ping Pong DMA 0x0 IDP_DMA_I6B 0x241E IDP DMA Channel 6 Index B for Ping Pong DMA 0x0 IDP_DMA_I7B 0x241F IDP DMA Channel 7 Index B for Ping Pong DMA 0x0 IDP DMA MO 0x2410 IDP DMA Channel 0 Modify 0x0 IDP DMA MI 0x2411 IDP DMA Channel 1 Modify 0x0 IDP_DMA_M2 0x2412 IDP DMA Channel 2 Modify 0x0 IDP_DMA_M3 0x2413 IDP DMA Channel 3 Modify 0x0 IDP_DMA_M4 0x2414 IDP DMA Channel 4 Modify 0x0 IDP_DMA_M5 0x2415 IDP DMA Channel 5 Modify 0x0 IDP_DMA_MG6 0x2416 IDP DMA Channel 6 Modify 0x0 IDP_DMA_M7 0x2417 IDP DMA Channel 7 Modify 0x0 IDP DMA CO 0x2420 IDP DMA Channel 0 Count 0x0 IDP DMA CI 0x2421 IDP DMA Channel 1 Count 0x0 IDP DMA C2 0x2422 IDP DMA C
69. 6 Processors Parallel Port For example assume PPDUR3 BHC 0 and the parallel port is in 8 bit mode The first byte on a new page takes six peripheral clock cycles three for the ALE cycle and three for the data cycle and the next sequential 255 bytes consume three peripheral clock cycles each Therefore the average data rate for a 256 byte page is 3 PCLK x 255 6 PCLK x 1 256 3 PLCK byte For a 333 MHz core this results in 166 MHz PCLK x 1 byte 3 PCLK 55 3M Bytes sec There should be a correlation between the ECPP and ICPP register values In 8 bit mode the ECPP value should be four times that of ICPP 16 Bit Access In 16 bit mode every word transfer consists of two ALE cycles and two data cycles Therefore for every 32 bit word transferred at least six PCLK cycles are needed to transfer the data plus an additional six PCLK cycles for the two ALE cycles for a total of 12 PCLK cycles per 32 bit transfer four bytes For a 333 MHz core clock this results in a maximum sustained data rate device of 166 MHz 3 55 5M Bytes sec There is a specific case which allows this maximum rate to be exceeded If the external address modifier EMPP is set to a strideof zero then only one ALE cycle is needed at the very start of the transfer Subsequent words essentially written to the same address do not require any ALE cycles and every parallel port cycle may be a 16 bit data cycle In this case the throughput is n
70. A channel enabled 3 1 Reserved 8 4 SLEN Serial Word Length Select Selects the word length in bits Word sizes can be from 8 bits SLEN 7 to 32 bits SLEN 31 A 36 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Registers Reference Table A 16 SPCTLx Register Bit Descriptions S Left Justified Contd Bit Name Description 9 PACK 16 bit to 32 bit Word Packing Enable 0 Disable 16 to 32 bit word packing 1 Enable 16 to 32 bit word packing 10 MSTR Master Clock Select 0 Select external clock and frame sync 1 Select internal clock and frame sync 11 OPMODE Sport Operation Mode 1 Selects the I7S or left justified mode Bit 17 is used to select either of both modes 14 12 Reserved 15 DIFS Data Independent Frame Sync Select 0 Serial port uses a data dependent frame sync sync when TX FIFO is not empty or when RX FIFO is not full 1 Serial port uses a data independent frame sync sync at selected interval 16 L FIRST Left Channel Word First Select Selects left or right channel Word first To select the channel order set the L FIRST bit 1 to transmit or receive on left channel first or clear the L FIRST bit 0 to trans mit or receive on right channel first 17 LAFS I2S or Left Justified Mode Select 0 I28 mode 1 Left justified mode See also bit 11 of
71. ADSP 21362 3 4 5 6 Processors 3 MEMORY TO MEMORY PORT DMA Table 3 1 and the following list describe the MTM features Table 3 1 MTM Port Feature Summary Feature Availability Connectivity Multiplexed Pinout No SRU DAI Required No SRU DAI Default Routing N A Interrupt Default Routing Yes P151 Protocol Master Capable Yes Slave Capable No Transmission Simplex Yes Transmission Half Duplex No Transmission Full Duplex No Access Type Data Buffer Yes Core Data Access No DMA Data Access Yes DMA Channels 2 DMA Chaining No Interrupt Source DMA Boot Capable No ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Features Table 3 1 MTM Port Feature Summary Contd Feature Availability Local Memory No Clock Operation PCLK Features The memory to memory port incorporates e 2 DMA channels read and write Internal to internal transfers Data engine for DTCP applications only for special part numbers Functional Description The memory to memory DMA controller is capable of transferring 64 bit bursts of data between internal memories The MTM controller supports data in normal word address space only 32 bit External DMA transfers are not supported DMA Channels Two DMA channels are used for memay to memory DMA transfers The write DMA channel has higher priority over the rea
72. ADSP 21362 3 4 5 6 Processors Serial Ports To transmit or receive words continuously in left justified mode load the FSDIV register with the same value as SLEN For example for 8 bit data words SLEN 7 set FSDIV 7 Left Justified Mode Timing Control Bits Several bits in the SPCTLx control register enable and configure left justi fied mode operation Operation mode 0PMODE 1 left justified mode Late frame sync LAFS 1 left justified mode Frame sync channel first L FIRST Master mode enable MSTR e Word length SLEN 8 32 bits e Channel enable SPEN_A or SPEN B For complete descriptions of these bits see SPORT Serial Control Regis ters SPCTLx on page A 30 Frame Sync Channel First L FIRST Using the L FIRST bit it is possible to select on which frame sync edge rising or falling that the SPORTs transmit or receive the first sample Setting the L FIRST bit to 1 frame on falling edge of frame sync 0 frame on rising edge of frame sync Figure 6 5 illustrates only one possible combination of settings attainable in the left justified mode In this example case OPMODE 1 LAFS 1 and L FIRST l1 ADSP 2136x SHARC Processor Hardware Reference 6 37 for the ADSP 21362 3 4 5 6 Processors Operating Modes SPORTX CLK SPORTx_FS WS LEFT JUSTIFIED MODE SPORTx_DA DB DATA nz SAMPLE n 1 SAMPLE n SAMPLE n 1 Figure 6 5 Word Select Timing in Left justified
73. ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors B INTERRUPTS This chapter provides a listing of the registers that are used to configure and control programmable interrupts For information on interrupt vector tables and the core interrupt registers see the SHARC Processor Program ming Reference Programmable Interrupt Control Registers The following sections provide descriptions of the programmable inter rupts that are used in the ADSP 2136x processors These registers allow programs to substitute the default interrupts for some other interrupt source For information on the interrupt registers and the interrupt vector table see Appendix B Interrupts Table B 1 lists the locations to be programmed in the programmable interrupt control registers PICR to route a peripheral interrupt source to a corresponding processor interrupt location Table B 1 also defines the PICR bits which should be programmed to select the source for each priority interrupt Priority programming can be accomplished by changing the sources for each priority interrupt For ADSP 2136x SHARC Processor Hardware Reference B 1 for the ADSP 21362 3 4 5 6 Processors Programmable Interrupt Control Registers example if peripheral x should be given high priority the high priority priority interrupt source should be set as that peripheral x Table B 1 Default Programmable Interrupt Controller Routing Table
74. Control 5 0x0 SRU_FSO 0x2450 SRU FS Control 0 0x2736 B4E3 SRU_FS1 0x2451 SRU FS Control 1 0x3DEF 7BDE SRU_FS2 0x2452 SRU FS Control 2 0x3DEF 7BDE SRU_FS3 0x2453 SRU FS Control 3 0x3DEF 7BDE SRU_PINO 0x2460 SRU Pin Control 0 0x04C8 0A94 SRU_PIN1 0x2461 SRU Pin Control 1 0x04E8 4B96 SRU_PIN2 0x2462 SRU Pin Control 2 0x0366 8C98 SRU_PIN3 0x2463 SRU Pin Control 3 0x03A7 14A3 SRU_PIN4 0x2464 SRU Pin Control 4 0x0569 4F9E ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors A 117 Register Listing Register Mnemonic Address Description Reset SRU EXT MISCA 0x2470 SRU External Misc A Control Ox3DEF 7BDE SRU EXT MISCB 0x2471 SRU External Misc B Control Ox3DEF 7BDE SRU PBENO 0x2478 SRU Pin Enable 0 0x0E24 82CA SRU PBENI 0x2479 SRU Pin Enable 1 0x1348 D30F SRU PBEN2 0x247A SRU Pin Enable 2 0x1A55 45D6 SRU PBEN3 0x247B SRU Pin Enable 3 Ox1D71 F79B DAI PIN PULLUP 0x247D Controls whether DAI bin buffers have pullups enabled OxFFFFF DAI Interrupt Registers DAI IRPTL FE 0x2480 DAI Falling Edge Interrupt Latch 0x0 DALIRPTL_RE 0x2481 DAI Rising Edge Interrupt Latch 0x0 DAI IRPTL PRI 0x2484 DAI Interrupt Priority 0x0 DAI_IRPTL_H 0x2488 DAI High Priority Interrupt Latch 0x0 DAI_IRPTL_L 0x2489 DAI Low Priority Interrupt Latch 0x0 DAI_IRPTL_HS 0x248C Shadow DAI High Priority Interrupt Latch 0x0 DAI_IRPTL_LS 0x248D Shadow DAI Low Pri
75. DEMO unes ensi vesci berlin IM UE 6 23 Companding Asa Function soiorn 6 24 Clock Signal Opti 6 25 Master Clock Divider Registers DIVE srsrorsninererasanis 6 25 x ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Contents Master aS Ca A H 6 25 Nor DIE SC NE Lain dedi Pontici S 6 26 Slave Mad 1eosssabemdat a tubid dani MM M RE E mE UU 6 26 Clock Spurce MOL MSTRI Lea sme erue atiis ipm rd cd nde 6 27 Sampling Edge RICE E 6 27 Frame Syne LODIORBE cosecusitewietudeo ied DIR a 6 28 Framed Versus Unframed Frame Syncs 1st reta ense 6 28 Internal Versus External Frame Syncs TES IMFS MS TR e 6 29 Logic Level Frame Synes LES LMES sisisciescsssicicasninsiessennica 6 30 Early Versus Late Frame Syncs LABS scicsiessareticicersceneeeseronse 6 31 Data Independent Frame Sync One Channel 1 5 ees 6 32 Data Independent Frame Sync Two Channels 6 33 Ne NUDO Loop ehaddios a NN QUNM ane 6 34 Standard Serial Mode diueecenanducdodi dde etse iR MER HMM DAC ERE 6 34 Timing Control o o 6 34 LAGOEDIEUOHDODE qustieavedikibbta upto to PR Rd dU 6 35 zr d nodo o MM 6 35 Leir ete Mode aautonipsdoptbun fcd diba s b RO b RD 6 36 Master Serial Clock and Frame Sync Rates i5 eectettnes 6 36 Left Justified Mode Timing Control Bits 6 37 Frame Syne Channel First L FIRST duuseaeiesesesibebesp nbiuiuss 6 37 P
76. DMA enable PPDEN A 12 DMA status PPDS bit A 13 enable PPEN A 12 external data width PP16 A 12 FIFO status PPS A 13 hold cycle PPBHC 4 8 parallel port chaining status PPCHS A 14 PP16 external data width A 12 PPBHD buffer hang disable A 13 PPBS bus status A 13 PPDEN DMA enable A 12 PPDS parallel port DMA status A 13 PPEN enable A 12 PPI parallel port interrupt 4 16 4 18 PPS FIFO status A 13 PPTRAN transmit receive select A 12 parallel port bits continued transmit receive select PPTRAN 4 6 4 24 4 25 PCG active low frame sync select for frame sync INVFSx bits 13 13 bypass mode 13 13 clock A source CLKASOURCE bit A 67 clock input CLKIN pin 13 3 13 21 control PCG_CTL_Ax registers 13 15 A 66 division ratios 13 17 frame sync A source FSASOURCE bit 13 15 A 67 frame sync B source FSBSOURCE bit 13 15 frame syncs 13 13 frequency of the frame sync output 13 10 one shot frame sync A or B STROBEx bits 13 13 one shot option 13 14 PCG CTLAO control register A 66 phase shift of frame sync 13 11 pulse width PCG PW register 13 13 13 14 setup for PS or left justified DAI example 13 16 synchronization with the external clock 13 9 PCI program control interrupt bit 2 22 2 25 2 27 2 28 4 13 parallel port 4 14 4 19 SPI 7 12 SPORTS 6 52 PCM audio 11 18 PDAP enable IDP PDAP EN bit A 52
77. Data Sheet Never share a clock buffer IC with a signal of a different clock fre quency This introduces excessive jitter Clocking To provide the clock generation for the core and system the processor uses an analog PLL with programmable state machine control The PLL design serves a wide range of applications It emphasizes embedded appli cations and low cost for general purpose processors in which performance flexibility and control of power dissipation are key features This broad range of applications requires a range of frequencies for the clock generation circuitry The input clock may be a crystal an oscillator or a buffered shaped clock derived from an external system clock oscillator Figure 14 1 illustrates a conceptual model of the PLL circuitry with con figuration inputs and resulting outputs In the figure the VCO voltage controlled oscillator is an intermediate clock from which the core clock CCLK and peripheral clock PCLK are derived Furthermore an imple mented bypass path allows programs to change any VCO frequency dynamically while the core is fed at CLKIN speed 14 4 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors System Design Subject to the maximum VCO frequency the PLL supports a wide range of multiplier ratios of the input clock CLKIN To achieve this wide multi plication range the processor uses a combination of programmable multipliers in the PLL fee
78. E SPICTL IISPI IMSPI RXSPI or SPI Data SPIDMAC CSPI CPSPI TXSPI SPIBAUD SPISTAT 21 F PPCTL IIPP IMPP ICPP RXPP or Parallel Port EIPP ECPB TXPP Data EMPP CPPP 22 G SPICTLB IISPIB IMSPIB RXSPIB or SPIB Data SPIDMACB CSPIB CPSPIB TXSPIB SPIBAUDB SPISTATB ADSP 2136x SHARC Processor Hardware Reference 2 13 for the ADSP 21362 3 4 5 6 Processors DMA Channel Priority Table 2 9 DMA Channel Priorities Contd DMA Peripheral Control Status Parameter Data Buffer Description Channel Group Registers Registers Number 23 H MTMCTL IIMTMW MTM FIFO Memory to IMMTMYW memory write CMTMW data 24 I MTMCTL IIMTMR MTM FIFO Memory to IMMTMR memory read CMTMR data DMA Channel Arbitration Modes DMA channel arbitration is the method that the arbiter uses to determine how groups rotate priority with other channels The default DMA channel priority is fixed prioritization by DMA channel group Peripheral DMA Bus DMA capable peripherals execute DMA data transfers to and from inter nal memory over the IOD bus Figure 2 1 When more than one of these peripherals requests access to the IOD bus in a clockcycle the bus arbiter which is attached to the IOD bus determines which master should have access to the bus and grants the bus to that master The core user breakpoint unit allows monitoring of the IOD bus activities For more information refer to the JTAG chapter in the SHAR
79. Each frame in the AES3 stream is made up of two subframes The first subframe is channel A and the second subframe is channel B A block is comprised of 192 frames The channel status is orga nized into two 192 bit blocks one for channel A and one for channel B Normally the channel status of channel A is equal to channel B It is extremely rare that they are ever different Three different preambles are used to indicate the start ofa block and the start of channel A or B Preamble Z indicates the start of a block and the start of subframe channel A Preamble X indicates the start of a channel A subframe when not at the start of a block Preamble Y indicates the start of a channel B subframe ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Audio Frame Formats The user bits from the channel A and B subframes are simply strung together For more information please refer to the AES3 standard CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL Y Y Y 1 2 1 2 1 2 SUBFRAME SUBFRAME 1 2 FRAMEO START OF BLOCK Figure C 4 S PDIF Block Structure The data carried by the SPDIF interfaceis transmitted serially In order to identify the assorted bits of information the data stream is divided into frames each of which are 64 time slots or 128 unit intervals in length Figure C 4 Since the time slots correspond with the data bits the frame is often described as bein
80. FIFO to zero C144 dB attenuation 12 10 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Asynchronous Sample Rate Converter This mode is useful for automatic detection of non PCM audio data received from the S PDIF receiver Register Descriptions The SRC uses five registers to confgure and operate the SRC module For complete register and bit descriptions see Sample Rate Converter Regis ters on page A 59 Initially programs configure the SRC control registers SRCCTLO and SRCCTL1 The SRCCTLO register contains control parameters for the SRCO and SRC1 modules and the SRCCTLI register contains control values for the SRC2 and SRC3 modules The control parameters include mute information data formats for input and output ports de emphasis enable dither enable and matched phase mode enable ADSP 21364 only for multiple SRCs Write the settings to the desired control register at least one cycle before setting the corresponding SRC module enable bit SRCx ENABLE The following sections provide details on the SRC s control registers within the ADSP 2136x processors Control Registers SRCCTLn When the SRCx ENABLE bit bit 31 in theSRCCTLx registers is set 1 the SRC begins its initialization routine where all locations in the FIFO are initialized to zero MUTE OUT signal is asserted and any output pins are enabled When setting and clearing the SRCx ENABLE bit it shou
81. Figure 5 7 for transmit and receive operation where the signal input of the assigned pin buffer is tied low The peripheral s data output signal is connected to thePBEN signal In open drain mode if PBEN low the level on the pin depends on the bus activities If PBEN high the driver is conducting input always low level and ties the bus to low level INTERFACE TO SRU SPIB MOSI PBEN O Figure 5 7 PIN BUFFER OUTPUT DAI PBxx O PIN BUFFER INPUT TIED LOW om O DAI_PBxx_l PIN BUFFER ENABLE Pin Buffer as Open Drain EXTERNAL DAI PIN BUFFER ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors 5 11 DAI Peripherals Miscellaneous Buffers The miscellaneous buffers are used to interconnect signals from different routing groups These buffers are similar to the DAI pin buffers with three basic differences 1 Only for internal connections no pin buffer enable required 2 MISCxx_0 output always feeds DAI interrupt latch register and Group F PBENx I 3 MISCxx I input sources collected from different groups The miscellaneous buffers act as intermediate buffer connections between the peripherals source node and the pin buffer enable destination node This allows for routing that is not possible among a single group The miscellaneous buffer allows interconnects which are not sup ported within a single DAI routing group MISCxx O OUTPUT PBEN I INPUT MISCx
82. For reference see Table 6 4 on page 6 11 Table 6 5 on page 6 19 and SPORT Serial Control Registers SPCTLx on page A 30 Standard Serial Mode The standard serial mode lets programs configure serial ports for use by a variety of serial devices such as serial data converters and audio codecs For more information see Appendix C Audio Frame Formats Timing Control Bits Several bits in the SPCTLx control register enable and configure standard serial mode operation Operation mode 0PMODE 0 standard serial mode Frame Sync Channel First LFS Frame Sync Required FSR Internal Frame Sync IFS Sampling Edges Frame Sync data CKRE Logic Level Frame Sync LFS 6 34 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Serial Ports Internal clock enable 1CLK e Word length SLEN 3 32 bits e Channel enable SPEN_A or SPEN B Clocking Options In standard serial mode the serial portscan either accept an external serial clock or generate it internally The ICLK bit in the SPCTL register deter mines the selection of these options For internally generated serial clocks the CLKDIV bits in the DIVx register configure the serial clock rate Finally programs can select whether the serial clock edge is used for sam pling or driving serial data and or fame syncs This selection is performed using the CKRE bit in the SPCTL register See SPORT Serial Control Regis ters SP
83. H SH are provided for registers DAI IRPTL L and DAI IRPTL H respectively Reads of the shadow registers returns the data in the DAI IRPTL L and DAI IRPTL H reg isters respectively without clearing the contents of these registers ADSP 2136x SHARC Processor Hardware Reference 5 29 for the ADSP 21362 3 4 5 6 Processors Debug Features Loop Back Routing The serial peripherals SPORT and SPI support an internal loop back mode If the loop back bit for each peripheral is enabled it connects the transmitter with the receiver block internally does not signal off chip The SRU can be used for this propose Table 5 4 describes the different possible routings based on the peripheral The peripheral s loop back mode for debug is independent from both of the signal routing units Table 5 4 Loop Back Routing Peripheral Loopback SRU Internal Routing for SRU External Routing for Mode Loopback Loopback IDP N A N A N A SPORT Yes SPORTx xx O SPORTx xx I SPORTx xx O DAI PBxx I DAI PBxx O SPORTx xx I S PDIF No DIT O DIR I DIT O DAI PBxx I Tx Rx DAI PBxx O DIR I Timer No TIMERx O TIMERx I TIMERx O DAI PBxx I DAI PBxx O TIMERx I SPI Yes No SPIx xx O DAI PBxx I DAI PBxx O SPIx xx I 5 30 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Digital Application Interface Programming Model As discussed in the
84. Hardware Reference 9 7 for the ADSP 21362 3 4 5 6 Processors Operation TMSTAT register To enable all three timers in parallel set all the TIMxEN bits in the TMSTAT register Before enabling a timer always program the corresponding timer s config uration TMxCTL register This register define the timer s operating mode the polarity of the TIMERx signal and the timer s interrupt behavior Do not alter the operating mode while the timer is running For more infor mation on the TMxCTL register see Timer Configuration Registers TMxCTL on page A 56 Mode Selection The three operating modes of the peripheral timer PWM OUT WDTH CAP and EXT CLK are described in Table 9 4 and the follow ing sections Table 9 4 Timer Signal Use TMxCTL PWM_OUT Mode WIDTH_CAP Mode EXT_CLK Mode Register Settings MODE 01 Output PWM Wave 10 Input Waveform 11 Input Event form TIMEN 1 Enable amp Start Timer 1 Enable amp Start Timer 1 Enable amp Start Timer 0 Disable Timer 0 Disable Timer 0 Disable Timer PULSE 1 Generate High Width 1 Measure High Width Count at event rise only 0 Generate Low Width 0 Measure Low Width PRDCNT 1 Generate PWM 1 Measure Period Unused 0 Single Width Pulse 0 Measure Width IRQEN 1 Enable Interrupt 1 Enable Interrupt 1 Enable Interrupt 0 Disable Interrupt 0 Disable Interrupt 0 Disable Interrupt Period WO Period Value RO
85. I Serial Input Port Frame Sync Input The frame sync pulse initiates shifting of serial data This sig nal must be generated externally and comply to the supported input formats IDP7 0 DAT I I Serial Input Port Data Input Unidirectional data pin Data signal must comply to the supported data formats SRU Descriptions The SRU signal routing unit needs to be programmed in order to con nect the IDP to the output pins as shown in Table 8 3 Table 8 3 IDP DAI SRU Signal Connections Internal Node DAI Group SRU Register Inputs IDP7 0 CLK I Group A SRU CLK3 2 IDP7 0 FS I Group C SRU FS3 2 IDP7 0 DAT I Group B SRU_DAT5 4 ADSP 2136x SHARC Processor Hardware Reference 8 5 for the ADSP 21362 3 4 5 6 Processors Serial Input Port Input Data Formats An audio signal that is normally 24 bits wide is contained within the 32 bit word An additional four bits ar available for status and formatting data compliant with the IEC 90958 S PDIF and AES3 standards An additional bit identifies the left right one half of the frame If the data is not in IEC standard format the serial data can be any data word up to 28 bits wide The remaining three bits are used to encode one of the eight channels being passed through the FIFO to the core The FIFO output may feed eight DMA channels where the appropriate DMA channel cor responding to the channel number is selected automatically R
86. IDP PP CTL IDP DMA I0A 0 supports DAI STAT IDP DMA IOB both IDP DMA PCO 13 IDP_CTLO IDP DMA Il IDP FIFO DAIIDP IDP CTLI IDP DMA MI Channel 1 IDP FIFO IDP DMA C1 DAI STAT IDP DMA II1A IDP DMA IIB IDP DMA PCI 14 IDP CTLO IDP DMA I2 IDP FIFO DAIIDP IDP CTLI IDP DMA M2 Channel 2 IDP FIFO IDP DMA C2 DAI STAT IDP DMA I2A IDP DMA I2B IDP DMA PC2 15 IDP CTLO IDP DMA I3 IDP FIFO DAIIDP IDP CTLI IDP DMA M3 Channel 3 IDP FIFO IDP DMA C3 DAI STAT IDP DMA I3A IDP DMA I3B IDP_DMA_PC3 2 12 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Table 2 9 DMA Channel Priorities Contd 1 O Processor DMA Peripheral Control Status Parameter Data Buffer Description Channel Group Registers Registers Number 16 D IDP_CTLO IDP_DMA_I4 IDP_FIFO DAI IDP IDP CTLI IDP DMA M4 Channel 4 IDP_FIFO IDP_DMA_C4 DAI STAT IDP DMA I4A IDP DMA I4B IDP_DMA_PC4 17 IDP_CTLO IDP_DMA_I5 IDP_FIFO DAI IDP IDP_CTLI IDP_DMA_M5 Channel 5 IDP_FIFO IDP_DMA_C5 DAI STAT IDP_DMA_I5A IDP DMA I5B IDP DMA PC5 18 IDP_CTLO IDP_DMA_I6 IDP_FIFO DAI IDP IDP CTLI IDP DMA M6 Channel 6 IDP_FIFO IDP_DMA_C6 DAI STAT IDP DMA I6A IDP DMA IGB IDP DMA PC6 19 IDP_CTLO IDP DMA I7 IDP FIFO DAIIDP IDP CTLI IDP DMA M7 Channel 7 IDP_FIFO IDP_DMA_C7 DAI STAT IDP DMA I7A IDP DMA I7B IDP DMA PC7 20
87. In case of a full write data FIFO the held offI O processor register read or write access incurs one extra core clock cycle 3 Interrupted IOP register reads and writes if preceded by another write creates one additional core stall cycle Interrupt Latency During an interrupt driven I O transfer from any peripheral that uses an IOP interrupt service routine a write into an IOP register to clear the interrupt causes a certain amount of latency If the program comes out of the interrupt service routine during that period of latency the interrupt is generated again To avoid the interrupt from being regenerated use one of the following solutions 1 Read an IOP register from the same peripheral block before the return from interrupt RTI The read forces the write to occur as shown in the example code below ISR Routine RO 0x0 dm SPICTL RO disable SPI RO dm SPICTL dummy read occurs only after write Es 2 Add sufficient NOP instructions after a write In the worst case pro grams need to add ten NOP instructions after a write as shown in the example code below ADSP 2136x SHARC Processor Hardware Reference 2 33 for the ADSP 21362 3 4 5 6 Processors I O Processor Register Access ISR Routine RO 0x0 dm SPICTL R0 disable SPI lcntr 10 do pc 1 until Ice nop rors TCB Chain Loading Access Table 2 17 lists the time required to load aspecific TCB from the internal memory into t
88. Increased numbers and kinds of configurations Connections can be made via software no hard wiring is required Inputs may only be connected to outputs 5 2 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Digital Application Interface Functional Description Figure 5 1 shows how the DAI pin buffers are connected via the SRU The DAI is comprised of four primary blocks e Peripherals A B C associated with the DAI ASignal Routing Unit SRU e DAII O pin buffers Miscellaneous buffers The peripherals shown in Figure 5 1 can have up to three connections if master or slave capable one acts as signal input one as signal output and the third as an output enable The SRUs are based on a group of multi plexers which are controlled by registers to establish the desired interconnects The miscellaneous buffers have an input and output and are used for group interconnection ADSP 2136x SHARC Processor Hardware Reference 5 3 for the ADSP 21362 3 4 5 6 Processors Functional Description OFF INTERNAL CHIP NODE ROUTING Figure 5 1 DAI Functional Block Diagram Note that Figure 5 1 is a simplified representation of a DAI system In a real representation the SRU and DAI would show several types of data being routed from several sources including the following e Serial ports SPORTS Precision clock generators PCG Input data port IDP 5 4 ADSP 213
89. Introduction Figure 1 1 illustrates a typical single processor system ADSP 2136x RESETOUT XTAL ALE CLK CFG1 0 AD15 0 BOOTCFG1 0 FLAG3 1 ADC OPTIONAL ssayqqv viva Figure 1 1 ADSP 2136x Processor Typical Single Processor System The ADSP 2136x processors address the five central requirements for sig nal processing 1 Fast Flexible Arithmetic The ADSP 21000 family processors exe cute all instructions in a single cycle They provide fast cycle times and a complete set of arithmetic operations The processor is IEEE floating point compatible and allows either interrupt on arithmetic exception or latched status exception handling 2 Unconstrained Data Flow The processor has a Super Harvard Architecture combined with a ten port data register file In every cycle the processor can write or read two operands to or from the ADSP 2136x SHARC Processor Hardware Reference 1 3 for the ADSP 21362 3 4 5 6 Processors ADSP 2136x SHARC Design Advantages register file supply two operands to the ALU supply two operands to the multiplier and receive three results from the ALU and mul tiplier The processor s 48 bit orthogonal instruction word supports parallel data transfers and arithmetic operations in the same instruction Computation Precision The processor handles 32 bit IEEE single precision or 40 bit IEEE extended precision floating point for mats The processors can carry 32 bit integer and
90. PS data IDPx CLK I l l FRAME SYNC L R IDPx FS 1 1 1 1 I i I Lu I Lu 125 SERIAL DATA f i i i i f i I I 0 63 62 33 32 9 FRAME n 1 FRAME n FRAME n RIGHT LEFT RIGHT Figure 8 5 Timing in I S Mode 8 8 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors Input Data Port Register Descriptions This section provides information on the IDP control and status registers Complete bit information can be found at Input Data Port Registers on page A 47 Control Registers IDP CTLx The ADSP 2136x SHARC processors have a new IDP control register IDP CTL1 The IDP CTL1 0 registers are used to control the IDP opera tions Note the SIP PDAP modules have a total of 6 different modes enable bits which are required for the different transfer types To enable the SIP two separate bits in two different registers must be set The first are the global IDP EN and IDP DMA EN bits in the IDP CTLO register and the second are the specific channel enable bits which is located in the IDP_CTL1 register Status Registers DAI STATO Several bits in DAI STATO registers can be used to monitor IDP FIFO operations FIFO overflow must be reset manually using the IDP CLROVR bit in the IDP CTLO register Writing one to this bit clears the overflow conditions for the channels in the DAI STAT register Since IDP CLROVR is a write only bit it always r
91. Processor Hardware Reference 2 25 for the ADSP 21362 3 4 5 6 Processors Configuring IOP Core Interaction A DMA sequence starts when one of the following occurs e Chaining is disabled and the DMA enable bit transitions from low to high e Chaining is enabled DMA is enabled and the chain pointer regis ter address field is written with a non zero value In this case TCB chain loading of the channel parameter registers occurs first e Chaining is enabled the chain pointer register address field is non zero and the current DMA sequence finishes Again TCB chain loading occurs A DMA sequence ends when one of the following occurs The count register decrements to zero and the chain pointer regis ter is Zero e Chaining is disabled and the channel s DMA enable bit transitions from high to low If the DMA enable bit goes low 0 and chain ing is enabled the channel enters chain insertion mode SPORT only and the DMA sequence continues Once a program starts a DMA process the process is influenced by two external controls DMA channel priority and DMA chaining Configuring IOP Core Interaction There are two methods the processor uses to monitor the progress of DMA operations interrupts which are the primary method and status polling The same program can useeither method for each DMA channel The following sections describe both methods in detail 2 26 ADSP 2136x SHARC Processor Hardware Reference for the A
92. R sister sl onan 9 5 Cowi Peo aao a 9 5 Counter Registers CUM SUN T auossntekorite i hips pipi 9 6 Period Register TM PRD Luussoncesbpcsxteentep t tre Hai eren 9 6 Pulse Width Registet TMW iepusdceesseb ziuo Lcid A Fon vi 9 6 Sracus and Control Registers 9 7 ADSP 2136x SHARC Processor Hardware Reference for the ADSP 21362 3 4 5 6 Processors xvii Contents dalla 9 7 Mode Seb eee ene Ed bati Gp C bed Hd 9 8 Pulse Width Modulation Mode PWM OUT 9 9 PWM Waveform Generation 1 5 expects a ab e te Ma EHE SR 9 12 Single Pulse Generation 2iussiesiaskend lebe etiani iati ti tud 9 13 Pabe Mode eM 9 13 Pulse Width Count and Capture Mode WDTH CAD 9 14 External Event Watchdog Mode EXT CLKJ ecer 0 17 BULUM Labor db dud dede dM aM DEMNM Ed 9 19 BOUE Lecce en odii E A E E ad REM M Rd n 9 19 Watchdog Functionality uiuuxeuiezeeei iae bopedi orbe ti iios deve eii 9 20 e eE pap E E E E E E 9 20 Debug Feats 9 21 Loopback BORNE saines 9 21 Programming Model i AAT 9 22 PYM Opr Mode sorcar ENNA 9 22 WOTH CAP Mode srining na 9 23 EXT GLE Mode ote roo E an 9 24 Programming Example ioseph ti min len a do iE NAME 9 25