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ANALOG DEVICES ADSP-21467/ADSP-21469 handbook

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1. 19 10 19 00 SQ A1 BALL A1 BALL 18 90 18 16 14 12 10 8 6 4 2 CORNER CORNER 17 15 13 11 9 7 5 3 1 000000000000000000 A 000000000000000000 000000000000000000 c 000000000000000000 D 000000000000000000 E 000000000000000000 F 17 00 000000000000000000 G BSC SQ 000000000000000000 200000000000000000 J 000000000000000000 K 000000000000000000 L 100 Bsc 4 9099000000000000000 N 1 000000000000000000 000000000000000000 R 000000000000000000 000000000000000000 v TOP VIEW 1 00 4 BOTTOM VIEW REF DETAIL A 1 80 1 31 1 71 1 21 1 56 DETAIL A 141 0 50 NOM Y Y 0 45 MIN 4 27 E SEATING 0 70 COPLANARITY PLANE lt 0 60 0 20 0 50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO 192 AAG 1 WITH THE EXCEPTION TO PACKAGE HEIGHT Figure 61 324 Ball Chip Scale Package Ball Grid Array CSP_BGA BC 324 1 Dimensions shown in millimeters SURFACE MOUNT DESIGN The following table is provided as an aid to PCB design For industry standard design recommendations refer to IPC 7351 Generic Requirements for Surface Mount Design and Land Pat tern Standard Package Solder Mask Package Package Ball Attach Type Opening Package Ball Pad Size 324 Ball 5 BGA BC 324 1 Solder Mask Defined 0 43 mm diameter 0 6 mm diameter Rev A Page710f72 December 2011 ADSP 21467 ADSP 21469
2. 72 Added information on correct pin termination for unused pins and revised pin descriptions and ball assignments Unused Pin Terminations 12 iudi er ra 13 CSP_BGA Ball Assignment Standard Models 68 Corrected document errata associated with the following speci fications lt 12 DDR2 SDRAM Read Cycle Timing 1 e 32 DORZ SDRAM Write Cycle Timing 33 AMI Bead 34 Added information for shared memory support Shared External Memory 7 Pit DeSenplibfi 12 Shared Memory Bus Request 222220444 rt ete 37 Ball Assignment Automotive Models 65 CSP Ball Assignment Standard Models 68 Rev A Page20f72 cR 21 ESD Liuius a 22 22 qr 60 Drive CUCPEDIS cabe 60 Loading eU e 61 Thermal 63 Ball Assignment Automotive Models 65 CSP Ball Assignment Standard Models 68 Outline Dimensi ns Liberi ER ERO iira eia 71 Surface Mount Desig 7 Automotive Product 72 Ordonne Clo MM TN 72
3. Parameter Min Max Unit Timing Requirements tsese Frame Sync Setup Before SCLK 2 5 Externally Generated Frame Sync in either Transmit or Receive Mode ns tHESE Frame Sync Hold After SCLK 2 5 Externally Generated Frame Sync in either Transmit or Receive Mode ns tspre Receive Data Setup Before Receive SCLK 1 9 ns Receive Data Hold After SCLK 2 5 ns tscLKW SCLK Width tpcLk X 4 2 1 2 ns X 4 ns Switching Characteristics tprsE Frame Sync Delay After SCLK 10 25 Internally Generated Frame Sync in either Transmit or Receive Mode ns Frame Sync Hold After SCLK 2 Internally Generated Frame Sync in either Transmit or Receive Mode ns tpprE Transmit Data Delay After Transmit SCLK 8 5 ns tuprE Transmit Data Hold After Transmit SCLK 2 ns Referenced to sample edge Referenced to drive edge Table 37 Serial Ports Internal Clock Parameter Min Max Unit Timing Requirements tsrs Frame Sync Setup Before SCLK 7 Externally Generated Frame Sync in either Transmit or Receive Mode ns Frame Sync Hold After SCLK 2 5 Externally Generated Frame Sync in either Transmit or Receive Mode ns tspni Receive Data Setup Before SCLK 7 ns Receive Data Hold After SCLK 2 5 ns Switching Characteristics Frame Sync Delay After SCLK Internally Generated Frame Sync in Transmit Mode 4 ns tHorsi Frame Sync Hold After SCLK Internally Generated Frame
4. i 2 2 oe A LACK1 0 LDATO 7 0 LDAT1 7 0 MLBCLK MLBDAT MEAS 1 1 5 V for non pinsanc Mes M pius MLBDO MLBSIG MLBSO AMI AMI ADDR23 0 DATA7 0 51 0 AMI RD AMI WR DAI P DPI P EMU FLAG3 0 RESETOUT TDO LCLK1 0 Table 57 Driver Types TESTER PIN ELECTRONICS 500 9 Luj m OUTPUT C DDR2_ADDR15 0 2 BA2 0 DDR2 CAS DDR2 DDR2 CS3 0 DDR2_DATA15 0 20 00 impedance DDR2 DM1 0 DDR2_ODT DDR2 RAS DDR2 WE T jt D TRUE DDR2 CLK1 0 2 DOS1 0 D COMP DDR2_CLK1 0 DDR2 DOS1 0 4000 NOTES THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED FOR THE OUTPUT TIMING ANALYSIS TO REFLECT THE TRANSMISSION LINE EFFECT AND MUST BE CONSIDERED THE TRANSMISSION LINE TD IS FOR LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN SYSTEM REQUIREMENT IF NECESSARY A SYSTEM MAY INCORPORATE EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES Figure 45 Equivalent Device Loading for AC Measurements Includes All Fixtures SOURCE SINK CURRENT mA MEAS OUTPUT 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 Figure 46 Voltage Reference Levels for AC Measurements SWEEP VOLTAGE V Figure 47 Output Buffer Characteristics Worst Case Non DDR2 Rev Page600f72 De
5. Parameter Min Max Unit Switching Characteristic Timer Pulse Width Output 2 1 2 2x 2 1 ns tpwmo PWM OUTPUTS Figure 13 Timer PWM OUT Timing Timer WDTH CAP Timing The following timing specification applies to Timer0 and Timerl in CAP pulse width count and capture mode Timer signals are routed to the DPI P14 1 pins through the SRU Therefore the timing specifications provided below are valid at the DPI P14 1 pins Table 25 Timer Width Capture Timing Parameter Min Max Unit Timing Requirement Timer Pulse Width 2 X tPCLK 2 2 1 tPCLK ns tewi TIMER CAPTURE INPUTS Figure 14 Timer Width Capture Timing Rev A Page280f72 December 2011 ADSP 21467 ADSP 21469 Pin to Pin Direct Routing DAI and DPI For direct pin connections only for example DAI 01 I to DAI PBO2 O Table 26 DAI and DPI Pin to Pin Routing Parameter Min Max Unit Timing Requirement Delay DAI DPI Pin Input Valid to DAI DPI Output Valid 1 5 12 ns DAI Pn DPI Pn DAI Pm DPI Pm Figure 15 DAl and DPI Pin to Pin Direct Routing Rev A Page290f72 December 2011 ADSP 21467 ADSP 21469 Precision Clock Generator Direct Pin Routing inputs and outputs are not directly routed to from DAI pins via pin buffers there is no timing data available All timing param eters and
6. AUTOMOTIVE PRODUCTS The ADSP 21467W and ADSP 21469W models are available grade products shown in Table 62 are available for use in auto with controlled manufacturing to support the quality and reli motive applications Contact your local ADI account ability requirements of automotive applications Note that representative for specific product ordering information and to automotive models may have specifications that differ from obtain the specific Automotive Reliability reports for these commercial models and designers should review the Specifica models tions section of this data sheet carefully Only the automotive Table 62 Automotive Product Models Model 1 23 Temperature Range SRAM Package Description Package Option AD21467WBBCZ3Axx 40 to 85 C 5 Mbits 324 Ball CSP BC 324 1 AD21469WBBCZ3xx 40 C to 85 5 Mbits 324 Ball BC 324 1 1 Z RoHS compliant part xx denotes silicon revision ROM version A 4 Referenced temperature is ambient temperature The ambient temperature is not a specification Please see Operating Conditions on Page 18 for junction temperature specification which is the only temperature specification ORDERING GUIDE Temperature On Chip Processor Instruction Package Model Range SRAM Rate Max Package Description Option ADSP 21469KBCZ 3 0 to 70 5 Mbits 400 MHz 324 Ball BGA BC 324 1 ADSP 21469BBCZ 3
7. Rev Page620f72 4 5 TYPE A FALL 4 y 0 0196x 1 2934 TYPE A RISE y 0 0152x 1 7611 a 3 5 TYPE B RISE X y 0 0060 1 7614 S ul a 2 5 lt 2 lt ul 15 x 1 0 5 0 0 25 50 75 100 125 150 175 200 LOAD CAPACITANCE pF Figure 54 Typical Output Rise Fall Delay Non DDR 3 0 2 8 TYPE C HALF DRIVE FALL y 0 0122x 2 0405 TYPE C HALF DRIVE RISE _ 2 6 0 0079 2 04706 B 4 2 4 ul a d 22 lt 2 2 0 p ae S a ig TYPE C FULL DRIVE RISE amp FALL 0 0023 1 9472 1 6 1 4 0 5 10 15 20 25 30 35 LOAD CAPACITANCE pF Figure 55 Typical Output Rise Fall Delay DDR Pad C Vpp Min December 2011 RISE AND FALL DELAY ns RISE AND FALL DELAY ns TYPE D HALF DRIVE TRUE FALL y 0 0123x 2 3194 TYPE D HALF DRIVE COMP FALL D HALF DRIVE TRUE RISE y 0 0077x 2 2912 TYPE D HALF DRIVE COMP RISE TYPE D FULL DRIVE COMP RISE y 0 0077x 2 2398 0 0022x 2 1499 TYPE D FULL DRIVE TRUE RISE amp FALL TYPE D FULL DRIVE COMP FALL y 0 0022x 2 2027 0 5 10 15 20 25 30 35 LOAD CAPACITANCE pF Figure 56 Typical Output Rise Fall Delay DDR Pad D Min TYPE C HALF DRIVE FALL y 0 0046x 1 0577 YPE C FULL DRIVE RISE amp FAL
8. Sample Edge 2 5 ns tPDCLKW Clock Width teen 2 23 BE tPDCLK Clock Period tpcik X 4 ns Switching Characteristics tPDHLDD Delay of PDAP Strobe After Last Capture Edge for a Word 2 3 ns tPDSTRB PDAP Strobe Pulse Width 2 1 ns 1 The 20 bits of external PDAP data can be provided through the AMI ADDR23 4 or DAI pins Source pins for serial clock and frame sync are 1 AMI ADDR3 2 pins 2 DAI pins SAMPLE EDGE t PDCLK epci kw DAI 20 1 tspHoLp Ld mo DAI P20 1 A 4 PDAP HOLD 7 N DAI 20 1 ADDR23 4 DATA 4 DAI 20 1 PDAP STROBE Figure 30 PDAP Timing Rev A Page460f72 December 2011 ADSP 21467 ADSP 21469 Sample Rate Converter Serial Input Port The ASRC input signals are routed from the P20 1 pins using the SRU Therefore the timing specifications provided in Table 43 are valid at the DAI P20 1 pins Table 43 ASRC Serial Input Port Parameter Min Max Unit Timing Requirements tsncsrs Frame Sync Setup Before Serial Clock Rising Edge 4 ns tsncHrs Frame Sync Hold After Serial Clock Rising Edge 5 5 ns tsrcsp Data Setup Before Serial Clock Rising Edge 4 ns tsrcHp Data Hold After Serial Clock Rising Edge 5 5 ns tSRCCLKW Clock Width 4 2 1 5 8 Clock Period 4 ns The serial cl
9. Valid frequency and voltage ranges are model specific See Operating Conditions on Page 18 ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Stresses greater than those listed in Table 15 may cause perma The information presented in Figure 4 and Table 16 provides nent damage to the device These are stress ratings only details about the package branding for the processor For a com functional operation of the device at these or any other condi plete listing of product availability see Ordering Guide on tions greater than those indicated in the operational sections of Page 72 this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Table 15 Absolute Maximum Ratings Parameter Rating Internal Core Supply Voltage 0 3 V to 1 32 V Analog PLL Supply Voltage 0 3Vto 1 15 V External I O Supply Voltage gxr 0 3 V to 3 6 V Thermal Diode Supply Voltage 0 3 V to 3 6 V Figure 4 Typical Package Brand DDR2 Controller Supply Voltage 0 3Vto 1 9 V ppm Table 16 Package Brand Information DDR2 Input Voltage 0 3Vto 41 9 V Brand Key Field Description Input Voltage 0 3 V to 3 6 V t Temperature Range Output Voltage Swing 0 3 V to Vpp gxr 0 5 V pp Package Type Storage Temperature Range 659 to 150 7 RoHS Compliant Option Junction Temperature While Biased 125 cc See Order
10. ADDR15 R13 DAI P15 RO4 DDR2 DATA05 A05 GND A18 AMI ADDR16 V12 DAI P16 DDR2_DATA06 06 GND C04 ADDR17 U12 DAI P17 003 DDR2_DATAO7 A06 GND C06 AMI ADDR18 T12 DAI P18 DDR2 DATAO8 08 GND C08 AMI ADDR19 R12 DAI P19 DDR2_DATA09 A08 GND 005 AMI ADDR20 11 DAI 20 T02 DDR2_DATA10 B09 GND D07 AMI_ADDR21 U11 DDR2_ADDRO D13 DDR2_DATA11 A09 GND 009 ADDR22 T11 DDR2_ADDRO1 C13 DDR2_DATA12 All GND D10 AMI_ADDR23 R11 DDR2_ADDRO2 D14 DDR2_DATA13 B11 GND D17 AMI_DATAO U18 DDR2 ADDRO3 C14 DDR2_DATA14 A12 GND E03 AMI_DATA1 T18 DDR2_ADDR04 B14 DDR2_DATA15 B12 GND E05 AMI_DATA2 R18 2 5 A14 DDR2 DMO GND E12 DATA3 P18 DDR2_ADDRO6 D15 DDR2_DM1 C11 GND E13 AMI_DATA4 17 DDR2_ADDRO7 C15 DDR2_DQSO A04 GND E16 DATAS U17 DDR2_ADDRO8 B15 DDR2 DQSO 04 GND F01 DATA6 17 DDR2_ADDRO9 A15 DDR2_DQS1 A10 GND F02 DATA7 R17 DDR2_ADDR10 D16 DDR2 DOST B10 GND F04 MSO T10 DDR2_ADDR11 C16 DDR2 ODT 01 GND F14 AMI 51 U10 DDR2_ADDR12 B16 DDR2_RAS 09 GND F16 RD 104 DDR2_ADDR13 A16 DDR2 WE C10 GND G05 AMI_WR v10 DDR2_ADDR14 B17 P01 R02 GND G07 CFGO 102 DDR2_ADDR15 A17 DPI 2 001 GND G08 BOOT_CFG1 J03 DDR2_BAO C18 T01 GND G09 Rev A Page 65 of 72 December 2011 ADSP 21467 ADSP 21469 Table 60 5 BGA Ball Assignment Alphabetical by Signal Continued Signal Ball No Signal Ball No Signal
11. Clock Signals The processor can use an external clock or a crystal See the CLKIN pin description in Table 10 Programs can configure the processor to use its internal clock generator by connecting the necessary components to CLKIN and XTAL Figure 8 shows the component connections used for a crystal operating in funda mental mode Note that the clock rate is achieved using a 25 MHz crystal and a PLL multiplier ratio 16 1 CCLK CLKIN achieves a clock speed of 400 MHz To achieve the full core clock rate programs need to configure the multiplier bits in the PMCTL register Figure 7 Clock Input Y1 25 000 MHz TYPICAL VALUES R2 SHOULD BE CHOSEN TO LIMIT CRYSTAL DRIVE POWER REFER TO CRYSTAL MANUFACTURER S SPECIFICATIONS Figure 8 Recommended Circuit for Fundamental Mode Crystal Operation Rev A Page250f72 December 2011 ADSP 21467 ADSP 21469 Reset Table 20 Reset Parameter Min Max Unit Timing Requirements twnsT RESET Pulse Width Low 4 X tck ns tsRsT RESET Setup Before CLKIN Low 8 ns Applies after the power up sequence is complete At power up the processor s internal phase locked loop requires no more than 100 while RESET is low assuming stable Vpp and CLKIN not including start up time of external clock oscillator twrst tsnsT Figure 9 Reset Running Reset The following timing specification applies to RESETOUT RUNRSTIN pin when it is c
12. D DDR2 wosicNALS SHARED MEMORY PINS Figure 59 Ball Configuration Automotive Model Rev A Page670f72 December 2011 ADSP 21467 ADSP 21469 CSP_BGA BALL ASSIGNMENT STANDARD MODELS Table 61 lists the standard model CSP_BGA ball assignments by signal Table 61 CSP_BGA Ball Assignment Alphabetical by Signal Signal Ball No Signal Ball No Signal Ball No Signal Ball No AGND H02 CLK_CFGO 601 2 C17 DPI 4 R01 AMI_ACK R10 CLK_CFG1 G02 DDR2_BA2 B18 DPI 5 P01 AMI_ADDRO v16 CLKIN L01 DDR2 CAS C07 2 ADDRO1 016 DAI ROG DDR2_CKE E01 P07 P03 ADDRO2 T16 DAI 2 05 DDR2 CLKO A07 PO8 P04 ADDRO3 R16 DAI P03 R07 DDR2_CLKO BO7 DPI 9 01 ADDROA V15 DAI 4 R03 DDR2 CLKT A13 DPI P10 02 ADDROS U15 DAI P05 005 DDR2 CLK1 B13 DPI P11 N03 AMI ADDROG T15 DAI_P06 T05 DDR2 50 C01 DPI P12 N04 ADDRO7 R15 DAI P07 V06 DDR2 CST 001 DPI 13 M03 V14 DAI 08 02 DDR2_CS2 C02 DPI P14 M04 AMI ADDRO9 014 DAI 09 R05 DDR2 53 002 EMU K02 10 T14 DAI_P10 04 DDR2_DATAO B02 FLAGO ROS AMI_ADDR11 R14 DAI_P11 004 DDR2_DATAO1 A02 FLAG1 V07 ADDR12 V13 DAI P12 T04 DDR2_DATA02 B03 FLAG2 907 ADDR13 013 DAI P13 006 082 DATAO3 A03 FLAG3 T07 AMI_ADDR14 T13 DAI_P14 002 DDR2_DATA04 B05 GND A01 AMI_ADDR15 R13 DAI_P15 R04 DDR2_DATA05 A05 GND A18 AMI_ADDR16 V12 DAI_P
13. 08 110 01 Vpp EXT 09 GND L11 RESETOUT RUNRSTIN M02 Vpp EXT 009 GND L12 TCK K15 Vpp EXT V09 GND L14 TDI L15 Vpp rxr BRT V08 GND M05 TDO M15 2 008 GND M07 THD M N12 INT D12 GND M08 THD P N11 INT E06 GND M09 TMS K16 VDD INT E08 Rev Page690f72 December 2011 ADSP 21467 ADSP 21469 A1 CORNER INDEX AREA amp poeooeooeoo oeopoococoocoooo pppocoecoeoooo popooeeoeeooo QODOUGODOOOQO OOpoooepcooo 9000900092 9 OOOOOOOeGO0OOOOOOOO 8 VREF AGND 0 op EXT THD 9 SHARED MEMORY Vpp oor 0 iim Figure 60 Ball Configuration Standard Model Rev A Page700f72 December 2011 ADSP 21467 ADSP 21469 OUTLINE DIMENSIONS The processors are available in a 19 mm by 19 mm CSP_BGA lead free package
14. Block 0 ROM Reserved Block 0 ROM Reserved Block 0 ROM Reserved Block 0 ROM Reserved 0 0004 0000 0x0004 7FFF 0 0008 0000 0 0008 AAA9 0x0008 0000 0x0008 FFFF 0x0010 0000 0x001 1 FFFF Reserved Reserved Reserved Reserved 0x0004 8000 0x0004 8FFF 0x0008 0 0008 BFFF 0x0009 0000 0x0009 1FFF 0x0012 0000 0x0012 3FFF Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0 0004 9000 0x0004 EFFF 0x0008 C000 0x0009 3FFF 0x0009 2000 0x0009 DFFF 0x0012 4000 0x0013 BFFF Reserved Reserved Reserved Reserved 0x0004 F000 0x0004 FFFF Block 1 ROM Reserved 0x0005 0000 0x0005 7FFF 0x0009 4000 0x0009 FFFF Block 1 ROM Reserved 0x000A 0000 0x000A AAA9 0x0009 E000 0x0009 FFFF Block 1 ROM Reserved 0x000A 0000 0 000 FFFF 0x0013 C000 0x0013 FFFF Block 1 ROM Reserved 0 0014 0000 0x0015 FFFF Reserved Reserved Reserved Reserved 0x0005 8000 0x0005 8FFF 0x000A AAAA 0x000A BFFF 0x000B 0000 0x000B 1FFF 0x0016 0000 0x0016 3FFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0 0005 9000 0x0005 EFFF 0x000A C000 0x000B 3FFF 0 000 2000 0x000B DFFF 0x0016 4000 0x0017 BFFF Reserved Reserved Reserved Reserved 0x0005 F000 0x0005 FFFF 0x000B 4000 0x000B FFFF 0x000B E000 0x000B FFFF 0x0017 C000 0x0017 FFFF Block 2 SRAM Block 2 SRAM Block 2 SRAM Block 2 SRAM 0 0006 0000 0x0006 3FFF 0 000 0000 0 000 5554 0 000 0000 0x000C 7FFF 0x0018 0000 0x0018 FFFF Reserved Reserved Reserved Reserved 0x0006 4000 0x0006 FFF
15. System Inputs Hold After TCK High 18 ns trRSTW TRST Pulse Width 4 X tck ns Switching Characteristics TDO Delay from Low 10 ns tpsys System Outputs Delay After TCK Low tek 2247 ns 1 System Inputs AMI DATA DDR2 DATA CLKCFG1 0 BOOTCFG2 0 RESET DAI DPI FLAG3 0 2 System Outputs AMI ADDR DATA DDR2_ADDR DATA AMI DDR2 CTRL DAI DPI FLAG3 0 EMU trek TCK tstap TMS TDI a toro tssvs tusvs SYSTEM INPUTS tpsys SYSTEM OUTPUTS Figure 44 IEEE 1149 1 JTAG Test Access Port Rev A Page590f72 December 2011 ADSP 21467 ADSP 21469 TEST CONDITIONS OUTPUT DRIVE CURRENTS The ac signal specifications timing parameters appear in Figure 47 and Figure 47 shows typical I V characteristics for the Table 20 on Page 26 through Table 56 on Page 59 These include output drivers of the processor and Table 57 shows the pins output disable time output enable time and capacitive loading associated with each driver The curves represent the current The timing specifications for the SHARC apply for the voltage drive capability of the output drivers as a function of output reference levels in Figure 45 voltage Timing is measured on signals when they cross the level as described in Figure 46 delays in nanoseconds are mea sured between the point that the first signal reaches VygAs and Driver Type Associated Pins E point 2 ee
16. or 40 bit data or combinations of different word sizes up to 5 Mbits All of the memory can be accessed as 16 bit 32 bit 48 bit or 64 bit words A 16 bit floating point storage format is supported that effectively doubles the amount of data that may be stored on chip Conver sion between the 32 bit floating point and 16 bit floating point formats is performed in a single instruction While each memory block can store combinations of code and data accesses are most efficient when one block stores data using the DM bus for transfers and the other block stores instructions and data using the PM bus for transfers December 2011 ADSP 21467 ADSP 21469 Using the DM bus and PM buses with one bus dedicated to a memory block assures single cycle execution with two data transfers In this case the instruction must be available in the cache The memory map in Table 3 displays the internal memory address space of the processors The 48 bit space section describes what this address range looks like to an instruction that retrieves 48 bit memory The 32 bit section describes what this address range looks like to an instruction that retrieves 32 bit memory On Chip Memory Bandwidth The internal memory architecture allows programs to have four accesses at the same time to any of the four blocks assuming there are no block conflicts The total bandwidth is realized using the DMD and PMD buses 2 x 64 bits CCLK speed and the IODO 1 bu
17. x Pp where Tcast case temperature C measured at the top center of the package junction to top of package characterization parameter is the typical value from Table 58 Pp power dissipation Values of are provided for package comparison and PCB design considerations be used for a first order approxi mation of the equation T 6j x Pp where ambient temperature Values are provided for package comparison and PCB design considerations when an external heat sink is required December 2011 ADSP 21467 ADSP 21469 Values of are provided for package comparison and PCB design considerations Note that the thermal characteristics val ues provided in Table 58 are modeled values Table 58 Thermal Characteristics for 324 Lead CSP_BGA Parameter Condition Typical Unit OJA Airflow 0 m s 22 7 C W OJMA Airflow 1 m s 20 4 C W OJMA Airflow 2 m s 19 5 C W 6 6 C W Vg Airflow 0 m s 0 11 C W Airflow 1 m s 0 19 C W Airflow 2 m s 0 24 C W Thermal Diode The processor incorporate thermal diodes to monitor the die temperature The thermal diode of is a grounded collector PNP bipolar junction transistor BJT The THD_P pin is connected to the emitter and the THD_M pin is connected to the base of the transistor These pins can be used by an external tempera ture sensor such as
18. 40 C to 85 5 Mbits 400 MHz 324 Ball BGA BC 324 1 ADSP 21469KBCZ 4 0 to 70 5 Mbits 450 MHz 324 Ball CSP_BGA BC 324 1 1 Z RoHS compliant part Referenced temperature is ambient temperature The ambient temperature is not a specification Please see Operating Conditions on Page 18 for junction temperature Tj specification which is the only temperature specification 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com uo La DEVICES Rev A Page720f72 December 2011
19. ADM 1021A or LM86 or others to read the die temperature of the chip Table 59 Thermal Diode Parameters Transistor Model The technique used by the external temperature sensor is to measure the change in when the thermal diode is operated at two different currents This is shown in the following equation nx s x In N where n multiplication factor close to 1 depending on process variations k Boltzmann s constant T temperature C q charge of the electron N ratio of the two currents The two currents are usually in the range of 10 uA to 300 uA for the common temperature sensor chips available Table 59 contains the thermal diode specifications using the transistor model Note that Measured Ideality Factor already takes into effect variations in beta B Symbol Parameter Min Typ Max Unit Irw Forward Bias Current 10 300 lE Emitter Current 10 300 Transistor Ideality 1 012 1 015 1 017 Ri Series Resistance 0 12 0 2 0 28 See the Engineer to Engineer Note EE 346 Analog Devices does not recommend operation of the thermal diode under reverse bias 100 tested Specified by design characterization 4 5 The series resistance can be used for more accurate readings as needed Rev A Page 64 of 72 The ideality factor nQ represents the deviation from ideal diode behavior as exemplified by the diode equation
20. Ball No Signal Ball No GND G10 GND P05 TRST N15 Vpp INT E09 GND G11 GND P07 VDD A H01 Vpp INT E14 GND G12 GND P09 Vpp DDR2 C05 INT E15 GND G15 GND P11 Vpp DDR2 C12 VDD INT F06 GND H04 GND P13 Vpp 2 D03 INT F07 GND H07 GND V01 Vpp 2 006 INT F08 GND H08 GND V18 Vpp DDR2 D08 INT F09 GND H09 GND R09 Vpp DDR2 D18 VDD INT F10 GND H10 GND IDo G03 VDD_DDR2 E02 VDD INT F11 GND H11 GND ID1 G04 Vpp E04 Vpp INT F12 GND H12 LACK 0 K17 Vpp DDR2 E07 INT F13 GND J01 LACK 1 P17 DDR2 E10 VDD INT G06 GND 307 LCLK 0 218 Vpp DDR2 E11 INT G13 GND 208 LCLK 1 N18 Vpp 2 E17 Vpp INT H05 GND J09 LDATO 0 E18 DDR2 F03 Vpp INT H06 GND J10 LDATO 1 F17 DDR2 F05 Vpp INT H13 GND J11 LDATO 2 F18 DDR2 F15 VDD INT H14 GND J12 LDATO 3 G17 Vpp DDR2 G14 INT J06 GND J14 LDATO 4 G18 Vpp 2 G16 INT J13 GND J17 LDATO 5 H16 Vpp EXT H15 INT K06 GND K05 LDATO 6 H17 Vpp H18 INT K13 GND K07 LDATO 7 J16 Vpp EXT J05 VDD INT 106 GND K08 1 0 18 Vpp EXT J15 INT L13 GND K09 LDAT1_1 L16 Vpp EXT K14 Vpp INT GND K10 LDAT1_2 L17 Vpp EXT 105 INT M13 GND K11 LDAT1_3 L18 Vpp M14 INT N06 GND K12 LDATI 4 M16 Vpp EXT M18 VDD INT N07 GND 107 LDAT1_5 M17 Vpp EXT N05 INT 8 GND 108 LDAT1_6 N16 EXT P06 Vpp INT N09 GND 109 LDAT1_7 P16 EXT P08 Vpp INT N13 GND L10 MLBCLK K03 Vpp EXT P10 Vpp THD N10 GND L11 ML
21. DDR2_CLKx Rising tAH DDR2 ADDR and Control Hold Time Relative to 1 0 0 9 ns DDR2 CLKx Rising order to ensure proper operation of the DDR2 all the DDR2 guidelines have to be strictly followed see Engineer to Engineer Note EE 349 DDR2 CLKx DDR2 CLKx 7 d tt DDR2 ADDR DDR2 CTL tac tpasck gt DDR2_DQSn DDR2_DQSn DDR2_DATA Figure 18 DDR2 SDRAM Controller Input AC Timing Rev A Page320f72 December 2011 ADSP 21467 ADSP 21469 DDR2 SDRAM Write Cycle Timing Table 30 DDR2 SDRAM Write Cycle Timing Vpp ppr2 Nominal 1 8 V 200 MHz 225 MHz Parameter Min Max Min Max Unit Switching Characteristics tck 2 CLKx DDR2 CLKx Period 4 8 4 22 ns tcu DDR2 CLKx High Pulse Width 2 35 2 75 2 05 2 45 ns tc DDR2 CLKx Low Pulse Width 2 35 2 75 2 05 2 45 ns 00552 DDR2 CLKx Rise to DDR2 DOSx Rise Delay 0 4 0 4 0 45 0 45 ns tps Last DDR2 DATA Valid to DDR2_DQSx Delay 0 6 0 5 ns DDR2_DQSx to First DDR2 DATA Invalid Delay 0 65 0 55 ns tpss DDR2 DOSx Falling Edge to DDR2 CLKx Rising Setup 1 95 1 65 ns Time tpsH DDR2_DQSx Falling Edge Hold Time From DDR2 2 05 1 8 ns Rising tposH DDR2 DOS High Pulse Width 2 05 1 65 ns tposL DDR2_DQS Low Pulse Width 2 0 1 65 ns twPRE Write Preamble 0 8 0 8 tck twPsT Write Postamble 0 5 0 5 tck tas DDR2_ADDR and Control Setup Time Relative to 1 85 1 65 ns DDR2 CLKx Rising tAH DDR2_ADDR and Control
22. Data Enable from External Transmit SCLK 2 ns Data Disable from External Transmit SCLK 11 5 ns Data Enable from Internal Transmit SCLK 1 ns Referenced to drive edge DRIVE EDGE DRIVE EDGE DAI 20 1 SCLK EXT 4 DAI 20 1 DATA CHANNEL A B DRIVE EDGE DAI 20 1 SCLK INT tppriN DAI 20 1 DATA CHANNEL Figure 26 Serial Ports Enable and Three State Rev A Page420f72 December 2011 ADSP 21467 ADSP 21469 The SPORTx_TDV_O output signal routing unit becomes active in SPORT multichannel mode During transmit slots enabled with active channel selection registers the SPORTx is asserted for communication with external devices Table 39 Serial Ports TDV Transmit Data Valid Parameter Min Max Unit Switching Characteristics tpRDVEN TDV Assertion Delay from Drive Edge of External Clock 3 ns tpFDVEN TDV Deassertion Delay from Drive Edge of External Clock 8 ns tpRDVIN TDV Assertion Delay from Drive Edge of Internal Clock 0 1 ns tDFDVIN TDV Deassertion Delay from Drive Edge of Internal Clock 2 ns Referenced to drive edge DRIVE EDGE DRIVE EDGE DAI P20 1 SCLK EXT TDVx EMEN 55 lt DAI P20 1 lt pRDvEN DRIVE EDGE DRIVE EDGE DAI P20 1 SCLK INT TDVx DAI 20 1 5 8 prpviN torpvin Figure 27 Serial Ports Transmit Data Valid Internal an
23. Ig x _1 where Is saturation current q electronic charge voltage across the diode Boltzmann Constant and T absolute temperature Kelvin December 2011 ADSP 21467 ADSP 21469 CSP BGA BALL ASSIGNMENT AUTOMOTIVE MODELS Table 60 lists the automotive 5 _ ball assignments by signal Table 60 5 Ball Assignment Alphabetical by Signal Signal Ball No Signal Ball No Signal Ball No Signal Ball No AGND H02 CLK_CFGO 601 2 C17 DPI 4 RO1 AMI_ACK R10 CLK_CFG1 602 DDR2_BA2 B18 5 P01 AMI_ADDRO v16 CLKIN L01 DDR2 CAS C07 2 ADDRO1 016 DAI ROG DDR2_CKE E01 7 ADDRO2 T16 DAI 2 05 DDR2 CLKO A07 DPI P04 ADDRO3 R16 DAI R07 DDR2_CLKO BO7 DPI 9 01 AMI ADDROA V15 DAI 4 R03 DDR2 CLKT A13 DPI P10 02 ADDROS U15 DAI P05 005 DDR2 13 DPI 11 N03 ADDROG T15 DAI T05 DDR2 CSO C01 DPI P12 N04 ADDRO7 R15 DAI P07 V06 DDR2 CST 001 DPI 13 M03 V14 DAI_P08 02 DDR2 CS2 C02 DPI P14 M04 AMI ADDRO9 4 DAI 9 R05 DDR2 53 002 EMU K02 10 T14 DAI_P10 V04 DDR2_DATAO 802 FLAGO ROS AMI_ADDR11 R14 DAI_P11 004 DDR2_DATAO1 A02 FLAG1 V07 ADDR12 V13 DAI P12 T04 DDR2_DATA02 B03 FLAG2 007 ADDR13 U13 DAI P13 006 082 DATAO3 A03 FLAG3 T07 AMI_ADDR14 T13 DAI_P14 002 DDR2_DATA04 05 GND A01
24. PEy unit in the normal word space NW This improves performance since there is no need to explicitly load the complimentary registers as in SISD mode Rev A Page70f72 VISA and ISA Access to External Memory The DDR2 controller also supports VISA code operation which reduces the memory load since the VISA instructions are com pressed Moreover bus fetching is reduced because in the best case one 48 bit fetch contains three valid instructions Code execution from the traditional ISA operation is also supported Note that code execution is only supported from bank 0 regard less of VISA ISA Table 5 shows the address ranges for instruction fetch in each mode Table 5 External Bank 0 Instruction Fetch Access Size Words Address Range ISA NW 4M 0x0020 0000 0x005F FFFF VISA SW 10M 0x0060 0000 FFFF Shared External Memory The processors support connection to common shared external DDR2 memory with other ADSP 2146x processors to create shared external bus processor systems This support includes Distributed on chip arbitration for the shared external bus Fixed and rotating priority bus arbitration e Bus time out logic Bus lock Multiple processors can share the external bus with no addi tional arbitration logic Arbitration logic is included on chip to allow the connection of up to two processors Table 10 on Page 13 provides descriptions of the pins used in multi
25. PMCTL LCLKR PLLBP LINK PORT CLOCK PLLI LCLK CLKIN CLKIN DIVIDER DIVIDER LOOP feu FILTER PMCTL XTAL DDR2CKR CLK CFGx PMCTL PMCTL INDIV PMCTL PLLBP DDR2 CLK 2 x PLLM DIVIDE PCLK BY2 PCLK CLKOUT TEST ONLY CCLK DELAY OF RESETOUT RESETOUT RESET 4096 CLKIN CYCLES CORERST Figure 5 Core Clock and System Clock Relationship to CLKIN Rev A Page230f72 December 2011 ADSP 21467 ADSP 21469 Power Up Sequencing The timing requirements for processor startup are given in Systems sharing these signals on the board must determine Table 18 While no specific power up sequencing is required if there are any issues that need to be addressed based on between VDD Ext and Vpp nt there are some con this behavior siderations that system designs should take into account Note that during power up when the Vpp ir power supply No power supply should be powered up for an extended comes up after Vpp ext a leakage current of the order of three period of time 200 ms before another supply starts to state leakage current pull up pull down may be observed on ramp up any pin even if that pin is an input only for example the RESET If Vpp int power supply comes up after Vpp pin pin until the Vpp has powered up such as RESETOUT and RESET may actually drive momentarily until the Vpp rail has powered up Table 18 Powe
26. RAM RAM INTERNAL MEMORY INTERFACE IODO 32 BIT yy SPEP BUS LINK CORE MLB EL 1 0 EXTERNAL PORT PIN MUX Specifications subject to change without notice No license is granted by implication One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A or otherwise under any patent or patent rights of Analog Devices Trademarks and Tel 781 329 4700 www analog com registered trademarks are the property of their respective companies Fax 781 326 3113 2011 Analog Devices Inc All rights reserved ADSP 21467 ADSP 21469 TABLE OF CONTENTS EE 1 Gonera Description 3 Family Core Architecture 4 Family Peripheral Architecture eee erit 7 i ca 10 Development Too bak x cb 11 Additional 11 Related Signal Chains a 11 Fin Fanchon Description iusscsscectexptc d nee bep Rx HI AR 12 ADU AT I 18 Operating 18 Electrical Chardctetist les auia ep E REFERRE 19 Absolute Maximum Ratings 2 21 REVISION HISTORY 12 11 Rev 0 to Rev A Revised both footnotes in SHARC Family Features 3 Added the ADSP 21467 model with internal ROM 2 Internal Memory Space 6 Automotive Products
27. RD AMI WR and strobe timing parameters only applies to asynchronous access mode 4 Test Conditions on Page 60 for calculation of hold times given capacitive and dc loads 5 Write to Write for both same bank and different bank For Write to Read 3 x for the same bank and different banks AMI_ADDR AMI_MSx lt twwr toaTRWH AMI_DATA AMI_ACK AMI_RD Figure 21 AMI Write Rev A Page360f72 December 2011 ADSP 21467 ADSP 21469 Shared Memory Bus Request Use these specifications for passing bus mastership between processors BRx Table 33 Shared Memory Bus Request Parameter Min Max Unit Timing Requirements tSBRI BRx Setup Before CLKIN High 2 4 ns tHBRI BRx Hold After CLKIN High 5 hs Switching Characteristics tpBRO BRx Delay After CLKIN High 20 fs tHBRO BRx Hold After CLKIN High 1 T CLKIN o 171 X FF o toro BRx OUT BR IN Figure 22 Shared Memory Bus Request Rev A Page370f72 December 2011 ADSP 21467 ADSP 21469 Link Ports Calculation of link receiver data setup and hold relative to link clock is required to determine the maximum allowable skew that can be introduced in the transmission path length differ ence between LDATA and LCLK Setup skew is the maximum Table 34 Link Ports Receive delay that c
28. RISE 0 0 3 y 0 0413x 0 2651 0 0342x 0 309 TYPE C amp D FULL DRIVE FALL 5 0 2 y 0 0058x 0 2113 vo 5 TYPE B DRIVE RISE 0 1 y 0 0153x 0 2131 4 z 0 3 0 5 10 15 20 25 30 35 40 d 53 LOAD CAPACITANCE pF a 5 2 Figure 51 Typical Output Rise Fall Time DDR2 o 2096 to 8096 DRIVE FALL PREX 1 y 0 0152x 0 1882 0 0 25 50 75 100 125 150 175 200 LOAD CAPACITANCE pF Figure 49 Typical Output Rise Fall Time Non DDR2 2096 to 8096 Vpp gxr Rev A Page610f72 December 2011 ADSP 21467 ADSP 21469 RISE AND FALL TIMES ns RISE AND FALL TIMES DELAY ns TYPE C amp D HALF DRIVE FALL y 0 0841x 0 8997 TYPE C amp D HALF DRIVE RISE 3 0 0617 0 7995 25 TYPE C amp D FULL DRIVE FALL 4 0 0421 0 9257 1 5 TYPE C amp D FULL DRIVE RISE 1 y 0 0304x 0 8204 0 5 0 5 10 15 20 25 30 35 40 LOAD CAPACITANCE pF Figure 52 Typical Output Rise Fall Time DDR2 2096 to 8096 gxr Min TYPE A DRIVE FALL y 0 0359 2 9227 TYPE A DRIVE RISE y 0 0256x 3 5876 TYPE B DRIVE RISE y 0 0116x 3 5697 TYPE B DRIVE FALL y 0 0136x 3 1135 0 25 50 75 100 125 150 175 200 LOAD CAPACITANCE pF Figure 53 Typical Output Rise Fall Delay Non DDR gr Min
29. Sync in Transmit Mode 1 0 ns tDFSIR Frame Sync Delay After SCLK Internally Generated Frame Sync in Receive Mode 9 75 ns 2 Frame Sync Hold After SCLK Internally Generated Frame Sync Receive Mode 1 0 ns Transmit Data Delay After SCLK 3 25 ns tupr Transmit Data Hold After SCLK 1 25 ns tscLKIW Transmit or Receive SCLK Width 2 1 2 2 1 5 ns Referenced to the sample edge Referenced to drive edge Rev A Page400f72 December 2011 DRIVE EDGE SAMPLE EDGE DRIVE EDGE tscukiw DAI P20 1 DAI P20 1 SCLK SCLK tuorsiR 20 1 20 1 FS FS DAI P20 1 DAI P20 1 DATA DATA CHANNEL A B CHANNEL DATA TRANSMIT INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE tscukw DAI P20 1 DAI P20 1 SCLK SCLK tuorsE DAI P20 1 DAI P20 1 SCLK FS gt DAI 20 1 20 1 NNEL M NNEL CHANNEL A B CHANNEL DATA RECEIVE INTERNAL CLOCK Rev ADSP 21467 ADSP 21469 DATA RECEIVE EXTERNAL CLOCK SAMPLE EDGE tsc kw gt tspre DATA TRANSMIT EXTERNAL CLOCK SAMPLE EDGE tscukw Figure 25 Serial Ports Page410f72 December 2011 tupnE ADSP 21467 ADSP 21469 Table 38 Serial Ports Enable and Three State Parameter Min Max Unit Switching Characteristics tppTEN
30. in SIMD mode two data values are transferred with each access of memory or the register file Independent Parallel Computation Units Within each processing element is a set of computational units The computational units consist of an arithmetic logic unit ALU multiplier and shifter These units perform all opera tions in a single cycle The three units within each processing element are arranged in parallel maximizing computational throughput Single multifunction instructions execute parallel ALU and multiplier operations In SIMD mode the parallel ALU and multiplier operations occur in both processing ele ments These computation units support IEEE 32 bit single precision floating point 40 bit extended precision floating point and 32 bit fixed point data formats Timer core timer that can generate periodic software interrupts The core timer can be configured to use FLAG3 as a timer expired signal Data Register File general purpose data register file is contained in each pro cessing element The register files transfer data between the computation units and the data buses and store intermediate Rev A Page40f72 results These 10 port 32 register 16 primary 16 secondary register files combined with the processor s enhanced Harvard architecture allow unconstrained data flow between computa tion units and internal memory The registers in PEX are referred to as RO R15 and in PEY as 50 515 Context
31. ipd resistor can be between 31 85 The three state voltage of ipu pads will not reach to full the level at typical conditions the voltage is in the range of 2 3 V to 2 7 V In this table the DDR2 pins SSTL18 compliant All other pins are LVTTL compliant Rev 15 72 December 2011 ADSP 21467 ADSP 21469 Table 10 Pin Descriptions Continued Name Type State During After Reset Description BR2 1 ipu BRT driven low by the processor with ID1 0 IDO 1 2 driven high by the processor with ID1 1 IDO 0 BR2 1 High Z if ID pins are at zero Bus request Used by the processor to arbitrate for bus mastership A processor only drives its own BRx line corresponding to the value of its ID1 0 inputs and monitors all others The processor s own BRx line must not be tied high or low because it is an output Chip ID Determines which bus request 1 is used by the processor ID 001 corresponds to BR1 and ID 010 corresponds to BR2 Use ID 000 or 001 in single processor systems These lines are a system configuration selection that should be hardwired or only changed at reset ID 101 110 and 111 are reserved High Z High Z Test Data Input JTAG Provides serial data for the boundary scan logic Test Data Output JTAG Serial scan output of the boundary scan path Test Mode Select JTAG Used to control the test st
32. pins are SSTL18 compliant All other pins are LVTTL compliant Rev 14 72 December 2011 ADSP 21467 ADSP 21469 Table 10 Pin Descriptions Continued Name Type State During After Reset Description DAI Po DPI Pi44 ipu ipu High Z High Z Digital Applications Interface These pins provide the physical interface to the DAI SRU The DAI SRU configuration registers define the combination of on chip audio centric peripheral inputs or outputs connected to the pin and to the pin s output enable The configuration registers of these peripherals then determine the exact behavior of the pin Any input or output signal present in the DAI SRU may be routed to any of these pins The DAI SRU provides the connection from the serial ports the S PDIF module input data ports 2 and the precision clock generators 4 to the DAI P20 1 pins Digital Peripheral Interface These pins provide the physical interface to the DPI SRU The DPI SRU configuration registers define the combination of on chip peripheral inputs or outputs connected to the pin and to the pin s output enable The configu ration registers of these peripherals then determines the exact behavior of the pin Any input or output signal present in the DPI SRU may be routed to any of these pins The DPI SRU provides the connection from the timers 2 SPls 2 UART 1 flags 12 and general purpose I O 9 to the DPI P
33. so that when there are 64 serial clock peri ods per LRCLK period the LSB of the data will be right justified to the next LRCLK transition Table 46 S PDIF Transmitter Right Justified Mode Figure 35 shows the default I S justified mode LRCLK is low for the left channel and HI for the right channel Data is valid on the rising edge of serial clock The MSB is left justified to an LRCLK transition but with a delay Figure 36 shows the left justified mode LRCLK is high for the left channel and LO for the right channel Data is valid on the rising edge of serial clock The MSB is left justified to an LRCLK transition with no delay Parameter Nominal Unit Timing Requirement trp LRCLK to MSB Delay in Right Justified Mode 16 Bit Word Mode 16 SCLK 18 Bit Word Mode 14 SCLK 20 Bit Word Mode 12 SCLK 24 Bit Word Mode 8 SCLK 20 1 LEFT RIGHT CHANNEL X DAI P20 1 un VVVVV DAI 20 1 ATA Ae TOOG Figure 34 Right Justified Mode Table 47 S PDIF Transmitter 125 Mode Parameter Nominal Unit Timing Requirement tizsp LRCLK to MSB Delay 125 Mode 1 SCLK DAI 20 1 FS DAI P20 1 SCLK 25 DAI 20 1 SDATA LEFT RIGHT CHANNEL XC VVVV VVVV Figure 35 S Justified Mode Rev A Page 50 of 72 December 2011 ADSP 21467 ADSP 21469 Table 48 S PDIF Transmitter Left Justified Mode Parameter Nominal Unit Timing Requir
34. the peripheral clock frequency FIR Accelerator The FIR finite impulse response accelerator consists of a 1024 word coefficient memory a 1024 word deep delay line for the data and four MAC units A controller manages the accelerator The FIR accelerator runs at the peripheral clock frequency Rev A 10 0 72 SYSTEM DESIGN The following sections provide an introduction to system design options and power supply issues Program Booting The internal memory boots at system power up from an 8 bit EPROM via the external port link port an SPI master or an SPI slave Booting is determined by the boot configuration 2 0 pins in Table 8 Table 8 Boot Mode Selection BOOTCFG2 0 Booting Mode 000 SPI Slave Boot 001 SPI Master Boot 010 AMI Boot for 8 bit Flash boot 011 No boot occurs processor executes from internal ROM after reset 100 Link Port 0 Boot 101 Reserved The running reset feature allows programs to perform a reset of the processor core and peripherals without resetting the PLL and DDR2 DRAM controller or performing a boot The function of the RESETOUT pin also acts as the input for initiat ing a running reset For more information see the ADSP 214xx SHARC Processor Hardware Reference Power Supplies The processors have separate power supply connections for the internal Vpp external Vpp xxr and analog A power supplies The internal and analog su
35. 14 1 pins 1 17 0 LCLKO LCLK1 LACKO LACK1 ipd ipd ipd High Z High Z High Z Link Port Data Link Ports 0 1 When configured as a transmitter the port drives both the data lines Link Port Clock Link Ports 0 1 Allows asynchronous data transfers When configured as a transmitter the port drives LCLKx lines An external 25 kO pull down resistor is required for the proper operation of this pin Link Port Acknowledge Link Port 0 1 Provides handshaking When the link ports are configured as a receiver the port drives the LACKx line An external 25 pull down resistor is required for the proper operation of this pin THD P THD M Thermal Diode Anode If unused can be left floating Thermal Diode Cathode If unused can be left floating MLBCLK MLBDAT MLBSIG MLBDO MLBSO in pin mode in 5 pin mode in pin mode in 5 pin mode O T O T High Z High Z High Z High Z Media Local Bus Clock This clock is generated by the MLB controller that is synchro nized to the MOST network and provides the timing for the entire MLB interface 49 152 MHz at FS 48 kHz If unused connect to ground see Table 9 on Page 12 Media Local Bus Data The MLBDAT line is driven by the transmitting MLB device and is received by all other MLB devices including the MLB controller The MLBDAT line carri
36. 16 DDR2_DATA06 06 GND C04 ADDR17 U12 DAI P17 003 DDR2_DATA07 A06 GND C06 AMI ADDR18 T12 DAI P18 DDR2_DATA08 08 GND C08 AMI ADDR19 R12 DAI P19 DDR2_DATA09 A08 GND 005 AMI ADDR20 11 DAI 20 T02 DDR2_DATA10 B09 GND D07 AMI_ADDR21 U11 DDR2_ADDRO D13 DDR2_DATA11 A09 GND 009 ADDR22 T11 DDR2_ADDRO1 C13 DDR2_DATA12 All GND D10 AMI_ADDR23 R11 DDR2_ADDRO2 D14 DDR2_DATA13 B11 GND D17 AMI_DATAO U18 2 ADDRO3 C14 DDR2_DATA14 A12 GND E03 AMI_DATA1 T18 DDR2_ADDR04 B14 DDR2_DATA15 B12 GND E05 AMI_DATA2 R18 DDR2 ADDRO5 A14 DDR2 DMO C03 GND E12 DATA3 P18 DDR2 ADDROG D15 DDR2 C11 GND E13 AMI_DATA4 17 DDR2_ADDRO7 C15 DDR2_DQSO A04 GND E16 AMI_DATA5 U17 DDR2_ADDRO8 B15 DDR2 DQSO 04 GND F01 DATA6 17 DDR2_ADDRO9 A15 DDR2_DQS1 A10 GND F02 AMI_DATA7 R17 DDR2_ADDR10 D16 DDR2_DQS1 B10 GND F04 50 T10 DDR2_ADDR11 C16 DDR2_ODT 01 GND 14 AMI 51 U10 DDR2_ADDR12 B16 DDR2_RAS C09 GND F16 RD 04 DDR2_ADDR13 A16 DDR2 WE C10 GND G05 AMI_WR V10 DDR2_ADDR14 B17 P01 R02 GND G07 CFGO 102 DDR2_ADDR15 A17 DPI 2 001 GND G08 BOOT_CFG1 J03 DDR2_BA0 C18 T01 GND G09 Rev A Page680f72 December 2011 ADSP 21467 ADSP 21469 Table 61 Ball Assignment Alphabetical by Signal Continued Signal Ball No Signal Ball No Signal Ball No Signal Ball No GND G10 GND M10 TRST N15 INT E09 GND G11 GND M11 VDD A H01
37. 324 Lead 0 115 0 110 C CSP_BGA Q 0 C to 70 C Tj Junction Temperature 324 Lead N A N A 40 125 C CSP_BGA 40 to 85 C Specifications subject to change without notice See Figure 3 on Page 11 for an example filter circuit 3 Applies to DDR2 signals 4 If unused see Table 9 on Page 12 Applies to input and bidirectional pins AMI ADDR23 0 AMI DATA7 0 FLAG3 0 DAI BOOTCFGx CLKCFGx RUNRSTIN RESET TMS TDI TRST 6 Applies to input pin CLKIN Rev A 180172 December 2011 ADSP 21467 ADSP 21469 ELECTRICAL CHARACTERISTICS 450 MHz 400 MHz Parameter Description Test Conditions Min Max Min Max Unit Vou High Level Output Min 1 0 mA 124 24 V Voltage VoL Low Level Output Vpp ext Min lo 1 0 mA 0 4 0 4 V Voltage DDR2 High Level Output Vpp Min 13 4 mA 1 4 1 4 V Voltage for DDR2 VoL 2 Low Level Output Vpp DDR Min IOL 13 4 mA 0 29 0 29 V Voltage for DDR2 Tu High Level Input Vpp Max 10 10 Current Vin Vpp Max I 5 Low Level Input Vpp gxr Max Vin 0 V 10 10 Current li pu Low Level Input Vpp Max VN 2 0 V 200 200 Current Pull up lip High Level Input Vpp 200 200 uA Current Pull down Viy Max lozu 8 Thre
38. 467 ADSP 21469 SPI Interface Slave Table 53 SPI Interface Protocol Slave Switching and Timing Specifications Parameter Min Max Unit Timing Requirements tsPICLKS Serial Clock Cycle 4 2 ns tsPiCHS Serial Clock High Period 2 2 ns tsPICLs Serial Clock Low Period 2 2 ns tspsco SPIDS Assertion to First SPICLK Edge CPHASE 0 or CPHASE 1 2xtpcik ns tups Last SPICLK Edge to SPIDS Not Asserted CPHASE 0 2 X ns tsspips Data Input Valid to SPICLK Edge Data Input Setup Time 2 ns 5 1 5 SPICLK Last Sampling Edge to Data Input Not Valid 2 ns tspppw SPIDS Deassertion Pulse Width CPHASE 0 2 X tPCLK ns Switching Characteristics tpsoE SPIDS Assertion to Data Out Active 0 6 8 ns tpsoE SPIDS Assertion to Data Out Active SPI2 0 8 ns tpspHI SPIDS Deassertion to Data High Impedance 0 10 5 ns tpspHi SPIDS Deassertion to Data High Impedance SPI2 0 10 5 ns 2052105 SPICLK Edge to Data Out Valid Data Out Delay Time 9 5 ns tupsPips SPICLK Edge to Data Out Not Valid Data Out Hold Time 2 5 tpsov SPIDS Assertion to Data Out Valid CPHASE 0 5 X ns l The timing for these parameters applies when the SPI is routed through the signal routing unit For more information see the processor hardware reference Serial Peripheral Interface Port chapter SPIDS INPUT 5 tspiciks SPICLK CP 0 CP 1
39. AMI Read Page 35 of 72 December 2011 ADSP 21467 ADSP 21469 AMI Write Use these specifications for asynchronous interfacing to memo ries Note that timing for AMI ACK AMI DATA AMI RD AMI WR and strobe timing parameters only apply to asyn chronous access mode Table 32 Memory Write Parameter Min Max Unit Timing Requirements tDAAK Delay from Address Selects tppg 9 7 W ns tDsAK AMI ACK Delay from AMI WR Low 3 W 6 ns Switching Characteristics tDAWH Address Selects to AMI WR Deasserted 3 1 W ns tpAWL Address Selects to AMI WR Low tppg cik 3 ns tww AMI WR Pulse Width W 1 3 ns tDDWH Data Setup Before AMI_WR High 3 0 W ns tDWHA Address Hold After AMI WR Deasserted H 0 15 ns tDWHD Data Hold After AMI_WR Deasserted H ns tDATRWH Data Disable After AMI WR Deasserted tppg2 1 37 H 2 4 9 ns twwR AMI WR High to AMI WR Low 2 cik 1 5 ns tpDWR Data Disable Before AMI RD Low 21082 6 ns AMI WR Low to Data Enabled tppg 3 5 ns W number of wait states specified AMICTLx register x 2 H number of hold cycles specified in AMICTLx register x tppg2 AMI ACK delay setup System must meet tpAAx for deassertion of AMI low 2 falling edge of AMI is referenced that timing for AMI AMI DATA AMI
40. ANALOG DEVICES SHARC Processor ADSP 21467 ADSP 21469 SUMMARY High performance 32 bit 40 bit floating point processor Available with unique audiocentric peripherals such as the optimized for high performance audio processing digital applications interface DTCP digital transmission Single instruction multiple data SIMD computational content protection protocol serial ports precision clock architecture generators S PDIF transceiver asynchronous sample rate 5 Mbits of on chip RAM 4 Mbits of on chip ROM converters input data port and more Up to 450 MHz operating frequency For complete ordering information see Ordering Guide on Qualified for automotive applications see Automotive Prod Page 72 ucts on Page 72 Code compatible with all other members of the SHARC family SIMD CORE CORE BUS CROSS BAR PMD 64 BIT FLAGx IRQx EPD BUS 64 BIT TMREXP PERIPHERAL BUS 32 BIT 1000 BUS PERIPHERAL BUS CORE PCG TIMER DPI ROUTING PINS DAI ROUTING PINS DPI PERIPHERALS DAI PERIPHERALS Figure 1 Functional Block Diagram SHARC and the SHARC logo are registered trademarks of Analog Devices Inc Rev Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use INTERNAL MEMORY BLOCK 0 BLOCK 1 BLOCK 2 BLOCK 3 RAM ROM RAM ROM
41. BDAT K04 Vpp EXT P12 VREF D04 GND L12 MLBDO L04 Vpp EXT P14 VREF D11 GND L14 MLBSIG 102 EXT P15 XTAL K01 GND M05 MLBSO L03 Vpp EXT 08 07 RESET 01 Vpp EXT T09 GND M08 RESETOUT RUNRSTIN M02 Vpp EXT 009 GND M09 TCK K15 Vpp EXT V09 GND M10 TDI L15 V08 GND M11 TDO M15 Vpp exr BR2 008 GND M12 THD M N12 INT D12 GND N14 THD P N11 Vpp INT E06 GND N17 TMS K16 INT E08 V This pin can be used for shared DDR2 memory between two processors Table 10 on Page 13 for appropriate connections Rev A Page660f72 December 2011 ADSP 21467 ADSP 21469 A1 CORNER INDEX AREA poooeooDooo ppooeoeeoo OOO 6O0000000Q0 oooeocoooococ 9 9 _ Vpp AGND 60 VREF
42. D A AND AGND PINS Figure 3 Analog Power Vpp Filter Circuit modification of memory registers and processor stacks The processor s JTAG interface ensures that the emulator will not affect target system loading or timing For complete information on Analog Devices SHARC DSP Tools product line of JTAG emulator operation see the appro priate Emulator Hardware User s Guide DEVELOPMENT TOOLS The processors are supported with a complete set of CROSS CORE software and hardware development tools including Analog Devices emulators and VisualDSP development environment The same emulator hardware that supports other SHARC processors also fully emulates the ADSP 21467 ADSP 21469 processors EZ KIT Lite Evaluation Board For evaluation of the processors use the EZ KIT Lite board being developed by Analog Devices The board comes with on chip emulation capabilities and is equipped to enable software development Multiple daughter cards are available Designing an Emulator Compatible DSP Board Target The Analog Devices family of emulators are tools that every DSP developer needs to test and debug hardware and software systems Analog Devices has supplied an IEEE 1149 1 JTAG Test Access Port TAP on each JTAG DSP Nonintrusive in circuit emulation is assured by the use of the processor s JTAG interface the emulator does not affect target system loading or timing The emulator uses the TAP to access the internal fe
43. December 2011 ADSP 21467 ADSP 21469 GENERAL DESCRIPTION The ADSP 21467 ADSP 21469 SHARC processors are mem bers ofthe SIMD SHARC family of DSPs that feature Analog Devices Super Harvard Architecture The processors are source code compatible with the ADSP 2126x ADSP 2136x ADSP 2137x and ADSP 2116x DSPs as well as with first generation ADSP 2106x SHARC processors in SISD single instruction single data mode These 32 bit 40 bit floating point processors are optimized for high performance audio applications with their large on chip SRAM multiple internal buses to eliminate I O bottlenecks and an innovative digital applications peripheral interfaces DAI DPI Table 1 shows performance benchmarks for the processor and Table 2 shows the product s features Table 1 Processor Benchmarks Speed Benchmark Algorithm at 450 MHz 1024 Point Complex FFT Radix 4 with Reversal 20 44 us FIR Filter Per 1 11 ns Filter Per Biquad 4 43 ns Matrix Multiply Pipelined x 3 x 3 x 1 10 0 ns Ax 4 x 4x 1 17 78 ns Divide y x 6 67 ns Inverse Square Root 10 0 ns Assumes two files in multichannel SIMD mode Table 2 SHARC Family Features Feature ADSP 21467 ADSP 21469 Maximum Frequency 450 MHz RAM 5 Mbits ROM 4 Mbits N A Audio Decoders in ROM Yes No DTCP Hardware Accelerator No Pulse Width Modulation Yes S PDIF Yes DDR2 Memory Interface Yes DDR2 Memory Bus Wid
44. F 0 000 5555 0 000 FFFF 0 000 8000 0 000 0x0019 0000 0 001 FFFF Block 3 SRAM Block 3 SRAM Block 3 SRAM Block 3 SRAM 0x0007 0000 0x0007 3FFF 0 000 0000 0x000E 5554 0x000E 0000 0x000E 7FFF 0x001C 0000 0x001C FFFF Reserved Reserved Reserved Reserved 0x0007 4000 0x0007 FFFF 0 000 5555 0x0000F FFFF 0 000 8000 0x000F FFFF 0x001D 0000 0x001F FFFF 1 Some processors include a customer definable ROM block ROM addresses on these models not reserved as shown in this table Please contact your Analog Devices sales representative for additional details Rev A Page60f72 December 2011 ADSP 21467 ADSP 21469 FAMILY PERIPHERAL ARCHITECTURE The processors contain a rich set of peripherals that support a wide variety of applications including high quality audio medi cal imaging communications military test equipment 3D graphics speech recognition motor control imaging and other applications External Port The external port interface supports access to the external mem ory through core and DMA accesses The external memory address space is divided into four banks Any bank can be pro grammed as either asynchronous or synchronous memory The external ports are comprised of the following modules An Asynchronous Memory Interface which communicates with SRAM Flash and other devices that meet the stan dard asynchronous SRAM access protocol The AMI supports 2M words of exte
45. Hold Time Relative to 1 0 0 9 ns DDR2_CLKx Rising order to ensure proper operation of the DDR2 all the DDR2 guidelines have to be strictly followed see Engineer to Engineer Note EE 349 2 Write command to first 008 delay WL x tcx tpass DDR2_CLKx DDR2_CLKx DDR2_ADDR DDR2_CTL DDR2_DQSn DDR2_DQSn DDR2_DATA DM Figure 19 DDR2 SDRAM Controller Output AC Timing Rev A Page330f72 December 2011 ADSP 21467 ADSP 21469 AMI Read Use these specifications for asynchronous interfacing to memo ries Note that timing for AMI ACK AMI DATA AMI RD AMI WR and strobe timing parameters only apply to asyn chronous access mode Table 31 Memory Read Parameter Min Max Unit Timing Requirements Address Selects Delay to Data Valid 2 3 W 2 5 4 ns tpRLD AMI RD Low to Data Valid 3 2 ns tsps Data Setup to AMI RD High 2 5 ns tHDRH Data Hold from RD High 5 0 ns tDAAK AMI ACK Delay from Address Selects 6 tppg 9 5 W ns tpsAK ACK Delay from AMI RD W 7 0 ns Switching Characteristics Address Selects Hold After RD High 0 20 ns Address Selects to AMI RD Low 3 8 ns trw AMI_RD Pulse Width W 14 ns tRWR AMI RD High to AMI RD Low HI tppgo 1 ns W number of wait states specified in AMICTLx register x RHC number of Read Hol
46. INPUT tspsco tpspui topspips MISO OUTPUT CPHASE 1 tsspips tuspips MOSI INPUT t tupspips t DDSPIDS DSDHI MISO OUTPUT tosov t CPHASE 0 i SSPIDS 4 gt am 6 INPUT Figure 40 SPI Slave Timing Page550f72 December2011 ADSP 21467 ADSP 21469 Media Local Bus All the numbers given are applicable for all speed modes 1024 FS 512 FS and 256 FS for 3 pin 512 FS and 256 FS for 5 pin unless otherwise specified Please refer to MediaLB specifi cation document rev 3 0 for more details Table 54 MLB Interface 3 Pin Specifications Parameter Min Typ Max Unit 3 Pin Characteristics tMLBCLK MLB Clock Period 1024 FS 20 3 ns 512FS 40 ns 256FS 81 ns tMckL MLBCLK Low Time 1024 FS 6 1 ns 512FS 14 ns 256 FS 30 ns tMckH MLBCLK High Time 1024 FS 9 3 ns 512FS 14 ns 256 FS 30 ns tMCKR MLBCLK Rise Time to 1024 FS 1 ns 512 FS 256 FS 3 ns MLBCLK Fall Time to 1024 FS 1 ns 512 FS 256 FS 3 ns MLBCLK Pulse Width Variation 1024 FS 0 7 ns p p 512 FS 256 FS 2 0 ns p p tpsMCF DAT SIG Input Setup Time 1 ns DAT SIG Input Hold Time 1 ns tMCFDZ DAT SIG Output Time to Three state 0 15 ns tMCDRV DAT SIG Output Data Delay From MLBCLK Rising Edge 8 ns 2 Bus Hold Time 1024 FS 2 ns 512 5 256 FS 4 ns DAT SIG Pin Load 1024 FS 40 pf 512FS 256 FS 60 pf P
47. L y 0 0007x 0 9841 TYPE C HALF DRIVE RISE 0 0032x 1 0622 10 15 20 25 30 35 LOAD CAPACITANCE pF Figure 57 Typical Output Rise Fall Delay DDR Pad C Vpp extr Max Rev Page630f72 ADSP 21467 ADSP 21469 1 4 T D HALF DRIVE TRUE RISE y 0 003x 1 1758 TYPE D HALF DRIVE TRUE FALL TYPE D HALF DRIVE COMP FALL y 0 0047x 1 1884 1 3 1 2 1 1 1 0 TYPE D FULL DRIVE COMP RISE y 0 0007x 1 0964 TYPE D HALF DRIVE COMP RISE y 0 0031x 1 1599 RISE AND FALL DELAY ns YPE D FULL DRIVE TRUE RISE amp FALL TYPE D FULL DRIVE COMP FALL y 0 0008x 1 1074 0 9 10 15 20 25 LOAD CAPACITANCE pF 30 35 Figure 58 Typical Output Rise Fall Delay DDR Pad D Vpp THERMAL CHARACTERISTICS The processors are rated for performance over the temperature range specified in Operating Conditions on Page 18 Table 58 airflow measurements comply with JEDEC standards JESD51 2 and JESD51 6 and the junction to board measure ment complies with JESD51 8 Test board design complies with JEDEC standards JESD51 7 5 BGA The junction to case measurement complies with MIL STD 883 All measurements use a 252 JEDEC test board To determine the junction temperature of the device while on the application PCB use junction temperature Toaset
48. P 21467 ADSP 21469 SPI Interface Master The processor contains two SPI ports Both primary and sec ondary are available through DPI only The timing provided in Table 52 and Table 53 applies to both Table 52 SPIInterface Protocol Master Switching and Timing Specifications Parameter Min Max Unit Timing Requirements tssPIDM Data Input Valid to SPICLK Edge Data Input Setup Time 82 ns tHsPIDM SPICLK Last Sampling Edge to Data Input Not Valid 2 ns Switching Characteristics tsPICLKM Serial Clock Cycle 8x tpcik 2 ns tsPICHM Serial Clock High Period 4 x 2 5 tsPICLM Serial Clock Low Period 4 xtpcik 2 ns tppsPIDM SPICLK Edge to Data Out Valid Data Out Delay Time 2 5 ns tHDSPIDM SPICLK Edge to Data Out Not Valid Data Out Hold Time 4 2 ns tspscim DPI Pin SPI Device Select Low to First SPICLK Edge 4 2 ns tHDsM Last SPICLK Edge to DPI Pin SPI Device Select High 4 2 ns Sequential Transfer Delay 4x tpi 1 DPI OUTPUT tspscim tspicum gt ja lt tspicLkm SPICLK CP 0 1 OUTPUT tupsPipm MOSI OUTPUT tsspipm gt 5 1 MISO INPUT topspipm I tupsPIDM MOSI OUTPUT t t CPHASE 0 SSPIDM HSPIDM MISO INPUT GEES Figure 39 SPI Master Timing Rev A Page540f72 December 2011 ADSP 21
49. ST BYTE FIRST BYTE TRANSMITTED TRANSMITTED lt gt LCLK gt LDAT7 0 OUT LACK IN NOTES The t and t specifications apply only to the LACK falling edge If these specifications met would extend and the dotted LCLK falling edge would not occur as shown The position of the dotted falling edge can be calculated using the t y Specification Min should be used fort acn and Max for t The t and t requirement apply to the falling edge of LCLK only for the first byte transmitted Figure 24 Link Ports Transmit Rev A Page390f72 December 2011 ADSP 21467 ADSP 21469 Serial Ports In slave transmitter mode and master receiver mode the maxi Serial port signals are routed to the DAI P20 1 pins using the mum serial port frequency is 8 To determine whether SRU Therefore the timing specifications provided below are communication is possible between two devices at clock speed valid at the DAI P20 1 pins In Figure 25 either the rising edge n the following specifications must be confirmed 1 frame sync or the falling edge of SCLK external or internal can be used as delay and frame sync setup and hold 2 data delay and data the active sampling edge setup and hold and 3 serial clock SCLK width Table 36 Serial Ports External Clock
50. Switch Many of the processor s registers have secondary registers that can be activated during interrupt servicing for a fast context switch The data registers in the register file the DAG registers and the multiplier result registers all have secondary registers The primary registers are active at reset while the secondary registers are activated by control bits in a mode control register Universal Registers These registers can be used for general purpose tasks The USTAT 4 registers allow easy bit manipulations Set Clear Toggle Test XOR for all system registers control status of the core The data bus exchange register PX permits data to be passed between the 64 bit PM data bus and the 64 bit DM data bus or between the 40 bit register file and the PM DM data buses These registers contain hardware to handle the data width difference Single Cycle Fetch of Instruction and Four Operands The processors feature an enhanced Harvard Architecture in which the data memory DM bus transfers data and the pro gram memory PM bus transfers both instructions and data see Figure 2 With the its separate program and data memory buses and on chip instruction cache the processor can simulta neously fetch four operands two over each data bus and one instruction from the cache all in a single cycle Instruction Cache The processors contain an on chip instruction cache that enables three bus operation for fetching an ins
51. Vpp INT E14 GND G12 GND M12 Vpp DDR2 C05 INT E15 GND G15 GND N14 Vpp DDR2 C12 INT F06 GND H04 GND N17 Vpp 2 D03 Vpp INT F07 GND H07 GND P05 Vpp 2 006 INT F08 GND H08 GND P07 Vpp DDR2 008 INT F09 GND H09 GND P09 VDD_DDR2 D18 VDD INT F10 GND H10 GND P11 Vpp DDR2 E02 VDD INT F11 GND H11 GND P13 Vpp 2 E04 Vpp INT F12 GND H12 GND R09 Vpp DDR2 E07 VDD INT F13 GND 201 GND V01 Vpp DDR2 E10 VDD INT G06 GND 207 GND V18 Vpp DDR2 E11 VDD INT G13 GND J08 GND IDO G03 VDD_DDR2 E17 INT H05 GND J09 GND ID1 G04 Vpp DDR F03 Vpp INT H06 GND J10 LACK 0 K17 Vpp 2 F05 INT H13 GND J11 LACK 1 P17 Vpp DDR2 F15 VDD INT H14 GND J12 LCLK 0 J18 Vpp DDR2 G14 VDD INT J06 GND J14 LCLK 1 N18 Vpp 2 G16 Vpp INT J13 GND J17 LDATO 0 E18 Vpp EXT H15 Vpp INT K06 GND K03 LDATO 1 F17 Vpp EXT H18 INT K13 GND K04 LDATO 2 F18 Vpp EXT J05 VDD INT 106 GND K05 LDATO 3 G17 Vpp EXT J15 VDD INT L13 GND K07 LDATO 4 G18 Vpp EXT K14 Vpp INT GND K08 LDATO 5 H16 Vpp EXT 105 INT M13 GND K09 LDATO 6 H17 Vpp M14 INT N06 GND K10 LDATO 7 J16 Vpp EXT M18 VDD INT N07 GND K11 LDAT1_0 K18 Vpp EXT N05 VDD INT 8 GND K12 1 1 L16 Vpp EXT P06 Vpp INT N09 GND 102 LDAT1_2 L17 Vpp EXT P08 Vpp INT N13 GND 103 LDAT1_3 L18 Vpp EXT P10 Vpp THD N10 GND 104 1 1 4 16 Vpp EXT P12 VREF D04 GND L07 LDAT1_5 M17 VDD_EXT P14 VREF D11 GND L08 LDAT1_6 N16 Vpp EXT P15 XTAL K01 GND 109 LDAT1_7 P16 EXT
52. a tures of the processor allowing the developer to load code set breakpoints observe variables observe memory and examine registers The processor must be halted to send data and commands but once an operation has been completed by the emulator the DSP system is set running at full speed with no impact on system timing To use these emulators the target board must include a header that connects the DSP s JTAG port to the emulator For details on target board design issues including mechanical layout single processor connections signal buffering signal ter mination and emulator pod logic see the EE 68 Analog Devices JTAG Emulation Technical Reference on the Analog Devices website www analog com use site search on EE 68 This document is updated regularly to keep pace with improvements to emulator support Rev A 11 of 72 Evaluation Kit Analog Devices offers a range of EZ KIT Lite evaluation plat forms to use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors platforms and software tools Each EZ KIT Lite includes an evaluation board along with an evaluation suite of the VisualDSP development and debugging environment with the compiler assembler and linker Also included are sample application programs power supply and a USB cable evaluation versions of the software tools are limited for use only with the EZ KIT Lite p
53. an be introduced in LDATA relative to LCLK setup skew min tprpcH 51 Hold skew is the maximum delay that can be introduced in LCLK relative to LDATA hold skew ticLKTWL min Parameter Min Max Unit Timing Requirements tsi pc Data Setup Before LCLK Low 0 5 ns tui pcr Data Hold After LCLK Low 1 5 ns tLCLKIW LCLK Period 6 ns ns ti CLKRWL LCLK Width Low 2 6 ns ti CLKRWH LCLK Width High 2 6 ns Switching Characteristics tpLALC LACK Low Delay After LCLK Low 5 12 ns ILACK goes low with tpr Arc relative to the fall of LCLK after first byte but does not go low if the receiver s link buffer is not about to fill ticukw gt ti cLkRwH LCLK LDAT7 0 LACK OUT Figure 23 Link Ports Receive Table 35 Link Ports Transmit Parameter Min Max Unit Timing Requirements 11 ACH LACK Setup Before LCLK Low 8 5 ns tHLACH LACK Hold After LCLK Low 0 ns Switching Characteristics tpipcH Data Delay After LCLK High 1 ns tHLDCH Data Hold After LCLK High 1 ns tLCLKTWL LCLK Width Low 0 5 X 0 4 0 6 0 41 ns ti CLKTWH LCLK Width High 0 4 x tici k 0 4 0 5 0 4 ns tDLACLK LCLK Low Delay After LACK High 2 8 5 1 1 2 5 ratio For other ratios this specification is 0 5 x 1 Rev A Page380f72 December 2011 ADSP 21467 ADSP 21469 LA
54. ate machine Test Clock JTAG Provides a clock for JTAG boundary scan The TCK signal must be asserted pulsed low after power up or held low for proper operation of the device Test Reset JTAG Resets the test state machine The TRST signal must be asserted pulsed low after power up or held low for proper operation of the processor Emulation Status Must be connected to the ADSP 21467 ADSP 21469 Analog Devices DSP Tools product line of JTAG emulators target board connector only CFG 1 9 CLKIN XTAL Core to CLKIN Ratio Control These pins set the start up clock frequency Note that the operating frequency can be changed by programming the PLL multiplier and divider in the PMCTL register at any time after the core comes out of reset The allowed values are 00 6 1 01 32 1 10 16 1 11 reserved Local Clock In Used in conjunction with XTAL CLKIN is the clock input It configures the processor to use either its internal clock generator or an external clock source Connecting the necessary components to CLKIN and XTAL enables the internal clock generator Connecting the external clock to CLKIN while leaving XTAL unconnected configures the processor to use the external clock source such as an external clock oscillator CLKIN may not be halted changed or operated below the specified frequency Crystal Oscillator Terminal Used in conjunction with CLKIN to drive an external crystal The foll
55. but not tested 12 Applies to all signal pins PGuaranteed but not tested Rev A 190 72 December 2011 ADSP 21467 ADSP 21469 Total Power Dissipation Total power dissipation has two components The ASF is combined with the CCLK frequency and Vpp INT dependent data in Table 14 to calculate this part External power consumption is due to the switching activity of the external pins 1 Internal power consumption 2 External power consumption Internal power consumption also comprises two components 1 1 Static due to leakage current Table 13 shows the static cur Sealing Hector CASI rent consumption Ipp srATIC as a function of junction Activity Scaling Factor ASF temperature Ty and core voltage Idle 0 38 2 Dynamic Ipp pyNAMC due to transistor switching char Low 0 58 acteristics and activity level of the processor The activity High 123 levelis reflected by the Activity Scaling Factor ASF which represents application code running on the processor core Peak 135 and having various levels of peripheral and external port Peak typical 50 50 0 87 activity Table 12 Dynamic current consumption is calcu Peak typical 60 40 0 94 lated by scaling the specific application by the ASF and Peak typical 70 30 1 00 using baseline dynamic current consumption as a 1 5 reference See Estimating Power for SHARC Processors EE 348 for more information on th
56. cember 2011 ADSP 21467 ADSP 21469 50 14 amp D FULL DRIVE 40 12 TYPE FALL 3 13 V 125 0 0746x 0 514 20 10 TYPE A RISE 2 y 0 0572 0 5571 10 2 8 0 E J TYPE B FALL a 6 y 0 0278x 0 3138 gt m 2 9 20 4 5 a 2 30 7 y 125 C TEE RISE TYPE C amp D FULL DRIVE 2 0 0258x 0 3684 40 50 0 0 0 5 1 0 1 5 0 25 50 75 100 125 150 175 200 SWEEP VOLTAGE V LOAD CAPACITANCE pF Figure 48 Output Buffer Characteristics Worst Case DDR2 Figure 50 Typical Output Rise Fall Time Non DDR2 CAPACITIVE LOADING 2096 to 80 gxr Min Output delays and holds are based on standard capacitive loads 30 pF on all pins see Table 57 Figure 53 through Figure 58 1 0 show graphically how output delays and holds vary with load 0 9 capacitance The graphs of Figure 49 through Figure 58 may not TYPE C amp D HALF DRIVE FALL 0 0217 0 26 be linear outside the ranges shown for Typical Output Delay vs 0 8 1 Load Capacitance and Typical Output Rise Time 20 to 80 V Mi Load C 0 7 D HALF DRIVE RISE Min vs Load Capacitance 05 E d 7 d 05 TYPE C amp D FULL DRIVE RISE 2 04 y 0 0061x 0 207 lt s e TYPE A DRIVE FALL TYPE A DRIVE
57. ces Each bank can be independently programmed with dif ferent timing parameters enabling connection to a wide variety of memory devices including SRAM Flash and EPROM as well as I O devices that interface with standard memory control lines Bank 0 occupies a 2M word window and banks 1 2 and 3 occupy a 4M word window in the processor s address space but if not fully populated these windows are not made contiguous by the memory controller logic External Port Throughput The throughput for the external port based on a 400 MHz clock is 66M bytes s for the AMI and 800M bytes s for DDR2 Link Ports Two 8 bit wide link ports can connect to the link ports of other DSPs or peripherals Link ports are bidirectional ports having eight data lines an acknowledge line and a clock line Link ports can operate at a maximum frequency of 166 MHz MediaLB The automotive model has a MLB interface which allows the processors to function as a media local bus device It includes support for both 3 pin and 5 pin media local bus protocols It supports speeds up to 1024 FS 49 25M bits sec FS 48 1 kHz and up to 31 logical channels with up to 124 bytes of data per media local bus frame The MLB interface supports MOST25 and 50 data rates The isochronous mode of transfer is not supported Pulse Width Modulation The PWM module is a flexible programmable PWM waveform generator that can be programmed to generate the required switchi
58. cription INT P Internal Power Vpp EXT P External Power A P Analog Power for PLL THD P Thermal Diode Power DDR2 Interface Power VREF P DDR2 Input Voltage Reference GND G Ground AGND G Analog Ground Applies to DDR2 signals Rev A Page17of72 December 2011 ADSP 21467 ADSP 21469 SPECIFICATIONS OPERATING CONDITIONS 450 MHz 400 MHz Parameter Description Min Nom Max Min Nom Max Unit INT Internal Core Supply Voltage 1 05 1 1 1 15 1 0 1 05 1 1 V EXT External 1 Supply Voltage 3 13 3 3 3 47 3 13 3 3 47 V Vpp 2 Analog Power Supply Voltage 1 05 1 1 1 15 1 0 1 05 1 1 V Vpp pp DDR2 Controller Supply Voltage 1 7 1 8 1 9 1 7 1 8 1 9 V THD Thermal Diode Supply Voltage 3 13 3 3 3 47 3 13 3 3 3 47 V VREF DDR2 Reference Voltage 0 84 0 9 0 96 0 84 0 9 0 96 V High Level Input Voltage 2 0 2 0 V Vpp Vi Low Level Input Voltage 0 8 0 8 V Vpp Min High Level Input Voltage 2 0 2 0 V Vpp Max VIL_CLKIN Low Level Input Voltage 1 32 1 32 V Vpp Min 2 DC DC Low Level Input Voltage Veer 0 125 0 125 V 2 DC DC High Level Input Voltage 0 125 Veer 0 125 V Low Level Input Voltage Vnrr 0 25 Veer 0 25 V ppR2 AC High Level Input Voltage 0 25 0 25 V Junction Temperature
59. d Cycles specified AMICTLx register x tDDR2 Where PREDIS 0 HI RHC Read to Read from same bank HI RHC IC Read to Read from different bank HI RHC Max IC 4 Read to Write from same or different bank Where PREDIS 1 HI RHC Max IC 4 x tppg2 1 Read to Write from same different bank RHC 3 x tDDR2 Read to Read from same bank HI RHC Max IC 3 x tppg2 Read to Read from different bank IC number of idle cycles specified in AMICTLx register x tppg2 number of hold cycles specified in AMICTLx register x tDDR2 Data delay setup System must meet tpap tsps 2 falling edge of AMI is referenced The maximum limit of timing requirement values for tpAp and tprip parameters are applicable for the case where is always high Note that timing for AMI ACK AMI DATA AMI RD AMI WR and strobe timing parameters only apply to asynchronous access mode hold User must meet in asynchronous access mode See Test Conditions on Page 60 for the calculation of hold times given capacitive and dc loads AMI delay setup User must meet tp Ax tpsax for deassertion of AMI low Rev Page340f72 December 2011 ADDR AMI MSx AMI DATA ACK AMI WR ADSP 21467 ADSP 21469 Rev Figure 20
60. d External Clock Rev A Page430f72 December 2011 ADSP 21467 ADSP 21469 Table 40 Serial Ports External Late Frame Sync Parameter Min Max Unit Switching Characteristics tppTLEse Data Delay from Late External Transmit Frame Sync or External 7 75 Receive Frame Sync with MCE 1 0 ns tppTeNFs Data Enable for MCE 1 MFD 0 0 5 ns 1 The tpprLESE and tppTENFS parameters apply to left justified as well as DSP serial mode and MCE 1 0 EXTERNAL RECEIVE FS WITH 1 0 DRIVE SAMPLE DRIVE 20 1 SCLK tursen tsrsen 20 1 FS tpprENrs t 20 1 DATA CHANNEL 1ST BIT lt gt tpprirsE LATE EXTERNAL TRANSMIT FS DRIVE SAMPLE DRIVE DAI P20 1 SCLK tursen tsrsen DAI 20 1 FS tpprEn topTENFs t 20 1 DATA CHANNEL 1ST BIT AIB t tpprirsE Figure 28 External Late Frame Sync Rev A Page440f72 December 2011 2ND BIT 2ND BIT ADSP 21467 ADSP 21469 Input Data Port IDP The timing requirements for the IDP are given in Table 41 IDP signals are routed to the DAI P20 1 pins using the SRU There fore the timing specifications provided below are valid at the DAI P20 1 pins Table 41 Input Data Port IDP Parameter Min Max Unit Timing Re
61. e On chip SRAM 5 Mbits e On chip mask programmable ROM 4 Mbits test access port for emulation and boundary scan The JTAG provides software debug through user break points which allows flexible exception handling Figure 1 on Page 1 also shows the peripheral clock domain also known as the I O processor which contains the following features IODO peripheral and IODI external port DMA buses for 32 bit data transfers Peripheral and external port buses for core connection External port with an AMI and DDR2 controller 4units for PWM control 1 MTM unit for internal to internal memory transfers Digital applications interface that includes four precision clock generators PCG an input data port IDP for serial and parallel interconnect an S PDIF receiver transmitter four asynchronous sample rate converters eight serial ports a flexible signal routing unit DAI SRU Digital peripheral interface that includes two timers a 2 wire interface one UART two serial peripheral interfaces SPI 2 precision clock generators PCG and a flexible signal routing unit DPI SRU December 2011 ADSP 21467 ADSP 21469 As shown in Figure 1 on Page 1 the processor uses two compu tational units to deliver a significant performance increase over the previous SHARC processors on a range of DSP algorithms With its SIMD computational hardware the processors can perform 2 7 GFLOPS ru
62. e State Leakage Vpp _ Max 10 10 Current Vin Vpp loz Three State Leakage Vpp_ext Vpp_ppr Max 10 10 Current Vi 20V lozi pu Three State Leakage Vpp Vy 0 V 200 200 Current Pull up lozHPD Three State Leakage Vpp gxr 200 200 Current Pull down Vpp_ext IppiNTvp 12 Supply Current gt 0 MHz Table 13 Table 13 mA Internal Table 14 x ASF Table 14 x ASF Ipp Supply Current Vpp A 10 10 mA Analog 13 Input Capacitance 25 C 5 5 Specifications subject to change without notice Applies to output and bidirectional pins AMI ADDR23 0 AMI DATA7 0 AMI RD AMI WR FLAG3 0 DAI EMU TDO 3See Output Drive Currents on Page 60 for typical drive current capabilities 4 Applies to input pins CLKCFGx RESET CLKIN Applies to input pins with internal pull ups TRST TMS TDI 6 Applies to input pins with internal pull downs MLBCLK 7 Applies to three statable pins all DDR2 pins Applies to three statable pins with pull ups EMU Applies to three statable pins with pull downs MLBDAT MLBSIG MLBDO MLBSO LDATO07 0 LDAT17 0 LCLK0 LCLK1 LACKO LACK1 0See Engineer to Engineer Note EE 348 Estimating Power Dissipation for ADSP 2146x SHARC Processors for further information Characterized
63. e explanation of the power vectors specific to the ASF table Ratio of continuous instruction loop core to DDR2 control code reads writes Table 13 Ipp static mA int 0 95 1 0 V 1 05 V 1 10V 1 15V 45 72 91 110 140 167 35 79 99 119 149 181 25 89 109 131 163 198 15 101 122 145 182 220 5 115 140 166 206 249 5 134 162 192 237 284 15 158 189 223 273 326 25 186 222 260 318 377 35 218 259 302 367 434 45 258 305 354 428 503 55 305 359 413 497 582 65 360 421 484 578 675 75 424 496 566 674 781 85 502 580 660 783 904 95 586 683 768 912 1048 105 692 794 896 1054 1212 115 806 921 1036 1220 1394 125 939 1070 1198 1404 1601 Valid temperature and voltage ranges are model specific See Operating Conditions on Page 18 Rev A Page200f72 December 2011 ADSP 21467 ADSP 21469 Table 14 Baseline Dynamic Current in CCLK Domain mA with ASF 1 0 Voltage int MHz 0 95V 1 0V 1 05 V 1 10V 1 15 100 78 82 86 91 98 150 115 121 130 136 142 200 150 159 169 177 188 250 186 197 208 219 231 300 222 236 249 261 276 350 259 275 288 304 319 400 293 309 328 344 361 450 N A N A 366 385 406 The values not guaranteed as standalone maximum specifications They must be combined with static current per the equations of Electrical Characteristics on Page 19
64. e300f72 December 2011 ADSP 21467 ADSP 21469 Flags The timing specifications provided below apply to AMI ADDR23 0 and AMI 7 0 when configured as FLAGS See Table 10 on Page 13 for more information on flag use Table 28 Flags Parameter Min Max Unit Timing Requirement tripw DPI P14 1 AMI ADDR23 0 7 0 FLAG3 0 IN Pulse Width 2 3 ns Switching Characteristic teopw DPI P14 1 AMI_ADDR23 0 AMI_DATA7 0 FLAG3 0 OUT Pulse Width 2 3 ns FLAG INPUTS FLAG OUTPUTS tropw gt Figure 17 Flags Rev A Page310f72 December 2011 ADSP 21467 ADSP 21469 DDR2 SDRAM Read Cycle Timing Table 29 DDR2 SDRAM Read Cycle Timing Vpp ppr2 Nominal 1 8 V 200 MHz 225 MHz Parameter Min Max Min Max Unit Timing Requirements tac Access Window of DDR2_DATA to 1 0 1 5 1 0 1 5 ns DDR2 CLKx DDR2 CLKx tposck Access Window of DDR2_DQSx DDR2_DQSxto 1 0 1 5 1 0 1 5 ns DDR2 CLKx DDR2 CLKx tposo DQS DATA skew for DDR2 DQSx and Associated 0 450 0 450 ns DDR2 DATA signals toH DDR2 DATA Hold Time From 1 9 1 71 ns DDR2_DQSx DDR2_DQSx Read Preamble 0 6 0 6 tck trpst Read Postamble 0 25 0 25 tck Switching Characteristics tck DDR2 CLKx DDR2 CLKx Period 4 8 4 22 ns tcu DDR2 CLKx High Pulse Width 2 35 2 75 2 05 2 45 ns DDR2 CLKx Low Pulse Width 2 35 2 75 2 05 2 45 ns tas DDR2_ADDR and Control Setup Time Relative to 1 85 1 65 ns
65. efault setting on this pin is reset out This pin also RUNRSTIN has a second function as RUNRSTIN which is enabled by setting bit 0 ofthe RUNRSTCTL register For more information see the ADSP 214xx SHARC Processor Hardware Reference BOOT Boot Configuration Select These pins select the boot mode for the processor The BOOT CFG pins must be valid before RESET hardware and software is de asserted The following symbols appear in the Type column of Table 10 A asynchronous input output S synchronous A D active drive O D open drain and T three state internal pull down resistor ipu internal pull up resistor The internal pull up ipu and internal pull down ipd resistors are designed to hold the internal path from the pins at the expected logic levels To pull up or pull down the external pads to the expected logic levels use external resistors Internal pull up pull down resistors cannot be enabled disabled and the value of these resistors cannot be programmed The range of an ipu resistor can be between 26 63 The range of an ipd resistor be between 31 85 The three state voltage of ipu pads will not reach to full the Vpp level at typical conditions the voltage is in the range of 2 3 V to 2 7 V In this table the DDR2 pins SSTL18 compliant All other pins are LVTTL compliant Table 11 Pin List Power and Ground Name Type Des
66. ement LRCLK to MSB Delay in Left Justified Mode 0 SCLK P20 1 LEFT RIGHT CHANNEL FS DAI 20 1 SCLK 20 1 SDATA Figure 36 Left Justified Mode S PDIF Transmitter Input Data Timing The timing requirements for the S PDIF transmitter are given in Table 49 Input signals are routed to the DAI P20 1 pins using the SRU Therefore the timing specifications provided below are valid at the DAI P20 1 pins Table 49 S PDIF Transmitter Input Data Timing Parameter Min Max Unit Timing Requirements Frame Sync Setup Before Serial Clock Rising Edge 3 ns tsiurs Frame Sync Hold After Serial Clock Rising Edge 3 ns tsisp Data Setup Before Serial Clock Rising Edge 3 ns Data Hold After Serial Clock Rising Edge 3 ns sITXCLKW Transmit Clock Width 9 ns tsiTXCLK Transmit Clock Period 20 ns tsiscLKW Clock Width 36 ns tsiscLK Clock Period 80 ns The serial clock data and frame sync signals can come from any of the DAI pins The serial clock and frame sync signals can also come via PCG SPORTs The PCG s input can be either CLKIN or any of the DAI pins Rev A Page510f72 December 2011 ADSP 21467 ADSP 21469 SAMPLE EDGE tsitxcLkw tsitxcLk 20 1 TxCLK tsiscLK tsiscLkw DAI P20 1 SCLK tsisrs gt tsiurs DAI P20 1 FS DAI P20 1 SDATA Figure 37 S PDIF Transmitter Input Timing Oversampl
67. es the actual data In 5 pin MLB mode this pin is an input only If unused connect to ground see Table 9 on Page 12 Media Local Bus Signal This is a multiplexed signal which carries the channel address generated by the MLB controller as well as the command and RxStatus bytes from MLB devices In 5 pin mode this pin is an input only If unused connect to ground see Table 9 on Page 12 Media Local Bus Data Output in 5 pin mode This pin is used only in 5 pin MLB mode This serves as the output data pin in 5 pin mode If unused connect to ground see Table 9 on Page 12 Media Local Bus Signal Output in 5 pin mode This pin is used only in 5 pin MLB mode and serves as the output signal pin in 5 pin mode If unused connect to ground see Table 9 on Page 12 The following symbols appear in the Type column of Table 10 A asynchronous input output S synchronous A D active drive O D open drain and T three state ipd internal pull down resistor ipu internal pull up resistor The internal pull up ipu and internal pull down ipd resistors are designed to hold the internal path from the pins at the expected logic levels To pull up or pull down the external pads to the expected logic levels use external resistors Internal pull up pull down resistors cannot be enabled disabled and the value of these resistors cannot be programmed The range of an ipu resistor can be between 26 63 The range of an
68. f 16 18 20 or 24 bits The serial data clock and frame sync inputs to the S PDIF receiver transmitter are routed through the signal routing unit SRU They can come from a variety of sources such as the SPORTs external pins and the precision clock generators PCGs and are controlled by the SRU control registers December 2011 ADSP 21467 ADSP 21469 Asynchronous Sample Rate Converter The asynchronous sample rate converter ASRC contains four ASRC blocks is the same core as that used in the AD1896 192 kHz stereo asynchronous sample rate converter and provides up to 128 dB SNR The ASRC block is used to perform synchro nous or asynchronous sample rate conversion across independent stereo channels without using internal processor resources The four SRC blocks can also be configured to oper ate together to convert multichannel audio data without phase mismatches Finally the ASRC can be used to clean up audio data from jittery clock sources such as the S PDIF receiver Input Data Port The IDP provides up to eight serial input channels each with its own clock frame sync and data inputs The eight channels are automatically multiplexed into a single 32 bit by eight deep FIFO Data is always formatted as a 64 bit frame and divided into two 32 bit words The serial protocol is designed to receive audio channels in I S left justified sample pair or right justified mode One frame sync cycle indicates one 64 bit left r
69. g applied to which mode registers including MR EMR EMR 2 and EMR 3 are loaded during the LOAD MODE REGISTER command DDR2 CAS O T High Z DDR2 Column Address Strobe Connect to DDR2 CAS in conjunction with other driven high DDR2 command pins defines the operation for the DDR2 to perform DDR2 CKE O T High Z DDR2ClockEnable Output to DDR2 Active high signal Connectto DDR2 CKE signal driven low DDR2_CS3 9 O T High Z DDR2 Chip Select All commands are masked when DDR2_CS3 9 is driven high driven high DDR2_CS3 9 are decoded memory address lines Each 0082 CS3 line selects the corresponding external bank DDR2_DATA15 9 _ 1 O T High Z DDR2 Data In Out Connect to corresponding DDR2 DATA pins DDR2 DM O T High Z DDR2 Input Data Mask Mask for the DDR2 write data if driven high Sampled on both driven high edges of DDR2 DOS at DDR2 side DMO corresponds to DDR2 DATA 7 0 and DM1 corresponds to DDR2_DATA15 8 DDR2_DQS 9 High Z Data Strobe Output with Write Data Input with Read Data 0050 corresponds to DDR2 051 0 Differential DDR2 DATA 7 0 and DQS1 corresponds to DDR2 DATA 15 8 Based on software control via the DDR2CTL3 register this pin can be single ended or differential DDR2 RAS O T High Z DDR2 Row Address Strobe Connect to DDR2 RAS pin in conjunction with other driven high DDR2 command pins defines the operation for the DDR2 to perform DDR2 WE O T High Z DDR2 Write Enable Connect to DDR2 WE p
70. generate periodic interrupts and be independently set to operate in one of three modes Pulse waveform generation mode e Pulse width count capture mode External event watchdog mode The core timer can be configured to use FLAGS as a timer expired signal and each general purpose timer has one bidirec tional pin and four registers that implement its mode of operation single control and status register enables or dis ables both general purpose timers independently 2 Wire Interface Port TWI The TWIis a bidirectional 2 wire serial bus used to move 8 bit data while maintaining compliance with the bus protocol The TWI master incorporates the following features 7 bit addressing Simultaneous master and slave operation on multiple device systems with support for multi master data arbitration Digital filtering and timed event processing 100 kbps and 400 kbps data rates Low interrupt rate Processor Features Automotive versions of the I O processor provide 67 channels of DMA while standard versions provide 36 channels of DMA as well as an extensive set of peripherals that are described in the following sections December 2011 ADSP 21467 ADSP 21469 DMA Controller The DMA controller allows data transfers without processor intervention The DMA controller operates independently and invisibly to the processor core allowing DMA operations to occur while the core is simultaneously execu
71. haracteristics to ensure that any timing requirement of a device connected to the processor such as memory is satisfied In the following sections Timing Requirements apply to signals that are controlled by circuitry external to the processor such as the data input for a read operation Timing requirements guar antee that the processor operates correctly with other devices Core Clock Requirements The processor s internal clock a multiple of CLKIN provides the clock signal for timing internal memory processor core and serial ports During reset program the ratio between the proces sor s internal clock frequency and external CLKIN clock frequency with the CFGI 0 pins The processor s internal clock switches at higher frequencies than the system input clock CLKIN To generate the internal clock the processor uses an internal phase locked loop PLL see Figure 5 This PLL based clocking minimizes the skew between the system clock CLKIN signal and the processor s internal clock Rev A Page 22 of 72 Voltage Controlled Oscillator VCO In application designs the PLL multiplier value should be selected in such a way that the VCO frequency never exceeds fyco specified in Table 19 The product of CLKIN and must never exceed 1 2 of fyco max in Table 19 if the input divider is not enabled INDIV 0 The product of CLKIN and must never exceed fyco max in Table 19 if the input divider is e
72. ight pair but data is sent to the FIFO as 32 bit words that is one half ofa frame at a time The processors support 24 and 32 bit 125 24 and 32 bit left justified and 24 20 18 and 16 bit right justified formats Precision Clock Generators The precision clock generators PCG consist of four units A B C and D each of which generates a pair of signals clock and frame sync derived from a clock input signal The units are identical in functionality and operate independently of each other The two signals generated by each unit are normally used as a serial bit clock frame sync pair Digital Peripheral Interface DPI The digital peripheral interface provides connections to two serial peripheral interface SPI ports one universal asynchro nous receiver transmitter UART 12 flags a 2 wire interface TWI and two general purpose timers The DPI includes the peripherals described in the following sections Serial Peripheral Interface The processors contain two serial peripheral interface ports SPI The SPI is an industry standard synchronous serial link enabling the SPI compatible port to communicate with other SPI compatible devices The SPI consists of two data pins one device select pin and one clock pin It is a full duplex synchronous serial interface supporting both master and slave modes The SPI port can operate in a multimaster environment by interfacing with up to four other SPI compatible devices ei
73. in in conjunction with other DDR2 driven high command pins defines the operation for the DDR2 to perform DDR2 CLKO O T High Z DDR2 Memory Clocks Two differential outputs available via software control DDR2 CLKO Differential driven low DDR2CTLO register Free running minimum frequency not guaranteed during reset DDR2_CLK1 DDR2_CLK1 DDR2_ODT O T High Z DDR2 On Die Termination ODT pin when driven high along with other require driven low ments enables the DDR2 termination resistances ODT is enabled disabled regardless of read or write commands The following symbols appear in the Type column of Table 10 A asynchronous input O output S synchronous A D active drive O D open drain and T three state ipd internal pull down resistor ipu internal pull up resistor The internal pull up ipu and internal pull down ipd resistors are designed to hold the internal path from the pins at the expected logic levels To pull up or pull down the external pads to the expected logic levels use external resistors Internal pull up pull down resistors cannot be enabled disabled and the value of these resistors cannot be programmed The range of an ipu resistor can be between 26 63 The range of an ipd resistor be between 31 85 The three state voltage of ipu pads will not reach to full the Vpp level at typical conditions the voltage is in the range of 2 3 V to 2 7 V In this table the DDR2
74. in EMIF mode and FLAG 0 3 pins are in FLAGS mode default Unused AMI pins can be left unconnected Memory Acknowledge External devices can deassert AMI low to add wait states to an external memory access is used by devices memory controllers or other peripherals to hold off completion of an external memory access Unused AMI pins can be left unconnected Memory Select Lines 0 1 These lines are asserted low as chip selects for the corre sponding banks of external memory on the AMI interface The 51 lines are decoded memory address lines that change at the same time as the other address lines When no external memory access is occurring the MS o lines are inactive they are active however when a conditional memory access instruction is executed whether or not the condition is true Unused AMI pins can be left unconnected The MS1 pin can be used in EPORT FLASH boot mode For more information see the ADSP 214xx SHARC Processor Hardware Reference AMIPortRead Enable RD isasserted wheneverthe processor reads a word from external memory External Port Write Enable AMI WR is asserted when the processor writes a word to external memory FLAG 1 FLAG 2 IRO2 AMI MS2 FLAG 3 TMREXP AMI MS3 FLAGIO IROO IROT ipu ipu ipu ipu FLAG O INPUT FLAG 1 INPUT FLAG 2 INPUT FLAG 3 INPUT FLAGO Interrupt Requesto FLAG1 Interru
75. ing Clock HFCLK Switching Characteristics The S PDIF transmitter has an oversampling clock This HFCLK input is divided down to generate the biphase clock Table 50 Oversampling Clock HFCLK Switching Characteristics Parameter Max Unit HFCLK Frequency for HFCLK 384 x Frame Sync Oversampling Ratio x Frame Sync lt 1 MHz HFCLK Frequency for HFCLK 256 x Frame Sync 49 2 MHz Frame Rate FS 192 0 kHz Rev A Page520f72 December 2011 ADSP 21467 ADSP 21469 S PDIF Receiver The following section describes timing as it relates to the S PDIF receiver Internal Digital PLL Mode In the internal digital phase locked loop mode the internal PLL digital PLL generates the 512 x FS clock Table 51 S PDIF Receiver Internal Digital PLL Mode Timing Parameter Min Max Unit Switching Characteristics tprsi LRCLK Delay After Serial Clock 5 ns tHOESI LRCLK Hold After Serial Clock 2 ns tppri Transmit Data Delay After Serial Clock 5 ns Transmit Data Hold After Serial Clock 2 ns Transmit Serial Clock Width 8 2 ns Serial clock frequency is 64 x Frame Sync where FS the frequency of LRCLK DRIVE EDGE SAMPLE EDGE pe tscukw 20 1 SCLK lt lt ts thors DAI P20 1 FS DAI P20 1 DATA CHANNEL AIB Figure 38 S PDIF Receiver Internal Digital PLL Mode Timing Rev A Page530f72 December 2011 ADS
76. ing Guide VVVVVV X Assembly Lot Code n n Silicon Revision RoHS Compliant Designation yyww Date Code Non automotive only For branding information specific to automotive products contact Analog Devices Inc Rev A Page210f72 December 2011 ADSP 21467 ADSP 21469 ESD SENSITIVITY ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality TIMING SPECIFICATIONS Use the exact timing information given Do not attempt to derive parameters from the addition or subtraction of others While addition or subtraction would yield meaningful results for an individual device the values given in this data sheet reflect statistical variations and worst cases Consequently it is not meaningful to add parameters to derive longer times See Figure 46 on Page 60 under Test Conditions for voltage refer ence levels In the following sections Switching Characteristics specify how the processor changes its signals Circuitry external to the pro cessor must be designed for compatibility with these signal characteristics Switching characteristics describe what the pro cessor will do in a given circumstance Use switching c
77. l operations for concise programming For example the processor can conditionally execute a multiply an add and a subtract in both processing elements while branching and fetch ing up to four 32 bit values from memory all in a single instruction Variable Instruction Set Architecture VISA In addition to supporting the standard 48 bit instructions from previous SHARC processors the processors support new instructions of 16 and 32 bits This feature called Variable Instruction Set Architecture VISA drops redundant unused bits within the 48 bit instruction to create more efficient and compact code The program sequencer supports fetching these 16 bit and 32 bit instructions from both internal and external DDR2 memory Source modules need to be built using the VISA option in order to allow code generation tools to create these more efficient opcodes Rev A Page50f72 On Chip Memory The processors contain 5 Mbits of internal RAM Each block can be configured for different combinations of code and data storage see Table 4 Each memory block supports single cycle independent accesses by the core processor and I O processor The memory architecture in combination with its separate on chip buses allows two data transfers from the core and one from the I O processor in a single cycle The processor s SRAM can be configured as a maximum of 160k words of 32 bit data 320k words of 16 bit data 106 7k words of 48 bit instructions
78. nabled INDIV 1 The VCO frequency is calculated as follows fvco 2 x x finput 2 x x PLLD where fvco VCO output PLLM Multiplier value programmed in the PMCTL register During reset the PLLM value is derived from the ratio selected using the CLK pins in hardware PLLD Divider value 2 4 8 or 16 based on the PLLD value programmed on the PMCTL register During reset this value is 2 finput input frequency to the PLL finpur CLKIN when the input divider is disabled CLKIN 2 when the input divider is enabled Note the definitions ofthe clock periods that are a function of CLKIN and the appropriate ratio control shown in and Table 17 All of the timing specifications for the peripherals defined in relation to See the peripheral specific section for each peripheral s timing information Table 17 Clock Periods Timing Requirements Description tck CLKIN Clock Period tccik Processor Core Clock Period Peripheral Clock Period 2 x Figure 5 shows core to CLKIN relationships with external oscil lator or crystal The shaded divider multiplier blocks denote where clock ratios can be set through hardware or software using the power management control register PMCTL For more information see the ADSP 214xx SHARC Processor Hard ware Reference December 2011 ADSP 21467 ADSP 21469 PMCTL
79. ng patterns for various applications related to motor and engine control or audio power control The PWM generator can generate either center aligned or edge aligned PWM waveforms In addition it can generate complementary signals on two outputs in paired mode or independent signals in non paired mode applicable to a single group of four PWM waveforms The PWM generator is capable of operating in two distinct modes while generating center aligned PWM wave forms single update mode or double update mode The entire PWM module has four groups of four PWM outputs each Therefore this module generates 16 PWM outputs in total Each PWM group produces two pairs of PWM signals on the four PWM outputs Rev A Page80f72 Digital Applications Interface DAI The digital applications interface DAT provides the ability to connect various peripherals to any of the DAI pins DAI P20 1 Programs make these connections using the signal routing unit SRU shown in Figure 1 on Page 1 The SRU is a matrix routing unit or group of multiplexers that enables the peripherals provided by the DAI to be intercon nected under software control This allows easy use of the DAI associated peripherals for a much wider variety of applications by using a larger set of algorithms than is possible with noncon figurable signal paths The DAI includes the peripherals described in the following sections Serial Ports The processors feature eight synchr
80. nning at 450 MHz and 2 4 GFLOPS running at 400 MHz FAMILY CORE ARCHITECTURE The processors are code compatible at the assembly level with the ADSP 2137x ADSP 2136x ADSP 2126x ADSP 21160 and ADSP 21161 and with the first generation ADSP 2106x SHARC processors The ADSP 21467 ADSP 21469 processors share architectural features with the ADSP 2126x ADSP 2136x ADSP 2137x and ADSP 2116x SIMD SHARC processors as shown in Figure 2 and detailed in the following sections SIMD Computational Engine The processor contains two computational processing elements that operate as a single instruction multiple data SIMD engine The processing elements are referred to as PEX and PEY and each contains an ALU multiplier shifter and register file PEX is always active and PEY may be enabled by setting the PEYEN mode bit in the MODEI register When this mode is enabled the same instruction is executed in both pro cessing elements but each processing element operates on different data This architecture is efficient at executing math intensive DSP algorithms Entering SIMD mode also has an effect on the way data is trans ferred between memory and the processing elements When in SIMD mode twice the data bandwidth is required to sustain computational operation in the processing elements Because of this requirement entering SIMD mode also doubles the band width between memory and the processing elements When using the DAGs to transfer data
81. ock data and frame sync signals can come from any of the DAI pins The serial clock and frame sync signals can also come via PCG or SPORTs The PCG s input can be either CLKIN or any of the DAI pins SAMPLE EDGE 20 1 SCLK tsRcsrs gt 4 tsrcurs gt DAI P20 1 FS tsncsp gt a tsrcHD DAI 20 1 SDATA Figure 31 ASRC Serial Input Port Timing Rev A Page470f72 December 2011 ADSP 21467 ADSP 21469 Sample Rate Converter Serial Output Port For the serial output port the frame sync is an input and it delay specification with regard to serial clock Note that the should meet setup and hold times with regard to the serial clock serial clock rising edge is the sampling edge and the falling edge on the output port The serial data output has a hold time and is the drive edge Table 44 ASRC Serial Output Port Parameter Min Max Unit Timing Requirements tsncsrs Frame Sync Setup Before Serial Clock Rising Edge 4 ns tsncHrs Frame Sync Hold After Serial Clock Rising Edge 5 5 ns tsRCCLKW Clock Width teck X 4 2 1 ns tSRCCLK Clock Period tecik X 4 ns Switching Characteristics tsactpp Transmit Data Delay After Serial Clock Falling Edge 9 9 ns Transmit Data Hold After Serial Clock Falling Edge 1 ns The serial clock data and frame sync signals can come from any of the DAI pins The serial clock and frame sync signals can also c
82. ome via PCG or SPORTs The PCG s input can be either CLKIN or any of the DAI pins SAMPLE EDGE ra DAI P20 1 SCLK 4 tsRccLkw tsncurs tsncsrs Lag DAI_P20 1 FS tsrctpp jh DAI P20 1 SDATA Figure 32 ASRC Serial Output Port Timing Rev A Page480f72 December 2011 ADSP 21467 ADSP 21469 Pulse Width Modulation PWM Generators The following timing specifications apply when the AMI_ADDR23 8 pins are configured as PWM Table 45 Pulse Width Modulation PWM Timing Parameter Min Max Unit Switching Characteristics tPWMW PWM Output Pulse Width 2 216 2 x 2 ns tPWMP PWM Output Period 2 1 5 216 1 x 1 5 ns tewmw PWM OUTPUTS tpwmP Figure 33 Timing Rev A 49 72 December 2011 ADSP 21467 ADSP 21469 S PDIF Transmitter Serial data input to the S PDIF transmitter can be formatted as left justified 125 right justified with word widths of 16 18 20 or 24 bits The following sections provide timing for the transmitter S PDIF Transmitter Serial Input Waveforms Figure 34 shows the right justified mode LRCLK is high for the left channel and low for the right channel Data is valid on the rising edge of serial clock The MSB is delayed minimum in 24 bit output mode or maximum in 16 bit output mode from an LRCLK transition
83. onfigured as RUNRSTIN Table 21 Running Reset Parameter Min Max Unit Timing Requirements wRUNRST Running RESET Pulse Width Low 4x tck ns tsRUNRST Running RESET Setup Before CLKIN High 8 ns CLKIN twRUNRST 4 tsRUNRST RUNRSTIN Figure 10 Running Reset Rev A Page260f72 December 2011 ADSP 21467 ADSP 21469 Interrupts The following timing specification applies to the FLAGO FLAGI and FLAG2 pins when they are configured as IRQO and IRQ interrupts as well as the DAI_P20 1 and DPI P14 1 pins when they are configured as interrupts Table 22 Interrupts Parameter Min Max Unit Timing Requirement tipw IROx Pulse Width 2 2 ns INTERRUPT INPUTS ipw Figure 11 Interrupts Core Timer The following timing specification applies to FLAG3 when it is configured as the core timer TMREXP Table 23 Core Timer Parameter Min Max Unit Switching Characteristic twcriM TMREXP Pulse Width 4 1 twcriw FLAG3 TMREXP Figure 12 Core Timer Rev A Page270f72 December 2011 ADSP 21467 ADSP 21469 Timer PWM_OUT Cycle Timing The following timing specification applies to Timer0 and Timerl in PWM_OUT pulse width modulation mode Timer signals are routed to the DPI P14 1 pins through the DPI SRU Therefore the timing specifications provided below are valid at the DPI P14 1 pins Table 24 Timer PWM OUT Timing
84. onous serial ports that pro vide an inexpensive interface to a wide variety of digital and mixed signal peripheral devices such as Analog Devices 183 family of audio codecs ADCs and DACs The serial ports are made up of two data lines a clock and frame sync The data lines can be programmed to either transmit or receive and each data line has a dedicated DMA channel Serial ports can support up to 16 transmit or 16 receive DMA channels of audio data when all eight SPORTS are enabled or four full duplex TDM streams of 128 channels per frame The serial ports operate at a maximum data rate of 4 Serial port data can be automatically transferred to and from on chip memory external memory via dedicated DMA chan nels Each of the serial ports can work in conjunction with another serial port to provide TDM support One SPORT pro vides two transmit signals while the other SPORT provides the two receive signals The frame sync and clock are shared Serial ports operate in five modes Standard DSP serial mode Multichannel TDM mode 125 mode e Packed IS mode Left justified mode S PDIF Compatible Digital Audio Receiver Transmitter The S PDIF receiver transmitter has no separate DMA chan nels It receives audio data in serial format and converts it into a biphase encoded signal The serial data input to the receiver transmitter can be formatted as left justified 128 or right justi fied with word widths o
85. owing symbols appear in the Type column of Table 10 A asynchronous input output S synchronous A D active drive O D open drain and T three state ipd internal pull down resistor ipu internal pull up resistor The internal pull up ipu and internal pull down ipd resistors are designed to hold the internal path from the pins at the expected logic levels To pull up or pull down the external pads to the expected logic levels use external resistors Internal pull up pull down resistors cannot be enabled disabled and the value of these resistors cannot be programmed The range of an ipu resistor can be between 26 kQ 63 The range of an ipd resistor be between 31 85 The three state voltage of ipu pads will not reach to full the Vpp_exr level at typical conditions the voltage is in the range of 2 3 V to 2 7 V In this table the DDR2 pins SSTL18 compliant All other pins are LVTTL compliant Rev 16 72 December2011 ADSP 21467 ADSP 21469 Table 10 Pin Descriptions Continued State During After Name Type Reset Description RESET Processor Reset Resets the processor to a known state Upon deassertion there is a 4096 CLKIN cycle latency for the PLL to lock After this time the core begins program execution from the hardware reset vector address The RESET input must be asserted low at power up RESETOUT ipu Reset Out Running Reset In The d
86. pplies must meet the Vpp specifications The external supply must meet the Vpp ext specification All external supply pins must be con nected to the same power supply Note that the analog power supply pin Vpp A powers the pro cessor s internal clock generator PLL To produce a stable clock itis recommended that PCB designs use an external filter circuit for the Vpp pin Place the filter components as close as possi ble to the A AGND pins For an example circuit see Figure 3 A recommended ferrite chip is the muRata BLMI8AGIO2SNID To reduce noise coupling the PCB should use a parallel pair of power and ground planes for Vpp int and GND Use wide traces to connect the bypass capacitors to the analog power A and ground AGND pins Note that the Vpp and AGND pins specified in Figure 3 are inputs to the processor and not the analog ground plane on the board the AGND pin should connect directly to digital ground GND at the chip Target Board JTAG Emulator Connector Analog Devices DSP Tools product line of JTAG emulators uses the IEEE 1149 1 JTAG test access port of the processor to moni tor and control the target board processor during emulation Analog Devices DSP Tools product line of JTAG emulators pro vides emulation at full processor speed allowing inspection and December 2011 ADSP 21467 ADSP 21469 ADSP 2146x 100nF HI Z FERRITE BEAD CHIP LOCATE ALL COMPONENTS CLOSE TO VD
87. pply VREF Leave floating unconnected MLBCLK MLBDAT MLBSIG MLBDO MLBSO Available on automotive models only In standard products using silicon revision 0 2 and above connect to ground GND In standard products using silicon revisions previous to revision 0 2 leave these pins floating if unused When the DDR2 controller is not used power down the receive path by setting the PWD bits of the DDR2PADCTLIx register Rev A 12 72 December 2011 ADSP 21467 ADSP 21469 Table 10 Pin Descriptions Name Type State During After Reset Description ADDR 9 AMI DATA o AMI MSo 1 AMI RD AMI WR ipu ipu 1 ipu O T ipu O T ipu O T ipu High Z driven low boot High Z High Z High Z High Z External Address The processor outputs addresses for external memory and periph erals on these pins The data pins can be multiplexed to support the PDAP and PWM After reset all AMI ADDR2s opins in external memory interface mode and FLAG 0 3 pins are in FLAGS mode default When configured in the register IDP channel 0 scans the AMI ADDRo3 o pins for parallel input data Unused AMI pins can be left unconnected External Data The data pins can be multiplexed to support the external memory interface data I O the PDAP FLAGS I O PWM After reset all AMI DATA pins are
88. processor systems DDR2 Support The processors support a 16 bit DDR2 interface operating at a maximum frequency of half the core clock Execution from external memory is supported External memory devices up to 2 Gbits in size can be supported DDR2 DRAM Controller The DDR2 DRAM controller provides a 16 bit interface to up to four separate banks of industry standard DDR2 DRAM devices Fully compliant with the DDR2 DRAM standard each bank can have its own memory select line DDR2_CS3 DDR2 50 and can be configured to contain between 32 Mbytes and 256 Mbytes of memory DDR2 DRAM external memory address space is shown in Table 6 set of programmable timing parameters is available to config ure the DDR2 DRAM banks to support memory devices Table 6 External Memory for DDR2 DRAM Addresses Bank Size in Words Address Range Bank 0 62M 0x0020 0000 FFFF Bank 1 64M 0x0400 0000 0x07FF FFFF Bank 2 64M 0x0800 0000 OxOBFF FFFF Bank 3 64M 0 0 00 0000 OxOFFF FFFF December 2011 ADSP 21467 ADSP 21469 Note that the external memory bank addresses shown are for normal word 32 bit accesses If 48 bit instructions as well as 32 bit data are both placed in the same external memory bank care must be taken while mapping them to avoid overlap Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I O devi
89. pt Request1 FLAG2 Interrupt Request2 Async Memory Select2 FLAG3 Timer Expired Async Memory Select3 The following symbols appear in the Type column of Table 10 A asynchronous input O output S synchronous A D active drive O D open drain and T three state internal pull down resistor ipu internal pull up resistor The internal pull up ipu and internal pull down ipd resistors are designed to hold the internal path from the pins at the expected logic levels To pull up or pull down the external pads to the expected logic levels use external resistors Internal pull up pull down resistors cannot be enabled disabled and the value of these resistors cannot be programmed The range of an ipu resistor can be between 26 63 The range of an ipd resistor be between 31 85 The three state voltage of ipu pads will not reach to full the Vpp level at typical conditions the voltage is in the range of 2 3 V to 2 7 V In this table the DDR2 pins are SSTL18 compliant All other pins are LVTTL compliant Rev Page130f72 December2011 ADSP 21467 ADSP 21469 Table 10 Pin Descriptions Continued State During After Name Type Reset Description DDR2 ADDR s g O T High Z DDR2 Address DDR2 address pins driven low DDR2_BA gt 9 O T High Z DDR2 Bank Address Input Defines which internal bank an ACTIVATE READ WRITE driven low or PRECHARGE command is bein
90. quirements tsisrs Frame Sync Setup Before Serial Clock Rising Edge 3 8 ns tsinFs Frame Sync Hold After Serial Clock Rising Edge 2 5 ns tsisp Data Setup Before Serial Clock Rising Edge 2 5 ns Data Hold After Serial Clock Rising Edge 2 5 ns tipPCLKW Clock Width teck X 4 2 1 ns tipPCLK Clock Period X 4 ns 1 The serial clock data and frame sync signals can come from any ofthe DAI pins The serial clock and frame sync signals can also come via PCG or SPORTs The PCG s input can be either CLKIN or any of the DAI pins SAMPLE EDGE tiepcLkw DAI P20 1 SCLK tsises gt tsiurs DAI 20 1 FS tsisp gt a DAI 20 1 SDATA Figure 29 IDP Master Timing Rev A Page450f72 December 2011 ADSP 21467 ADSP 21469 Parallel Data Acquisition Port PDAP The timing requirements for the PDAP are provided in Table 42 PDAP is the parallel mode operation of channel 0 of the For details on the operation of the PDAP see the PDAP chapter of the ADSP 214xx SHARC Processor Hardware Reference Table 42 Parallel Data Acquisition Port PDAP Parameter Min Max Unit Timing Requirements tspHoLp PDAP_HOLD Setup Before PDAP_CLK Sample Edge 2 5 ns tupHOLD PDAP HOLD Hold After Sample Edge 2 5 ns tppsp PDAP_DAT Setup Before Serial Clock PDAP_CLK Sample Edge 3 85 ns tPDHD DAT Hold After Serial Clock
91. r Up Sequencing Timing Requirements Processor Startup Parameter Min Max Unit Timing Requirements tRSTVDD RESET Low Before Vpp Vpp_ext Vpp 2 On 0 ms tiVDD EVDD Vpp On Before Vpp 200 200 ms DDR2VDD On Before 2 200 200 ms tcikvpp CLKIN Valid After Vpp INT Vpp Or _ 2 Valid 0 200 ms tCLKRST CLKIN Valid Before RESET Deasserted 10 ms tPLLRST PLL Control Setup Before RESET Deasserted 20 ms Switching Characteristic tCORERST Core Reset Deasserted After RESET Deasserted 4096 x tck 2 x tccik ms Valid Vpp assumes that the supply is fully ramped to its nominal value Voltage ramp rates vary from microseconds to hundreds of milliseconds depending on the design of the power supply subsystem Assumesa stable CLKIN signal after meeting worst case startup timing of crystal oscillators Refer to your crystal oscillator manufacturer s data sheet for startup time Assume 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal Based on CLKIN cycles 4 Applies after the power up sequence is complete Subsequent resets require a minimum of four CLKIN cycles for RESET to be held low in order to properly initialize and propagate default states at all I O pins 5 4096 cycle count depends specification in Table 20 If setup time is no
92. rnal memory in bank 0 and 4M words of external memory in bank 1 bank 2 and bank 3 ADDR2 DRAM controller External memory devices up to 2 Gbits in size can be supported Arbitration logic to coordinate core and DMA transfers between internal and external memory over the external port External Memory The external port on the processors provide a high perfor mance glueless interface to a wide variety of industry standard memory devices The external port may be used to interface to synchronous and or asynchronous memory devices through the use of its separate internal DDR2 memory controller The 16 bit DDR2 DRAM controller connects to industry standard syn chronous DRAM devices while the second 8 bit asynchronous memory controller is intended to interface to a variety of mem ory devices Four memory select pins enable up to four separate devices to coexist supporting any desired combination of syn chronous and asynchronous device types Non DDR2 DRAM external memory address space is shown in Table 4 Table 4 External Memory for Non DDR2 DRAM Addresses Bank Size in Words Address Range Bank 0 2M 0x0020 0000 0x003F FFFF Bank 1 4M 0x0400 0000 FFFF Bank 2 4M 0x0800 0000 0x083F FFFF Bank3 4M 0 0 00 0000 OxOC3F FFFF SIMD Access to External Memory The DDR2 controller supports SIMD access on the 64 bit EPD external port data bus which allows to access the complemen tary registers on the
93. roduct The USB controller on the EZ KIT Lite board connects the board to the USB port of the user s PC enabling the VisualDSP evaluation suite to emulate the on board proces sor in circuit This permits the customer to download execute and debug programs for the EZ KIT Lite system It also allows in circuit programming of the on board Flash device to store user specific boot code enabling the board to run as a stand alone unit without being connected to the PC With a full version of VisualDSP installed sold separately engineers can develop software for the EZ KIT Lite or any cus tom defined system Connecting one of Analog Devices JTAG emulators to the EZ KIT Lite board enables high speed non intrusive emulation ADDITIONAL INFORMATION This data sheet provides a general overview of the ADSP 21467 ADSP 21469 architecture and functionality For detailed infor mation on the core architecture and instruction set refer to the SHARC Processor Programming Reference RELATED SIGNAL CHAINS A signal chain is a series of signal conditioning electronic com ponents that receive input data acquired from sampling either real time phenomena or from stored data in tandem with the output of one portion of the chain supplying input to the next Signal chains are often used in signal processing applications to gather and process data or to apply system controls based on analysis of real time phenomena For more information about thi
94. s term and related topics see the signal chain entry in Wikipedia or the Glossary of EE Terms on the Analog Devices website Analog Devices eases signal processing system development by providing signal processing components that are designed to work together well A tool for viewing relationships between specific applications and related components is available on the www analog com website The Application Signal Chains page in the Circuits from the Lab site http www analog com signal chains provides Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications Drill down links for components in each chain to selection guides and application information Reference designs applying best practice design techniques December 2011 ADSP 21467 ADSP 21469 PIN FUNCTION DESCRIPTIONS Use the termination descriptions in Table 9 when not using the Warning System designs must comply with these termination DDR 2 or MIB interfaces rules to avoid causing issues of quality reliability and power leakage at these pins Table 9 Unused Pin Terminations Pin Name Unused Termination DDR2 DDR2 CS DDR2 DM DDR2 DOSx Leave floating 082 DOSx DDR2 RAS DDR2 CAS Internally three state by setting the DIS DDRCTL bit of the DDR2CTLO register DDR2 WE DDR2 CLKx DDR2 CLKx DDR2 ADDR DDR2 BA DDR2 DATA Connect to the Vpp su
95. ses 2 32 bit PCLK speed Nonsecured ROM For nonsecured ROM booting modes are selected using the pins as shown in Table 8 on Page 10 In this mode emulation is always enabled and the IVT is placed on the inter nal RAM except for the case where BOOTCFGx 011 Table 3 Internal Memory Space ROM Based Security The ROM security feature provides hardware support for secur ing user software code by preventing unauthorized reading from the internal code when enabled When using this feature the processors do not boot load any external code executing exclusively from internal ROM Additionally the processors are not freely accessible via the JTAG port Instead a unique 64 bit key which must be scanned in through the JTAG or Test Access Port will be assigned to each customer Digital Transmission Content Protection The DTCP specification defines a cryptographic protocol for protecting audio entertainment content from illegal copying intercepting and tampering as it traverses high performance digital buses such as the IEEE 1394 standard Only legitimate entertainment content delivered to a source device via another approved copy protection system such as the DVD content scrambling system is protected by this copy protection system IOP Registers 0 0000 0000 0x0003 FFFF Extended Precision Normal or Long Word 64 Bits Instruction Word 48 Bits Normal Word 32 Bits Short Word 16 Bits
96. switching characteristics apply to external DAI pins DAI POI DAI P20 This timing is only valid when the SRU is configured such that the precision clock generator PCG takes its inputs directly from the DAI pins via pin buffers and sends its outputs directly to the DAI pins For the other cases where the PCG s Table 27 Precision Clock Generator Direct Pin Routing Parameter Min Max Unit Timing Requirements Input Clock Period 4 ns tsTRIG PCG Trigger Setup Before Falling Edge of PCG Input 4 5 ns Clock tHTRIG PCG Trigger Hold After Falling Edge of PCG Input 3 ns Clock Switching Characteristics tppccio PCG Output Clock and Frame Sync Active Edge Delay 2 5 10 After PCG Input Clock ns tDTRIGCLK PCG Output Clock Delay After PCG Trigger 2 5 2 5 x tecaip 10 2 5 x tpcaip ns tprRIGFS PCG Frame Sync Delay After PCG Trigger 2 5 2 5 D xXtpcgip 10 2 5 D ns tpccow Output Clock Period 2 x 1 ns D FSxDIV PH FSxPHASE For more information see the ADSP 214xx SHARC Processor Hardware Reference Precision Clock Generators chapter Normal mode of operation DAI Pn DPI Pn PCG TRIGx DAI Pm DPI Pm PCG EXTx CLKIN DAI Py DPI Py PCK CLKx O totriccLk topccio DAI_Pz DPI_Pz PCG FSx O pim tprgicrs Figure 16 Precision Clock Generator Direct Pin Routing Rev A Pag
97. t met one additional CLKIN cycle may be added to the core reset time resulting in 4097 cycles maximum trstvop RESET S VDDINT DAE 728 CLKIN tci knsT STRE 411 tPLLRST tconERsT RESETOUT 2 Figure 6 Power Up Sequencing Rev A Page240f72 December 2011 ADSP 21467 ADSP 21469 Clock Input Table 19 Clock Input 400 MHz 450 MHz Parameter Min Max Min Max Unit Timing Requirements tck CLKIN Period 153 100 13 26 100 ns tcKL CLKIN Width Low 15 45 6 63 45 ns tckH CLKIN Width High 7 5 45 6 63 45 ns CLKIN Rise Fall 0 4 V to 2 0 V 3 3 ns tccue CCLK Period 2 5 10 2 22 10 ns VCO Frequency 200 900 200 900 MHz tci 8 CLKIN Jitter Tolerance 250 250 250 250 ps Applies to all 400 MHz models See Ordering Guide on Page 72 Applies to all 450 MHz models See Ordering Guide on Page 72 3 Applies only for CLK_CFG1 0 00 and default values for PLL control bits in PMCTL Guaranteed by simulation but not tested on silicon Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tccrk 6 See Figure 5 on Page 23 for VCO diagram 7 Actual input jitter should be combined with ac specifications for accurate timing analysis Jitter specification is maximum peak to peak time interval error TIE jitter CLKIN
98. th 16 Bits Shared DDR2 External Memory Yes Direct DMA from SPORTs to External Memory Yes FIR IIR FFT Accelerator Yes MLB Interface Automotive Models Only IDP Yes Serial Ports 8 DAI SRU DPI SRU2 20 14 pins UART 1 Link Ports 2 AMI Interface with 8 Bit Support Yes Rev A Page30f72 Table 2 SHARC Family Features Continued Feature ADSP 21467 ADSP 21469 SPI 2 TWI Yes SRC Performance 128 dB Package 324 Ball 5 BGA Factory programmed ROM includes Dolby AC 3 5 1 Decode Dolby Pro Logic Dolby Intelligent Mixer eMix Dolby Volume postprocessor Dolby Headphone v2 DTS Neo 6 and Decode DTS 5 1 Decode 96 24 Math Tables Twiddle Factors 256 and 512 FFT and ASRC Please visit www analog com for complete product information and availability 2 Contact your local Analog Devices sales office for more information regarding availability of ADSP 21467 ADSP 21469 processors which support DTCP Figure 1 on Page 1 shows the two clock domains that make up the processor The core clock domain contains the following features Two processing elements PEx PEy each of which com prises an ALU multiplier shifter and data register file e Data address generators DAGI DAG2 Program sequencer with instruction cache One periodic interval timer with pinout PM and DM buses capable of supporting 2 x 64 bit data transfers between memory and the core at every core pro cessor cycl
99. ther acting as a master or slave device The SPI compatible peripheral implementation also features programmable baud rate clock phase and polarities The SPI compatible port uses open drain drivers to support a multimaster configuration and to avoid data contention Rev A Page90f72 UART Port The processors provide a full duplex Universal Asynchronous Receiver Transmitter UART port which is fully compatible with PC standard UARTs The UART port provides a simpli fied UART interface to other peripherals or hosts supporting full duplex DMA supported asynchronous transfers of serial data The UART also has multiprocessor communication capa bility using 9 bit address detection This allows it to be used in multidrop networks through the RS 485 data interface standard The UART port also includes support for 5 to 8 data bits 1 or 2 stop bits and none even or odd parity The UART port supports two modes of operation PIO programmed I O The processors send or receive data by writing or reading I O mapped UART registers The data is double buffered on both transmit and receive DMA direct memory access The DMA controller trans fers both transmit and receive data This reduces the number and frequency of interrupts required to transfer data to and from memory Timers The processors have a total of three timers a core timer that can generate periodic software interrupts and two general purpose timers that can
100. ting its program instructions DMA transfers can occur between the processor s internal memory and its serial ports the SPI compatible serial peripheral interface ports the IDP input data port the paral lel data acquisition port PDAP or the UART Up to 67 channels of DMA are available as shown in Table 7 Programs can be downloaded to the processor using DMA transfers Other DMA features include interrupt generation upon completion of DMA transfers and DMA chaining for automatic linked DMA transfers Delay Line DMA Delay line DMA allows processor reads and writes to external delay line buffers and hence to external memory with limited core interaction Scatter Gather DMA Scatter gather allows reads writes to from non contiguous memory blocks Table 7 DMA Channels Peripheral DMA Channels SPORTs 16 IDP PDAP 8 SPI 2 UART 2 External Port 2 Link Port 2 Accelerators 2 Memory to Memory 2 31 Automotive models only IIR Accelerator The IIR infinite impulse response accelerator consists of a 1440 word coefficient memory for storage of biquad coeffi cients a data memory for storing the intermediate data and one MAC unit A controller manages the accelerator The IIR accel erator runs at the peripheral clock frequency FFT Accelerator FFT accelerator implements radix 2 complex real input com plex output FFT with no core intervention The FFT accelerator runs at
101. truction and four data values The cache is selective only the instructions whose fetches conflict with PM bus data accesses are cached This cache allows full speed execution of core looped operations such as digital filter multiply accumulates and FFT butterfly processing Data Address Generators With Zero Overhead Hardware Circular Buffer Support The two data address generators DAGs are used for indirect addressing and implementing circular data buffers in hardware Circular buffers allow efficient programming of delay lines and other data structures required in digital signal processing and are commonly used in digital filters and Fourier transforms The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers 16 primary register sets 16 secondary The DAGs automatically handle address pointer wraparound reduce overhead increase perfor mance and simplify implementation Circular buffers can start and end at any memory location December 2011 SIMD Core DMD PMD 64 1 DAG1 DAG2 16 x 32 16 x 32 MULTIPLIER 16 x 40 BIT MRF MRB 80 BIT 80 BIT ASTATx STYKx ADSP 21467 ADSP 21469 PM ADDRESS 24 PM DATA 48 PM ADDRESS 32 SYSTEM VF DM ADDRESS 32 USTAT PM DATA 64 4 x 32 BIT PX DM DATA 64 64 BIT ASTATy STYKy Figure 2 SHARC Core Block Diagram Flexible Instruction Set The 48 bit instruction word accommodates a variety of paralle
102. ue to OR ing logic on the pins must be accounted for 3 When a node is not driving valid data onto the bus the MLBSO and MLBDO output lines shall remain low If the output lines can float at anytime including while in reset external pull down resistors are required to keep the outputs from corrupting the MediaLB signal lines when not being driven Rev A Page570f72 December 2011 ADSP 21467 ADSP 21469 MLBSIG MLBDAT Rx Input tosmcr MLBCLK n gt ucRDL MLBSO VALID MLBDO Tx Output Figure 42 MLB Timing 5 Pin Interface MLBCLK tupwv gt gt Figure 43 MLB 3 Pin and 5 Pin MLBCLK Pulse Width Variation Timing Universal Asynchronous Receiver Transmitter UART Ports Receive and Transmit Timing For information on the UART port receive and transmit opera tions see the ADSP 214xx SHARC Hardware Reference Manual 2 Wire Interface TWI Receive and Transmit Timing For information on the TWI receive and transmit operations see the ADSP 214xx SHARC Hardware Reference Manual Rev A Page580f72 December 2011 ADSP 21467 ADSP 21469 JTAG Test Access Port and Emulation Table 56 JTAG Test Access Port and Emulation Parameter Min Max Unit Timing Requirements trck TCK Period 20 ns TDI TMS Setup Before High 5 ns tHTAP TDI TMS Hold After TCK High 6 ns tssys System Inputs Setup Before TCK High 7 ns tusvs
103. ulse width variation is measuredat 1 25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge measured in nanoseconds peak to peak ns p p The board must be designed to ensure that the high impedance bus does not leave the logic state of the final driven bit for this time period Therefore coupling must be minimized while meeting the maximum capacitive load listed Rev A Page560f72 December 2011 ADSP 21467 ADSP 21469 MLBSIG MLBDAT Rx Input lt tpsucr MLBCLK MLBSIG MLBDAT Tx Output Figure 41 MLB Timing 3 Pin Interface Table 55 MLB Interface 5 Pin Specifications Parameter Min Typ Max Unit 5 Pin Characteristics tMLBCLK MLB Clock Period 512FS 40 ns 256FS 81 ns MLBCLK Low Time 512 FS 15 ns 256 FS 30 ns MLBCLK High Time 512FS 15 ns 256FS 30 ns tMCKR MLBCLK Rise Time to 6 ns MLBCLK Fall Time to 6 ns tmpwy MLBCLK Pulse Width Variation 2 ns p p DAT SIG Input Setup Time 3 ns tpHMCF DAT SIG Input Hold Time 5 ns tMCDRV DS DO Output Data Delay From MLBCLK Rising Edge 8 ns DO SO Low From MLBCLK High 512FS 10 ns 256FS 20 ns Cmts DS DO Pin Load 40 pf Pulse width variation is measured at 1 25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge measured in nanoseconds peak to peak ns Gate delays d

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