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ANALOG DEVICES ADAU1772: Four ADC Two DAC Low Power Codec with Audio Processor Data Sheet (Rev 0 2012-07-18-)

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1. 0 020 500 0 015 450 0 010 0 005 400 s 0 350 0 005 3 gt 300 ong X d 1 0 015 E 250 gt 0 020 5 200 S 0 025 9 0 030 6 150 0 035 100 0 040 0 045 50 0 050 0 gt 100 1k 10k 5 0 2 6 10 12 16 18 2 5 FREQUENCY FREQUENCY kHz 8 Figure 46 Relative Level vs Frequency Figure 49 Group Delay vs Frequency fs 48 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing 48 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing to ASRC to ADC_SDATAO to ASRC to ADC_SDATAO 200 10 0 100 300 30 400 40 500 7 50 600 60 9 700 800 E 900 a lt 1000 lt 90 1100 a 100 1200 110 1300 120 1400 130 1500 1600 pos 1700 F190 1800 160 0 2 4 6 8 10 12 14 16 18 20 5 0 0 2 04 0 6 0 8 1 0 1 2 14 1 6 1 8 20 5 FREQUENCY kHz 8 FREQUENCY kHz Figure 47 Phase vs Frequency 20 kHz Bandwidth Figure 50 Phase vs Frequency 2 kHz Bandwidth fs 48 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing 48 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing to ASRC to ADC_SDATAO to ASRC to ADC_SDATAO
2. 0 04 120 0 100 0 02 90 0 04 006 3 9 Aus 7 d 0 10 60 ul 0 12 5 50 lt 0 14 t 40 0 16 30 0 18 0 20 20 0 22 10 0 24 2 0 a 100 1k 10k 3 0 2 4 6 8 10 12 14 16 18 205 FREQUENCY Hz 8 2 8 Figure 10 Relative Level vs Frequency Figure 13 Group Delay vs Frequency fs 48 kHz Signal Path AINO to DSP Without Processing to LOUTLx 48 kHz Signal Path AINO to DSP Without Processing to LOUTLx 40 6 20 4 2 20 3 80 8 100 gt 10 Q 120 8 12 Aan A4 160 16 180 gu 200 252 220 24 240 26 260 28 280 30 0 2 4 6 8 10 12 14 16 18 202 02 04 06 08 10 12 14 16 18 20 5 FREQUENCY kHz 8 FREQUENCY kHz 8 Figure 11 Phase vs Frequency 20 kHz Bandwidth Figure 14 Phase vs Frequency 2 kHz Bandwidth 48 kHz Signal Path AINO to DSP Without Processing to LOUTLx 48 kHz Signal Path AINO to DSP Without Processing to LOUTLx 0 2 0 1 0 0 1 0 2 a a 03 04 gt s 5 0 5 E 0 6 5 0 7 3 08 ag 1 0 1 1 1 2 1 3 d 100 1k 10k 0 4 8 12 16 20 24 28 32 36 40 5 2 8 FREQUENCY kHz 8 Figure 12 Relative Level vs Frequency Figure 15 Group Delay vs Frequenc
3. Reg Name Bits Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0 0000 CLK CONTROL 7 0 PLL EN RESERVED SPK FLT DIS DIS CLKSRC CC CDIV CC MDIV COREN 0x00 RW 0x0001 PLL CTRLO 7 0 M MSB 0x00 RW 0x0002 PLL CTRL1 7 0 M LSB 0x00 RW 0x0003 PLL CTRL2 7 0 MSB 0x00 RW 0x0004 PLL CTRL3 7 0 LSB 0x00 RW 0 0005 PLL_CTRL4 7 0 RESERVED R X PLL TYPE 0x00 RW 0 0006 PLL 5 7 0 RESERVED LOCK 0 00 R 0x0007 CLKOUT SEL 7 0 RESERVED CLKOUT FREQ 0x00 RW 0x0008 REGULATOR 7 0 RESERVED REG PD REGV 0x00 RW 0x0009 CORE CONTROL 7 0 ZERO STATE BANK SL RESERVED CORE FS CORE RUN 0x04 RW 0x000B CORE ENABLE 7 0 RESERVED LIM EN DSP CLK EN 0 03 RW 0x000C DBREGO 7 0 DBVALO 0 00 R 0x000D DBREG1 7 0 DBVAL1 0x00 R 0 000 DBREG2 7 0 DBVAL2 0x00 R 0 000 CORE MUX 0 1 7 0 CORE MUX SEL 1 CORE IN MUX SEL 0 0 10 0 0010 CORE IN MUX 2 3 7 0 CORE IN MUX SEL 3 CORE IN MUX SEL 2 0x32 RW 0 0011 DAC SOURCE 0 1 7 0 DAC SOURCE DAC SOURCEO 0 10 0x0012 SOURCE 0 1 7 0 PDM SOURCE PDM SOURCEO 0x32 RW 0 0013 SOUT SOURCE 1 7 0 SOUT SOURCE 5 SOURCEO 0x54 RW 0x0014 SOUT SOURCE 2 3 7 0 SOUT SOURCE SOUT SOURCE 0x76 RW 0 0015 SOUT SOURCE A 5 7 0 SOUT SOURCES SOUT_SOURCE4 0x54 RW 0 0016 SOUT SOURCE 6 7 7 0 5 SOURCE7 SOUT_SOURCE6 0x76 RW 0
4. 91 Serial Data Output 6 Serial Data Output 7 Input Select Register n 68 PDM Enable Register etitm aree 92 ADC_SDATA0 ADC_SDATAI Channel Select Register 69 Pattern Setting Register 93 Output ASRCO Output ASRCI Source Register 70 MPO Function Setting Register 93 Output ASRC2 Output ASRC3 Source Register 71 1 Function Setting Register esse 94 Input ASRC Channel Select 72 MP2 Function Setting Register sss 95 ADCO0 ADCI Control 0 Register 73 Function Setting Register 2222 96 ADC2 ADC3 Control 0 Register 74 MP4 Function Setting Register 97 Control 1 Register vv v sv 1 111v111111111111111111111111111 75 MP5 Function Setting Register 98 ADC2 ADC3 Control 1 Register 76 MP6 Function Setting Register sese 99 ADCO Volume Control Register Push Button Volume Settings Register 100 ADCI Volume Control Register Push Button Volume Control Assignment Register 101 ADC2 Volume Control Register Debounce Modes Register 102 ADC3 Volume Control Register Headphone Line Output Select Register 102 Control 0 Decimator Power Control Register 104 PGA Control 1 Register 79
5. Bits Bit Name Settings Description Reset Access 0100 ADCO 0101 ADC1 0110 ADC2 0111 ADC3 1000 Serial Input O 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 3 0 ASRC OUT SOURCE2 Output ASRC Channel 2 source select 0 2 RW 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 ADCO 0101 ADC1 0110 ADC2 0111 ADC3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 INPUT ASRC CHANNEL SELECT REGISTER Address 0x001A Reset 0x00 Name ASRC MODE B7 88 BS B2 B 7 4 RESERVED RW E lt 0 ASRC_IN_EN RW 3 2 ASRC_IN_CH RW T Sad Input Port Channel 1 1 ASRC OUT EN RW 01 Serial Input Port Channel 2 Serial Output ASRC enable Input Port Channel 3 0 Disabled 10 Serial Input Port Channel 4 Serial 1 Enabled Input Port Channel 5 11 Serial Input Port Channel 6 Serial Input Port Channel 7 Table 55 Bit Descriptions for ASRC MODE Bits Bit Name Settings Description Reset Access 3 2 ASRC IN CH Input ASRC channel select 0 0 RW 00 Serial Input Port Channel 0 Serial Input Port Channel 1 01 Serial Input Port Channel 2 Serial Input Port Channel 3
6. Rev 0 36 of 116 01772 Table 17 Parameter Addresses Bank Assignment Order BO Max Gain B1 Min Gain B2 Attack A1 Decay A2 Threshold 0 0 0100 0 0120 0 0140 0 0160 1 Ox00E1 0x0101 0x0121 0x0141 0x0161 2 Ox00E2 0x0102 0x0122 0x0142 0x0162 3 0 0103 0 0123 0 0143 0 0163 4 0 00 4 0 0104 0 0124 0 0144 0 0164 5 5 0 0105 0 0125 0 0145 0 0165 6 OxOOE6 0x0106 0x0126 0x0146 0x0166 7 0 00 7 0 0107 0 0127 0 0147 0 0167 8 OxOOE8 0x0108 0x0128 0x0148 0x0168 9 OxOOE9 0x0109 0x0129 0x0149 0x0169 10 0 010 0 012 0 014 0 016 11 0 0108 0 0128 0 0148 0 0168 12 0x010C 0x012C 0x014C 0x016C 13 0x00ED 0x010D 0x012D 0x014D 0x016D 14 0x00EE 0x010E 0x012E 0x014E 0x016E 15 0x00EF 0x010F 0x012F 0x014F 0x016F 16 0x00F0 0x0110 0x0130 0x0150 0x0170 17 0x00F1 0x0111 0x0131 0x0151 0x0171 18 0x00F2 0x0112 0x0132 0x0152 0x0172 19 0x00F3 0x0113 0x0133 0x0153 0x0173 20 0x00F4 0x0114 0x0134 0x0154 0x0174 21 0x00F5 0x0115 0x0135 0x0155 0x0175 22 0x00F6 0x0116 0x0136 0x0156 0x0176 23 0x00F7 0x0117 0x0137 0x0157 0x0177 24 0x00F8 0x0118 0x0138 0x0158 0x0178 25 0x00F9 0x0119 0x0139 0x0159 0x0179 26 OxOOFA 0x011A 0x013A 0x015A 0x017A 27 0 0118 0 0138 0 0158 0 0178 28 0 011 0x013C 0x015C 0x017C 29 0x00FD 0x011D 0x013D 0x015D 0x017D 30 Ox011E 0x0
7. Rev 0 Page 72 of 116 01772 Bits Bit Name Settings Description Reset Access 10 Serial Input Port Channel 4 Serial Input Port Channel 5 11 Serial Input Port Channel 6 Serial Input Port Channel 7 1 ASRC_OUT_EN Output ASRC enable 0 0 RW 0 Disabled 1 Enabled 0 ASRC_IN_EN Input ASRC enable 0 0 RW 0 Disabled 1 Enabled ADCO ADC1 CONTROL 0 REGISTER Address 0x001B Reset 0x19 Name ADC_CONTROLO B7 B5 B4 B3 B2 B 0 0 0 1 1 0 0 1 7 6 RESERVED RW 1 0 ADC 0 1 FS RW 5 RESERVED RW Sets ADC sample rate 00 96 kHz 4 ADC1 MUTE RW 01 192 kHz Mute ADC1 10 Reserved 0 Unmuted 11 Reserved a 2 RESERVED RW 3 ADCO_MUTE RW Mute ADCO 0 Unmuted 1 Muted Table 56 Bit Descriptions for ADC_CONTROLO Bits Bit Name Settings Description Reset Access 4 ADC1_MUTE Mute ADC1 Muting is accomplished by setting the volume control to 0 1 RW maximum attenuation This bit has no effect if volume control is bypassed 0 Unmuted 1 Muted 3 ADCO MUTE Mute ADCO Muting is accomplished by setting the volume control to 0 1 RW maximum attenuation This bit has no effect if volume control is bypassed 0 Unmuted 1 Muted 1 0 ADC_0_1_FS Sets ADC sample rate 0 1 RW 00 96 kHz 01 192 kHz 10 Reserved 11 Reserved Rev 0 Page 73 of 116 01772 ADC2 ADC3 CONTROL 0 REGISTER Address
8. B B B 7 0 TALKTHRU_GAINO_VAL Sets the DAC 0 volume when DSP bypass mode is enabled Table 72 Bit Descriptions for TALKTHRU GAINO Bits Bit Name Settings Description Reset Access 7 0 TALKTHRU VAL Sets the DACO volume when DSP bypass mode is enabled 0x00 RW DSP BYPASS GAIN FOR REGISTER Address 0x002C Reset 0x00 Name TALKTHRU GAINI B B B 7 0 TALKTHRU GAIN VAL mem 0 Sets the DAC 1 volume when DSP bypass mode is enabled Table 73 Bit Descriptions for TALKTHRU GAINI Bits Bit Name Settings Description Reset Access 7 0 TALKTHRU_GAIN1_VAL Sets the DAC1 volume when DSP bypass mode is enabled 0x00 RW Rev 0 Page 85 of 116 ADAUI772 MIC BIASO 1 CONTROL REGISTER Address 0x002D Reset 0x00 Name MIC BIAS 7 6 RESERVED RW 5 MIC EN1 RW B7 B6 B5 B4 B3 B2 B1 BO a L wm RW Level of the BIASO output 0 0 9 x AVDD MIC BIAS1 output enable 4 065 x AVDD 0 Disabled 1 Enabled 1 MIC GAIN1 RW 4 MIC ENO RW Level of the BIAS1 output 0 0 9 x AVDD MIC spud output enable 4 086 x AVDD 0 Disabled 1 Enabled 2 RESERVED RW Table 74 Bit Descriptions for MIC BIAS 3 RESERVED RW Bits Bit Name Settings Description Reset Access 5 MICBIAS1 output enable 0 0 RW 0 Disabled 1 Enabled 4 MIC_ENO MICBIASO output ena
9. Bits Bit Name Settings Description Reset Access 3 MOD 1 EN DAC Modulator 1 enable 0 0 RW 0 Powered down 1 Powered up 2 MOD 0 EN DAC Modulator 0 enable 0 0 RW 0 Powered down 1 Powered up 1 INT_1_EN ASRC Interpolator 1 enable 0 0 RW 0 Powered down 1 Powered up 0 0 ASRC Interpolator 0 enable 0 0 RW 0 Powered down 1 Powered up ANALOG BIAS CONTROL 0 REGISTER Address 0x0046 Reset 0x00 Name BIAS_CONTROLO B7 5 B4 1 0 ADC_IBIASO1 RW 7 6 HP_IBIAS RW Headphone output bias current setting 00 Normal operation default 01 Extreme power saving 10 Enhanced performance 11 Power saving 5 4 AFE_IBIASO1 RW Analog Front End 0 and Analog Front End 1 bias current setting 00 Normal operation default 01 Extreme power saving 10 Enhanced performance 11 Power saving Rev 0 Page 105 of 116 ADCO and ADC1 bias current setting 00 Normal operation default 01 Reserved 10 Enhanced performance 11 Power saving 3 2 ADC_IBIAS23 RW ADC2 and ADC3 bias current setting 00 Normal operation default 01 Reserved 10 Enhanced performance 11 Power saving ADAUI772 Table 97 Bit Descriptions for BIAS CONTROLO Bits Bit Name Settings Description Reset Access 7 6 HP_IBIAS Headphone output bias current setting Higher bias currents result in 0 0 RW higher performance 00 Norma
10. 01772 DEBOUNCE MODES REGISTER Address 0x0041 Reset 0x05 Name DEBOUNCE_MODE B7 B5 B4 B3 B2 B1 7 3 RESERVED RW 2 0 DEBOUNCE RW The debounce time setting for the MPx inputs 000 Debounce 300 ps 001 Debounce 600 ps 010 Debounce 900 ps 011 Debounce 5 ms 100 Debounce 10 ms 101 Debounce 20 ms 110 Debounce 40 ms 111 No debounce Table 93 Bit Descriptions for DEBOUNCE MODE Bits Bit Name Settings Description Reset Access 2 0 DEBOUNCE The debounce time setting for the MPx inputs 0x5 RW 000 Debounce 300 us 001 Debounce 600 us 010 Debounce 900 us 011 Debounce 5 ms 100 Debounce 10 ms 101 Debounce 20 ms 110 Debounce 40 ms 111 No debounce HEADPHONE LINE OUTPUT SELECT REGISTER Address 0x0043 Reset 0 0 Name OP STAGE CTRL B7 5 4 B2 B1 B 7 6 RESERVED RW 1 1 0 HP_PDN_L RW ae Output stage power control 5 _ _ RW 00 HPOUTLN and Sets the right channel in line HPOUTLP LOUTL outputs output or headphone mode enabled 0 Right output in line output mode 01 HPOUTLN enabled 1 Right output in headphone mode HPOUTLP LOUTL disabled 10 HPOUTLN disabled HPOUTLP LOUTL enabled 11 Left output stages powered 4 HP_EN_L RW Sets the left channel in line output or headphone mode down 0 Left output in line output mode 1 Left output in headphone output 3 2 HP_PDN_R RW mode Output stage po
11. volume 00000000 0 dB 00000001 0 375 dB 11111111 95 625 4 Table 63 Bit Descriptions for ADC3_VOLUME Bits Bit Name Settings Description Reset Access 7 0 ADC_3_VOL ADC3 volume setting 0x00 RW 00000000 0dB 00000001 0 375 dB 11111111 95 625 dB Rev 0 Page 78 of 116 01772 PGA CONTROL 0 REGISTER Address 0x0023 Reset 0x40 Name PGA_CONTROL_0 This register controls the PGA connected to AINO B8 B4 B2 B1 B7 7 PGA_ENO RW 5 0 PGA_GAINO RW Select line or microphone ME Set the gain of PGAO 0 AINO used as a single ended line 000000 12 dB input PGA powered down 000001 11 25 dB 1 AINO used as a single ended 010000 0 dB microphone input PGA powered up 111110 34 5 dB win 111111 435 25 dB 6 PGA MUTEO RW Enable PGA mute 0 Unmuted 1 Muted Table 64 Bit Descriptions for PGA CONTROL 0 Bits Bit Name Settings Description Reset Access 7 PGA ENO Select line or microphone input Note that the PGA inverts the signal 0 0 going through it 0 AINO used as a single ended line input PGA powered down 1 AINO used as a single ended microphone input PGA powered up with slewing RW 6 PGA_MUTEO Enable PGA mute When PGA is muted PGA_GAINO is ignored 0 1 0 Unmuted 1 Muted RW 5 0 PGA_GAINO Set the gain of PGAO 0 0 000000 12 000001 11 25 dB 010000 111110 34 5 dB 11111
12. B7 B8 B5 B4 B3 B2 B1 BO 7 2 RESERVED RW 0 DSP CLK EN RW Enable the clock to the core 0 Core clock disabled 1 Core dock enabled 1 LIM EN RW Limiter Enable 0 Disabled 1 Enabled Table 40 Bit Descriptions for CORE ENABLE Bits Bit Name Settings Description Reset Access 1 LIM EN Limiter enable When the limiter function is disabled a fixed max gain Ox1 RW setting is applied to instructions using the limiters 0 Disabled 1 Enabled 0 DSP_CLK_EN Enable the clock to the core Directly controls the clock to the core It should 0 1 RW be set to 0 when the chip is used in a codec only configuration in which the core is not used Writing to any of the biquad coefficient registers Parameter Memory Address to Address 0x2BF is blocked until this bit is 1 This bit should not be used to start or stop the core while it is running because it would immediately start or stop the core clock and not allow the program to finish Instead use CORE_RUN in Register CORE_CONTROL to start or stop the core 0 Core clock disabled 1 Core clock enabled Rev 0 Page 58 of 116 1772 VALUE REGISTER 0 READ Address 0x000C Reset 0x00 Name DBREGO The core can write data to this register and the data is automatically converted to a level in dB The most common usage is to determine the rms value of a signal by taking the absolute value and then performing low pass fil
13. Bits Bit Name Settings Description Reset Access 5 4 SLEW RATE Controls how fast the PGA is slewed when changing gain 0x0 RW 00 21 5 ms 01 42 5 ms 10 85 ms 3 SLEW_PD3 PGA3 slew disable 0x0 RW 0 PGA slew enabled 1 PGA slew disabled 2 SLEW_PD2 PGA2 slew disable 0x0 RW 0 PGA slew enabled 1 PGA slew disabled 1 SLEW_PD1 PGA1 slew disable 0x0 RW 0 PGA slew enabled 1 PGA slew disabled 0 SLEW_PDO PGAO slew disable 0 0 RW 0 PGAslew enabled 1 PGA slew disabled Rev 0 Page 82 of 116 1772 10 dB BOOST REGISTER Address 0 0028 Reset 0x00 PGA_10DB_BOOST Each PGA can have an additional 10 dB gain added making the PGA gain range 2 dB to 46 dB 85 84 B3 B2 Bi BO 7 4 RESERVED RW C o PGA_0_BOOST RW NUR Buo R Boost control for PGAO E onra for M W 0 Default PGA gain set in Register PGA CONTROL 0 0 Default PGA gain set in Register 1 Additional 10 dB gain above setting in PGA CONTROL 3 Register CONTROL 0 1 Additional 10 dB gain above setting in Register PGA CONTROL 3 1 PGA 1 BOOST RW Boost control for PGA1 0 Default PGA gain set in Register PGA CONTROL 1 1 Additional 10 dB gain above setting in Register PGA CONTROL 1 2 PGA 2 BOOST RW Boost control for PGA2 0 Default PGA gain set in Register PGA CONTROL 2 1 Additional 10 dB gain above setting in Register PGA CONTROL 2 Table 69
14. Current with IOVDD 3 3 V Crystal oscillator enabled Slave Mode fs 48 kHz 2 05 mA fs 192 kHz 2 28 mA fs 8 kHz 1 99 mA Master Mode fs 48 kHz 24 192 kHz 3 62 fs 8 kHz 2 05 mA Power Down 7 Analog Current AVDD See Table 5 Power Down AVDD 1 8V 0 6 AVDD 3 3 V 13 6 DISSIPATION Operation fs 192 kHz see conditions in Table 5 All Supplies 15 5 mW Digital Supply 0 7 mW Analog Supply Includes regulated DVDD current 14 8 mW Power Down All Supplies 1 uW Rev 0 8 of 116 1772 TYPICAL POWER CONSUMPTION Typical active noise cancelling ANC settings Master clock 12 288 MHz fs 192 kHz On board regulator enabled Two analog to digital converters ADCs with PGA enabled and two ADCs configured for line input no input signal Two digital to analog converters DACs configured for differential headphone operation DAC outputs unloaded Both MICBIASO and MICBIAS1 enabled ASRCs and pulse density modulated PDM modulator disabled Core running 26 out of 32 possible instructions For total power consumption add IOVDD at 8 kHz slave current listed in Table 4 Table 5 Typical AVDD Power Consumption Typical ADCTHD N Typical HP Output Operating Voltage Power Management Setting mA THD dB AVDD IOVDD 3 3V Normal default 11 5 93 87 5 Extreme power saving 9 4 93 86 5 Power saving 9 8
15. 14 ESD Caution 14 Pin Configuration and Function Descriptions 15 Typical Performance Characteristics 17 System Block Diagrams 27 Theory of Op rdtion annn 28 System Clocking and Power Up seen 29 Clock Initialization irte ebbe qas 29 29 Clock Output otra eme vs 30 Power Sequencing eee i cei SEA 30 Signal ROU er D E 31 Input Signal Paths eet en etie iternm 32 Analog 32 Digital Microphone Input see 33 Analog to Digital Converters sse 33 Paths teret tette is 34 Analog et 34 Digital to Analog 2 22 4 09 50 34 34 Asynchronous Sample Rate Converters 35 oet rr ERR RR RARE 35 Signal Processing i e ertet dre erede tips 36 Instructions een 36 Data Memory Parameters Control Port Jet 39 DC POR c c e uu E 39 SPL cen IH EHE RS 42 Self conca n e NER a Fee 43 Multipurpose 44 Push Button Volume Controls ee 44 Limiter Compression Enable 44 Parameter Bank Switching ENEE 44 44 DSP Bypass eR ER RENE 45 Serial Data Input Output Ports 46 Tristating Unused Channels 46 Applications Information ENE
16. Figure 19 Phase vs Frequency 2 kHz Bandwidth 96 kHz Signal Path AINO to DSP Without Processing to LOUTLx 70 WI 0 10 20 30 40 50 60 70 80 10804 019 Figure 20 Group Delay vs Frequency 192 kHz Signal Path AINO to DSP Without Processing to LOUTLx 0 0 2 0 4 06 08 1 0 1 2 14 16 18 20 FREQUENCY kHz 10804 020 Figure 21 Phase vs Frequency 2 kHz Bandwidth 192 kHz Signal Path AINO to DSP Without Processing to LOUTLx 1772 RELATIVE LEVEL dB PHASE Degrees RELATIVE LEVEL dB FREQUENCY Hz Figure 22 Relative Level vs Frequency 48 kHz Signal Path AINO to ASRC to ADC_SDATAO 0 04 0 02 0 0 02 0 04 0 06 0 08 0 10 0 12 0 14 0 16 0 18 0 20 100 1k 10k 0 2 4 6 8 10 12 14 16 18 2 Figure 23 Phase vs Frequency 20 kHz Bandwidth 48 kHz Signal Path AINO to ASRC to ADC_SDATAO 20 1 0 1 4 1 6 1 8 2 0 2 2 100 1k 10k FREQUENCY Hz Figure 24 Relative Level vs Frequency 96 k
17. SYSTEM CLOCKING AND POWER UP CLOCK INITIALIZATION The ADAUI772 can generate its clocks either from an externally provided clock or from a crystal oscillator In both cases the on board PLL can be used or the clock can be fed directly to the core When a crystal oscillator is used it is desirable to use a 12 288 MHz crystal and the crystal oscillator function must be enabled in the COREN bit Address 0x0000 If the PLL is used it should always be set to output 24 576 MHz The PLL can be bypassed if a clock of 12 288 MHz or 24 576 MHz is available in the system Bypassing the PLL saves system power The MDIV and CC CDIV bits should not be changed after setup but the CLKSRC bit can be switched while the core is running The MDIV and CDIV bits should be set so that the core and internal master clock are always 12 288 MHz for example when using a 24 576 MHz external source clock or if using the PLL it is necessary to use the internal divide by 2 see Table 11 Table 11 Clock Configuration Settings CC MDIV CC CDIV Description 1 1 Divide PLL external clock by 1 Use these settings for a 12 288 MHz direct input clock Source 0 0 Divide PLL external clock by 2 Use these settings for a 24 576 MHz direct input clock source or if using the PLL PLL Bypass Setup On power up the ADAU1772 comes out of an internal reset after 12 ms The rate of the internal master clock must be set properly using t
18. The SigmaStudio software is used to program and control the core through the control port Along with designing and tuning a signal flow the tools can be used to configure all ofthe ADAU1772 registers The SigmaStudio graphical interface allows anyone with digital or analog audio processing knowledge to easily design the DSP signal flow and port it to a target application The interface also provides enough flexibility and programmability for an experienced DSP programmer to have in depth control of the design In SigmaStudio the user can connect graphical blocks such as biquad filters volume controls and arithmetic operations compile the design and load the program and parameter files into the ADAU1772 memory through the control port SigmaStudio also allows the user to download the design to an external EEPROM for self boot operation Signal processing blocks available in the provided libraries include the following e Single precision biquad filters e Second order filters e Absolute value and two input adder e Volume controls e Limiter The ADAUI772 can generate its internal clocks from a wide range of input clocks by using the on board fractional PLL The PLL accepts inputs from 8 MHz to 27 MHz For standalone operation the clock can be generated using the on board crystal oscillator The ADAUI772 is provided in a small 40 lead 6 mm x 6 mm LFCSP with an exposed bottom pad Rev 0 Page 28 of 116 1772
19. 0 00 PCM DSP Short Frame Sync Figure 92 1 1 X 00 PCM DSP Long Frame Sync Figure 93 1 0 X 01 1X don t care LRCLK N gt gt ma 2 BCLK 64 x fo LEUKEN el kt AA A A AT eA ES 24 BIT LEFT CHANNEL ws XX XX SEN RIGHT CHANNEL 10804 078 Figure 86 PS Mode 16 Bits to 24 Bits per Channel Rev 0 Page 46 of 116 1772 770777777 77 LRCLK 1 2 3 23 24 25 32 33 34 35 55 56 57 64 X KON CON FUN V N V A f X FX CERA LEFT CHANNEL RIGHT CHANNEL Figure 87 Left Justified Mode 16 Bits to 24 Bits per Channel Le 27 772 1 2 9 10 11 12 31 32 38 34 41 42 43 44 63 64 su AN A RJ 24 817 X X X Xx LEFT CHANNEL RIGHT CHANNEL Figure 88 Right Justified Mode 24 Bits per Channel 7775777 LRCLK 1 2 17 18 19 20 31 32 33 34 49 50 51 52 63 64 f NAN VN VN VN V A N YA V A NYA A YA A Y A Y K RJ 2681 es il X Sse X X se LEFT CHANNEL RIGHT CHANNEL Figure 89 Right Justified Mode 16 Bits per Channel 10804 079 10804 080 10804 081 LRCLK 256 BCLKs UU 256 BCLKs 10804 082 Ir rn TEE BCLK eae ea IA II I GA et 1d TDM MSB TDM DATA N
20. 1 7 5 RESERVED RW SSS p 0 ADDRO PU RW 4 SELFBOOT PU RW daane Pull up disable 0 Pull up enabled 1 Pull up disabled 1 ADDR1_PU RW 3 SCL_PU RW Tae eames 1 Pull up disabled 1 Pull up disabled 2 SDA_PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled Table 100 Bit Descriptions for PAD CONTROLI Bits Bit Name Settings Description Reset Access 4 SELFBOOT_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 3 SCL_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 2 SDA_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 1 ADDR1_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 0 ADDRO_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled Rev 0 Page 108 of 116 1772 DIGITAL PULL DOWN CONTROL 0 REGISTER Address 0x004A Reset 0x00 Name PAD CONTROI2 Controls the behavior of the pad Possible to enable pull down 7 RESERVED RW 6 DMIC2 3 PD RW Pull down enable 0 Pull down disabled 1 Pull down enabled 5 DMICO 1 PD RW Pull down enable 0 Pull down disabled 1 Pull down enabled 4 LRCLK PD RW Pull down enable 0 Pull down disabled 1 Pull down enabled B7 B5 B4 B3 B2 B1 AN LL 1L 1 Table 101 Bit Descriptions for PAD_CONTROL2 Pull down enable 0 Pull down dis
21. 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 3 0 PDM_SOURCEO PDM Modulator Channel 0 input source 0 2 RW 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 Rev 0 Page 64 of 116 1772 SERIAL DATA OUTPUT 0 SERIAL DATA OUTPUT 1 INPUT SELECT REGISTER Address 0x0013 Reset 0x54 Name SOUT_SOURCE_0_1 B5 B4 B3 B2 B1 BO B7 B8 7 4 SOUT SOURCE1 RW 3 0 SOUT SOURCEO RW Serial Data Output Channel 1 source Serial Data Output Channel 0 source select select 0000 Reserved 0000 Reserved 0001 Reserved 0001 Reserved 0010 Reserved 0010 Reserved 0011 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 0111 Output ASRC Channel 3 1000 Serial Input O 1000 Serial Input O 1001 Serial Input 1 1001 Serial Input 1 1010 Serial Input 2 1010 Serial Input 2 1011 Serial Input 3 1011 Serial Input 3 1100 Serial Input 4 1100 Serial Input 4 1101 Serial Input 5 1101 Serial Input 5 1110 Serial Input 6 1110 Serial Input 6 1111 Seria
22. 8 1 6 125 18 0x31 0x12 0x00 0 70 0 00 13 1 3 1625 1269 0x19 OxF5 0x04 0x59 0x06 14 4 2 6 75 62 0x33 0 00 0 4 0 00 19 2 2 5 25 3 0x2B 0x03 0x00 0x19 0x00 26 2 3 1625 1269 0x1B OxF5 0x04 0x59 0x06 27 2 3 1125 721 0 1 1 0 02 0 65 0 04 Rev 0 30 of 116 1772 SIGNAL ROUTING AINOREF AINO ADC MODULATOR DECIMATOR AIN1REF CH O HPOUTLP LOUTLP ADC MODULATOR HPOUTLN LOUTLN DECIMATOR HPOUTRP LOUTRP DMICO_1 MP4 DIGITAL CORE MICROPHONE INPUT PROCESSING HPOUTRN LOUTRN DMIC2_3 MP5 INPUTS SELECTION CORE SELECTION AIN2REF MODULATOR gt AIN2 MODULATOR AIN3REF DC O STEREO INPUT SRC DAC_SDATA OUTPUT ASRCs SERIAL ADC_SDATAO1 OUTPUT PORT SDATA1 10804 062 1 SDATAO AND PDMOUT FUNCTIONS SHARE A PHYSICAL SO ONLY ONE OF THESE FUNCTIONS BE USED AT A TIME Figure 69 Input and Output Signal Routing Rev 0 Page 31 of 116 01772 INPUT SIGNAL PATHS There are four input paths from either an ADC or a digital microphone that can be routed to the core The input sources ADC or digital microphone must be configured in pairs for example 0 and 1 2 and 3 but each channel can be routed individually The core inputs can also be s
23. L 5 10 Figure 59 Decimation Pass Band Response 96 kHz 20 40 5 10 15 20 FREQUENCY kHz 60 80 100 2 Figure 60 Total Decimation Response fs 96 kHz MAGNITUDE dBFS 10804 057 MAGNITUDE dBFS 8 10804 100 MAGNITUDE dBFS 10804 101 Rev 0 Page 25 of 116 10804 102 FREQUENCY kHz Figure 61 Decimation Pass Band Response fs 192 kHz 0 100 120 0 10 20 30 40 50 60 70 80 90 100 FREQUENCY kHz 1 E 8 10804 103 Figure 62 Total Decimation Response fs 192 kHz 2 1 0 A 2 3 4 0 5 10 15 20 2 10804 104 Figure 63 Interpolation Pass Band Response fs 96 kHz ADAUI772 MAGNITUDE dBFS MAGNITUDE dBFS b 100 120 FREQUENCY kHz Figure 64 Total Interpolation Response fs 96 kHz 2 1 0 1 2 3 4 0 5 10 15 20 FREQUENCY kHz Figure 65 Interpolation Pass Band Response fs 192 kHz MAGNITUDE dBFS 10804 105 10804 106 Rev 0 Page 26 of 116 40 60 80 100 0 1 2 3 4 5 6 7 8 9 FREQUENCY kHz Figure 66 Total Interpolation Response fs 192 kHz
24. Page 98 of 116 1772 MP6 FUNCTION SETTING REGISTER Address 0x003E Reset 0x11 Name MODE_MP6 B1 BO 85 84 B3 0 0 0 1 B7 7 5 RESERVED RW Table 90 Bit Descriptions for MODE_MP6 TT E 6 VAL RW Sets the function of Pin ADC_SDATA1 CLKOUT MP6 00000 Serial Output 1 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute DAC1 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down 10010 Clock Output Bits Bit Name Settings Description Reset Access 4 0 MODE MP6 VAL 00000 Serial Output 1 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down 10010 Clock output Sets the function of Pin ADC_SDATA1 CLKOUT MP6 0x11 RW Rev 0 Page 99 of 116 ADAUI772 PUSH BUTTON VOLUME SETTINGS REGISTER Address 0x003F Reset 0x00 Name
25. There are two parameter banks available Each bank can hold full set of 160 parameters 32 filters x 5 coefficients Users can switch between Bank A and Bank B allowing for two sets of parameters to be saved in memory and switched on the fly while the codec is running Bank switching can be achieved by writing to the CORE_CONTROL register Address 0x0009 or by using the multipurpose push button switches but not using a combination of the two Parameters in the active bank should not be updated while the core is running this will likely result in noises on the outputs Parameters are assigned to instructions in the order in which the instructions are instantiated in the code The instruction types that use parameters are the biquad filters and limiters Table 17 shows the addresses of each parameter in Bank A that are associated with each of the 32 instructions and Table 18 shows the addresses of each parameter in Bank B Table 16 shows the addresses of the LSB aligned 10 bit program words Table 16 Program Addresses Instruction Instruction Address 0 0 0080 1 0 0081 2 0 0082 3 0 0083 4 0 0084 5 0 0085 6 0 0086 7 0 0087 8 0 0088 9 0 0089 10 0 008 11 0x008B 12 0 008 13 14 15 16 0 0090 17 0 0091 18 0 0092 19 0 0093 20 0 0094 21 0 0095 22 0 0096 23 0 0097 24 0 0098 25 0 0099 26 0 009 27 0 0098 28 0 009 29 0x009D 30 9 31
26. 0 4 500 0 2 450 0 400 02 5 m 350 gt 300 0 6 5 250 2 200 3 1 0 9 42 D 150 1 4 100 1 6 50 1 8 0 E 100 10k 5 4 12 16 20 24 28 32 36 40 2 8 FREQUENCY kHz 8 Figure 48 Relative Level vs Frequency Figure 51 Group Delay vs Frequency 96 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing 96 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing to ASRC to ADC_SDATAO to ASRC to ADC_SDATAO Rev 0 Page 23 of 116 01772 200 10 5 0 0 5 200 10 400 20 T o 25 600 _30 800 gt 35 a 40 1000 45 2 2 1200 55 60 1400 ep 70 1600 75 1800 80 85 2000 90 y 4 8 12 16 20 24 28 32 36 40 0 02 04 06 08 10 12 14 16 18 20 5 FREQUENCY kHz 8 FREQUENCY kHz 8 Figure 52 Phase vs Frequency 40 kHz Bandwidth Figure 55 Phase vs Frequency 2 kHz Bandwidth fs 96 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing f 96 kHz Signal Path DAC_SDATA to A
27. 0000 Reserved 0000 Reserved 0001 Reserved 0001 Reserved 0010 Reserved 0010 Reserved 0011 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 0111 Output ASRC Channel 3 1000 Serial Input 0 1000 Serial Input O 1001 Serial Input 1 1001 Serial Input 1 1010 Serial Input 2 1010 Serial Input 2 1011 Serial Input 3 1011 Serial Input 3 1100 Serial Input 4 1100 Serial Input 4 1101 Serial Input 5 1101 Serial Input 5 1110 Serial Input 6 1110 Serial Input 6 1111 Serial Input 7 1111 Serial Input 7 Table 49 Bit Descriptions for SOUT SOURCE 2 3 Bits Bit Name Settings Description Reset Access 7 4 SOUT SOURCE3 Serial Data Output Channel 3 source select 0 7 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 3 0 SOUT SOURCE2 Serial Data Output Channel 2 source select 0x6 RW 0000 Reserved 0001 Reserved 0010 Reserved Rev 0 Page 66 of 116 01772 Bits Bit Name Settings Description Reset Access 0011 Reser
28. 0x001C Reset 0x19 Name CONTROLI Table 57 7 6 RESERVED RW 5 RESERVED RW 4 ADC3 MUTE RW Mute ADC3 0 Unmuted 1 Muted B7 B8 B5 B4 B3 B2 B1 BO 1 0 ADC 2 3 FS RW Sets ADC sample rate 00 96 kHz 01 192 kHz 10 Reserved 11 Reserved 2 RESERVED RW 3 ADC2 MUTE RW Mute ADC2 0 Unmuted 1 Muted Bit Descriptions for ADC CONTROLI Bits Bit Name Settings Description Reset Access 4 ADC3 MUTE Mute ADC3 Unmuted Muted Ox1 RW ADC2 MUTE Mute ADC2 Muting is accomplished by setting the volume control to maximum attenuation This bit has no effect if volume control is bypassed Unmuted Muted Ox1 RW 1 0 ADC 2 3 FS Sets ADC sample rate 96 kHz 192 kHz Reserved Reserved Ox1 RW Rev 0 Page 74 of 116 1772 ADCO ADC1 CONTROL 1 REGISTER Address 0x001D Reset 0x00 ADC_CONTROL2 B7 B5 B4 B3 B2 To o o 7 RESERVED RW 6 5 HP 0 1 EN RW High pass filter settings 00 Off 01 1 Hz 10 4 Hz 11 8 Hz 4 DMIC_POLO RW Selects microphone polarity 0 0 positive 1 negative 1 1 positive 0 negative Table 58 Bit Descriptions for ADC_CONTROL2 T m ADC 0 EN RW Enable ADCO 0 Disable 1 Enable 1 ADC 1 EN RW Enable ADC1 0 Disable 1 Enable 2 DCM 0 1 RW Sets the input source to ADCs or
29. 1 dBFS AVDD 1 8 V 27 mW 75 dB 1 dBFS AVDD 3 3 V Po 90 mW 83 dB 24 Load 2 dBFS AVDD 1 8 V Po 28 mW 75 dB 1 dBFS AVDD 3 3 V Po 118 mW 77 16 Load 3 dBFS AVDD 1 8 V 33 mW 75 dB 1 dBFS AVDD 3 3 V 175 mW 83 dB Headphone Output Power 32 Q Load AVDD 1 8 V lt 0 1 THD N 32 5 mW AVDD 3 3 V 0 196 THD 111 8 mW 24 Q Load AVDD 1 8 V 0 196 THD N 37 6 mW AVDD 3 3 V 0 196 THD 148 3 mW 16 Q Load AVDD 1 8 V lt 0 1 THD N 41 5 mW AVDD 3 3 V lt 0 1 THD 189 2 mW Gain Error Headphone mode 0 25 Offset Error 0 1 mV Interchannel Isolation 1 kHz 0 dBFS input signal 100 dB Power Supply Rejection Ratio CM capacitor 22 uF 100 mV p p at 1 kHz 73 dB CM REFERENCE CM pin Common Mode Reference Output AVDD 2 V Common Mode Source Impedance 5 REGULATOR Line Regulation 1 mV V Load Regulation 6 mV mA Dynamic range is the ratio of the sum of noise and harmonic power in the band of interest with a 60 dBFS signal present to the full scale power level in decibels SNRis the ratio of the sum of all noise power in the band of interest with no signal present to the full scale power level in decibels 3 These specifications are with 4 7 uF decoupling and 5 0 load on pin CRYSTAL AMPLIFIER SPECIFICATIONS Supply voltages AVDD IOVDD 1 8 V DVDD 1 1 V unless otherwise noted Table 2 Parameter Test Conditions Comments Min Typ Max Unit
30. 15 8 Register memory address 7 0 data data 1 Continues to end of data su Um ru unu un wr 10804 074 Figure 81 SPI Write to ADAU1772 Clocking Single Write Mode 8s _ oe owt oa 10804 075 Figure 82 SPI Read from ADAU1772 Clocking Single Read Mode Rev 0 Page 42 of 116 1772 SELF BOOT The ADAU1772 boots up from an EEPROM over the bus when the SELFBOOT pin is set high at power up and the PD pin is set high The state of the SELFBOOT pin is checked only when the ADAU1772 comes out of a reset via the PD pin and the EEPROM is not used after a self boot is complete During booting ensure that there is a stable DVDD in the system The PD pin should remain high during the self boot operation The master SCL clock output from the ADAU17722 is derived from the input clock on XTALI MCLKIN A divide by 64 circuit ensures that the SCL output frequency during the self boot operation is never greater than 400 kHz for most input clock frequencies With the external master clock to the ADAUI772 being between 12 MHz and 27 MHz the SCL frequency ranges from 176 kHz to 422 kHz If the self boot EEPROM is not rated for operation above 400 kHz be sure to use a master clock that is no faster than 25 6 MHz Table 25 shows the list of instructions that are possible during an ADAUI772 self boot The 0x01 and 0x05 ins
31. Bit Descriptions for 10DB BOOST Bits Bit Name Settings Description Reset Access 3 PGA 3 BOOST Boost control for PGA3 0 0 RW 0 Default PGA gain set in Register PGA_CONTROL_3 1 Additional 10 dB gain above setting in Register PGA_CONTROL_3 2 PGA 2 BOOST Boost control for PGA2 0 0 RW 0 Default PGA gain set in Register PGA_CONTROL_2 1 Additional 10 dB gain above setting in Register PGA_CONTROL_2 1 PGA 1 BOOST Boost control for 1 0 0 RW 0 Default PGA gain set in Register PGA_CONTROL_1 1 Additional 10 dB gain above setting in Register PGA_CONTROL_1 0 0 5 Boost control for PGAO 0 0 RW 0 Default PGA gain set in Register PGA_CONTROL_O 1 Additional 10 dB gain above setting in Register PGA_CONTROL_O Rev 0 Page 83 of 116 ADAUI772 INPUT AND OUTPUT CAPACITOR CHARGING REGISTER Address 0x0029 Reset 0x3F Name POP_SUPPRESS B7 B8 B5 B4 B3 B2 0 DISO RW Disable pop suppression 7 6 RESERVED RW 5 HP_POP_DIS1 RW Disable pop suppression on Headphone 1 Disabled Output 1 0 Enabled 1 PGA_POP_DIS1 RW 1 Disabled Disable pop suppression on PGA1 0 Enabled 4 HP_POP_DISO RW 1 Disabled Disable pop suppression on Headphone Output 0 2 PGA_POP_DIS2 RW 0 Enabled Disable pop suppression on PGA2 inpu 1 Disabled 0 Enabled 1 Disabled 3 PGA_POP_DIS3 RW Disable pop su
32. Jitter 270 500 ps Frequency Range 8 27 MHz Load Capacitance 20 pF Rev 0 Page 7 of 116 01772 DIGITAL INPUT OUTPUT SPECIFICATIONS 40 lt Ta lt 85 C IOVDD 3 3 V 1096 and 1 8 5 10 Table 3 Parameter Test Conditions Comments Min Typ Max Unit Input Voltage High Vin IOVDD 3 3 2 0 IOVDD 1 81 1 1 V Input Voltage Low IOVDD 3 3 0 8 IOVDD 1 8 V 0 45 V Input Leakage IOVDD 3 3 V lin at Viu 2 0 V 10 at Vi 0 8 V 10 IOVDD 1 8 liu at 1 1 V 10 at Vi 0 45 V 10 Output Voltage High with Low Drive Strength lou 1 IOVDD 0 6 V Output Voltage High with High Drive Strength lou 3 mA IOVDD 0 6 V Output Voltage Low Voi with Low Drive Strength lo 1 mA 0 4 V Output Voltage Low with High Drive Strength lo 3mA 0 4 V Input Capacitance 5 pF POWER SUPPLY SPECIFICATIONS Supply voltages AVDD IOVDD 1 8 V DVDD 1 1 V unless otherwise noted PLL disabled direct master clock Table 4 Parameter Test Conditions Comments Min Typ Max Unit SUPPLIES AVDD Voltage 1 71 1 8 3 63 V DVDD Voltage 1 045 1 1 1 98 V IOVDD Voltage 1 71 1 8 3 63 V Digital Current with IOVDD 1 8 V Crystal oscillator enabled Slave Mode fs 48 kHz 0 35 192 kHz 0 49 fs 8 kHz 0 32 mA Master Mode fs 48 kHz 0 53 mA fs 192 kHz 1 18 mA fs 8 kHz 0 35 mA Power Down 0 Digital
33. PB VOL SET This register must be written before Bits VOL CONV VAL are set to something other than the default value Otherwise the push button volume control is initialized to 96 dB B7 B5 B4 B3 B2 B1 BO 7 3 PB_VOL_INIT_VAL RW z HOLD RW Sets the initial volume of the push button volume control 00000 0 0 dB 00001 1 5 dB 11111 46 5 dB 000 150 ms 001 300 ms 010 450 ms 011 600 ms 100 900 ms 101 1200 ms Table 91 Bit Descriptions for PB VOL SET Sets the length of time that the button is held before the volume ramp begins Bits Bit Name Settings Description Reset Access 7 3 PB VOL INIT VAL Sets the initial volume of the push button volume control Each increment of 0x00 RW this register attenuates the level by 1 5 dB from 0 dB to 46 5 dB 00000 0 0 dB 00001 1 5 dB 11111 46 5 dB 2 0 HOLD Sets the length of time that the button is held before the volume ramp 0x0 RW begins 000 150 ms 001 300 ms 010 450 ms 011 600 ms 100 900 ms 101 1200 ms Rev 0 Page 100 of 116 1772 PUSH BUTTON VOLUME CONTROL ASSIGNMENT REGISTER Address 0x0040 Reset 0x87 Name PB VOL CONV 7 6 GAINSTEP RW Sets the gain step for each click of the volume control button 00 0 375 dB click B7 B8 B F 000 ADC0 and ADC1 001 ADC2 and ADC3 2 0
34. RESERVED RW Table 39 Bit Descriptions for CORE CONTROL Bits Bit Name Settings Description Reset Access 7 ZERO STATE Zeroes the state of the data memory during bank switching When 0x0 RW switching active parameter banks between two settings zeroing the state of the bank prevents the new filter settings from being active on old data that is recirculating in filters Zeroing the state may prevent filter instability or unwanted noises upon bank switching 0 Do notzero state during bank switch 1 Zero state during back switch 6 5 BANK SL Selects active filter bank 0 0 RW 00 Bank A active 01 Bank B active 10 Reserved 11 Reserved 2 1 CORE FS This bit sets the core sample rate This setting should not be changed while the core is running CORE RUN must be set to 0 for this setting to be updated 00 Reserved 01 96 kHz 10 192 kHz 11 Reserved 0 CORE RUN Run bit for the core This bit should only be enabled when the program 0x0 RW and parameters are loaded and the sample rate settings have been set CORE RUN starts and stops the core at the beginning of the program 0 Core off 1 Coreon Rev 0 Page 57 of 116 ADAUI772 FILTER ENGINE AND LIMITER CONTROL REGISTER Address 0x000B Reset 0x03 Name CORE_ENABLE Disabling the limiter only disables the attack operation The decay operation is always active so a limiter can be safely disabled while it performs gain adjustments
35. TALKTHRU 7 0 RESERVED TALKTHRU PATH 0x00 RW 0 002 TALKTHRU 7 0 TALKTHRU GAINO VAL 0x00 RW 0 002 TALKTHRU GAINT 7 0 TALKTHRU GAINT VAL 0x00 RW 0x002D MIC BIAS 7 0 RESERVED MIC EN1 MIC ENO RESERVED RESERVED GAIN1 MIC GAINO 0x00 RW 0 002 DAC CONTROL1 7 0 RESERVED DAC POL MUTE DACO_MUTE RESERVED DACI EN 0 18 0x002F DACO VOLUME 7 0 DAC 0 VOL 0x00 RW 0x0030 DAC1 VOLUME 7 0 DAC 1 VOL 0x00 RW 0x0031 OP STAGE MUTES 7 0 RESERVED HP MUTE R HP MUTE L OxOF RW 0x0032 SAI 0 7 0 SDATA FMT SAI SER PORT FS 0x00 RW 0x0033 SAI 1 7 0 TDM TS BCLK TDMC LR MODE LR POL SAI MSB BCLKRATE BCLKEDGE SAI MS 0x00 RW 0x0034 SOUT CONTROLO 7 0 TDM7 DIS TDM6 DIS TDM5 DIS TDMA4 DIS TDM3 DIS TDM2 DIS TDMI DIS TDMO DIS 0x00 RW 0x0036 OUT 7 0 RESERVED PDM CTRL PDM CH PDM EN 0x00 RW 0x0037 PDM PATTERN 7 0 PATTERN 0x00 RW 0x0038 MODE MPO 7 0 RESERVED MODE MPO VAL 0x00 RW 0x0039 MODE MP1 7 0 RESERVED MODE MP1 VAL 0 10 0x003A MODE MP2 7 0 RESERVED MODE MP2 VAL 0x00 RW 0 003 MODE MP3 7 0 RESERVED MODE MP3 VAL 0x00 RW 0x003C MODE MP4 7 0 RESERVED MODE MP4 VAL 0x00 RW Rev 0 Page 50 of 116 01772 Bits Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW 0x003D _ 5 7 0 RESERVED MO
36. kHz Figure 30 Phase vs Frequency 80 kHz Bandwidth 192 kHz Signal Path AINO to ASRC to ADC_SDATAO PHASE Degrees de b L L 1 O Qi O Q O Q O o O Q O o O LG 10804 027 GROUP DELAY ys 10804 028 PHASE Degrees 10804 029 Rev 0 Page 20 of 116 0 0 2 0 4 0 6 0 8 10 1 2 1 4 16 18 2 FREQUENCY kHz Figure 31 Phase vs Frequency 2 kHz Bandwidth fs 96 kHz Signal Path AINO to ASRC to ADC_SDATAO 300 280 260 240 220 200 180 160 140 120 10 20 30 40 50 60 70 80 FREQUENCY kHz Figure 32 Group Delay vs Frequency 192 kHz Signal Path AINO to ASRC to ADC_SDATAO 0 0 2 0 4 06 08 10 12 14 16 18 20 FREQUENCY kHz Figure 33 Phase vs Frequency 2 kHz Bandwidth 192 kHz Signal Path AINO to ASRC to ADC_SDATAO 10804 030 10804 031 10804 032 01772 RELATIVE LEVEL dB PHASE Degrees RELATIVE LEVEL dB FREQUENCY Hz Figure 34 Relative Level vs Frequency 48 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY kHz Figure 35 Phase vs
37. 0 Powered down 1 Powered up Table 95 Bit Descriptions for DECIM PWR MODES Bits Bit Name Settings Description Reset Access 7 DEC 3 EN Control power to the ASRC3 decimator 0 0 RW 0 Powered down 1 Powered up 6 DEC 2 EN Control power to the ASRC2 decimator 0 0 RW 0 Powered down 1 Powered up 5 DEC_1_EN Control power to the ASRC1 decimator 0 0 RW 0 Powered down 1 Powered up 4 DEC 0 Control power to the 5 decimator 0 0 RW 0 Powered down 1 Powered up 3 SINC_3_EN ADC3 filter power control 0 0 RW 0 Powered down 1 Powered up 2 SINC 2 EN ADC2 filter power control 0 0 RW 0 Powered down 1 Powered up 1 SINC_1_EN ADC1 filter power control 0 0 RW 0 Powered down 1 Powered up 0 SINC 0 EN ADCO filter power control 0 0 RW 0 Powered down 1 Powered up Rev 0 Page 104 of 116 1772 ASRC INTERPOLATOR AND DAC MODULATOR POWER CONTROL REGISTER Address 0x0045 Reset 0x00 Name INTERP_PWR_MODES B7 5 B4 B3 7 4 RESERVED RW 3 MOD 1 EN RW DAC Modulator 1 enable 0 Powered down 1 Powered up Table 96 Bit Descriptions for INTERP PWR MODES tS 0 INT 0 EN RW ASRC Interpolator 0 enable 0 Powered down 1 Powered up 1 INT 1 EN RW ASRC Interpolator 1 enable 0 Powered down 1 Powered up 2 MOD 0 EN RW DAC Modulator 0 enable 0 Powered down 1 Powered up
38. 0x01F9 0x0219 26 0x019A 0x01BA 0x01DA 0x01FA 0x021A 27 0x019B 0x01BB 0x01DB 0x01FB 0x021B 28 0 019 0x01BC 0x01DC 0 021 29 0x019D 0x01BD 0x01DD 0x01FD 0x021D 30 0 019 0x01DE 0 021 31 0 019 0x01BF 0x01DF 0x01FF 0x021F Rev 0 Page 38 of 116 1772 CONTROL PORT The ADAU1772 has both a 4 wire SPI control port and a 2 wire bus control port Each can be used to set the memories and registers The IC defaults to mode but can be put into SPI control mode by pulling the 55 pin low three times The control port is capable of full read write operation for all addressable memories and registers Most signal processing parameters are controlled by writing new values to the param eter memories using the control port Other functions such as mute and input output mode control are programmed through the registers All addresses can be accessed in either single address mode or burst mode The first byte Byte 0 of a control port write contains the 7 bit IC address plus the R W bit The next two bytes Byte 1 and Byte 2 are the 16 bit subaddress of the memory or register location within the ADAU1772 All subsequent bytes starting with Byte 3 contain the data such as register data program data or parameter data The number of bytes per word depends on the type of data that is being written Table 19 shows the word length of the ADAUI17725 different
39. 1 0010 Core Output 2 0011 Core Output 3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 Rev 0 Page 63 of 116 01772 MODULATOR INPUT SELECT REGISTER Address 0x0012 Reset 0x32 Name PDM_SOURCE_0_1 7 4 PDM_SOURCE1 RW PDM_SOURCEO RW Modulator Channel 1 input source 0000 0001 0010 0011 Core Output 0 Core Output 1 Core Output 2 Core Output 3 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input ASRC Channel 0 Input ASRC Channel 1 B B5 B4 B3 B2 B1 BO 0011 Table 47 Bit Descriptions for PDM_SOURCE_0_1 Core Output 0 Core Output 1 Core Output 2 Core Output 3 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input ASRC Channel 0 Input ASRC Channel 1 Modulator Channel 0 input source 0000 0001 0010 Bits Bit Name Settings Description Reset Access 7 4 PDM_SOURCE1 PDM Modulator Channel 1 input source 0x3 RW 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved
40. 10 10804 107 ADAU1772 SYSTEM BLOCK DIAGRAMS 10 0 1017 Te 2 FAO 4 LEFT_AUDIO gt RIGHT MICROPHONE RIGHT_AUDIO 10 B 10pF Figure 67 ADAU1772 System Block Diagram with Analog Microphones Self Boot Mode DMICO_1 MP4 DMIC2_3 MP5 MICBIASO MICBIAS1 AINO AINOREF AIN1 E SOURCE BCLK MP2 DAC SDATA MPO ADC SDATAO PDMOUT MP1 ADC SDATA1 CLKOUT MP6 Rev 0 Page 27 of 116 LEFT HEADPHONE RIGHT HEADPHONE CONTROL INTERFACE SWITCHES AND POTENTIOMETERS WN 1000 22 1 10804 060 ADAUI772 THEORY OF OPERATION The ADAUI772 is a low power audio codec with an optimized audio processing core making it ideal for noise cancelling applications that require high quality audio low power small size and low latency The four ADC and two DAC channels each have an SNR of at least 96 dB and a THD of atleast 88 dB The serial data port is compatible with PS left justified right justified and TDM modes with tristating for interfacing to digital audio data The operating voltage range is 1 8 V to 3 63 V with an on board regulator generating the internal digital supply voltage If desired the regulator can be powered down and the vol
41. 10 ns LRCLK setup time to BCLK rising slave mode Du 10 ns LRCLK hold time from BCLK rising slave mode tss 5 ns DAC_SDATA setup time to BCLK rising master and slave modes 5 5 ns DAC_SDATA hold time from BCLK rising master and slave modes tts 10 ns BCLK falling to LRCLK timing skew master mode 0 34 ns ADC_SDATAx delay time from BCLK falling master and slave modes tsorp 30 ns BCLK falling to SDATAx driven TDM tristate mode tsorx 30 ns BCLK falling to SDATAx tristated in tristate mode SPI PORT 6 25 2 SCLK frequency teceL 80 ns SCLK pulse width low tcceH 80 ns SCLK pulse width high tas 5 ns SS setup time to SCLK rising 100 ns SS hold time from SCLK rising 80 ns SS pulse width high tcps 10 ns MOSI setup time to SCLK rising 10 ns MOSI hold time from SCLK rising 101 ns MISO delay time from SCLK falling PORT 400 kHz SCL frequency 0 6 us SCL high 1 3 us SCL low tscs 0 6 us SCL rise setup time to SDA falling relevant for repeated start condition tscr 250 ns SCL and SDA rise time 400 pF tscH 0 6 us SCL fall hold time from SDA falling relevant for start condition 105 100 ns SDA setup time to SCL rising tscr 250 ns SCL fall time 400 pF tspr 250 ns SDA fall time 400 pF terr 0 6 us SCL rise setup time to SDA rising relevant for stop condition EEPROM SELF BOOT tscHE 26 x tup 70 ns S
42. 10804 083 Figure 91 8 TDM Mode Pulse LRCLK Rev 0 Page 47 of 116 01772 LRCLK 1 2 3 4 16 17 18 19 20 32 33 34 NX NANA A AV A V LEFT CHANNEL RIGHT CHANNEL Figure 92 PCM DSP Mode 16 Bits per Channel Short Frame Sync 10804 084 CC 17 D 1e m IA 3 me N V V A V A NY AV A V A Y ANA A Y KO X we K X XA ie X mas X LEFT CHANNEL RIGHT CHANNEL Figure 93 PCM DSP Mode 16 Bits per Channel Long Frame Sync 10804 085 Rev 0 Page 48 of 116 1772 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 0 1 uF capacitor The connections to each side of the capacitor should be as short as possible and the trace should be routed on a single layer with no vias For maximum effectiveness locate the capacitor equidistant from the power and ground pins or slightly closer to the power pin if equidistant placement is not possible Thermal connections to the ground planes should be made on the far side of the capacitor Each supply signal on the board should also be bypassed with a single bulk capacitor 10 to 47 VDD GND CAPACITOR 10804 086 TO GND Figure 94 Recommended Power Supply Bypass Capacitor Layout LAYOUT Pin 24 is the AVDD supply for the headphone amplifiers If the
43. 11 Power saving Table 98 Bit Descriptions for BIAS CONTROLI Bits Bit Name Settings Description Reset Access 6 CBIAS_DIS Central analog bias circuitry Higher bias currents result in higher 0x0 RW performance 0 Powered up 1 Powered down 0 Page 106 of 116 01772 Bits Bit Name Settings Description Reset Access 5 4 AFE_IBIAS23 Analog Front End 2 and Analog Front End 3 bias current setting Higher 0 0 RW bias currents result in higher performance 00 Normal operation default 01 Extreme power saving 10 Enhanced performance 11 Power saving 3 2 5 Microphone input bias current setting Higher bias currents result in 0 0 RW higher performance 00 Normal operation default 01 Extreme power saving 10 Enhanced performance 11 Power saving 1 0 DAC_IBIAS DAC bias current setting Higher bias currents result in higher performance 0 0 RW 00 Normal operation default 01 Power saving 10 Superior performance 11 Enhanced performance DIGITAL PIN PULL UP CONTROL 0 REGISTER Address 0x0048 Reset 0x7F Name PAD CONTROLO Controls the behavior of the pad Possible to enable pull up 7 RESERVED RW 6 DMIC2 3 PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled 5 1 PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled 4 LRCLK PU RW Pull up disable 0 Pull up enab
44. 93 86 5 Enhanced performance 12 65 93 90 5 AVDD IOVDD 1 8V Normal default 9 37 86 91 Extreme power saving 7 40 84 5 87 Power saving 7 78 84 5 87 5 Enhanced performance 10 4 86 94 5 DIGITAL FILTERS Table 6 Parameter Test Conditions Comments Min Typ Max Unit ADC INPUT TO DAC OUTPUT PATH Pass Band Ripple DC to 20 kHz fs 192 kHz 0 02 dB Group Delay fs 192 kHz 38 Us SAMPLE RATE CONVERTER Pass Band LRCLK lt 63 kHz 0 0 475 xfs kHz 63 kHz lt LRCLK lt 130 kHz 0 0 4286 fs LRCLK gt 130 kHz 0 0 4286 x fs Pass Band Ripple Upsampling 96 kHz 0 27 0 05 Upsampling 192 kHz 0 06 0 05 Downsampling 96 kHz 0 0 07 dB Downsampling 192 kHz 0 0 07 dB Input Output Frequency Range 8 192 kHz Dynamic Range 100 dB Total Harmonic Distortion Noise 90 Startup Time 15 ms PDM MODULATOR Dynamic Range A Weighted 112 dB Total Harmonic Distortion Noise 92 Rev 0 9 of 116 01772 DIGITAL TIMING SPECIFICATIONS 40 lt Ta lt 85 C IOVDD 1 71 V to 3 63 V DVDD 1 045 V to 1 98 V Table 7 Digital Timing Limit Parameter Tmin Tmax Unit Description MASTER CLOCK 37 125 ns MCLKIN period 8 MHz to 27 MHz input clock using PLL 77 82 ns Internal MCLK period direct MCLK and PLL output divided by 2 SERIAL PORT teL 40 ns BCLK low pulse width master and slave modes teu 40 ns BCLK high pulse width master and slave modes tis
45. ASRC Channel 0 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 0111 Output ASRC Channel 3 1000 Serial Input O 1000 Serial Input O 1001 Serial Input 1 1001 Serial Input 1 1010 Serial Input 2 1010 Serial Input 2 1011 Serial Input 3 1011 Serial Input 3 1100 Serial Input 4 1100 Serial Input 4 1101 Serial Input 5 1101 Serial Input 5 1110 Serial Input 6 1110 Serial Input 6 1111 Serial Input 7 1111 Serial Input 7 Table 51 Bit Descriptions for SOUT SOURCE 6 7 Bits Bit Name Settings Description Reset Access 7 4 SOUT SOURCE7 Serial Data Output Channel 7 source select 0 7 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved Rev 0 Page 68 of 116 ADAU1772 Bits Bit Name Settings Description Reset Access 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input O 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 3 0 SOUT SOURCE6 Serial Data Output Channel 6 source select 0x6 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial
46. B2 B1 BO 0 0 0 0 0 0 0 0 7 1 RESERVED RW 0 LOCK R Flag to indicate if the PLL is locked This bit is read only 0 PLL unlocked 1 PLL locked Table 36 Bit Descriptions for PLL_CTRL5 Bits Bit Name Settings Description Reset Access 0 LOCK Flag to indicate if the PLL is locked This bit is read only 0 0 0 unlocked locked CLKOUT SETTING SELECTION REGISTER Address 0x0007 Reset 0x00 Name CLKOUT_SEL When Pin ADC_SDATA1 CLKOUT MP6 is set to clock output mode the frequency of the output clock is set here CLKOUT can be used to provide a master clock to another IC the clock for digital microphones or as the clock for the PDM output stream The 12 MHz 24 MHz setting is used when clocking another IC 3 MHz 6 MHz for PDMOUT and 1 5 MHz 3 MHz when clocking digital microphones The CLKOUT frequency is derived from the master clock frequency which is assumed to and always should be 12 288 MHz The 12 288 MHz and 24 576 MHz output modes are not functional if PDM is enabled Register PDM_OUT Bits 1 0 7 3 RESERVED RW B7 B8 B5 B4 B3 B2 Rev 0 55 of 116 B1 BO 2 0 CLKOUT_FREQ RW CLKOUT pin frequency 000 Master clock 2 24 576 MHz 001 Master clock 12 288 MHz 010 Master clock 2 6 144 MHz 011 Master clock 4 3 072 MHz 100 Master clock 8 1 536 MHz 111 Clock output off 0 ADAUI772 Table 37 Bit Descriptions f
47. D IN Address 1 ADDR1 SPI Data Input MOSI 4 ADDRO SS D IN Address 0 ADDRO SPI Latch Signal SS This pin must go low at the beginning of an SPI transaction and high at the end of a transaction Each SPI transaction can take a different number of SCLK cycles to complete depending on the address and read write bit that are sent at the beginning of the SPI transaction 5 SELFBOOT D IN Self Boot Pull this pin up to IOVDD at power up to enable the self boot mode 6 MICBIASO A OUT Bias Voltage for Electret Microphone Decouple with a 1 uF capacitor 7 MICBIAS1 A OUT Bias Voltage for Electret Microphone Decouple with a 1 uF capacitor 8 AINOREF A IN ADCO Input Reference This reference pin should be ac coupled to ground with a 10 capacitor 9 AINO A IN ADCO Input 10 AVDD PWR 1 8 V to 3 3 V Analog Supply This pin should be decoupled to AGND with a 0 1 uF capacitor 11 AGND PWR Analog Ground The AGND and DGND pins can be tied directly together in a common ground plane AGND should be decoupled to AVDD with a 0 1 uF capacitor 12 CM A OUT AVDD 2 V Common Mode Reference A 10 uF to 47 decoupling capacitor should be connected between this pin and ground to reduce crosstalk between the ADCs and DACs The material of the capacitors is not critical This pin can be used to bias external analog circuits as long as they are not drawing current from CM for example the noninverting input of an op amp Rev 0 Page
48. Input O 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 ADC SDATAO ADC SDATA1 CHANNEL SELECT REGISTER Address 0x0017 Reset 0x04 ADC SDATA CH 7 4 RESERVED RW B8 B5 B4 B3 B2 B1 BO B7 Been 1 0 ADC SDATAO ST RW SDATAO Output Channel Output Select 00 Channel 0 01 Channel 2 10 Channel 4 11 Channel 6 3 2 ADC SDATA1 ST RW SDATA1 Output Channel Output Select 00 Channel 0 01 Channel 2 10 Channel 4 11 Channel 6 Rev 0 Page 69 of 116 ADAUI772 Table 52 Bit Descriptions for ADC_SDATA_CH Bits Bit Name Settings Description Reset Access 3 2 ADC_SDATA1_ST SDATA1 output channel output select Selects the output channel at which 0 1 RW ADC_SDATA1 starts to output data The output port sequentially outputs data following this start channel according to the setting of Bit SAI 00 Channel 0 01 Channel 2 10 Channel 4 11 Channel 6 1 0 ADC SDATAO ST SDATAO output channel output select Selects the output channel at which 0x0 RW ADC SDATAO starts to output data The output port sequentially outputs data following this start channel according to the setting of Bit SAI 00 Channel 0 01 Channel 2 10 Channel 4 11 Channel 6 OUTPUT ASRCO OUTPUT ASRC1 SOURCE REGISTER Address 0x0018 Reset 0x10 Name ASRCO SOURC
49. PB_VOL_CONV_VAL RW Converters controlled by push button volume 01 1 5 dB dick 010 All ADCs 10 3 0 4 011 DACO and DAC1 11 4 5 dBiclick 100 DACO 5 3 RAMPSPEED RW 101 DAC1 Sets the speed in dB sec at which the 110 Reserved volume control will ramp when a button is 111 None held 000 60 dB sec 001 48 dB sec 010 36 dB sec 011 30 dB sec 100 24 dB sec 101 18 dB sec 110 12 dB sec 111 6 dB sec Table 92 Bit Descriptions for PB_VOL_CONV Bits Bit Name Settings Description Reset Access 7 6 GAINSTEP Sets the gain step for each press of the volume control button 0x2 RW 00 0 375 dB press 01 1 5 dB press 10 3 0 dB press 11 4 5 dB press 5 3 RAMPSPEED Sets the speed in dB sec at which the volume control ramps when a 0x0 RW button is pressed 000 60 dB sec 001 48 dB sec 010 36 dB sec 011 30 dB sec 100 24 dB sec 101 18 dB sec 110 12 dB sec 111 6 dB sec 2 0 PB_VOL_CONV_VAL Converters controlled by push button volume The push button volume 0x7 RW control is enabled when these bits are set to something other than the default setting 111 When set to 111 the push button volume is disabled and the converter volumes are set by the ADCx_VOLUME and DACx_VOLUME registers 000 ADCO and ADC1 001 ADC2 and ADC3 010 All ADCs 011 and 100 101 110 111 None default Rev 0 Page 101 of 116
50. R Pull down enable 3 RW 0 Pull down disabled Pull down enable 1 Pull down enabled 0 Pull down disabled 1 Pull down enabled 2 SDA PD RW Pull down enable 0 Pull down disabled 1 Pull down enabled Table 102 Bit Descriptions for PAD CONTROL3 Bits Bit Name Settings Description Reset Access 4 SELFBOOT PD Pull down enable 0 0 RW 0 Pull down disabled 1 Pull down enabled 3 SCL_PD Pull down enable 0 0 RW 0 Pull down disabled 1 Pull down enabled 2 SDA_PD Pull down enable 0 0 RW 0 Pull down disabled 1 Pull down enabled 1 ADDR1_PD Pull down enable 0 0 RW 0 Pull down disabled 1 Pull down enabled 0 ADDRO_PD Pull down enable 0 0 RW 0 Pull down disabled 1 Pull down enabled Rev 0 110 of 116 1772 DIGITAL DRIVE STRENGTH CONTROL 0 REGISTER Address 0x004C Reset 0x00 Name DAD CONTROLA 7 RESERVED RW 6 RESERVED RW 5 RESERVED RW 4 LRCLK_DRV RW Drive strength control 0 Low drive strength 1 High drive strength B5 B4 B3 B2 B1 BO s To Ts L ET Table 103 Bit Descriptions for PAD CONTROLA4 0 RESERVED RW 1 ADC SDATAO DRV RW Drive strength control 0 Low drive strength 1 High drive strength 2 ADC SDATA1 DRV RW Drive strength control 0 Low drive strength 1 High drive strength BCLK DRM RW Drive strength control 0 Low
51. Reserved 1 0 PDM_EN Enable PDM output on Pin PDMOUT 0 0 RW 00 disabled 01 PDM left signal in both PDM channels 10 PDM right signal in both PDM channels 11 PDM stereo Rev 0 Page 92 of 116 1772 PATTERN SETTING REGISTER Address 0x0037 Reset 0x00 Name PDM_PATTERN B4 B3 B2 B1 BO B7 B5 7 0 PATTERN RW PDM pattern byte Table 83 Bit Descriptions for PDM PATTERN Bits Bit Name Settings Description Reset Access 7 0 PATTERN PDM pattern byte The PDM pattern byte should not be changed while 0x00 RW the PDM channel is operating and transmitting the pattern MPO FUNCTION SETTING REGISTER Address 0x0038 Reset 0x00 Name MODE MPO B7 B6 B5 B4 B3 B2 BO 7 5 RESERVED RW TT OO 4 0 MPO VAL RW Sets the function of Pin DAC SDATA MPO 00000 Serial Input O 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute DAC1 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down Table 84 Bit Descriptions for MODE MPO Bits Bit Name Settings Description Reset Access 4 0 MODE MPO VAL Sets the function of Pin DAC SDATA MPO 0x00 RW 00000 Serial Input O 00001 Mute ADCO
52. bits must be changed after the ADAU1772 is running the CORE_RUN bit first must be disabled PLL The PLL uses the MCLKIN signal as a reference to generate the core clock The PLL settings are set in Register 0x0000 to Register 0x0005 Depending on the MCLK frequency the PLL must be set for either integer or fractional mode The PLL can accept input frequencies in the range of 8 MHz to 27 MHz TO PLL CLOCK DIVIDER MCLK E x R N M Figure 68 PLL Block Diagram 10804 061 Input Clock Divider Before reaching the PLL the input clock signal goes through an integer clock divider to ensure that the clock frequency is within a suitable range for the PLL The X bits in the PLL_CTRL4 register Bits 2 1 Address 0x0005 sets the PLL input clock divide ratio Integer Mode Integer mode is used when the clock input is an integer multiple of the PLL output For example if MCLKIN 12 288 MHz and X 1 1 and fs 48 kHz then PLL Required Output 24 576 MHz R 2 24 576 MHz 12 288 MHz 2 where R 2 2 or R 4 In integer mode the values set for N and M are ignored Table 12 lists common integer PLL parameter settings for 48 kHz sampling rates Fractional Mode Fractional mode is used when the clock input is a fractional multiple of the PLL output For example if MCLKIN 13 MHz X 1 1 and fs 48 kHz then PLL Required Output 24 576 MHz 1 2 x R N M 24 576 MHz 13 MHz 1 2 x 3 1269 1625 whe
53. data types The exact formats for specific types of writes are shown in Figure 77 and Figure 78 Table 19 Data Word Sizes Data Type Word Size bytes Registers 1 Program 2 Parameters 4 If large blocks of data need to be downloaded to the ADAU1772 the output of the core can be halted using the CORE RUN bit in the core control register Address 0x0009 new data can be loaded and then the core can be restarted This is typically done during the booting sequence at start up or when loading a new program into memory Registers and bits shown as reserved in the register map read back 05 When writing to these registers and bits such as during a burst write across a reserved register or when writing to reserved bits in a register with other used bits write 05 large amounts of data to contiguous memory locations This increment happens automatically after single word write unless the control port communication is stopped that is a stop condition is issued for or SS is brought high for SPI The registers and RAMs in the ADAU1772 range in width from one to four bytes so the auto increment feature knows the mapping between subaddresses and the word length of the destination register or memory location PORT ADAUI772 supports a 2 wire serial PC compatible microprocessor bus driving multiple peripherals uses two pins serial data SDA and serial clock SCL to carry data between the ADAU1
54. down PD can be tied directly to IOVDD for normal operation Power Down Considerations When powering down the ADAU1772 be sure to mute the outputs before AVDD power is removed otherwise pops or clicks may be heard The easiest way to achieve this is to use a regulator that has a power good PGOOD signal to power the ADAU1772 or generate a power good signal using additional circuitry external to the regulator itself Typically on such regulators the power good signal changes state when the regulated voltage drops below 90 of its target value This power good signal can be connected to one of the ADAU1772 multipurpose pins and used to mute the DAC outputs by setting the multipurpose pin functionality to mute both DACs in Register 0x0038 to Register 0x003E This ensures that the outputs are muted before power is completely removed Table 12 Integer PLL Parameter Settings for PLL Output 24 576 MHz Input Divider PLL_CTRL4 Settings MCLK Input MHz X 1 Integer R Denominator M Numerator N Address 0x0005 12 288 1 4 Don t care Don t care 0x20 24 576 1 2 Don t care Don t care 0x10 Table 13 Fractional PLL Parameter Settings for PLL Output 24 576 MHz PLL CTRL 4 0 Settings MCLK Input Address 0 0005 to Address 0x0001 Input Divider Integer Denominator Numerator PLL_CTRL4 CTRL3 CTRL2 PLL CTRL1 CTRLO MHz X 1 R M N 0x0005 0x0004 0x0003 0x0002 0x0001
55. headphone amplifiers are enabled the PCB trace to this pin should be wider than traces to other pins to increase the current carrying capacity A wider trace should also be used for the headphone output lines GROUNDING A single ground plane should be used in the application layout Components in an analog signal path should be placed away from digital signals EXPOSED PAD PCB DESIGN The ADAU1772 has an exposed pad on the underside of the LFCSP This pad is used to couple the package to the PCB for heat dissipation When designing a board for the ADAU1772 special consideration should be given to the following e copper layer equal in size to the exposed pad should be on all layers of the board from top to bottom and should connect somewhere to a dedicated copper board layer see Figure 95 e Vias should be placed to connect all layers of copper allowing for efficient heat and energy conductivity For an example see Figure 96 which has nine vias arranged in a 3 x 3 grid in the pad area 10804 087 VIAS COPPER SQUARES Figure 95 Exposed Pad Layout Example Side View Not to Scale Figure 96 Exposed Pad Layout Example Top View Not to Scale 10804 088 Rev 0 Page 49 of 116 ADAUI772 REGISTER SUMMARY Table 29 Low Latency Codec Register Summary
56. switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down Rev 0 Page 95 of 116 ADAUI772 MP3 FUNCTION SETTING REGISTER Address 0x003B Reset 0x00 Name MODE MP3 B7 B8 B5 B4 B3 B2 B1 BO oe 6 7 5 RESERVED RW 4 0 MODE_MP3_VAL RW Sets the function of Pin LRCLK MP3 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Table 87 Descriptions for MODE_MP3 Left right clock Mute ADCO Mute ADC1 Mute ADC2 Mute ADC3 Mute ADCO and ADC1 Mute ADC2 and ADC3 Mute all ADCs Mute DACO Mute DAC1 Mute both DACs bank switch Reserved Reserved Enable compression DSP bypass enable Push button volume up Push button volume down Bits Bit Name Settings Description Reset Access 4 0 MODE MP3 VAL Sets the function of Pin LRCLK MP3 0x00 RW 00000 Left right clock 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button v
57. the HPOUTLP LOUTLP and HPOUTRP LOUTRP pins should be used to output the signals and the HPOUTLN LOUTLN and HPOUTRN LOUTRN pins should be powered down DIGITAL TO ANALOG CONVERTERS The ADAU1772 includes two 24 bit digital to analog converters DACs DAC Full Scale Level The full scale output from the DACs 0 dBFS scales linearly with AVDD At AVDD 3 3 V the full scale output level is 1 94 V rms for a differential output or 0 97 V rms for a single ended output Digital DAC Volume Control The volume of each DAC can be digitally attenuated using the DACx_VOLUME registers Address 0x002F and Address 0 0030 The volume can set to be between 0 dB and 95 625 dB in 0 375 dB steps PDM OUTPUT The ADAU1772 includes a 2 channel pulse density modulated modulator The pin can be used to drive a PDM input amplifier such as the SSM2517 mono 2 4 W amplifier Two SSM2517 devices can be connected to the PDMOUT data stream to enable a stereo output The PDM output signal is clocked by the CLKOUT pin output The PDM output stream must be clocked by this pin and not by a clock from another source such as another audio IC even if the other clock is of the same frequency as CLKOUT The PDM output Rev 0 Page 34 of 116 1772 data is clipped at the 6 dB level to prevent overdriving a connected amplifier like the SSM2517 The ADAU1772 has the ability to output PDM control pattern
58. 0 kHz 1 dBFS AVDD 1 8V 90 AVDD 3 3 V 94 Offset Error 0 1 mV Gain Error 0 2 Interchannel Isolation CM capacitor 22 100 dB Power Supply Rejection Ratio CM capacitor 22 100 mV p p at 1 kHz 55 dB SINGLE ENDED PGA INPUT PGA_ENx 1 PGA_x_BOOST 0 Full Scale Input Voltage Scales linearly with AVDD AVDD 3 63 Vrms AVDD 1 8V 0 49 Vrms AVDD 1 8 V 0 dBFS 1 38 Vp p AVDD 3 3 V 0 90 Vrms AVDD 3 3 V 0 dBFS 2 54 Vp p Dynamic Range 20 Hz to 20 kHz 60 dB input With A Weighted Filter RMS AVDD 1 8V 96 dB AVDD 3 3 V 102 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 94 dB AVDD 3 3 V 99 dB Rev 0 Page4 of 116 1772 Parameter Test Conditions Comments Min Typ Max Unit Total Harmonic Distortion Noise 20 Hz to 20 kHz 1 dBFS AVDD 1 8V 88 AVDD 3 3 V 90 Signal to Noise Ratio With A Weighted Filter RMS AVDD 1 8V 96 dB AVDD 3 3 V 102 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 94 dB AVDD 3 3 V 99 dB PGA Gain Variation With 12 Setting Standard deviation 0 05 dB With 35 25 dB Setting Standard deviation 0 15 dB PGA Boost PGA_x_BOOST 10 dB PGA Mute Attenuation PGA_MUTEx 65 Interchannel Gain Mismatch 0 005 dB Offset Error 0 Gain Error 0 2 dB Interchannel Isolation 83 dB Power Supply Rejection Ratio CM capacitor 22 100 mV at 1 kHz 63 dB MICROPHONE BIAS 1
59. 00 84 dB 00110000 78 dB 11100000 12 dB 11110000 6 dB 11111111 0 375 DB VALUE REGISTER 2 READ Address 0x000E Reset 0x00 Name DBREG2 The core can write data to this register and the data is automatically converted to a level in dB The most common usage is to determine the rms value of a signal by taking the absolute value and then performing low pass filtering and moving the result to the DBREG2 register B7 B8 B5 B4 B3 B2 B1 BO 7 0 2 RW DB Value Register 2 read 00000000 96 dB 00010000 90 dB 00100000 84 dB 00110000 78 dB 11100000 12 dB 11110000 6 dB 11111111 0 375 dB Table 43 Bit Descriptions for DBREG2 Bits Bit Name Settings Description Reset Access 7 0 DBVAL2 DB Value Register 2 read 0x00 R 00000000 96 dB 00010000 90 dB 00100000 84 00110000 78 dB 11100000 12 dB 11110000 6 dB 11111111 0 375 dB Rev 0 Page 60 of 116 1772 CORE CHANNEL 0 CORE CHANNEL 1 INPUT SELECT REGISTER Address 0x000F Reset 0x10 Name CORE IN 0 1 Core Input Channel 1 source 0000 AINO DMICO 0001 AIN1 DMIC1 0010 AIN2 DMIC2 0011 AIN3 DMIC3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 B7 B5 B4 B3 B2
60. 00010 Mute 1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 01010 Mute both DACs Rev 0 Page 93 of 116 ADAUI772 Bits Bit Name Settings Description Reset Access 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down MP1 FUNCTION SETTING REGISTER Address 0x0039 Reset 0x10 Name MODE MPI B7 B5 B4 B3 B2 BO 7 5 RESERVED RW i HI VAL RW Sets the function of Pin ADC SDATAO PDMOUT MP1 00000 Serial Output 0 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute DAC1 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down 10010 PDM modulator output Table 85 Bit Descriptions for MODE Bits Bit Name Settings Description Reset Access 4 0 MODE MP1 VAL Sets the function of Pin ADC_SDATAO PDMOUT MP1 0x10 RW 00000 Serial Output 0 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 a
61. 0017 ADC SDATA CH 7 0 RESERVED ADC SDATA1 ST ADC SDATAO ST 0x04 RW 0x0018 ASRCO SOURCE 1 7 0 ASRC OUT SOURCE ASRC OUT SOURCEO 0 10 0x0019 ASRCO SOURCE 2 3 7 0 ASRC OUT SOURCE3 ASRC OUT SOURCE2 0x32 RW 0x001A ASRC MODE 7 0 RESERVED ASRC IN CH ASRC OUT EN ASRC IN EN 0 00 RW 0x001B ADC CONTROLO 7 0 RESERVED RESERVED ADC1_MUTE MUTE RESERVED ADC 0 1 FS 0 19 0 001 ADC CONTROL1 7 0 RESERVED RESERVED ADC3 MUTE 2 MUTE RESERVED ADC 2 3 FS 0 19 RW 0x001D ADC CONTROL2 7 0 RESERVED HP 0 1 EN DMIC POLO DMIC SWO DCM 0 1 ADC 1 EN ADC 0 EN 0x00 RW 0x001E ADC CONTROL3 7 0 RESERVED HP 2 3 DMIC POL1 DMIC SW1 DCM 2 3 ADC 3 EN ADC 2 EN 0x00 RW 0x001F ADCO VOLUME 7 0 ADC 0 VOL 0x00 RW 0 0020 ADC1 VOLUME 7 0 ADC 1 VOL 0x00 RW 0x0021 ADC2 VOLUME 7 0 ADC 2 VOL 0x00 RW 0x0022 ADC3 VOLUME 7 0 ADC 3 VOL 0x00 RW 0 0023 PGA CONTROL o 7 0 PGA ENG PGA MUTEO PGA GAINO 0x40 RW 0x0024 PGA CONTROL 1 7 0 PGA EN1 PGA MUTET PGA_GAIN1 0x40 RW 0 0025 PGA CONTROL 2 7 0 PGA ENZ PGA MUTE2 PGA GAIN2 0 40 RW 0x0026 PGA CONTROL 3 7 0 PGA ENZ PGA MUTE3 PGA GAIN3 0x40 RW 0x0027 PGA STEP CONTROL 7 0 RESERVED SLEW RATE SLEW PD3 SLEW PD2 SLEW PD1 SLEW PDO 0x00 RW 0x0028 PGA 10DB BOOST 7 0 RESERVED PGA 3 BOOST PGA 2 BOOST 1 BOOST PGA 0 5 0 00 RW 0x0029 POP SUPPRESS 7 0 RESERVED HP POP DIS1 POP DISO PGA POP DIS3 PGA POP DIS2 PGA POP DIS1 PGA POP DISO Ox3F RW 0x002A
62. 1 35 25 dB RW PGA CONTROL 1 REGISTER Address 0x0024 Reset 0x40 Name PGA_CONTROL_1 This register controls the PGA connected to B6 B5 B4 B2 7 PGA EN1 RW 5 0 GAIN1 RW Select line or microphone ME Setthe gain of PGA1 0 AIN1 used as a single ended line 000000 12 dB input PGA powered down 000001 11 25 dB 1 AIN1 used as a single ended 010000 0 dB microphone input PGA powered up 111110 345 dB with slewing 111111 435 25 dB 6 PGA MUTE1 RW Enable PGA1 mute 0 Unmuted 1 Muted Rev 0 Page 79 of 116 ADAUI772 Table 65 Bit Descriptions for PGA_CONTROL_1 Bits Bit Name Settings Description Reset Access 7 PGA_EN1 Select line or microphone input Note that the PGA inverts the signal 0 0 RW going through it 0 used as a single ended line input PGA powered down 1 AIN1 used as a single ended microphone input PGA powered up with slewing 6 PGA_MUTE1 Enable PGA1 mute When PGA is muted PGA_GAIN1 is ignored 0 1 RW 0 Unmuted 1 Muted 5 0 PGA_GAIN1 Set the gain of PGA1 0 0 RW 000000 12 000001 11 25 010000 111110 34 5 dB 111111 35 25 dB PGA CONTROL 2 REGISTER Address 0x0025 Reset 0x40 PGA_CONTROL_2 This register controls the PGA connected to AIN2 B7 B6 B5 B4 B3 B2 BO 0 1 0 0 0 0 0 0 7 PGA_EN2 RW 5 0 PGA_GAIN2 RW Select line or microph
63. 110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 B7 B5 B4 B3 B2 B1 BO 7 4 CORE_IN_MUX_SEL_3 RW p CORE_IN_MUX_SEL_2 RW Core Input Channel 2 source 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Table 45 Bit Descriptions for CORE IN MUX 2 3 AINO DMICO AIN1 DMIC1 AIN2 DMIC2 AIN3 DMIC3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input ASRC Channel 0 Input ASRC Channel 1 Bits Bit Name Settings Description Reset Access 7 4 CORE IN MUX SEL 3 Core Input Channel 3 source 0 3 RW 0000 AINO DMICO 0001 AIN1 DMIC1 0010 AIN2 DMIC2 0011 AIN3 DMIC3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 3 0 CORE IN MUX SEL 2 Core Input Channel 2 source 0 2 RW 0000 AINO DMICO 0001 AIN1 DMIC1 0010 AIN2 DMIC2 0011 AIN3 DMIC3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 Rev 0 Page 62 of 116 1772 DAC INPUT SELECT REGISTER Address 0x0011 Reset 0x10 Name D
64. 13E 0 015 0 017 31 0x011F 0x013F 0 015 0x017F Table 18 Parameter Addresses Bank B Assignment Order BO Max Gain B1 Min Gain B2 Attack A1 Decay A2 Threshold 0 0x0180 0x01A0 0x01CO 0 0200 1 0 0181 1 0 01 1 0 0201 2 0 0182 0 01 2 0x01C2 2 0 0202 3 0x0183 0x01A3 0x01C3 0 0203 4 0 0184 0x01A4 0x01C4 0 01 4 0 0204 5 0 0185 0 01 5 0 01 5 0 01 5 0 0205 6 0 0186 0x01A6 0x01C6 0x01E6 0x0206 7 0x0187 0 01 7 0x01C7 7 0 0207 8 0 0188 0x01A8 0x01C8 8 0 0208 9 0 0189 0x01A9 0x01C9 9 0 0209 10 0x018A 0 020 11 0 018 0x01AB 0x01CB 0 0208 12 0x018C 0x01AC 0x01CC 0 020 13 0x018D 0x01AD 0x01CD 0x01ED 0x020D 14 0 018 0 020 15 0 018 0x01CF 0 020 16 0 0190 0x01B0 0x01D0 0x01FO 0x0210 Rev 0 Page 37 of 116 ADAUI772 Assignment Order BO Max Gain B1 Min Gain B2 Attack A1 Decay A2 Threshold 17 0x0191 0x01B1 0x01D1 1 0 0211 18 0 0192 0 0182 0 0102 0 01 2 0 0212 19 0 0193 0x01B3 0x01D3 0x01F3 0x0213 20 0x0194 0x01B4 0x01D4 4 0 0214 21 0 0195 0 0185 0 0105 5 0 0215 22 0 0196 0x01B6 0x01D6 0x01F6 0x0216 23 0x0197 0x01B7 0x01D7 7 0 0217 24 0 0198 0x01B8 0x01D8 0x01F8 0x0218 25 0x0199 0x01B9 0x01D9
65. 15 of 116 01772 Pin Description 13 AIN1REF A_IN ADC1 Input Reference This reference pin should be ac coupled to ground with a 10 pF capacitor 14 AIN1 A_IN ADC1 Input 15 AIN2REF A_IN ADC2 Input Reference This reference pin should be ac coupled to ground with a 10 pF capacitor 16 AIN2 A_IN ADC2 Input 17 AIN3REF A_IN ADC3 Input Reference This reference pin should be ac coupled to ground with 10 capacitor 18 AIN3 A_IN ADC3 Input 19 AVDD PWR 1 8 V to 3 3 V Analog Supply This pin should be decoupled to AGND with a 0 1 uF capacitor 20 AGND PWR Analog Ground 21 HPOUTLN LOUTLN A_OUT Left Headphone Inverted HPOUTLN Line Output Inverted LOUTLN 22 HPOUTLP LOUTLP A_OUT Left Headphone Noninverted HPOUTLP Line Output Noninverted Single Ended Line Output LOUTLP 23 AGND PWR Headphone Amplifier Ground 24 AVDD PWR Headphone Amplifier Power 1 8 V to 3 3 V Analog Supply This pin should be decoupled to AGND with a 0 1 capacitor The PCB trace to this pin should be wider to supply the higher current necessary for driving the headphone outputs 25 HPOUTRN LOUTRN A_OUT Right Headphone Inverted HPOUTRN Line Output Inverted LOUTRN 26 HPOUTRP LOUTRP A_OUT Right Headphone Noninverted HPOUTRP Line Output Noninverted Single Ended Line Output LOUTRP 27 PD D_IN Active Low Power Down All digital and analog circuits are powered down There is an internal
66. 35 FOR PROPER CONNECTION OF 0 80 THE EXPOSED PAD REFER TO aa THE PIN CONFIGURATION AND 0 75 0 05 MAX FUNCTION DESCRIPTIONS 0 70 0 02 i COPLANARITY 0 08 SEATING 0 20 REF PLANE 05 06 2011 COMPLIANT STANDARDS MO 220 WJJD Figure 97 40 Lead Lead Frame Chip Scale Package LFCSP_WQ 6mm 6 mm Body Very Very Thin Quad CP 40 10 Dimension shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADAU1772BCPZ 40 to 85 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 40 10 ADAU1772BCPZ R7 40 to 85 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ 7 Tape and Reel CP 40 10 ADAU1772BCPZ RL 40 to 85 C 40 Lead Lead Frame Chip Scale Package LFCSP_WQ 13 Tape and Reel CP 40 10 EVAL ADAU1772Z Evaluation Board 17 RoHS Compliant Part Rev 0 Page 113 of 116 ADAUI772 NOTES Rev 0 Page 114 of 116 1772 5 0 115 01116 ADAUI772 NOTES 2012 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D10804 0 7 12 0 DEVICES Rev 0 Page 116 of 116
67. 72 can be configured as differential or single ended outputs The analog output pins are capable of driving headphone or earpiece speakers The line outputs can drive a load of at least 10 kO or can be put into headphone mode to drive headphones or earpiece speakers The analog output pins are biased at AVDD 2 ANALOG OUTPUTS Headphone Output The output pins can be driven by either a line output driver or a headphone driver by setting the HP EN Land HP EN R bits in the headphone line output select register Address 0x0043 The headphone outputs can drive a load of at least 16 Headphone Output Power Up Sequencing To prevent pops when turning on the headphone outputs the user must wait at least 6 ms to unmute these outputs after enabling the headphone output using the HP EN x bits Waiting 6 ms allows an internal capacitor to charge before these outputs are used Figure 73 illustrates the headphone output power up sequencing USER DEFINED HP EN X 1 HEADPHONE HP_MUTE_R AND HP_MUTE_L 00 UNMUTE INTERNAL PRECHARGE 10804 066 Figure 73 Headphone Output Power Up Timing Ground Centered Headphone Configuration The headphone outputs can also be configured as ground centered outputs by connecting coupling capacitors in series with the output pins Ground centered headphones should use the AGND pin as the ground reference When the headphone outputs are configured in this manner the capacitors create
68. 772 and the system master controller In mode the ADAU1772 is always a slave on the bus except when the IC is self booting See the Self Boot section for details about using the ADAUI772 in self boot mode Each slave device is recognized by a unique 7 bit address The ADAUI772 address format is shown in Table 21 The LSB of this first byte sent from the master sets either a read or write operation Logic Level 1 corresponds to a read operation and Logic Level 0 corresponds to a write operation Pin ADDRO and Pin ADDRI set the LSBs of the address Table 22 therefore each ADAU1772 can set to one of four unique addresses This allows multiple ICs to exist on the same bus without address contention The 7 bit addresses are shown in Table 22 An data transfer is always terminated by a stop condition Both SDA and SCL should have 2 0 pull up resistors on the lines connected to them The voltage on these signal lines should not be higher than IOVDD Table 21 Address Format Bit 6 Bit5 Bit4 Bit3 Bit 2 Bit 1 Bit 0 0 1 1 1 1 ADDR1 ADDRO Table 22 Addresses The control port pins are multifunctional depending on the ADDRT ADDR0 Slave Address mode in which the part is operating Table 20 details these 0 0 0 3 multiple functions 0 0x3D 1 0 Table 20 Control Port Pin Functions 1 1 Ox3F Pin Mode SPI Mode
69. AC_SOURCE_0_1 B5 B4 B3 B2 B1 BO 7 B6 7 4 DAC SOURCE1 RW J DAC SOURCEO RW 1 i 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Core Output 0 Core Output 1 Core Output 2 Core Output 3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input ASRC Channel 0 Input ASRC Channel 1 DACH input source 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 Table 46 Bit Descriptions for DAC_SOURCE_0_1 Bits Bit Name Settings Description Reset Access 7 4 DAC_SOURCE1 DAC1 input source This setting should not be changed while the core is 0 1 RW running CORE_RUN must be set to 0 for this setting to be updated 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 3 0 DAC_SOURCEO DACO input source This setting should not be changed while the core is 0x0 RW running CORE RUN must be set to 0 for this setting to be updated 0000 Core Output 0 0001 Core Output
70. AINxREF pins to the CM pin and connect the microphone signal to the inverting input of the PGAs AINx as shown in Figure 70 ADAU1772 PGA 12dB TO 435 25dB MICBIASx 10804 063 Figure 70 Single Ended Microphone Configuration Analog Line Inputs Line level signals can be input on the AINx pins of the analog inputs Figure 71 shows a single ended line input using the AINx pins The AINxREF pins should be tied to CM When using single ended line input the PGA should be disabled using the PGA_ENx bits and the corresponding PGA pop suppression bit should be disabled using the POP SUPPRESS register Address 0x0029 ADAU1772 LINE INPUT 0 oO LINE INPUT 1 0 LINE INPUT 20 4 LINE INPUT 3 0 10804 064 Figure 71 Single Ended Line Inputs Precharging Input Capacitors Precharge amplifiers are enabled by default to quickly charge large series capacitors on the inputs and outputs Precharging these capacitors helps to prevent pops in the audio signal The precharge circuits are powered up by default on startup and can be disabled in the POP_SUPPRESS register The precharge amplifiers are automatically disabled when the PGA or headphone amplifiers are enabled For unused PGAs and headphone outputs these precharge amplifiers should be disabled using the POP_SUPPRESS register The precharging time is dependent on the input output series capacitors The impedance looking into the pin is 500 in this mode Howev
71. ANALOG DEVICES FEATURES Programmable audio processing engine 192 kHz processing path Biquad filters limiters volume controls mixing Low latency 24 bit ADCs and DACs 102 dB SNR signal through PGA and ADC with A weighted filter 107 dB combined SNR signal through DAC and headphone with A weighted filter Serial port sample rates from 8 kHz to 192 kHz 38 us analog to analog latency 4 single ended analog inputs configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output single ended or differential configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full duplex asynchronous sample rate converters ASRCs Power supplies Analog and digital I O of 1 8 V to 3 3 V Digital signal processing DSP core of 1 1 V to 1 8 V Four ADC Two DAC Low Power Codec with Audio Processor ADAU1772 Low power 15 mW for typical noise cancelling solution PC and SPI control interfaces self boot from IC EEPROM 7 MP pins supporting dual stereo digital microphone inputs stereo PDM output mute DSP bypass push button volume controls and parameter bank switching APPLICATIONS Noise cancelling handsets headsets and headphones Bluetooth ANC handsets headsets and headphones Personal navigation devices Digital still and video cameras GENERAL DESCRIPTION The ADAU1772 is a codec with four inputs and two outputs that incorporates a d
72. B1 BO 7 4 CORE_IN_MUX_SEL_1 RW C U p CORE_IN_MUX_SEL_0 RW Core Input Channel 0 source Table 44 Bit Descriptions for CORE IN MUX 0 1 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 AINO DMICO AIN1 DMIC1 AIN2 DMIC2 AIN3 DMIC3 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Input ASRC Channel 0 Input ASRC Channel 1 Bits Bit Name Settings Description Reset Access 7 4 CORE IN MUX SEL 1 Core Input Channel 1 source 0 1 RW 0000 AINO DMICO 0001 AIN1 DMIC1 0010 AIN2 DMIC2 0011 AIN3 DMIC3 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 3 0 CORE IN MUX SEL O Core Input Channel 0 source 0 0 RW 0000 AINO DMICO 0001 AIN1 DMIC1 0010 AIN2 DMIC2 0011 AIN3 DMIC3 0100 0101 0110 0111 Reserved 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Input ASRC Channel 0 1101 Input ASRC Channel 1 Rev 0 Page 61 of 116 ADAUI772 CORE CHANNEL 2 CORE CHANNEL 3 INPUT SELECT REGISTER Address 0x0010 Reset 0x32 Name CORE MUX 2 3 Core Input Channel 3 source 0000 AINO DMICO 0001 AIN1 DMIC1 0010 AIN2 DMIC2 0011 AIN3 DMIC3 0100 Reserved 0101 Reserved 0
73. Bias Voltage 0 65 x AVDD AVDD 1 8 V MIC_GAINx 1 1 16 V AVDD 3 3 V MIC GAINx 1 2 12 V 0 90 x AVDD AVDD 1 8 V MIC GAINx 0 1 63 V AVDD 3 3 V MIC GAINx 0 2 97 V Bias Current Source 3 mA Output Impedance 1 5 Isolation MIC_GAINx 0 95 dB MIC_GAINx 1 99 dB Noise in the Signal Bandwidth AVDD 1 8 V 20 Hz to 20 kHz MIC_GAINx 0 27 nV VHz MIC_GAINx 1 16 nV VHz AVDD 3 3 V 20 Hz to 20 kHz MIC_GAINx 0 35 nV VHz MIC_GAINx 1 19 nV VHz DIGITAL TO ANALOG CONVERTERS DAC Resolution All DACs 24 Bits Digital Attenuation Step 0 375 dB Digital Attenuation Range 95 dB DAC SINGLE ENDED OUTPUT Single ended operation and HPOUTRP pins Full Scale Output Voltage Scales linearly with AVDD AVDD 3 4 Vrms AVDD 1 8V 0 53 Vrms AVDD 1 8 V 0 dBFS 1 5 Vp p AVDD 3 3 V 0 97 Vrms AVDD 3 3 V 0 dBFS 2 74 Vp p Mute Attenuation 72 Dynamic Range Line output mode 20 Hz to 20 kHz 60 input With A Weighted Filter RMS AVDD 1 8V 100 dB AVDD 3 3 V 104 With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 97 dB AVDD 3 3 V 101 dB Signal to Noise Ratio Line output mode 20 Hz to 20 kHz With A Weighted Filter RMS AVDD 1 8V 100 dB AVDD 3 3 V 104 With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 98 dB AVDD 3 3 V 102 Rev 0 5 of 116 ADAU1772 Parameter Test Conditions Comments Min Typ Max Unit Interchannel Gain Mismatch Line output mode 20 mdB Total H
74. CL fall hold time from SDA falling relevant for start condition tue is the input clock on the MCLKIN pin tscse 38 x tue 70 ns SCL rise setup time to SDA falling relevant for repeated start condition 70 x tue 70 ns SCL rise setup time to SDA rising relevant for stop condition tose 6 x twp 70 ns Delay from SCL falling to SDA changing Ia 32 x ns SDA rising in self boot stop condition to SDA falling edge for external master start condition MULTIPURPOSE AND POWER DOWN PINS tai 1 5 x 1 fs us MPx input latency time until high or low value is read by core 20 ns PD low pulse width Rev 0 Page 10 of 116 1772 Limit Parameter Tmin Tmax Unit Description DIGITAL MICROPHONE tcr 20 ns Digital microphone clock fall time tcn 20 ns Digital microphone clock rise time tps 40 Digital microphone valid data start time toe 0 ns Digital microphone valid data end time PDM OUTPUT tocr 20 ns PDM clock fall time tocr 20 ns PDM clock rise time 0 30 ns PDM delay time for valid data Digital Timing Diagrams o o T o LRCLK amp 155 a DAC SDATA LEFT JUSTIFIED MSB MSB 1 MODE 155 ee DAC_SDATA e DAC SDATA RIGHT JUSTIFIED MODE 4 P 8 BIT CLOCKS 24 BIT DATA i M9 12 BIT CLOCKS 20 BIT DATA 14 BIT CLOCKS 18 BIT DATA 155 lt 4 16 BIT CL
75. Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 ADCO 0101 ADC1 0110 ADC2 0111 ADC3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 OUTPUT ASRC2 OUTPUT ASRC3 SOURCE REGISTER Address 0x0019 Reset 0x32 Name ASRCO SOURCE 2 3 B5 B B 7 4 ASRC OUT SOURCE3 RW 3 0 ASRC OUT SOURCE2 RW Output ASRC Channel 3 source select Output ASRC Channel 2 source select 0000 Core Output 0 0000 Core Output 0 0001 Core Output 1 0001 Core Output 1 0010 Core Output 2 0010 Core Output 2 0011 Core Output 3 0011 Core Output 3 0100 ADCO 0100 ADCO 0101 ADC1 0101 ADC1 0110 ADC2 0110 ADC2 0111 ADC3 0111 ADC3 1000 Serial Input O 1000 Serial Input O 1001 Serial Input 1 1001 Serial Input 1 1010 Serial Input 2 1010 Serial Input 2 1011 Serial Input 3 1011 Serial Input 3 1100 Serial Input 4 1100 Serial Input 4 1101 Serial Input 5 1101 Serial Input 5 1110 Serial Input 6 1110 Serial Input 6 1111 Serial Input 7 1111 Serial Input 7 Table 54 Bit Descriptions for ASRCO SOURCE 2 3 Bits Bit Name Settings Description Reset Access 7 4 ASRC_OUT_SOURCE3 Output ASRC Channel 3 source select 0 3 RW 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 Rev 0 71 of 116 01772
76. DE_MP5_VAL 0x00 MODE MP6 7 0 RESERVED MODE MP6 VAL Ox11 BW PB VOL SET 7 0 PB VOL INIT VAL HOLD 0 00 0x0040 PB VOL CONV 7 0 GAINSTEP RAMPSPEED PB VOL CONV VAL 0x87 0 0041 DEBOUNCE MODE 7 0 RESERVED DEBOUNCE 0x05 RW 0x0043 OP STAGE CTRL 7 0 RESERVED HP EN R HP HP PDN R HP PDN L 0 0044 DECIM PWR MODES 7 0 DEC 3 DEC 2 EN DEC 1 EN DEC 0 EN SINC 3 EN SINC 2 EN SINC 1 EN SINC 0 EN 0x00 0 0045 INTERP PWR MODES 7 0 RESERVED MOD 1 EN MOD 0 EN INT 1 EN INT 0 EN 0x00 0x0046 BIAS CONTROLO 7 0 HP IBIAS AFE 501 ADC IBIAS23 ADC IBIASO1 0x00 0x0047 BIAS_CONTROL1 7 0 RESERVED CBIAS_DIS 523 5 DAC IBIAS 0x00 0x0048 PAD CONTROLO 7 0 RESERVED DMIC2 3 PU 1 PU PU BCLK PU ADC SDATA1 ADC SDATAO SDATA 0 7 RW PU PU PU 0x0049 PAD CONTROL1 7 0 RESERVED SELFBOOT PU SCL PU SDA PU ADDRI PU ADDRO PU 0 004 PAD_CONTROL2 7 0 RESERVED DMIC2 3 DMICO 1 PD BCLK PD ADC SDATA1 ADC SDATAO SDATA 0 00 RW PD PD PD 0 004 PAD CONTROL3 7 0 RESERVED SELFBOOT PD SCL PD SDA PD ADDR1_PD ADDRO_PD 0x00 0 004 PAD_CONTROL4 7 0 RESERVED RESERVED RESERVED LRCLK_DRV BCLK_DRV ADC_SDATA1_ ADC SDATAO RESERVED 0x00 DRV DRV 0x004D PAD_CONTROL5 7 0 RESERVED RESERVED SCL_DRV SDA_DRV RESERVED RESERVED 0x00 Rev 0 Page 51 o
77. Disab High pass filter settings gas 1 Enable 00 Off 01 1 Hz 1 ADC 3 EN RW 10 4 Hz Enable ADC3 11 8 Hz 0 Disable 4 DMIC_POL1 RW ISS Microphone polarity 2 DCM 2 3 RW 0 0 positive 1 negative Sets the input source to ADCs or 1 1 positive 0 negative digital microphones 0 Decimator source set to ADC 1 Decimator source set to digital microphone 3 DMIC SW1 RW Digital microphone swap 0 Channel swap off left channel on rising edge right channel on fallinc edge 1 Swap left and right Table 59 Bit Descriptions for ADC CONTROL3 Bits Bit Name Settings Description Reset Access 6 5 HP 2 3 EN High pass filter settings 0 0 RW 00 Off 01 1Hz 10 4Hz 11 8Hz 4 DMIC_POL1 Microphone polarity 0 0 RW 0 Opositive 1 negative 1 1 positive 0 negative 3 DMIC_SW1 Digital microphone swap 0 0 RW 0 Channel swap off left channel on rising edge right channel on falling edge 1 Swap left and right 2 2 3 Sets the input source to ADCs or digital microphones 0 0 RW 0 Decimator source set to ADC 1 Decimator source set to digital microphone 1 ADC_3_EN Enable ADC3 This bit must be set in conjunction with the SINC_3_EN bit 0 0 RW in the DECIM_PWR_MODES register to fully enable or disable the ADC 0 Disable 1 Enable 0 ADC_2_EN Enable ADC2 This bit must be set in conjunction with the SINC_2_EN bit 0 0 RW in the DECIM_PWR_MODES register to fully enabl
78. Disable data in TDM Output Slot 3 0 0 RW 0 Output channel enabled 1 Output channel disabled 2 TDM2_DIS Disable data in TDM Output Slot 2 0 0 RW 0 Output channel enabled 1 Output channel disabled 1 TDM1_DIS Disable data in TDM Output Slot 1 0 0 RW 0 Output channel enabled 1 Output channel disabled 0 TDMO_DIS Disable data in TDM Output Slot 0 0 0 RW 0 Output channel enabled 1 Output channel disabled Rev 0 Page 91 of 116 01772 ENABLE REGISTER Address 0x0036 Reset 0x00 Name PDM_ OUT Si 7 5 RESERVED RW 1 0 PDM_EN RW Enable PDM output on Pin 4 PDM_CTRL RW PDMOUT Enable the control pattern in the data stream 00 PDM disabled 0 Disabled channels 1 Enabled 10 right signal in both channels 11 PDM stereo 3 2 PDM CH RW Selects the channel on which the control patterns are written 00 Both channels 01 Left channel 10 Right channel 01 PDM left signal in both PDM 11 Reserved Table 82 Bit Descriptions for PDM OUT Bits Bit Name Settings Description Reset Access 4 PDM CTRL Enable the control pattern in the PDM data stream 0 0 RW 0 Disabled 1 Enabled 3 2 PDM_CH Selects the channel on which the control patterns are written These 0 0 RW control bits should not be changed while the PDM channel is operating and transmitting audio 00 Both channels 01 Left channel 10 Right channel 11
79. E 0 1 B5 B B P 0 0 0 1 0 0 0 0 7 4 ASRC_OUT_SOURCE1 RW 130 ASRC_OUT_SOURCEO RW Output ASRC Channel 1 source select Output ASRC Channel 0 source select 0000 Core Output 0 0000 Core Output 0 0001 Core Output 1 0001 Core Output 1 0010 Core Output 2 0010 Core Output 2 0011 Core Output 3 0011 Core Output 3 0100 ADCO 0100 ADCO 0101 ADC1 0101 ADC1 0110 ADC2 0110 ADC2 0111 ADC3 0111 ADC3 1000 Serial Input 0 1000 Serial Input 0 1001 Serial Input 1 1001 Serial Input 1 1010 Serial Input 2 1010 Serial Input 2 1011 Serial Input 3 1011 Serial Input 3 1100 Serial Input 4 1100 Serial Input 4 1101 Serial Input 5 1101 Serial Input 5 1110 Serial Input 6 1110 Serial Input 6 1111 Serial Input 7 1111 Serial Input 7 Table 53 Bit Descriptions for ASRCO_SOURCE_0_1 Bits Bit Name Settings Description Reset Access 7 4 ASRC_OUT_SOURCE1 Output ASRC Channel 1 source select 0 1 RW 0000 Core Output 0 0001 Core Output 1 0010 Core Output 2 0011 Core Output 3 0100 ADCO 0101 ADC1 0110 ADC2 0111 ADC3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 Rev 0 Page 70 of 116 ADAU1772 Bits Bit Name Settings Description Reset Access 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 3 0 ASRC_OUT_SOURCEO Output ASRC Channel 0 source select 0 0 RW 0000
80. E 49 Power Supply Bypass Capacitors 49 49 EIDEN 49 Exposed Pad PCB Design 49 Register Summary Mer 50 Register Details 52 Clock Control Register ENEE 52 PLL Denominator MSB Register sese 53 PLL Denominator LSB Register 53 PLL Numerator MSB Register 53 PLL Numerator LSB Register seen 54 PLL Integer Setting Register een 54 PEL Lock Flag Regist r teretes 55 CLKOUT Setting Selection Register 55 Regulator Control Register 56 Core Control Register 57 Filter Engine and Limiter Control Register 58 DB Value Register 0 Read sse 59 DB Val e Register 1 Read eee 59 DB Value Register 2 Read 60 Core Channel 0 Core Channel 1 Input Select Register 61 Core Channel 2 Core Channel 3 Input Select Register 62 DAC Input Select Register 63 Modulator Input Select Register 64 Serial Data Output 0 Serial Data Output 1 Input Select Doug RE 65 Rev 0 Page 2 of 116 1772 Serial Data Output 2 Serial Data Output 3 Input Select Headphone Output Mutes 88 nuc 66 Serial Port Control 0 Register 89 Serial Data Output 4 Serial Data Output 5 Input Select Register aee 67 Serial Port Control 1 Register een 90 TDM Output Channel Disable
81. Frequency 20 kHz Bandwidth 48 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 100 1k 10k FREQUENCY Hz Figure 36 Relative Level vs Frequency 96 kHz Signal Path DAC_SDATA to ASRC to LOUTLx GROUP DELAY us 10804 033 PHASE Degrees 10804 034 GROUP DELAY us 10804 035 Rev 0 21 of 116 300 280 260 240 220 200 180 160 140 120 100 4 6 8 10 12 14 16 18 20 FREQUENCY kHz 10804 036 Figure 37 Group Delay vs Frequency 48 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 0 0 2 04 06 08 10 12 14 16 18 2 0 FREQUENCY kHz 10804 037 Figure 38 Phase vs Frequency 2 kHz Bandwidth 48 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 8 12 16 20 24 28 32 36 40 FREQUENCY kHz 10804 038 Figure 39 Group Delay vs Frequency 96 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 01772 PHASE Degrees PHASE Degrees RELATIVE LEVEL dB b 4 8 12 16 20 24 28 32 36 40 FREQUENCY kHz Figure 40 Phase vs Frequency 40 kHz Bandwidth 96 kHz Signal Path DAC_SDATA to ASRC to
82. GH BYTE LOW BYTE DELAY LENGTH LENGTH PROGRAM RAM ADDRESS 9e o 59 DATA DATA DATA PLL LOCK NO OP END 1 LENGTH 3 Figure 83 A List of Example Self Boot EEPROM Instructions Rev 0 Page 43 of 116 10804 090 ADAUI772 MULTIPURPOSE PINS The ADAU1772 has seven multipurpose MP pins that can be used for serial data I O clock outputs and control in a system without a microcontroller Each pin can be individually set to either its default or MP setting The functions include push button volume controls enabling the compressors parameter bank switching DSP bypass mode and muting the outputs The function of each of these pins is set in Register 0x0038 to Register 0x003E By default each pin is configured as an input Table 26 Multipurpose Pin Functions Pin No Default Pin Function Secondary Pin Functions 31 LRCLK Multipurpose control inputs 32 BCLK Multipurpose control inputs 33 DAC_SDATA Multipurpose control inputs 34 MP1 acting as push ADC_SDATAO PDM output button volume up multipurpose control inputs 35 MP6 acting as push ADC_SDATA1 CLKOUT button volume down multipurpose control inputs 36 DMIC2_3 Multipurpose control inputs 37 1 Multipurpose control inputs PUSH BUTTON VOLUME CONTROLS The ADC and DAC volume controls can be set up to be controlled with two push buttons one for volume up and on
83. Hz Signal Path AINO to ASRC to ADC_SDATAO GROUP DELAY us 10804 021 PHASE Degrees 10804 022 GROUP DELAY us 10804 023 Rev 0 Page 19 of 116 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY kHz 10804 024 Figure 25 Group Delay vs Frequency fs 48 kHz Signal Path AINO to ASRC to ADC_SDATAO 0 0 2 0 4 06 08 10 12 14 16 18 20 2 10804 025 Figure 26 Phase vs Frequency 2 kHz Bandwidth fs 48 kHz Signal Path AINO to ASRC to ADC_SDATAO 0 4 12 16 20 24 28 32 36 40 FREQUENCY kHz 10804 026 Figure 27 Group Delay vs Frequency fs 96 kHz Signal Path AINO to ASRC to ADC_SDATAO 01772 PHASE Degrees RELATIVE LEVEL dB PHASE Degrees 4 8 12 16 20 24 28 32 36 40 FREQUENCY kHz Figure 28 Phase vs Frequency 40 kHz Bandwidth 96 kHz Signal Path AINO to ASRC to ADC_SDATAO 100 1k 10k FREQUENCY Hz Figure 29 Relative Level vs Frequency 192 kHz Signal Path AINO to ASRC to ADC_SDATAO 10 20 30 40 50 60 70 80 FREQUENCY
84. IS RW Disable data in TDM Output Slot 7 0 Output channel enabled 1 Output channel disabled 6 TDM6 DIS RW Disable data in TDM Output Slot 6 0 Output channel enabled 1 Output channel disabled 5 TDM5 DIS RW Disable data in TDM Output Slot 5 0 Output channel enabled 1 Output channel disabled 4 TDM4 DIS RW Disable data in TDM Output Slot 4 0 Output channel enabled 1 Output channel disabled 20000000 0 TDMO DIS RW Disable data TDM Output Slot 0 Output channel enabled 1 Output channel disabled 1 TDM1_DIS RW Disable data in TDM Output Slot 0 Output channel enabled 1 Output channel disabled 2 TDM2_DIS RW Disable data in TDM Output Slot 0 Output channel enabled 1 Output channel disabled 3 TDM3_DIS RW Disable data in TDM Output Slot 0 Output channel enabled 1 Output channel disabled Table 81 Bit Descriptions for SOUT_CONTROLO Bits Bit Name Settings Description Reset Access 7 TDM7_DIS Disable data in TDM Output Slot 7 0 0 RW 0 Output channel enabled 1 Output channel disabled 6 TDM6 DIS Disable data in TDM Output Slot 6 0 0 RW 0 Output channel enabled 1 Output channel disabled 5 TDM5 DIS Disable data in TDM Output Slot 5 0 0 RW 0 Output channel enabled 1 Output channel disabled 4 TDM4_DIS Disable data in TDM Output Slot 4 0 0 RW 0 Output channel enabled 1 Output channel disabled 3 TDM3 DIS
85. Input 1 DMICO 1 General Purpose Input 4 38 XTALO A OUT Crystal Clock Output This pin is the output of the crystal amplifier and should not be used to provide a clock to other ICs in the system If a master clock output is needed use CLKOUT Pin 35 39 XTALI MCLKIN D IN Crystal Clock Input XTALI Master Clock Input MCLKIN 40 IOVDD PWR Supply for Digital Input and Output Pins The digital output pins are supplied from IOVDD and this sets the highest input voltage that should be seen on the digital input pins The current draw of this pin is variable because it is dependent on the loads of the digital outputs IOVDD should be decoupled to DGND with a 0 1 capacitor EP Exposed Pad The exposed pad is connected internally to the ADAU1772 grounds For increased reliability of the solder joints and maximum thermal capability it is recommended that the pad be soldered to the ground plane See the Exposed Pad PCB Design section for more information IO digital input output D IN digital input A OUT analog output A IN analog input PWR power A IN analog input Rev 0 Page 16 of 116 1772 TYPICAL PERFORMANCE CHARACTERISTICS
86. LOUTLx 100 1k 10k FREQUENCY Hz Figure 41 Relative Level vs Frequency fs 192 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 10 20 30 40 50 60 70 FREQUENCY kHz Figure 42 Phase vs Frequency 80 kHz Bandwidth 192 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 80 PHASE Degrees 10804 039 GROUP DELAY 10804 040 PHASE Degrees 10804 041 Rev 0 Page 22 of 116 0 0 2 0 4 06 08 10 12 14 16 18 20 FREQUENCY kHz Figure 43 Phase vs Frequency 2 kHz Bandwidth 96 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 0 10 20 30 40 50 60 70 80 FREQUENCY kHz Figure 44 Group Delay vs Frequency 192 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 0 0 2 04 0 6 0 8 1 0 1 2 14 16 18 2 FREQUENCY kHz Figure 45 Phase vs Frequency 2 kHz Bandwidth 192 kHz Signal Path DAC_SDATA to ASRC to LOUTLx 10804 042 10804 043 10804 044 1772
87. LOUTRP unmuted HPOUTRN LOUTRN muted 11 Both output pins muted 1 0 HP_MUTE_L Mute the left output pins When a pin is muted it can be used as a 0x3 RW common mode output 00 Outputs unmuted 01 HPOUTLP LOUTLP muted HPOUTLN LOUTLN unmuted 10 HPOUTLP LOUTLP unmuted HPOUTLN LOUTLN muted 11 Both output pins muted Rev 0 Page 88 of 116 1772 SERIAL PORT CONTROL 0 REGISTER Address 0x0032 Reset 0x00 Name SAI_0 Using 16 bit serial I O limits device performance 7 6 SDATA_FMT RW Serial data format 00 I2S data delayed from edge 0000 48 kHz B7 B8 B5 B4 B3 B2 B1 BO 3 0 SER PORT FS RW Sampling rate on the serial ports of LRCLK by 1 BCLK 0001 8 kHz 01 TDM left justified data 0010 12 kHz synchronized to edge of LRCLK 0011 16 kHz 10 Right justified 24 bit data 0100 24 kHz 11 Right justified 16 bit data 0101 32 kHz 0110 96 kHz 5 4 SAI RW Serial port mode 00 Stereo 125 left justified right justified 01 TDM2 10 11 TDM8 Table 79 Descriptions for SAI_0 0111 192 kHz Bits Bit Name Settings Description Reset Access 7 6 SDATA EMT Serial data format 0 0 RW 00 I S data delayed from edge of LRCLK 1 BCLK cycle 01 TDM left justified data synchronized to edge of LRCLK 10 Right justified 24 bit data 11 Right justified 16 bit data 5 4 SAI Serial port mode 0 0 RW 00 St
88. OCKS 16 BIT DATA Figure 2 Serial Input Port Timing Rev 0 11 of 116 10804 002 ADAU1772 tty et trs BCLK LRCLK ADC_SDATAx LEFT JUSTIFIED MODE ADC_SDATAx 128 MODE gt j Lors ADC_SDATAx HIGH Z HIGH Z ien ss X X tsop ra SDATAx MODE P 8 BIT CLOCKS 24 BIT DATA 48 12 BIT CLOCKS 20 BIT DATA 98 14 BIT CLOCKS 18 BIT DATA E 16 BIT CLOCKS 16 BIT DATA Figure 3 Serial Output Port Timing 10804 004 4 lcop tos tscu SDA SCL lt lt tscs gt Fe terr gt Figure 5 Port Timing 10804 005 Rev 0 12 of 116 10804 003 01772 lscuE ipse lt SDA 10804 006 gt tscse Figure 6 Self Boot Timing CLKOUT DMICO 1 DMIC2 3 10804 007 VALID LEFT SAMPLE VALID RIGHT SAMPLE VALID LEFT SAMPLE Figure 7 Digital Microphone Timing CLKOUT PDMOUT RIGHT 10804 008 Figure 8 PDM Output Timing Rev 0 Page 13 of 116 ADAU1772 ABSOLUTE MAXIMUM RATINGS Table 8 Parameter Rating Power Supply AVDD IOVDD 0 3 V to 3 63 V Digital Supply DVDD 0 3 V to 1 98 V Input Current Except Supply Pins 20 mA Analog Input Voltage Signal Pins 0 3 V to AVDD 0 3 V Digital Input Voltage Signal Pins 0 3
89. OL DACO volume setting 0x00 RW 00000000 0 dB 00000001 0 375 dB 11111111 95 625 dB VOLUME CONTROL REGISTER Address 0x0030 Reset 0x00 Name VOLUME 7 0 DAC 1 VOL RW 5 B4 B3 B2 BO DAC1 volume 00000000 0 dB 00000001 0 375 dB 11111111 95 625 dB Rev 0 Page 87 of 116 01772 Table 77 Bit Descriptions for VOLUME Bits Bit Name Settings Description Reset Access 7 0 DAC 1 VOL volume setting 0x00 RW 00000000 0dB 00000001 0 375 dB 11111111 95 625 dB HEADPHONE OUTPUT MUTES REGISTER Address 0x0031 Reset OP STAGE MUTES 88 B5 84 B3 B2 7 4 RESERVED RW 1 0 HP MUTE L RW Mute the left output pins 00 Outputs unmuted 01 HPOUTLP LOUTL muted HPOUTLN unmuted 10 HPOUTLP LOUTL unmuted HPOUTLN muted 11 Both output pins muted 3 2 HP MUTE R RW Mute the right output pins 00 Outputs unmuted 01 HPOUTRP LOUTR muted HPOUTRN unmuted 10 HPOUTRP LOUTR unmuted HPOUTRN muted 11 Both output pins muted Table 78 Bit Descriptions for OP STAGE MUTES Bits Bit Name Settings Description Reset Access 3 2 MUTE R Mute the right output pins When a pin is muted it can be used as a 0x3 RW common mode output 00 Outputs unmuted 01 HPOUTRP LOUTRP muted HPOUTRN LOUTRN unmuted 10 HPOUTRP
90. PGA3 mute 0 Unmuted 111111 35 25 dB Bit Descriptions for CONTROL 3 Bit Name Settings Description Reset Access 7 PGA EN3 Select line or microphone input Note that the PGA inverts the signal going through it AIN3 used as a single ended line input PGA powered down AIN3 used as a single ended microphone input PGA powered up with slewing 0x0 RW PGA_MUTE3 Enable PGA3 mute When PGA is muted PGA_GAIN3 is ignored Unmuted Muted 0x1 RW 5 0 PGA_GAIN3 000000 000001 010000 111110 111111 Set the gain of PGA3 12 dB 11 25 dB 0 dB 34 5 dB 35 25 dB 0x0 RW Rev 0 Page 81 of 116 ADAUI772 PGA SLEW CONTROL REGISTER Address 0x0027 Reset 0x00 PGA STEP CONTROL If PGA slew is disabled with the SLEW PDx controls the SLEW parameter is ignored for that PGA block B7 B8 B5 B4 B3 B2 0 SLEW_PDO RW PGAO slew enable 0 PGA slew enabled 1 PGA slew disabled 7 6 RESERVED RW 5 4 SLEW RATE RW Controls how fast the PGA is slewed when changing gain 00 21 5 1 SLEW_PD1 RW 01 42 5 PGA1 slew enable 10 85 ms 0 PGA slew enabled 3 SLEW_PD3 RW 1 PGA slew enabled slew enable 2 SLEW_PD2 RW 0 PGA slew enabled PGA2 slew enable 1 PGA slew enabled 0 PGA slew enabled 1 PGA slew enabled Table 68 Bit Descriptions for STEP CONTROL
91. Pressing and holding the switch closed enables the DSP bypass signal path as defined in the TALKTHRU register Address 0x002A The DAC volume control setting is switched from the default gain setting to the new TALKTHRU_GAINx register setting Address 0x002B and Address 0x002C DSP bypass is enabled only on ADCO and ADCI DSP bypass signal path is from the output of ADCx to the input of the DAC s When DSP bypass is enabled the current DAC volume setting is ramped down to 95 625 dB and the DSP bypass volume setting is ramped up to avoid pops when switching paths ADAU1772 DAC AND HP AMPLIFIER 10804 076 DAC AND HP AMPLIFIER 10804 077 Figure 85 DSP Bypass Path Enabled Rev 0 Page 45 of 116 ADAUI772 SERIAL DATA INPUT OUTPUT PORTS The serial data input and output ports of the ADAU1772 can be set to accept or transmit data in a 2 channel format or in a 4 channel or 8 channel TDM stream to interface to external ADCs DACs DSPs and SOCs Data is processed in twos complement MSB first format The left channel data field always precedes the right channel data field in the 2 channel streams In 8 channel TDM mode the data channels are output sequentially starting with the channel set by the SDATAO ST and ADC SDATAIL ST bits The serial modes and the position of the data in the frame are set in the serial data port SAI 0 SAI 1 and serial output control registers GOUT SOURCE x x Address 0x0013 t
92. SCL SCLK SCL input SCLK input Addressing 2 4 12 Initially each device on the bus is in an idle state and ib monitoring the SDA and SCL lines for a start condition and ADDRO SS Address Bit O input SS input Burst Mode Communication Burst mode addressing in which the subaddresses are automati cally incremented at word boundaries can be used for writing the proper address The master initiates a data transfer by establishing a start condition defined by a high to low transition on SDA while SCL remains high This indicates that an address data stream follows All devices on the bus respond to the start condition and shift the next eight bits the 7 bit address plus the Rev 0 Page 39 of 116 ADAUI772 R W bit MSB first The device that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse This ninth bit is known as an acknowledge bit All other devices withdraw from the bus at this point and return to the idle condition The R W bit determines the direction of the data A Logic 0 on the LSB of the first byte indicates that the master will write information to the peripheral whereas a Logic 1 indicates that the master will read information from the peripheral after writing the subaddress and repeating the start address A data transfer takes place until a stop condition is encountered A stop condition occurs when SDA transitions from low to hig
93. SRC to DSP Without Processing to ASRC to ADC_SDATAO to ASRC to ADC_SDATAO 2 500 0 450 2 400 MEL 6 350 8 x 300 5 5 10 amp 250 12 5 s x 3 200 150 16 Ap 100 20 50 22 g 0 2 100 1 10 i 0 10 20 30 40 50 60 70 80 5 2 8 FREQUENCY kHz Figure 53 Relative Level vs Frequency Figure 56 Group Delay vs Frequency 192 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing 192 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing to ASRC to ADC_SDATAO to ASRC to ADC_SDATAO 200 10 0 5 200 0 5 400 10 600 2 15 5 800 5 20 8 1000 25 2 1200 2 30 8 1400 35 40 1600 Ap 1800 50 2000 55 2200 2 60 8 0 10 20 30 40 50 60 70 80 0 0 2 04 06 0 8 10 12 14 16 18 20 5 2 8 2 Figure 54 Phase vs Frequency 80 kHz Bandwidth Figure 57 Phase vs Frequency 2 kHz Bandwidth 192 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing fs 192 kHz Signal Path DAC_SDATA to ASRC to DSP Without Processing to ASRC to ADC_SDATAO to ASRC to ADC_SDATAO Rev 0 Page 24 of 116 01772 INPUT IMPEDANCE MAGNITUDE dBFS MAGNITUDE dBFS 35 30 25 20 b 6 0 6 12 18 24 30 PGA GAIN SETTING dB Figure 58 Input Impedance vs PGA Gain see the Input Impedance section 36
94. X X X X X X N ACKNOWLEDGE ACKNOWLEDGE STOP BY BY ADAU1772 BY ADAU1772 MASTER FRAME 3 FRAME 4 lt SUBADDRESS BYTE 2 DATA BYTE 1 10804 068 Figure 75 Write to ADAU1772 Clocking SCL SDA START BY ACKNOWLEDGE ACKNOWLEDGE MASTER BY ADAU1772 BY ADAU1772 lt 1 gt a FRAME 2 gt CHIP ADDRESS BYTE SUBADDRESS BYTE 1 CONTINUED 11 LL I SDA CONTINUED ACKNOWLEDGE REPEATED ACKNOWLEDGE BY ADAU1772 START BY MASTER BY ADAU1772 3 4 IT SUBADDRESS BYTE 2 CHIP ADDRESS BYTE CONTINUED EE ACKNOWLEDGE BY ADAU1772 U SDA CONTINUED ACKNOWLEDGE STOP BY BYADAU1772 MASTER 10804 069 4 5 6 READ DATA BYTE 1 READ DATA BYTE 2 Figure 76 Read from ADAU1772 Clocking Rev 0 Page 40 of 116 1772 PC Read and Write Operations Figure 77 shows the timing of a single word write operation Every ninth clock pulse the ADAU1772 issues an acknowledge by pulling SDA low Figure 78 shows the timing of a burst mode write sequence This figure shows an example where the target destination words are two bytes such as the program memory The ADAU1772 knows to increment its subaddress register every two bytes because the requested subaddress corresponds to a register or memory area with a 2 byte word length The timing of a single word re
95. a high pass filter on the outputs The corner frequency of this filter which has an attenuation of 3 dB at this point is calculated by the following formula fas Mn x Rx where Ris the impedance of the headphones C is the capacitor value For a typical headphone impedance of 32 and a 220 uF capacitor the corner frequency is 23 Hz Pop and Click Suppression On power up the precharge circuitry is enabled on all four analog output pins to suppress pops and clicks After power up the precharge circuitry can be put into a low power mode using the HP_POP_DISx bits in the POP_SUPRRESS register Address 0x0029 The precharge time depends on the value of the capacitor connected to the CM pin and the RC time constant of the load on the output pin For a typical line output load the precharge time is between 2 ms and 3 ms After this precharge time the HP_POP_DISx bit can be set to low power mode To avoid clicks and pops all analog outputs that are in use should be muted while changing any register settings that may affect the signal path These outputs can then be unmuted after the changes have been made Line Outputs The analog output pins HPOUTLP LOUTLP HPOUTLN LOUTLN HPOUTRP LOUTRP and HPOUTRN LOUTRN can be used to drive both differential and single ended loads In their default settings these pins can drive typical line loads of 10 or greater When the line output pins are used in single ended mode
96. abled 1 Pull down enabled Pull down enable 0 Pull down disabled 1 Pull down enabled Pull down enable 0 Pull down disabled 1 Pull down enabled 3 BCLK_PD RW Pull down enable 0 Pull down disabled 1 Pull down enabled 0 DAC_SDATA_PD RW 1 ADC SDATAO PD RW 2 ADC SDATA1 PD RW Bits Bit Name Settings Description Reset Access 6 DMIC2 3 PD Pull down enable Pull down disabled Pull down enabled 0 0 RW DMICO_1_PD Pull down enable Pull down disabled Pull down enabled 0x0 RW LRCLK_PD Pull down enable Pull down disabled Pull down enabled 0 0 RW BCLK_PD Pull down enable Pull down disabled Pull down enabled 0 0 RW ADC_SDATA1_PD Pull down enable Pull down disabled Pull down enabled 0 0 RW ADC SDATAO PD Pull down enable Pull down disabled Pull down enabled 0 0 RW DAC_SDATA_PD Pull down enable Pull down disabled Pull down enabled 0 0 RW Rev 0 109 of 116 ADAUI772 DIGITAL PIN PULL DOWN CONTROL 1 REGISTER Address 0x004B Reset 0x00 Name PAD_CONTROL3 Controls the behavior of the pad Possible to enable pull down B7 B8 B5 B4 B3 B2 7 5 RESERVED RW 0 ADDRO_PD RW Pull down enable 4 SELFBOOT_PD RW 0 disabled Pull down enable ull down disa 1 Pull down enabled 0 Pull down disabled 1 Pull down enabled 1 ADDR1 PD RW 31 SCL PD
97. ad operation is shown in Figure 79 Note that the first R W bit is 0 indicating a write operation This is because the subaddress still needs to be written to set up the internal address After the ADAU1772 acknowledges the receipt of the subaddress the master must issue a repeated start command followed by the chip address byte with the R W set to 1 read This causes the ADAU1772 SDA to reverse and begin driving 2 D PC ADDRESS SUBADDRESS HIGH SUBADDRESS LOW 1 2 as B Figure 77 Single Word Write Format 12 ADDRESS SUBADDRESS SUBADDRESS DATAWORD 1 DATAWORD 1 DATAWORD 2 DATAWORD 2 R W 0 LOW BYTE 1 BYTE 2 BYTE 1 BYTE 2 data back to the master The master then responds every ninth pulse with an acknowledge pulse to the ADAU1772 Figure 80 shows the timing of a burst mode read sequence This figure shows an example where the target read words are two bytes The ADAU1772 increments its subaddress every two bytes because the requested subaddress corresponds to a register or memory area with word lengths of two bytes Other address ranges may have a variety of word lengths ranging from one to four bytes The ADAU1772 always decodes the subaddress and sets the auto increment circuit so that the address increments after the appropriate number of bytes Figure 77 to Figure 80 use the following abbreviations S start bit P stop bit AM ack
98. als to share the same readback line All SPI transactions have the same basic format shown in Table 23 A timing diagram is shown in Figure 81 and Figure 82 All data should be written MSB first The ADAU1772 can only be taken out of SPI mode by pulling the PD pin low or by powering down the IC Table 23 Generic SPI Word Format Read Write The first byte of an SPI transaction indicates whether the com munication is a read or a write with the R W bit The LSB of this first byte determines whether the SPI transaction is a read Logic Level 1 or a write Logic Level 0 Subaddress The 16 bit subaddress word is decoded into a location in one of the memories or registers This subaddress is the location of the appropriate memory location or register Data Bytes The number of data bytes varies according to the register or memory being accessed During a burst mode write an initial subaddress is written followed by a continuous sequence of data for consecutive memory register locations A sample timing diagram for a single write SPI operation to the parameter RAM is shown in Figure 81 A sample timing diagram of a single read SPI operation is shown in Figure 82 The MISO pin goes from tristate to being driven at the beginning of Byte 3 In this example Byte 0 to Byte 2 contain the addresses and the R W bit and subsequent bytes carry the data Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 0000000 R W Register memory address
99. armonic Distortion Noise Line output mode 20 Hz to 20 kHz 1 dBFS dB AVDD 1 8 93 dB AVDD 3 3 V 94 dB Gain Error Line output mode 0 1 dB Dynamic Range Headphone mode 20 Hz to 20 kHz 60 dB input With A Weighted Filter RMS AVDD 1 8 100 AVDD 3 3 V 104 With Flat 20 Hz to 20 kHz Filter AVDD 1 8 V 97 AVDD 3 3 V 101 Signal to Noise Ratio Headphone mode 20 Hz to 20 kHz With A Weighted Filter RMS AVDD 1 8V 100 dB AVDD 3 3 V 104 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8 V 98 dB AVDD 3 3 V 102 dB Interchannel Gain Mismatch Headphone mode 50 mdB Total Harmonic Distortion Noise Headphone mode 20 Hz to 20 kHz 1 dBFS 32 load AVDD 1 8 V 6 7 mW 77 AVDD 3 3 V 22 4 mW 80 24 Q load AVDD 1 8 V 8 9 mW 76 AVDD 3 3 V 30 mW 79 16 load AVDD 1 8 V 13 mW 74 AVDD 3 3 V 44 mW 77 Headphone Output Power 32 Load AVDD 1 8 lt 0 1 THD 8 4 mW AVDD 3 3 V 0 196 THD 28 1 mW 24 Q Load AVDD 1 8 V 0 196 THD 11 2 mW AVDD 3 3 V 0 196 THD 374 mW 16 Load AVDD 1 8 V 0 196 THD 16 25 mW AVDD 3 3 V 0 196 THD 55 8 mW Gain Error Headphone mode 0 1 dB Offset Error 0 1 mV Interchannel Isolation 1 kHz 0 dBFS input signal 100 dB Power Supply Rejection Ratio CM capacitor 22 pF 100 mV p p at 1 kHz 70 dB DAC DIFFERENTIAL OUTPUT Differential operation Fu
100. ble 0 0 RW 0 Disabled 1 Enabled 1 MIC_GAIN1 Level of the MICBIAS1 output 0 0 RW 0 0 9x AVDD 1 0 65 x AVDD 0 MIC_GAINO Level of the MICBIASO output 0 0 RW 0 0 9 x AVDD 1 0 65 x AVDD DAC CONTROL REGISTER Address 0x002E Reset 0x18 Name DAC CONTROLI 7 6 RESERVED RW 5 DAC POL RW Invert input polarity B7 B6 B5 B4 B3 B2 B1 BO ep iude 0 DACO RW Enable DACO 0 Disable DACO 1 Enable DACO 0 Normal 1 Inverted 1 DAC1 EN RW Enable DAC1 NN re E i 0 Disable DAC1 1 Enable DAC1 0 Unmuted 1 Muted 2 RESERVED RW DACO MUTE RW Mute DACO 0 Unmuted 1 Muted Rev 0 Page 86 of 116 ADAU1772 Table 75 Bit Descriptions for DAC CONTROLI Bits Bit Name Settings Description Reset Access 5 DAC POL Invert input polarity 0x0 RW 0 Normal 1 Inverted 4 DAC1_MUTE Mute DAC1 0 1 RW 0 Unmuted 1 Muted 3 DACO_MUTE Mute DACO 0 1 RW 0 Unmuted 1 Muted 1 DAC1_EN Enable DAC1 0x0 RW 0 Disable 1 Enable DAC1 0 _ 0x0 RW 0 Disable DACO 1 Enable DACO DACO VOLUME CONTROL REGISTER Address 0x002F Reset 0x00 DACH VOLUME BS B2 BI B 7 0 DAC 0 VOL Rwy T DACO volume setting 00000000 0 dB 00000001 0 375 dB 11111111 95 625 dB Table 76 Bit Descriptions for VOLUME Bits Bit Name Settings Description Reset Access 7 0 DAC 0 V
101. digital microphones 0 Decimator source set to ADC 1 Decimator source set to digital microphones DMIC SWO RW Digital microphone swap 0 Channel swap off left channel on rising edge right channel on fallinc edge 1 Swap left and right Bits Bit Name Settings Description Reset Access 6 5 HP 01 EN High pass filter settings 0 0 RW 00 Off 01 1Hz 10 4Hz 11 8Hz 4 DMIC_POLO Selects microphone polarity 0 0 RW 0 Opositive 1 negative 1 1 positive 0 negative 3 DMIC SWO Digital microphone swap 0x0 RW 0 Channel swap off left channel on rising edge right channel on falling edge 1 Swap left and right 2 DCM 01 Sets the input source to ADCs or digital microphones 0 0 RW 0 Decimator source set to ADC 1 Decimator source set to digital microphones 1 ADC_1_EN Enable ADC1 This bit must be set in conjunction with the SINC_1_EN bit 0 0 RW in the DECIM_PWR_MODES register to fully enable or disable the ADC 0 Disable 1 Enable 0 ADC 0 Enable ADCO This bit must be set in conjunction with the SINC EN bit 0 0 RW in the DECIM PWR MODES register to fully enable or disable the ADC 0 Disable 1 Enable Rev 0 Page 75 of 116 01772 ADC2 ADC3 CONTROL 1 REGISTER Address 0x001E Reset 0x00 Name ADC_CONTROL3 B7 B8 B5 B4 B3 B2 0 19121211219 7 RESERVED RW ix T m ADC_2_EN RW Enable ADC2 6 5 _2 3 RW 0
102. drive strength 1 High drive strength Bits Bit Name Settings Description Reset Access 4 LRCLK DRV Drive strength control Low drive strength High drive strength 0 0 RW BCLK_DRV Drive strength control Low drive strength High drive strength 0x0 RW ADC_SDATA1_DRV Drive strength control Low drive strength High drive strength 0 0 RW ADC SDATAO DRV Drive strength control Low drive strength High drive strength 0 0 RW Rev 0 111 of 116 ADAUI772 DIGITAL PIN DRIVE STRENGTH CONTROL 1 REGISTER Address 0x004D Reset 0x00 Name PAD CONTROLS5 7 5 RESERVED RW 4 RESERVED RW 3 SCL DRV RW Drive strength control 0 Low drive strength 1 High drive strength B7 B6 B5 B4 B3 B2 B1 a LE Table 104 Descriptions for PAD CONTROL5 0 RESERVED RW 1 RESERVED RW 2 SDA_DRV RW Drive strength control 0 Low drive strength 1 High drive strength Bits Bit Name Settings Description Reset Access 3 SCL_DRV Drive strength control 0 0 RW Low drive strength High drive strength 2 SDA_DRV Drive strength control 0 0 RW Low drive strength High drive strength Rev 0 112 of 116 01772 OUTLINE DIMENSIONS 6 10 0 30 I 800 sa 023 PIN1 5 90 0 18 INDICATOR PIN 1 INDICATOR 0 45 L L TOP VIEW 24 1 BOTTOM VIEW 0 25 MIN 0
103. e for volume down The volume setting can either be changed with a click of the button or be ramped by holding the button The volume settings change when the signal on the pin from the button goes from low to high When in push button mode the initial volume level is set with Bits PB_VOL_INIT_VAL By default MP1 acts as the push button volume up and MP6 acts as the push button volume down however any of the MPx pins can be set to act as the push button up and push button down volume controls When the ADC and or DAC volumes are controlled with the push buttons the corresponding volume control registers no longer allow control of the volume from the control port Therefore writing to these volume control registers has no effect on the codec volume level LIMITER COMPRESSION ENABLE This function allows a user to enable limiter compression regardless of the signal level Setting an MPx pin low when this function is enabled causes the limiter to compress the incoming signal by the minimum gain setting When the MPx pin is released the limiter resumes normal behavior PARAMETER BANK SWITCHING An MPx pin can be used to switch the active parameter bank between Bank A and Bank B When this setting is selected Bank A is active when the pin is high and Bank B is active when the pin is low Care should be taken to set the BANK_SL bits in the CORE_CONTROL register Address 0x0009 to the default value of 0x00 before enabling MPx pin contro
104. e or disable the ADC 0 Disable 1 Enable Rev 0 Page 76 of 116 1772 ADCO VOLUME CONTROL REGISTER Address 0x001F Reset 0x00 Name ADCO_VOLUME When SINC_0_EN is set the volume starts to ramp from 95 625 dB to the value in this register The volume ramp time is number of steps x 16 6 where there are 256 steps between 0 dB and 95 625 dB For example with fs 192 kHz the volume ramps from 95 625 dB to 0 dB in 21 ms B7 B5 B4 B3 B2 BO 7 0 0 VOL RW ADCO volume 00000000 0 dB 00000001 0 375 dB 11111111 95 625 dB Table 60 Bit Descriptions for ADCO_VOLUME Bits Bit Name Settings Description Reset Access 7 0 ADC 0 VOL ADCO volume setting 0x00 RW 00000000 0dB 00000001 0 375 dB 11111111 95 625 dB ADC1 VOLUME CONTROL REGISTER Address 0x0020 Reset 0x00 Name ADC1_VOLUME When SINC_1_EN is set the volume starts to ramp from 95 625 dB to the value in this register The volume ramp time is number of steps x 16 fs where there are 256 steps between 0 dB and 95 625 dB For example with 6 192 kHz the volume ramps from 95 625 dB to 0 dB in 21 ms B7 5 B4 B3 B2 BO J 7 0 1 VOL RW ADC1 volume 00000000 0 dB 00000001 0 375 dB 11111111 95 625 4 Table 61 Bit Descriptions for ADC1_VOLUME Bit
105. egister PLL CTRL5 is 1 Note that after COREN is enabled writing to the parameters is disabled until setting 5 EN in the CORE ENABLE register 0 Main clock disabled 1 Main clock enabled PLL DENOMINATOR MSB REGISTER Address 0x0001 Reset 0x00 Name CTRLO This register should only be written when PLL EN 0 in Register CONTROL B5 B3 B2 BI 7 0 M MSB RW PLL Denominator MSB Table 31 Bit Descriptions for CTRLO Bits Bit Name Settings Description Reset Access 7 0 M MSB PLL denominator MSB 0x00 RW PLL DENOMINATOR LSB REGISTER Address 0x0002 Reset 0x00 Name PLL_CTRL1 This register should only be written when PLL_EN 0 in Register CLK_CONTROL 85 B2 7 0 LSB RW J PLL Denominator LSB Table 32 Bit Descriptions for PLL_CTRL1 Bits Bit Name Settings Description Reset Access 7 0 M_LSB PLL denominator LSB 0x00 RW PLL NUMERATOR MSB REGISTER Address 0x0003 Reset 0x00 Name PLL_CTRL2 This register should only be written when PLL_EN 0 in Register CLK_CONTROL 7 0 N MSB RW Numerator MSB Rev 0 Page 53 of 116 ADAU1772 Table 33 Bit Descriptions for 2 Bits Bit Name Settings Description Reset Access 7 0 N_MSB PLL numerator MSB 0x00 RW PLL NUMERATOR LSB REGISTER Address 0x0004 Reset 0x00 Name PLL_CTRL3 This register s
106. er at startup the impedance looking into the pin is dominated by the time constant of the CM pin because the precharge amplifiers reference the CM voltage Microphone Bias The ADAU1772 includes two microphone bias outputs MICBIASO and MICBIASI These pins provide a voltage reference for electret analog microphones The MICBIASx pins can also be used to cleanly supply voltage to digital or analog MEMS microphones with separate power supply pins The MICBIASx voltage is set in the microphone bias control register Address 0x002D Using this register either the MICBIASO or MICBIASI output can be enabled and disabled The gain options provide two possible voltages 0 65 x AVDD or 0 90 x AVDD Many applications require enabling only one of the two bias outputs The two bias outputs should both be enabled when many microphones are used in the system or when the positioning of the microphones on the PCB does not allow one pin to bias all microphones Rev 0 Page 32 of 116 1772 DIGITAL MICROPHONE INPUT When using a digital microphone connected to the DMICO 1 MP4 and DMIC2_3 MP5 pins the 0 1 and DCM_2_3 bits in Register 0x001D and Register 0x001E must be set to enable the digital microphone signal paths The pin functions should also be set to digital microphone input in the corresponding pin mode registers Address 0x003C and Address 0x003D The DMICO DMIC2 and DMIC1 DMIC3 channels be swapped left righ
107. ereby improving the signal integrity of the clock and data lines These can set in the DAD CONTROLA register Address 0x004C Table 27 Serial In Out Port Master Slave Mode Capabilities 2 Channel Modes PS Left Justified 4 Channel 8 Channel fssp Right Justified TDM TDM 48 kHz Yes Yes Yes 96 kHz Yes Yes No 192 kHz Yes No No Table 28 describes the proper serial port settings for standard audio data formats More information about the settings in this table can be found in the Serial Port Control 0 and Serial Port Control 1 registers Address 0x0032 and Address 0x0033 descriptions TRISTATING UNUSED CHANNELS Unused outputs can be tristated so that multiple ICs can drive a single TDM line This function is available only when the serial ports of the ADAU1772 are operating in TDM mode Channels that are inactive can be set in the SOUT CONTROLO register Address 0x0034 The tristating of inactive channels is set in the SAI 1 register Address 0x0033 which offers the option of tristating or driving the inactive channel In a 32 bit TDM frame with 24 bit data the eight unused bits are tristated Inactive channels are also tristated for the full frame LRCLK Polarity LRCLK Type BCLK Polarity MSB Position Format LR POL LR MODE BCLKEDGE SDATA_FMT 25 Figure 86 0 0 0 00 Left Justified Figure 87 1 0 0 01 Right Justified Figure 88 and Figure 89 1 0 0 100r 11 TDM Figure 90 and Figure 91 1 Dor
108. ereo IS left justified right justified 01 TDM2 10 TDM4 11 TDM8 3 0 SER_PORT_FS Sampling rate on the serial ports 0 0 RW 0000 48 kHz 0001 8 kHz 0010 12 kHz 0011 16 kHz 0100 24 kHz 0101 32 kHz 0110 96 kHz 0111 192 kHz Rev 0 Page 89 of 116 ADAUI772 SERIAL PORT CONTROL 1 REGISTER Address 0x0033 Reset 0x00 Name SAI_1 Using 16 bit serial I O limits device 5 B4 B3 B2 7 TS RW 0 SAI MS RW Select whether to tristate unuse Sets the serial port into master or TDM channels or to actively slave mode these data slots 0 LRCLK BCLK slave 0 Unused outputs driven 1 LRCLK BCLK master 1 Unused outputs tristated 1 BCLKEDGE RW 6 BCLK TDMC RW Sets the bit clock edge on which Bit width in TDM mode data changes 0 24 bit data in each TDM channel 0 Data changes on falling edge 1 16 bit data in each TDM channel 1 Data changes on rising edge 5 LR MODE RW 2 BCLKRATE RW Sets LRCLK mode Sets the number of bit clock cycles 0 5096 duty cycle clock per data channel 1 Pulse LRCLK is a single BCLK 0 32 BCLKs channel cycle wide pulse 1 16 BCLKs channel POL RW SAILMSB RW Sets LRCLK polarity Sets data to be input output either 0 50 when LRCLK goes low and MSB or LSB first then high pulse mode is short 0 MSB first data positive pulse 1 LSB first data 50 when LRCLK goes high and then l
109. f 116 01772 REGISTER DETAILS CLOCK CONTROL REGISTER Address 0x0000 Reset 0x00 Name CLK_CONTROL This register is used to enable the internal clocks Table 30 7 RW Enable PLL 0 PLL disabled 1 PLL enabled 6 RESERVED RW 5 SPK_FLT_DIS RW Disable 2 spike filter 0 2 spike filter enabled 1 DC spike filter disabled 4 XTAL_DIS RW Disable crystal oscillator 0 Crystal oscillator enabled 1 Crystal oscillator disabled SES E 0 RW Main clock enable 0 Main clock disabled 1 Main clock enabled 1 CC_MDIV RW MCLK divider control 0 Div 2 divide PLL external clock by 2 1 Div 1 divide PLL external clock by 1 2 CC_CDIV RW SCLK divider control 0 Div 2 divide PLL external clock by 2 1 Div 1 divide PLL external clock by 1 3 CLKSRC RW Main clock source 0 External pin drives main clock 1 PLL drives main clock This bit should only be set after LOCK in Register CTRL5 has gone high Bit Descriptions for CLK CONTROL Bits Bit Name Settings Description Reset Access 7 PLL EN Enable PLL When this bit is set to 0 the PLL is powered down and the PLL output clock is disabled The PLL should not be enabled until after all the PLL control settings Register PLL_CTRLO to Register CTRL5 have been set The PLL clock output is active when both EN 1 COREN 1 PLL disabled PLL enab
110. h while SCL is held high Figure 75 shows the timing of an write and Figure 76 shows an read Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations the ADAU1772 immediately SCL SDA START BY ACKNOWLEDGE MASTER BY ADAU1772 jumps to the idle condition During a given SCL high period the user should only issue one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADAU1772 does not issue an acknowledge and returns to the idle condition If the user exceeds the highest subaddress while in auto increment mode one of two actions is taken In read mode the ADAU1772 outputs the highest subaddress register contents until the master device issues a no acknowledge indicating the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth clock pulse on SCL If the highest subaddress location is reached while in write mode the data for the invalid byte is not loaded into any subaddress register a no acknowledge is issued by the ADAU1772 and the part returns to the idle condition ACKNOWLEDGE BY ADAU1772 FRAME 1 FRAME 2 CHIP ADDRESS BYTE SUBADDRESS BYTE 1 CONTINUED SDA comit X X X X X X X X N K X
111. he MDIV bit in the clock control register Address 0x0000 When bypassing the PLL the clock associated with MCLKIN must be either 12 288 MHz or 24 576 MHz The internal master clock of the ADAU1772 is disabled until the COREN bit is asserted PLL Enabled Setup The core clock of the ADAU1772 is disabled by the default setting of Bit COREN and should remain disabled during the PLL lock acquisition period The user can poll the LOCK bit to determine when the PLL has locked After lock is acquired the ADAUI772 can be started by asserting the COREN bit This bit enables the core clock for all the internal blocks of the ADAU1772 To program the PLL during initialization or reconfiguration of the codec the following procedure must be followed 1 Ensure that EN Bit 7 Address 0x0000 is set low 2 Set reset the PLL control registers Address 0x0001 to Address 0x0005 3 Enable the PLL using the PLL EN bit 4 Poll the PLL lock bit in Register 0x0006 5 Set the COREN bit in Register 0x0000 after PLL lock is acquired Control Port Access During Initialization During the lock acquisition period only Register 0x0000 to Register 0x0006 are accessible through the control port A read or write to any other register is prohibited until the core clock enable bit and the lock bit are both asserted After the CORE_RUN bit Address 0x0009 is set high the DAC SOURCEO0 and DAC SOURCE register bits should not be changed If these
112. he digital outputs and one stereo ASRC is available for the digital input signals The ASRCs can convert serial output data from the core rate of up to 192 kHz back down to less than 8 kHz All intermediate frequencies and ratios are also supported SIGNAL LEVELS The ADCs DACs and ASRCs have fixed gain settings that should be considered when configuring the system These settings were chosen to maximize performance of the converters and to ensure that there is 0 dB gain for any signal path from the input of the ADAU1772 to its output Therefore the full scale level of a signal in the processing core will be slightly different from a full scale level external to the IC Input paths such as through the ADCs and input ASRCs are scaled by 0 75 or about 2 5 dB Output paths such as through the DACs or output ASRCs are scaled by 1 33 or about 2 5 dB This is shown in Figure 74 ADC CORE DAC OUTPUT ASRCS Figure 74 Signal Level Diagram V 10804 067 Because of this input and output scaling output signals from the core should be limited to 2 5 dB full scale to prevent the DACs and ASRCs from clipping Rev 0 Page 35 of 116 ADAUI772 SIGNAL PROCESSING The ADAU1772 processing core is optimized for active noise cancelling ANC processing The processing capabilities of the core include biquad filters limiters volume controls and mixing The core has four inputs and four outputs The core is controlled w
113. hould only be written when PLL_EN 0 in Register CLK_CONTROL 88 85 B Bi B 7 0 N_LSB RW J PLL Numerator LSB Table 34 Bit Descriptions for CTRL3 Bits Bit Name Settings Description Reset Access 7 0 N_LSB PLL numerator LSB 0x00 RW PLL INTEGER SETTING REGISTER Address 0x0005 Reset 0x00 PLL_CTRL4 This register should only be written when PLL_EN 0 in Register CLK_CONTROL B5 B B 0 0 0 0 0 0 0 0 7 RESERVED RW 0 PLL_TYPE RW 6 3 R RW PLL Type 0 Integer PLL integer setting 1 Fractional 0000 Reserved 0001 Reserved 2 1 X RW 0010 2 PLL input clock divide ratio 0011 3 00 Pin clock input 1 0100 4 01 Pin clock input 2 0101 5 10 Pin clock input 3 0110 6 11 Pin clock input 4 0111 7 1000 8 Table 35 Bit Descriptions for Bits Bit Name Settings Description Reset Access 6 3 R PLL integer setting 0 0 RW 0000 Reserved 0001 Reserved 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 Rev 0 Page 54 of 116 1772 Bits Bit Name Settings Description Reset Access 2 1 X PLL input clock divide ratio 0 0 RW 00 Pin clock input 1 01 Pin clock input 2 10 Pin clock input 3 11 Pin clock input 4 0 PLL_TYPE PLL type 0x0 RW 0 Integer 1 Fractional PLL LOCK FLAG REGISTER Address 0x0006 Reset 0x00 Name PLL_CTRL5 87 B5 B4 B3
114. ial input sample rate 48 kHz measurement bandwidth 20 Hz to 20 kHz word width 24 bits ambient temperature 25 C outputs line loaded with 10 ANALOG PERFORMANCE SPECIFICATIONS Supply voltages AVDD IOVDD 1 8 V DVDD 1 1 V unless otherwise noted PLL disabled direct master clock Table 1 Parameter Test Conditions Comments Min Typ Max Unit ANALOG TO DIGITAL CONVERTERS ADC Resolution All ADCs 24 Bits Digital Attenuation Step 0 375 dB Digital Attenuation Range 95 dB INPUT RESISTANCE Gain settings do not include 10 dB gain from PGA_x_BOOST settings this additional gain does not affect input impedance PGA_POP_DISx 1 Single Ended Line Input 0 dB 14 3 kQ PGA Inputs 12 dB gain 32 0 kQ 0 dB gain 20 kQ 35 25 dB gain 0 68 kQ SINGLE ENDED LINE INPUT PGA_ENx 0 PGA_x_BOOST 0 PGA_POP_DISx 1 Full Scale Input Voltage Scales linearly with AVDD AVDD 3 63 Vrms AVDD 1 8V 0 49 Vrms AVDD 1 8 V 0 dBFS 1 38 Vp p AVDD 3 3 V 0 90 Vrms AVDD 3 3 V 0 dBFS 2 54 Vp p Dynamic Range 20 Hz to 20 kHz 60 dB input With A Weighted Filter RMS AVDD 1 8V 97 dB AVDD 3 3 V 102 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 94 dB AVDD 3 3 V 99 dB Signal to Noise Ratio SNR With A Weighted Filter RMS AVDD 1 8V 98 dB AVDD 3 3 V 103 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 96 dB AVDD 3 3 V 100 dB Interchannel Gain Mismatch 40 mdB Total Harmonic Distortion Noise THD N 20 Hz 2
115. igital processing engine to perform filtering level control signal level monitoring and mixing The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise cancelling headsets With the addition of just a few passive components a crystal and an EEPROM for booting the ADAU1772 provides a complete headset solution FUNCTIONAL BLOCK DIAGRAM MICBIASO MICROPHONE A BIAS GENERATORS 2 9 gt gt gt gt w lt lt lt O OQO ADAU1772 POWER LDO MICBIAS1 MANAGEMENT REGULATOR AINOREF Tess _ gt ADC_SDATA1 CLKOUT MP6 1 AINO 1 PLL ett XTALIIMCLKIN ADC becmaron gt Q XTALO AIN1REF Q E gt CO HPOUTLP LOUTLP ADC DAC AINI MODULATOR HPOUTLN LOUTLN DECIMATOR INPUT OUTPUT SIGNAL STEREO PDM DMICO_1 MP4 DIGITAL ROUTING MODULATOR MICROPHONE DMIC2_3 MP5 INPUTS AIN2REF ADC DECIMATOR HPOUTRP LOUTRP HPOUTRN LOUTRN AIN2 SERAL DAC_SDATA MPO MODULATOR BIDIRECTIONAL INPUT ADC_SDATA0 PDMOUT MP1 111 ASRCS OUTPUT BCLK MP2 AIN3REF DSP CORE PORT OO LRCLK MP3 BIQUAD FILTERS AINS DECIMATOR U ADC MODULATOR CM O DGND O Figure 1 Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibili
116. iin Interpolator and DAC Modulator Power Control Se K u Y PGA Control itte en 80 5 Bc a Analog Bias Control 0 Register EEN 105 ontro uiid M HE Analog Bias Control 1 Register EEN 106 ew Control Register 82 i Bd ei Digital Pin Pull Up Control 0 Register 107 ain Boost Regtster S Digital Pin Pull Up Control 1 Register 108 Input and Output Capacitor Charging Register 84 DPE Xd Digital Pin Pull Down Control 0 Register 109 ass Path Register 85 ER d ae oe 85 Digital Pin Pull Down Control 1 Register 110 ass Gain for Caii Gen Dd i ROS S Digital Pin Drive Strength Control 0 Register 111 ass Gain for 1 Register jessie 85 MIO e T nds 5 Digital Pin Drive Strength Control 1 Register 112 E _1 Control Register P Outline Dimensions 113 DAC Control Register 86 Ordering Guide tti ieget 113 Volume Control Register see 87 Volume Control Register 87 REVISION HISTORY 7 12 Revision 0 Initial Version Rev 0 Page3 of 116 01772 SPECIFICATIONS Master clock core clock 12 288 MHz ser
117. ith a 10 bit program word with a maximum of 32 instructions per frame INSTRUCTIONS complete list of instructions processing blocks along with documentation can be found in the SigmaStudio software for the ADAUI772 The processing blocks available are e Single precision biquad second order filters e Absolute value Two input addition e connection in SigmaStudio e Limiter with without external detector loop e Linear gain e Volume slider e Mute DBREG level detection DATA MEMORY The ADAUI772 data path is 26 bits 5 21 format The data memory is 32 words of 2 x 26 bits The double length memory enables the core to double precision arithmetic with double length data and single length coefficients PARAMETERS Parameters such as filter coefficients limiter settings and volume control settings are saved in parameter registers Each parameter is a 32 bit number The format of this number depends on whether it is controlling a filter or a limiter The number formats of different parameters are shown in Table 15 When the parameter formats use less than the full 32 bit memory space as with the limiter parameters the data is LSB aligned Table 15 Parameter Number Formats Parameter Type Format Filter Coefficient BO B1 B2 5 27 Filter Coefficient A1 2 27 sign extended Filter Coefficient A2 1 27 sign extended Maximum Gain 2 23 Minimum Gain 2 23 Attack Time 24 0 Decay Time 24 0 Threshold 2 23
118. l Input 7 1111 Serial Input 7 Table 48 Bit Descriptions for SOUT SOURCE 0 1 Bits Bit Name Settings Description Reset Access 7 4 SOUT SOURCE Serial Data Output Channel 1 source select 0x5 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 3 0 SOUT SOURCEO Serial Data Output Channel 0 source select 0 4 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 Rev 0 Page 65 of 116 ADAU1772 Bits Bit Name Settings Description Reset Access 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 SERIAL DATA OUTPUT 2 SERIAL DATA OUTPUT 3 INPUT SELECT REGISTER Address 0x0014 Reset 0x76 Name SOUT_SOURCE_2_3 85 B4 B2 Bi 7 4 SOUT_SOURCE3 RW T 3 0 SOUT_SOURCE2 RW Serial Data Output Channel 3 source Serial Data Output Channel 2 source select select
119. l operation default 01 Extreme power saving 10 Enhanced performance 11 Power saving 5 4 AFE_IBIASO1 Analog Front End 0 and Analog Front End 1 bias current setting Higher 0x0 RW bias currents result in higher performance 00 Normal operation default 01 Extreme power saving 10 Enhanced performance 11 Power saving 3 2 ADC_IBIAS23 ADC2 and ADC3 bias current setting Higher bias currents result in higher 0 0 RW performance 00 Normal operation default 01 Reserved 10 Enhanced performance 11 Power saving 1 0 ADC_IBIASO1 ADCO and ADC1 bias current setting Higher bias currents result inhigher 0 0 RW performance 00 Normal operation default 01 Reserved 10 Enhanced performance 11 Power saving ANALOG BIAS CONTROL 1 REGISTER Address 0x0047 Reset 0x00 Name BIAS CONTROLI B7 B5 B4 B3 B2 BO o L JL 1 7 RESERVED RW 1 0 DAC_IBIAS RW 6 DIS RW DAC bias current setting i 00 Normal operation default Central analog bias circuitry 01 Power saving 0 Powered up 2 10 Superior performance 1 Powered down 11 Enhanced performance 5 4 AFE IBIAS23 RW o Front End 2 and Analog ka can Front End 3 current setting d SE 00 Normal operation default 00 Normal operation default a 01 Extreme power saving 01 Extreme power saving 10 Enhanced performance 10 Enhanced performance 11 Power saving
120. l over bank switching Simultaneous control of bank switching by both register setting and MPx pin selection is not possible Bit ZERO_STATE selects whether the data memory of the codec is set to 0 during a bank switch If the data is not set to 0 when a new set of filter coefficients is enabled via a bank switch there may pop in the audio as the old data is circulated in the new filters MUTE The MPx pins can be put into a mode to mute the ADCs or DACs When in this mode mute is enabled when an MPx pin is set low The full combination of possible mutes for ADCs and DACs using MPx pins are set in Register 0x0038 to Register 0x003E Rev 0 Page 44 of 116 1772 DSP BYPASS When DSP bypass mode is enabled a direct path from the ADC outputs to the DACs is set up to enable bypassing the core pro cessing to listen to environmental sounds This is useful for listening to someone speaking without having to remove the noise cancelling headphones The DSP bypass path is enabled by setting an MPx pin low Figure 84 shows the DSP bypass path disabled and Figure 85 shows the DSP bypass path enabled by pressing the push button switch The DSP bypass feature works for both analog and digital microphone inputs DSP bypass is enabled when a switch connected to an MPx pin that is set to DSP bypass mode is closed and the MPx pin signal AINXREF PGA AND ADC NORMAL SETTING ADAU1772 is pulled low
121. led 0x0 RW SPK_FLT_DIS Disable spike filter By default the SDA and SCL inputs have 50 ns spike suppression filter When the control interface is in SPI mode this filter is disabled regardless of this setting spike filter enabled spike filter disabled 0 0 RW XTAL_DIS Disable crystal oscillator Crystal oscillator enabled Crystal oscillator disabled 0x0 RW CLKSRC Main clock source External pin drives main clock PLL drives main clock This bit should only be set after LOCK in Register PLL_CTRL5 has gone high 0x0 RW CC_CDIV SCLK divider control The core clock SCLK is used only by the core It must run at 12 288 MHz Div 2 divide PLL external clock by 2 Div 1 divide PLL external clock by 1 0x0 RW CC_MDIV MCLK divider control The internal master clock MCLK of the IC is used by all digital logic except the core It must run at 12 288 MHz Div 2 divide PLL external clock by 2 Div 1 divide PLL external clock by 1 0 0 RW Rev 0 Page 52 of 116 1772 Bits Bit Name Settings Description Reset Access 0 Main clock enable When 0 it is only possible to write to this 0 0 RW register and the PLL control registers PLL_CTRLO to PLL_CTRL5 This control also enables the PLL clock If using the PLL do not set COREN 1 until LOCK in R
122. led 1 Pull up disabled B7 B6 B5 B4 B3 B2 L 0 DAC SDATA PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled 1 ADC SDATAO PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled 2 SDATA1 PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled 3 BCLK PU RW Pull up disable 0 Pull up enabled 1 Pull up disabled Table 99 Bit Descriptions for PAD CONTROLO Bits Bit Name Settings Description Reset Access 6 DMIC2 3 PU Pull up disable Pull up enabled Pull up disabled 0 1 RW DMICO_1_PU Pull up disable Pull up enabled Pull up disabled 0 1 RW LRCLK_PU Pull up disable Pull up enabled Pull up disabled 0 1 RW Rev 0 107 of 116 ADAUI772 Bits Bit Name Settings Description Reset Access 3 BCLK_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 2 ADC_SDATA1_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 1 ADC SDATAO PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled 0 DAC_SDATA_PU Pull up disable 0 1 RW 0 Pull up enabled 1 Pull up disabled DIGITAL PIN PULL UP CONTROL 1 REGISTER Address 0x0049 Reset 0x1F Name PAD CONTROLI Controls the behavior of the pad Possible to enable pull up B7 B5 B4 B3 B2 BO 0 0 0 1 1 1
123. ll Scale Output Voltage Scales linearly with AVDD AVDD 1 8 V rms AVDD 1 8 V 1 0 Vrms AVDD 1 8 V dBFS 2 58 V p p AVDD 33 1 83 Vrms AVDD 3 3 V 0 dBFS 5 49 Vp p Mute Attenuation 72 Dynamic Range Line output mode 20 Hz to 20 kHz 60 dB input With A Weighted Filter RMS AVDD 1 8V 104 dB AVDD 3 3 V 107 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8 V 101 dB AVDD 3 3 V 105 dB Signal to Noise Ratio Line output mode 20 Hz to 20 kHz With A Weighted Filter RMS AVDD 1 8 V 105 dB AVDD 3 3 V 108 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8 V 102 dB AVDD 3 3 V 105 dB Interchannel Gain Mismatch Line output mode 20 mdB Total Harmonic Distortion Noise Line output mode 20 Hz to 20 2 1 dBFS dB AVDD 1 8 V 96 dB AVDD 3 3 V 96 dB Gain Error Line output mode Rev 0 Page 6 of 116 1772 Parameter Test Conditions Comments Min Typ Max Unit Dynamic Range Headphone mode 20 Hz to 20 kHz 60 dB input With A Weighted Filter RMS AVDD 1 8V 104 dB AVDD 3 3 V 107 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 102 dB AVDD 3 3 V 104 Signal to Noise Ratio Headphone mode 20 Hz to 20 kHz With A Weighted Filter RMS AVDD 1 8V 105 dB AVDD 3 3 V 108 dB With Flat 20 Hz to 20 kHz Filter AVDD 1 8V 103 dB AVDD 3 3 V 106 Interchannel Gain Mismatch Headphone mode 75 mdB Total Harmonic Distortion Noise Headphone mode 32 Load
124. nd ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable Rev 0 Page 94 of 116 1772 Bits Bit Name Settings Description Reset Access 10000 Push button volume up 10001 Push button volume down 10010 modulator output MP2 FUNCTION SETTING REGISTER Address 0x003A Reset 0x00 Name MODE MP2 B7 B6 B5 B4 B3 B2 B 5 7 5 RESERVED RW 4 0 MODE_MP2_VAL RW Sets the function of Pin BCLK MP2 00000 Bit clock 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute DAC1 01010 Mute both DACs 01011 bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down Table 86 Bit Descriptions for MODE_MP2 Bits Bit Name Settings Description Reset Access 4 0 MODE_MP2_VAL Sets the function of Pin BCLK MP2 0x00 RW 00000 Bit clock 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute 01010 Mute both DACs 01011 A B bank
125. nowledge by master AS acknowledge by slave 10804 070 10804 071 Figure 78 Burst Mode Write Format 12C ADDRESS SUBADDRESS SUBADDRESS RW 0 LOW H ADDRESS 1 2 DATA BYTE e 10804 072 Figure 79 Single Word Read Format 12 ADDRESS SUBADDRESS SUBADDRESS 5 12 ADDRESS DATAWORD 1 DATAWORD 1 R W 0 LOW R W 1 BYTE 1 BYTE2 10804 073 Figure 80 Burst Mode Read Format Rev 0 Page 41 of 116 01772 SPI PORT By default the ADAU1772 is in mode but it can be put into SPI control mode by pulling SS low three times This can be easily accomplished by issuing three SPI writes which are in turn ignored by the ADAU1772 The next fourth SPI write is then latched into the SPI port The SPI port uses a 4 wire interface consisting of SS SCLK MOSI and MISO signals and is always a slave port The 55 signal should go low at the beginning of a transaction and high at the end of a transaction The SCLK signal latches MOSI on a low to high transition MISO data is shifted out of the ADAU1772 on the falling edge of SCLK and should be clocked into a receiving device such as a microcontroller on the SCLK rising edge The MOSI signal carries the serial input data and the MISO signal is the serial output data The MISO signal remains tristated until a read operation is requested This allows other SPI compatible peripher
126. o Address 0x0016 The serial data clocks do not need to be synchronous with the 01772 master clock input but the LRCLK and BCLK must be synchronous to each other The LRCLK and BCLK pins are used to clock both the serial input and output ports The ADAUI772 can be set to be either the master or the slave in system Because there is only one set of serial data clocks the input and output ports must always both be either master or slave The serial data control registers allow control of the clock polarity and the data input modes The valid data formats are IS left justified right justified 24 or 16 bit PCM and TDM In all modes except for the right justified modes the serial port inputs an arbitrary number of bits up to a limit of 24 Extra bits do not cause an error but they are truncated internally The serial port can operate with an arbitrary number of BCLK transitions in each LRCLK frame The LRCLK in TDM mode can be input to the ADAU1772 either as a 50 duty cycle clock or as a bit wide pulse Table 27 lists the modes in which the serial input output port can function When using low IOVDD 1 8 V with a high Table 28 Serial Port Data Format Settings rate 12 288 MHz a sample rate of 192 kHz TDM8 mode operating at a sample rate of 48 kHz it is recommended to use the high drive settings on the serial port pins The high drive strength effectively speeds up the transition times of the waveforms th
127. olume down Rev 0 Page 96 of 116 1772 MP4 FUNCTION SETTING REGISTER Address 0x003C Reset 0x00 Name MODE_MP4 7 5 RESERVED RW B7 B6 B5 B4 B3 o KEE J Table 88 Bit Descriptions for MODE_MP4 B2 BO 4 0 MODE_MP4_VAL RW Sets the function of Pin DMICO_1 MP4 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Digital Microphone Input Channel O Digital Microphone Input Channel 1 Mute ADCO Mute ADC1 Mute ADC2 Mute ADC3 Mute ADCO and ADC1 Mute ADC2 and ADC3 Mute all ADCs Mute DACO Mute DAC1 Mute both DACs bank switch Reserved Reserved Enable compression DSP bypass enable Push button volume up Push button volume down Bits Bit Name Settings Description Reset Access 4 0 MODE VAL Sets the function of Pin DMICO 1 0x00 RW 00000 Digital Microphone Input Channel 0 Digital Microphone Input Channel 1 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button
128. one input Set the gain of PGA2 0 AIN2 used as a single ended line 000000 12 dB input PGA powered down 000001 1 1 25 dB 1 AIN2 used as a single ended 010000 0 dB microphone input PGA powered up 111110 34 5 88 with sewing 111144 435 25 dB 6 PGA MUTE2 RW Enable PGA2 mute 0 Unmuted 1 Muted Table 66 Bit Descriptions for CONTROL 2 Bits Bit Name Settings Description Reset Access 7 PGA EN2 Select line or microphone input Note that the PGA inverts the signal 0 0 RW going through it 0 AIN2 used as a single ended line input PGA powered down 1 AIN2 used as single ended microphone input PGA powered up with slewing 6 PGA_MUTE2 Enable PGA2 mute When PGA is muted PGA_GAIN2 is ignored 0 1 RW 0 Unmuted 1 Muted 5 0 PGA_GAIN2 Set the gain of PGA2 0 0 RW 000000 12 dB 000001 11 25 dB 010000 OdB 111110 34 5 dB 111111 35 25 dB Rev 0 Page 80 of 116 01772 PGA CONTROL 3 REGISTER Address 0x0026 Reset 0x40 Name PGA_CONTROL_3 This register controls the PGA connected to AIN3 Table 67 Bits 7 PGA_EN3 RW B7 B8 B5 B4 B3 B2 B1 5 0 PGA GAIN3 RW Select line or microphone ME Set the gain of PGA3 0 AING used as a single ended line 000000 12 dB input PGA powered down 000001 11 25 dB 1 used as a single ended 010000 0 dB microphone input PGA powered up 111110 34 5 dB with slewing 6 MUTE3 RW Enable
129. or CLKOUT_SEL Bits Bit Name Settings Description Reset Access 2 0 CLKOUT_FREQ CLKOUT pin frequency 0x0 RW 000 Master clock x 2 24 576 MHz 001 Master clock 12 288 MHz 010 Master clock 2 6 144 MHz 011 Master clock 4 3 072 MHz 100 Master clock 8 1 536 MHz 111 Clock output off 0 REGULATOR CONTROL REGISTER Address 0x0008 Reset 0x00 Name REGULATOR B7 B6 B5 B4 B3 B2 B 7 3 RESERVED RW 1 0 RW Set regulator output voltage 00 1 2V 01 1 1 V 10 Reserved 11 Reserved 2 REG PD RW Powers down LDO regulator 0 Regulator active 1 Regulator powered down Table 38 Bit Descriptions for REGULATOR Bits Bit Name Settings Description Reset Access 2 REG PD Powers down LDO regulator 0 0 RW 0 Regulator active 1 Regulator powered down 1 0 REGV Set regulator output voltage 0 0 RW 00 12V 01 1 1V 10 Reserved 11 Reserved Rev 0 56 of 116 1772 CORE CONTROL REGISTER Address 0x0009 Reset 0x04 Name CORE_CONTROL 7 ZERO_STATE RW Zeros the state of the data memory during bank switching 0 Do not zero state during bank switch 1 Zero state during back switch 6 5 BANK_SL RW Selects active filter bank 00 Bank A active 01 Bank B active 10 Reserved 11 Reserved 4 3 RESERVED RW x pes 0 CORE RUN RW Run bit for the core 0 Core off 1 Core on 2 1
130. ourced from a stereo input ASRC ANALOG INPUTS The ADAUI772 can accept both line level and microphone inputs Each of the four analog input channels can be configured in a single ended mode or a single ended with PGA mode There are also inputs for up to four digital microphones The analog inputs are biased at AVDD 2 Unused input pins should be connected to the CM pin or ac coupled to ground Signal Polarity Signals routed through the PGAs are inverted As a result signals input through the PGA are output from the ADCs with a polarity that is opposite that of the input Single ended inputs are not inverted The ADCs are noninverting Input Impedance The input impedance of the analog inputs varies with the gain of the PGA This impedance ranges from 0 68 at the 35 25 dB gain setting to 32 0 at the 12 dB setting The input impedance on each pin can be calculated as follows 40 19 Gain 20 1 Riy where Gain is set PGA_GAINx The optional 10 dB PGA boost set in PGA_x_BOOST does not affect the input impedance This is an alternative way of increasing gain without decreasing input impedance however it causes some degradation in performance Analog Microphone Inputs For microphone signals the ADAU1772 analog inputs can be configured in single ended with PGA mode The PGA settings are controlled in Register 0x0023 to Register 0x0026 The PGA is enabled by setting the PGA_ENx bits Connect the
131. ow pulse mode is short negative pulse Table 80 Bit Descriptions for 1 Bits Bit Name Settings Description Reset Access 7 TDM_TS Select whether to tristate unused TDM channels or to actively drive these 0 0 RW data slots 0 Unused outputs driven 1 Unused outputs tristated 6 BCLK_TDMC Bit width in TDM mode 0 0 RW 0 24 bit data in each TDM channel 1 16 bit data in each TDM channel 5 LR MODE Sets LRCLK mode 0 0 RW 0 50 duty cycle clock 1 Pulse LRCLK is a single BCLK cycle wide pulse 4 LR_POL Sets LRCLK polarity 0 0 RW 0 50 when LRCLK goes low and then high pulse mode is short positive pulse 1 50 when LRCLK goes high and then low pulse mode is short negative pulse 3 SAI_MSB Sets data to be input output either MSB or LSB first 0 0 RW 0 MSB first data 1 LSB first data 2 BCLKRATE Sets the number of bit clock cycles per data channel 0 0 RW 0 32 BCLK cycles channel 1 16 BCLK cycles channel 1 BCLKEDGE Sets the bit clock edge on which data changes 0 0 RW 0 Data changes on falling edge 1 Data changes on rising edge 0 SAI MS Sets the serial port into master or slave mode 0 0 RW 0 LRCLK BCLK slave 1 LRCLK BCLK master Rev 0 Page 90 of 116 1772 OUTPUT CHANNEL DISABLE REGISTER Address 0x0034 Reset 0x00 Name SOUT_CONTROLO This register is for use only in TDM mode B7 B6 B5 B4 B3 B2 7 TDM7 D
132. phones are to be used in a system then up to two microphones would be con nected to both DMICO 1 and DMIC2 3 and the CLKOUT signal would be fanned out to the clock input of all of the microphones ANALOG TO DIGITAL CONVERTERS The ADAU1772 includes four 24 bit X A analog to digital con verters ADCs with a selectable sample rate of 192 kHz 96 kHz ADC Full Scale Level The full scale input to the ADCs 0 dBFS scales linearly with AVDD At AVDD 3 3 V the full scale input level is 1 V rms Signal levels above the full scale value cause the ADCs to clip Digital ADC Volume Control The volume setting of each ADC can be digitally attenuated in the ADCx_VOLUME registers Address 0x001F to Address 0x0022 The volume can be set between 0 dB and 95 625 dB in 0 375 dB steps The ADC volume can also be digitally muted in the ADC_CONTROL registers Address 0x001B to Address 0 001 High Pass Filter A high pass filter is available on the ADC path to remove offsets this filter can be enabled or disabled using the HP_x_x_EN bits At fs 192 kHz the corner frequency of this high pass filter can be set to 1 Hz 4 Hz or 8 Hz Rev 0 Page 33 of 116 01772 OUTPUT SIGNAL PATHS Data from the serial input port can be routed to the core either directly or through a sample rate converter Data can be routed to the serial output port the stereo DAC and the stereo modulator The analog outputs of the ADAU17
133. ppression on PGA3 inpu 0 Enabled 1 Disabled Table 70 Bit Descriptions for POP_SUPPRESS Bits Bit Name Settings Description Reset Access 5 HP_POP_DIS1 Disable pop suppression on Headphone Output 1 0 1 RW 0 Enabled 1 Disabled 4 HP_POP_DISO Disable pop suppression on Headphone Output 0 0 1 RW 0 Enabled 1 Disabled 3 PGA POP DIS3 Disable pop suppression on PGA3 input 0 1 RW 0 Enabled 1 Disabled 2 PGA_POP_DIS2 Disable pop suppression on PGA2 input 0 1 RW 0 Enabled 1 Disabled 1 PGA POP DIS1 Disable pop suppression on 1 input Ox1 RW 0 Enabled 1 Disabled 0 PGA_POP_DISO Disable pop suppression on PGAO input 0 1 RW 0 Enabled 1 Disabled Rev 0 Page 84 of 116 1772 DSP BYPASS PATH REGISTER Address 0x002A Reset 0x00 Name TALKTHRU B7 5 B4 B3 B2 BO 7 2 RESERVED RW 1 0 TALKTHRU PATH RW Signal path when DSP bypass is enabled 00 No DSP bypass 01 ADCO to DACO 10 ADC1 to DAC1 11 ADCO and ADC1 to DACO and DACH Table 71 Bit Descriptions for TALKTHRU Bits Bit Name Settings Description Reset Access 1 0 TALKTHRU PATH Signal path when DSP bypass is enabled 0x0 RW 00 No DSP bypass 01 ADCO to DACO 10 ADCI to 11 ADCO and ADC1 DACO DSP BYPASS GAIN FOR PGAO REGISTER Address 0x002B Reset 0x00 Name TALKTHRU GAINO
134. pull down resistor on this pin therefore the ADAU1772 is held in power down mode if its input signal is floating while power is applied to the supply pins 28 REG_OUT A_OUT Regulator Output Voltage This pin should be connected to DVDD if the internal voltage regulator is being used to generate DVDD voltage 29 DVDD PWR Digital Core Supply The digital supply can be generated from an on board regulator or supplied directly from an external supply In each case DVDD should be decoupled to DGND with a 0 1 capacitor 30 DGND PWR Digital Ground The AGND DGND pins can be tied directly together in a common ground plane 31 LRCLK MP3 D IO Serial Data Port Frame Clock LRCLK General Purpose Input MP3 32 BCLK MP2 D IO Serial Data Port Bit Clock BCLK General Purpose Input MP2 33 DAC SDATA MPO D IO DAC Serial Input Data DAC SDATA General Purpose Input MPO 34 ADC SDATAO PDMOUT MP1 D IO ADC Serial Data Output 0 SDATAO Stereo PDM Output to Drive a High Efficiency Class D Amplifier PDMOUT General Purpose Input MP1 35 SDATAT CLKOUT MP6 D IO Serial Data Output 1 SDATAT Master Clock Output Clock for the Digital Microphone Input and PDM Output CLKOUT General Purpose Input MP6 36 DMIC2 3 MP5 D IN Digital Microphone Stereo Input 2 and Digital Microphone Stereo Input 3 DMIC2 3 General Purpose Input MP5 37 DMICO_1 MP4 D_IN Digital Microphone Stereo Input 0 and Digital Microphone Stereo
135. re R 3 1269 1625 Rev 0 29 of 116 ADAUI772 Table 13 lists common fractional PLL parameter settings for 48 kHz sampling rates When the PLL is used in fractional mode it is very important that the N M fraction be kept in the range of 0 1 to 0 9 to ensure correct operation of the PLL The PLL can output a clock in the range of 20 5 MHz to 27 MHz which should be taken into account when calculating PLL values and MCLK frequencies CLOCK OUTPUT The CLKOUT pin can be used as a master clock output to clock other ICs in the system or as the clock for the digital microphone inputs and PDM output This clock can be generated from the 12 288 MHz master clock of the ADAU1772 by factors of 2 1 and If PDM mode is enabled only 4 and settings produce a clock signal on CLKOUT The factor of 2 multiplier works properly only if the input clock was previously divided by 2 using the CC_MDIV bit POWER SEQUENCING AVDD and IOVDD can each be set to any voltage between 1 8 V and 3 3 V and DVDD can be set between 1 1 V and 1 8 V or between 1 1 V and 1 2 V if using the on board regulator On power up AVDD must be powered up before or at the same time as IOVDD IOVDD should not be powered up when power is not applied to AVDD Enabling the PD pin powers down all analog and digital circuits Before enabling PD that is setting it low be sure to mute the outputs to avoid any pops when the IC is powered
136. s SDA MISO SCL SCLK ADDR1 MOSI ADDRO SS SELFBOOT MICBIASO MICBIAS1 AINOREF AINO NOTES 35 ADC_SDATA1 CLKOUT MP 34 ADC SDATAO PDMOUT MP 33 DAC SDATA MPO 32 BCLK MP2 30 DGND 29 DVDD 28 REG OUT 27 PD 26 HPOUTRP LOUTRP 25 HPOUTRN LOUTRN 24 AVDD 23 AGND 22 HPOUTLP LOUTLP 21 HPOUTLN LOUTLN ADAU1772 TOP VIEW Not to Scale CM 12 AINTREF 13 AIN3 18 AVDD 19 AGND 20 _ 1 THE EXPOSED PAD IS CONNECTED INTERNALLY TO THE ADAU1772 GROUNDS FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE SEE THE EXPOSED PAD PCB DESIGN SECTION FOR MORE INFORMATION 10804 059 Figure 9 Configuration Pin No Mnemonic Type Description 1 SDA MISO D IO Data SDA This pin is bidirectional open collector The line connected to this pin should have a 2 0 pull up resistor SPI Data Output MISO This SPI data output is used for reading back registers and memory locations It is tristated when an SPI read is not active 2 SCL SCLK D IN Clock SCL This pin is always an open collector input when the device is in C control mode When the device is in self boot mode this pin is an open collector output master The line connected to this pin should have a 2 0 kO pull up resistor SPI Clock SCLK This pin can either run continuously or be gated off between SPI transactions 3 ADDR1 MOSI
137. s Wait Time The self boot operation starts after 16 568 clock cycles are seen on the XTALI MCLKIN pin after PD is set high With a 12 288 MHz clock this corresponds to approximately a 1 35 ms wait time from power up This delay ensures that the crystal used for generating the master clock has ramped up to a stable oscillation Table 25 EEPROM Self Boot Instructions both banks There is inherently some overhead for instructions Instruction Byte to control the self boot procedure Instruction BytelD Description Following Bytes 0x00 End self boot CRC Table 24 Maximum EEPROM Size 0x01 Write multibyte length Length high byte Word Size minus two bytes starting length low byte ADAU1772 Bytes per Total EEPROM Space at target address address high byte Memory Blocks Word Words Requirement Bytes address low byte Program 2 32 64 data 0 data 1 p data length 3 Bank 0 Parameters 4 160 32x5 640 Saw RES S Ge Bank 1 Parameters 4 160 640 0x02 elays by the 16 bit setting elay high byte x 2048 clock cycles delay low byte UA e Ke s 0x03 No operation None ii dac 0x04 Wait for PLL lock None 0x05 Write single byte to target Address high byte address address low byte data 7 9s DELAY DELAY DELAY WRITE LENGTH LENGTH ADDRESS ADDRESS LOW BYTE LOW BYTE T HI
138. s Bit Name Settings Description Reset Access 7 0 ADC_1_VOL ADC1 volume setting 0x00 RW 00000000 0dB 00000001 0 375 dB 11111111 95 625 dB Rev 0 Page 77 of 116 ADAUI772 ADC2 VOLUME CONTROL REGISTER Address 0x0021 Reset 0x00 Name ADC2 VOLUME When SINC_2_EN is set the volume starts to ramp from 95 625 dB to the value in this register The volume ramp time is number of steps x 16 fs where there are 256 steps between 0 dB and 95 625 dB For example with fs 192 kHz the volume ramps from 95 625 dB to 0 dB in 21 ms B7 B5 B4 B3 B2 BO 7 0 2 RW ADC2 volume 00000000 0 dB 00000001 0 375 dB 11111111 95 625 dB Table 62 Bit Descriptions for ADC2_VOLUME Bits Bit Name Settings Description Reset Access 7 0 2 VOL ADC2 volume setting 0x00 RW 00000000 0dB 00000001 0 375 dB 11111111 95 625 dB ADC3 VOLUME CONTROL REGISTER Address 0x0022 Reset 0x00 Name ADC3_ VOLUME When SINC_3_EN is set the volume starts to ramp from 95 625 dB to the value in this register The volume ramp time is number of steps x 16 fs where there are 256 steps between 0 dB and 95 625 dB For example with fs 192 kHz the volume ramps from 95 625 dB to 0 dB in 21 ms B7 5 B4 B3 B2 BO 7 0 3 RW
139. s to configure devices such as the SSM2517 Each pattern is a byte long and is written with a user defined pattern in the PDM PATTERN register Address 0x0037 The control pattern is enabled and the output channel selection is configured the PDM_OUT register Address 0x0036 The PDM pattern should not be changed while the ADAU1772 is outputting the control pattern to the external device After the external device is configured the control pattern can be disabled For the SSM2517 the control pattern must be repeated a minimum of 128 times to configure the part Table 14 describes typical control patterns for the SSM2517 Table 14 55 2517 Control Pattern Descriptions Pattern Control Description Power down All blocks off except for the interface Normal start up time Gain optimized for PVDD 5 V operation Overrides GAIN_FS pin setting OxD4 Gain optimized for PVDD 3 6 V operation Overrides GAIN_FS pin setting 2 Gain optimized for PVDD 2 5 V operation Overrides GAIN_FS pin setting 1 set to opposite value determined by GAIN FS pin OxE1 Ultralow EMI mode OxE2 Half clock cycle pulse mode for power savings 0 4 Special 32 2 128 x fs operation mode ASYNCHRONOUS SAMPLE RATE CONVERTERS The ADAU1772 includes asynchronous sample rate converters ASRCs to enable synchronous full duplex operation of the serial ports Two stereo ASRCs are available for t
140. setting HP_MUTE_L in the OP_STAGE_MUTES register to 00 HPOUTLN LOUTLN and HPOUTLP LOUTLP outputs enabled HPOUTLN LOUTLN enabled HPOUTLP LOUTLP disabled HPOUTLN LOUTLN disabled HPOUTLP LOUTLP enabled Left output stages powered down 0 3 0 3 RW RW Rev 0 Page 103 of 116 ADAUI772 DECIMATOR POWER CONTROL REGISTER Address 0x0044 Reset 0x00 DECIM PWR MODES These bits enable clocks to the digital filters and ASRC decimator filters of the ADCs These bits must be enabled for all channels that will be used in the design To use ADCs these SINC x EN bits must be enabled along with the appropriate ADC x EN bits in the ADC CONTROL2 and ADC CONTROLS registers If the digital microphone inputs are used the SINC x EN bits can be set without setting ADC x EN B8 B3 B2 7 DEC 3 EN RW DD 0 SINC 0 EN RW Control power to the MESE ADCO filter power control decimator 0 Powered down 0 Powered down 1 Powered up 1 SINC_1_EN RW 6 DEC 2 EN RW ADC1 filter power control Control power to the ASRC2 0 Powered down decimator 1 Powered up 0 Powered down 2 SINC 2 EN RW 1 ADC2 filter power control 5 DEC_1_EN RW 0 Powered down Control power to the ASRC1 1 Powered up decimator 0 Powered down 3 SINC_3_EN RW 1 Powered up filter power control 0 Powered down 4 DEC 0 EN RW 1 Powered up Control power to the ASRCO decimator
141. t swap by writing to the DMIC_SW0 DMIC_SW1 bits in the ADC_CONTROL2 ADC CONTROLS registers Address 0x001D and Address 0x001E In addition the micro phone polarity can be reversed by setting the DMIC_POLx bit which reverses the phase of the incoming audio by 180 The digital microphone inputs are clocked from the CLKOUT pin The digital microphone data stream must be clocked by this pin and not by a clock from another source such as another audio IC even if the other clock is of the same frequency as CLKOUT The digital microphone signal bypasses the analog input path and the ADCs and is routed directly into the decimation filters The digital microphone and the ADCs share digital filters and therefore both cannot be used simultaneously The digital micro phone inputs are enabled in pairs The ADAU1772 inputs can be set for either four analog inputs four digital microphone inputs or two analog inputs and two digital microphone inputs Figure 72 depicts the digital microphone interface and signal routing 1 8V TO 3 3V ADMP421 ADAU1772 L R SELECT GND ADMP421 L R SELECT GND 10804 065 Figure 72 Digital Microphone Interface Block Diagram Figure 72 shows two ADMP421 digital microphones connected to Pin DMICO 1 of the ADAU1772 These microphones could also be connected to DMIC2 3 if that signal path is to be used for digital microphones If more than two digital micro
142. tage can be supplied externally The input signal path includes flexible configurations that can accept single ended analog microphone inputs as well as up to four digital microphone inputs Two microphone bias pins provide seamless interfacing to electret microphones Each input signal has its own programmable gain amplifier PGA for volume adjustment The ADCs DACs are high quality 24 bit Z A converters that operate at a selectable 192 kHz or 96 kHz sampling rate The ADCs have an optional high pass filter with a cutoff frequency of 1 Hz 4 Hz or 8 Hz The ADCs and DACs also include very fine step digital volume controls The stereo DAC output is capable of differentially driving a headphone earpiece speaker with 16 impedance or higher One side of the differential output can be powered down if single ended operation is required There is also the option to change to line output mode when the output is lightly loaded The core has a reduced instruction set that optimizes this codec for noise cancellation The program and parameter RAMs can beloaded with custom audio processing signal flow built using the SigmaStudio graphical programming software from Analog Devices Inc The values stored in the parameter RAM control individual signal processing blocks ADAU1772 also has a self boot function that can be used to load the program and parameter RAM along with the register settings on power up using an external EEPROM
143. tering and moving the result to the DBREGO register B7 B8 B5 B4 B3 B2 7 0 DBVALO RW DB Value Register 0 read 00000000 96 dB 00010000 90 dB 00100000 84 dB 00110000 78 dB 11100000 12 dB 11110000 6 dB 11111111 0 375 dB Table 41 Bit Descriptions for DBREGO ak Bits Bit Name Settings Description Reset Access 7 0 DBVALO DB Value Register 0 read 00000000 96 dB 00010000 90 dB 00100000 84 00110000 78 11100000 12 11110000 6 dB 11111111 0 375 0 00 R DB VALUE REGISTER 1 READ Address 0x000D Reset 0x00 Name DBREG1 The core can write data to this register and the data is automatically converted to a level in dB The most common usage is to determine the rms value of a signal by taking the absolute value and then performing low pass filtering and moving the result to the DBREG1 register B7 B6 B5 B4 B3 B2 7 0 DBVAL1 RW DB Value Register 1 read 00000000 96 dB 00010000 90 dB 00100000 84 dB 00110000 78 dB 11100000 12 dB 11110000 6 dB 11111111 0 375 dB 0 Page 59 of 116 ADAUI772 Table 42 Bit Descriptions for 1 Bits Bit Name Settings Description Reset Access 7 0 DBVAL1 DB Value Register 1 read 0x00 R 00000000 96 dB 00010000 90 dB 001000
144. tings Description Reset Access 7 4 SOUT SOURCES Serial Data Output Channel 5 source select 0x5 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 Rev 0 Page 67 of 116 ADAU1772 Bits Bit Name Settings Description Reset Access 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 3 0 SOUT_SOURCE4 Serial Data Output Channel 4 source select 0x4 RW 0000 Reserved 0001 Reserved 0010 Reserved 0011 Reserved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 SERIAL DATA OUTPUT 6 SERIAL DATA OUTPUT 7 INPUT SELECT REGISTER Address 0x0016 Reset 0x76 Name SOUT_SOURCE_6_7 BS B2 Bi 7 4 SOUT_SOURCE7 RW 3 0 SOUT_SOURCE6 RW Serial Data Output Channel 7 source Serial Data Output Channel 6 source select select 0000 Reserved 0000 Reserved 0001 Reserved 0001 Reserved 0010 Reserved 0010 Reserved 0011 Reserved 0011 Reserved 0100 Output
145. to IOVDD 0 3 V Operating Temperature Range Case 40 C to 85 C Storage Temperature Range 65 to 150 THERMAL RESISTANCE represents the junction to ambient thermal resistance represents the junction to case thermal resistance Thermal numbers are simulated on a 4 layer JEDEC PCB with the exposed pad soldered to the PCB was simulated at the exposed pad on the bottom of the package Table 9 Thermal Resistance Package Type Bic Unit Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 40 Lead LFCSP 29 1 8 C W ESD CAUTION A ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev 0 Page 14 of 116 1772 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 10 Pin Function Description
146. truction bytes are used to load the register program and parameter settings EEPROM Size The self boot circuit is compatible with an EEPROM that has a 2 byte address For most EEPROM families a 2 byte address is used on devices that are 32 kB or larger The EEPROM must be set to Address 0x50 Examples of two compatible EEPROMs include Atmel AT24C32D and STMicroelectronics M24C32 F Table 24 lists the maximum necessary EEPROM size assuming that there is 10096 utilization of the program and parameters CRC An 8 bit CRC validates the content of the EEPROM This CRC is strong enough to detect single error bursts of up to eight bits in size The terminate self boot instruction 0x00 instruction byte must be followed by a CRC byte The CRC is generated using all of the EEPROM bytes from Address 0x0000 to the last 0x00 instruction byte The polynomial for the CRC is xx 1 If the CRC is incorrect or if an unrecognized instruction byte is read during self boot the boot process is immediately stopped and restarted after a 250 ms delay for a 12 288 MHz input clock When SigmaStudio is used the CRC byte is generated auto matically when a configuration is downloaded to the EEPROM Delay The delay instruction 0x02 instruction byte delays by the 16 bit setting x 2048 clock cycles Boot Time The time to self boot the ADAU1772 from an EEPROM be calculated using the following equation Boot Time 64 MCLK Frequency x Total Byte
147. ty is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners IMITERS VOLUME CONTROLS MIXING I2C SPI CONTROL INTERFACE AND SELF BOOT O O O x lt zzz 9 666 lt lt lt lt 9592 5 e 5 8 One Technology Way 9106 Norwood 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2012 Analog Devices Inc All rights reserved ADAU1772 TABLE OF CONTENTS Features 1 Applications ir ee ot Hae 1 General Description tertiis eie dee e etd e atado aud 1 Functional Block Diagram eene 1 R vision History 3 Specifications 4 Analog Performance 4 Crystal Amplifier Specifications sss 7 Digital Input Output Specifications EE 8 Power Supply Specifications sse 8 Typical Power Consumption 9 Digital upa 9 Digital Timing Specifications 10 Absolute Maximum Ratings 14 Thermal Resistance
148. ved 0100 Output ASRC Channel 0 0101 Output ASRC Channel 1 0110 Output ASRC Channel 2 0111 Output ASRC Channel 3 1000 Serial Input 0 1001 Serial Input 1 1010 Serial Input 2 1011 Serial Input 3 1100 Serial Input 4 1101 Serial Input 5 1110 Serial Input 6 1111 Serial Input 7 SERIAL DATA OUTPUT 4 SERIAL DATA OUTPUT 5 INPUT SELECT REGISTER Address 0x0015 Reset 0x54 Name SOUT SOURCE 4 5 B7 B6 B5 B4 B3 B2 B1 BO 7 4 SOUT_SOURCES RW 3 0 SOUT_SOURCE4 RW Serial Data Output Channel 5 source select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output ASRC Channel 0 Output ASRC Channel 1 Output ASRC Channel 2 Output ASRC Channel 3 Serial Input 0 Serial Input 1 Serial Input 2 Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Table 50 Bit Descriptions for SOUT_SOURCE_4_5 Serial Data Output Channel 4 source select 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reserved Reserved Reserved Reserved Output ASRC Channel 0 Output ASRC Channel 1 Output ASRC Channel 2 Output ASRC Channel 3 Serial Input 0 Serial Input 1 Serial Input 2 Serial Input 3 Serial Input 4 Serial Input 5 Serial Input 6 Serial Input 7 Bits Bit Name Set
149. volume down Rev 0 Page 97 of 116 ADAUI772 MP5 FUNCTION SETTING REGISTER Address 0x003D Reset 0x00 Name MODE_MP5 B7 B8 B5 B4 B3 B2 B1 BO a eae 7 5 RESERVED RW 4 0 MODE_MP5_VAL RW Sets the function of Pin DMIC2_3 MP5 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 Table 89 Descriptions for MODE_MP5 Digital Microphone Input Channel 2 Digital Microphone Input Channel 3 Mute ADCO Mute ADC1 Mute ADC2 Mute ADC3 Mute ADCO and ADC1 Mute ADC2 and ADC3 Mute all ADCs Mute DACO Mute DAC1 Mute both DACs AJB bank switch Reserved Reserved Enable compression DSP bypass enable Push button volume up Push button volume down Bits Bit Name Settings Description Reset Access 4 0 MODE_MP5_VAL Sets the function of Pin DMIC2_3 MP5 0x00 RW 00000 Digital Microphone Input Channel 2 Digital Microphone Input Channel 3 00001 Mute ADCO 00010 Mute ADC1 00011 Mute ADC2 00100 Mute ADC3 00101 Mute ADCO and ADC1 00110 Mute ADC2 and ADC3 00111 Mute all ADCs 01000 Mute DACO 01001 Mute 01010 Mute both DACs 01011 A B bank switch 01100 Reserved 01101 Reserved 01110 Enable compression 01111 DSP bypass enable 10000 Push button volume up 10001 Push button volume down Rev 0
150. wer control 00 HPOUTRN and HPOUTRP LOUTR outputs enabled 01 HPOUTRN enabled HPOUTRP LOUTR disabled 10 HPOUTRN disabled HPOUTRP LOUTR enabled 11 Right output stages powered down Rev 0 Page 102 of 116 1772 Table 94 Bit Descriptions for 5 Bits Bit Name Settings Description Reset Access 5 HP_EN_R Sets the right channel in line output or headphone mode Right output in line output mode Right output in headphone mode 0x0 RW HP_EN_L Sets the left channel in line output or headphone mode Left output in line output mode Left output in headphone output mode 0x0 RW 3 2 1 0 HP_PDN_R HP_PDN_L 00 01 10 11 00 01 10 11 Output stage power control Powers down the right output stage regardless of whether the device is in line output or headphone mode After enabling the headphone output wait at least 6 ms before unmuting the headphone output by setting HP_MUTE_R in the OP_STAGE_MUTES register to 00 HPOUTRN LOUTRN and HPOUTRP LOUTRP outputs enabled HPOUTRN LOUTRN enabled HPOUTRP LOUTRP disabled HPOUTRN LOUTRN disabled HPOUTRP LOUTRP enabled Right output stages powered down Output stage power control Powers down the left output stage regardless of whether the device is in line output or headphone mode After enabling the headphone output wait at least 6 ms before unmuting the headphone output by
151. y fs 96 kHz Signal Path AINO to DSP Without Processing to LOUTLx 96 kHz Signal Path AINO to DSP Without Processing to LOUTLx Rev 0 17 of 116 01772 50 0 50 100 150 200 8 250 amp 300 o o lt 350 a n 400 450 500 550 600 e 0 4 8 12 16 20 24 28 32 36 40 FREQUENCY kHz 8 Figure 16 Phase vs Frequency 40 kHz Bandwidth fs 96 kHz Signal Path AINO to DSP Without Processing to LOUTLx 1 0 1 2 5 o 22 3 gt gt lt 4 E 5 4 2 e 7 8 9 e 100 1k 10k 5 FREQUENCY S Figure 17 Relative Level vs Frequency fs 192 kHz Signal Path AINO to DSP Without Processing to LOUTLx 200 100 0 100 200 300 8 400 8 5 500 600 u lt 700 N 4 800 900 1000 1100 1200 1300 0 10 20 30 40 50 60 70 80 i FREQUENCY kHz 8 Figure 18 Phase vs Frequency 80 kHz Bandwidth 192 kHz Signal Path AINO to DSP Without Processing to LOUTLx Rev 0 18 of 116 0 0 2 04 0 6 0 8 10 1 2 14 16 1 8 2 0 FREQUENCY kHz 10804 018

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