ANALOG DEVICES ADD5203: 8-String White LED Driver with SMBus PWM Input for LCD Backlight Applications Data Sheet (Rev 0 2010-05-28-)
Contents
1. SLAVE TO MASTER MASTER SLAVE Figure 22 Write Byte Protocol Figure 23 Slave Address Definition Rev 0 Page 14 of 24 08717 023 DATA BYTE 08717 022 device is in read mode the LSB is set to 1 and the slave address byte 08717 020 08717 021 SMBUS REGISTER DESCRIPTION The ADD5203 has four registers to control and monitor brightness fault status identifications and operating mode Those registers are one byte wide and accessible via the SMBus read write byte protocols Brightness Control Register Address 0x00 This register consists of eight bits BRT7 to BRTO which are used to control the LED brightness level in 256 steps An SMBus write byte cycle to this register sets the brightness level if the device is in SMBus mode In addition a write byte cycle to this register sets the brightness level if the device is in SMBus mode Furthermore a write byte cycle to this register has no effect when the device is in a mode other than SMBus mode The operating mode is selected by the device control register Address 0x01 An SMBus read byte cycle to this register returns the current brightness level regardless of the value of PWM SEL An SMBus setting of OxFF for this register sets the device to the maximum brightness output and a setting of 0x00 sets the device to the minimum brightness output This register is both readable and writable for all bits The d2. sse 11 Step Up Switching Regulator 4 PWM Dimming 12 LED Current Regulation Specifications 4 Safety Features socer n e 12 SMBus 2 44 4 0 tentent 5 SM Bus Interface ciae tita vu Eg RHEINE 13 General Specifications eerte 6 SMBus Register Description sese 15 Absolute Maximum Ratings essent 7 External Component Selection Guide 17 Thermal Resistante 7 Layout Guidelines o Ete tiere ind 18 ESD Caution ep eee teen 7 Typical Application Circuits 220 Pin Configuration and Function 8 Outline Dimensions eene 23 Typical Performance Characteristics eee 9 Orderine Guides oe etre toten 23 REVISION HISTORY 5 10 Revision 0 Initial Version Rev 0 Page 2 of 24 CIRCUIT DIAGRAM VIN VDDIO 9 TSD FAULT THERME ADD5203 LIGHT LOAD L SHUTDOWN OCP FAULT Pi M HEADROOM CONTROL LED OPEN SHORT CURRENT FAULT DETECTOR REFERENCE _ 1 T CURRENT SOURCE 1 4 FB2 13 CURRENT SOURCE 2 ren co CURRENT SOURCE 3 co CURRENT SOURCE 4 b H b I
3. EN EN 5G 4 VDDIO ADD5203 EN EN EN EN tur 7 2 SEL1 FB2 5 3 5 12 2 9c FB5 12 ras 5 20pF m Bad 2 4 8 27 FSLCT PGND e sag d 28 D 25 R3 R4 150kO 56 100nF 08717 027 Figure 27 Typical Application Circuit for PWM Interface with DC Current Dimming Mode Rev 0 Page 22 of 24 OUTLINE DIMENSIONS PIN 1 INDICATOR 0 70 ADD5203 0 25 020 515 0 15 PIN 1 INDICATOR 2 70 26050 250 VIEW FOR PROPER CONNECTION THE EXPOSED PAD REFER TO i 0 05 MAX THE PIN CONFIGURATION AND 0 02 FUNCTION DESCRIPTIONS SEATING BE d PLANE Figu 1 COPLANARITY SECTION OF THIS DATA SHEET 0 08 0 20 REF 112108 A COMPLIANT TO JEDEC STANDARDS MO 220 WGGE 28 28 Lead Lead Frame Chip Scale Package LFCSP_WQ 4mm x 4mm 0 75 mm Body Very Very Thin Dual CP 28 5 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADD5203ACPZ RL 259 to 85 C 28 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 28 5 1 Z RoHS Compliant Part Rev 0 Page 23 of 24 ADD5203 NOTES 02010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D08717 0 5 10 0 DEVICES www analo g com Rev 0 Page 24 of 24
4. GND In this condition open load protection OLP is activated if is less than 200 mV until the boost converter output voltage rises up to the OVP level Short Circuit Protection SCP The ADD5203 contains the short circuit protection SCP If a few LEDs at any strings are shorted during normal operation the current source headroom voltage Vur is increasing In this condition SCP is activated if is higher than 7 2 V therefore the string that includes short LEDs is disabled Undervoltage Lockout UVLO An undervoltage lockout circuit is included with built in hysteresis The ADD5208 turns on when VIN rises above 5 V typical and shuts down when VIN falls below 4 6 V typical ADD5203 Thermal Overload Protection Thermal overload protection prevents excessive power dissipation from overheating the ADD5203 When the junction temperature exceeds 160 C a thermal sensor immediately activates the fault protection which shuts down the device allowing the IC to cool The device self starts when the junction temperature of the die falls below 130 C SMBUS INTERFACE SMBus mode can be selected using the SEL1 and SEL2 mode selection pins When in SMBus mode the ADD5203 can be controlled with an SMBus serial interface Read Byte As shown in Figure 21 the read byte protocol is four bytes long and starts with the slave address followed by the command code which translates to the register index The
5. MHz by using an external resistor Re A frequency of 350 kHz is recommended to optimize the regulator for high efficiency and a frequency of 1 MHz is recommended for small external components See Figure 14 for considerations when selecting a switching frequency and an adjustment resistor Re 1100 1000 800 700 600 500 SWITCHING FREQUENCY kHz 400 300 120 170 220 270 320 370 420 470 08717 014 Figure 14 Switching Frequency vs Rr DIMMING FREQUENCY The ADD5203 contains an internal oscillator to generate the PWM dimming signal for LED brightness control The LED dimming frequency is adjustable in the range of 200 Hz to 10 kHz by using an external resistor and capacitor Creww The Rreww should be in the range of 13 to 110 and the Cieww should be in the range of 20 pF to 390 pF ADD5203 Table 8 and Recommendation Dimming Freq Rrewm Crew pF 200 Hz 110 390 500 Hz 75 200 1 kHz 50 150 5 kHz 18 47 10 kHz 13 20 CURRENT SOURCE The ADD5203 contains eight current sources to provide accurate current sinking for each LED string String to string tolerance is kept within 1 5 at 20 mA Each LED string current is adjusted up to 30 mA by an external resistor The ADD5203 contains an LED open and short fault protection circuit for each channe
6. PARALLEL 08717 010 3VIDIV 1 5VIDIV 1 1 10mA DIV Figure 12 LED Current Waveforms Brightness 0 3996 Vin 12V BRIGHTNESS 25 LEDs 10 SERIES x 8 PARALLEL 08717 011 PWM 3VIDIV 5VIDIV 1 10mA DIV Figure 13 LED FBx Waveforms Brightness 1096 Rev 0 Page 10 of 24 08717 012 08717 013 THEORY OPERATION CURRENT MODE STEP UP SWITCHING REGULATOR OPERATION The ADD5203 uses a current mode PWM boost regulator to provide the minimal voltage needed to enable the LED string at the programmed LED current The current mode regulation system allows fast transient response while maintaining a stable output voltage By selecting the proper resistor capacitor network from COMP to GND the regulator response can be optimized for a wide range of input voltages output voltages and load conditions The ADD5203 can provide a 45 V maximum output voltage and drive up to 13 LEDs 3 4 V 30 mA type of LEDs for each channel INTERNAL 3 3 V REGULATOR The ADD5203 contains a 3 3 V linear regulator The regulator is used for biasing internal circuitry The internal regulator requires 1 bypass capacitor Place this bypass capacitor between VDDIO Pin 4 and GND as close as possible to Pin VDDIO BOOST CONVERTER SWITCHING FREQUENCY The ADD5203 boost converter switching frequency is user adjustable between 350 kHz to 1
7. half of the inductor ripple current is less than the rated saturation current of the inductor In addition ensure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator For duty cycles greater than 50 that occur with input voltages greater than half the output voltage slope compensation is required to maintain stability of the current mode regulator The inherent open loop stability causes subharmonic instability when the duty ratio is greater than 50 To avoid subharmonic instability the slope of the inductor current should be less than half of the compensation slope Inductor manufacturers include Coilcraft Inc Sumida Corporation and Toko Input and Output Capacitors Selection The ADD5203 requires input and output bypass capacitors to supply transient currents while maintaining a constant input and output voltage Use a low effective series resistance ESR 10 or greater capacitor for the input capacitor to prevent noise at the ADD5203 input Place the input between the VIN and GND as close as possible to the ADD5203 Ceramic capacitors ADD5203 are preferred because of their low ESR characteristics Alternatively use a high value medium ESR capacitor in parallel with a 0 1 uF low ESR capacitor as close as possible to the ADD5203 The output capacitor maintains the output voltage and supplies current to the load while the ADD5203 switch is on The value and
8. to 50 V SHDN SDA SCL PWMI SEL1 and SEL2 0 3V to 6 V Iser FSLCT COMP R FPWM 0 3V to 3 6V VDDIO 0 3 V to 3 7V FB1 FB2 FB3 FB4 FB5 FB6 FB7 and FB8 0 3 V to 50 V OVP 0 3 V to 3 V Maximum Junction Temperature max 150 C Operating Temperature Range Ta 25 to 85 C Storage Temperature Range Ts 65 C to 150 Reflow Peak Temperature 20 sec to 40 sec 260 C ADD5203 THERMAL RESISTANCE is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages Table 6 Thermal Resistance Package Type Unit 28 Lead LFCSP_WQ 32 6 14 C W ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge A without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of
9. use an ultrafast junction diode The output diode for a boost regulator must be chosen depending on the output voltage and the output current The diode must be rated for a reverse voltage equal to or greater than the output voltage used The average current rating must be greater than the maximum load current expected and the peak current rating must be greater than the peak inductor current Using Schottky diodes with lower forward voltage drop decreases power dissipation and increases efficiency The diode must be rated to handle the average output load current Many diode Rev 0 Page 17 of 24 ADD5203 manufacturers derate the current capability of the diode as a function of the duty cycle Verify that the output diode is rated to handle the average output load current with the minimum duty cycle The minimum duty cycle of the ADD5203 is Vo UT ViN OUT D umn where Vm is the maximum input voltage For example Dum is 0 5 when Vour is 30 V and Vm 18 15 V Schottky diode manufacturers include ON Semiconductor Diodes Incorporated Central Semiconductor Corp and Sanyo Loop Compensation The external inductor output capacitor and the compensation resistor and capacitor determine the loop stability The inductor and output capacitor are chosen based on performance size and cost The compensation resistor Rc and compensation capacitor Cc at the COMP pin are selected to optimize control lo
10. 6 V to 21 V but the device can function with a voltage as low as 5 6 V The ADD5203 also has multiple safety protection features to prevent damage during fault conditions If any LED is open or short the device automatically disables the faulty current source The internal soft start prevents inrush current during startup Thermal shutdown protection prevents thermal damage The ADD5203 is available in a low profile thermally enhanced 4mm x 4 mm x 0 75 mm 28 lead RoHS compliant lead frame chip scale package LFCSP_WQ and is specified over the industrial temperature range of 25 C to 85 C One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2010 Analog Devices Inc All rights reserved ADD5203 TABLE OF CONTENTS Features atk tele ES AA E RN eta isl UE EUN 1 Operation ete 11 5 1 Current Mode Step Up Switching Regulator Operation 11 Functional Block Diagram eerte 1 Internal 3 3 V 11 General Description eoe oe RE IE IRR 1 Boost Converter Switching Frequency 2 11 Revision History E 2 Dimming Frequency feww eerte 11 Circuit Diagram s 2 Current SOUTCE n AU cia cea eee LEE 11 Specifications esie itte deter tede 4 Dimming Control Interface
11. 8 SERIES E m S 40 5 l o A 5 t E 0 5 5 10 15 20 25 9 0 25 50 75 100 125 150 175 200 225 250 5 INPUT VOLTAGE V 8 SMBus BRIGHTNESS SETTING Figure 4 Boost Converter Efficiency vs Input Voltage Figure 7 LED Current vs SMBus Brightness Setting 32 25 30 28 26 z g 15 22 E 5 5 20 18 O 10 5 16 5 14 5 12 10 8 5 0 2 85 105 125 145 165 185 205 225 245 265 7 5 10 15 20 5 Rser INPUT VOLTAGE V 5 Figure 5 LED Current vs Rser Figure 8 LED Current vs Input Voltage 20 mA Vour 20 20V DIV BRIGHTNESS 100 LEDs 12 SERIES x 8 PARALLEL 15 Vew 20V DIV 219 SHDN 3VIDIV ul EI 5 IL 1AIDIV 2 0 8 0 10 20 30 40 50 60 70 80 90 1005 PWM DUTY CYCLE 8 Figure 6 LED Current vs PWM Input Duty Cycle Figure 9 Start Up Waveforms Brightness 10096 Rev 0 Page 9 of 24 ADD5203 E Vin 7V fsw 1MHz E BRIGHTNESS 100 LEDs 10 SERIES x 8 PARALLEL Figure 10 Switching Waveforms Vin 7 V Vin 21V 1MHz F BRIGHTNESS 100 LEDs 10 SERIES x 8 PARALLEL Figure 11 Switching Waveforms Vn 21 V Vour 200mV DIV AC Vsw 20V DIV IL 500mA DIV Vout 200mV DIV AC Vsw 20V DIV IL 500mA DIV Vin 12 BRIGHTNESS 0 39 LEDs 10 SERIES 8
12. ANALOG 8 String White LED Driver with SMBus and DEVICES PWM Input for LCD Backlight Applications ADD5203 FEATURES White LED driver based on inductive boost converter Integrated 50 V MOSFET with 2 9 A peak current limit Input voltage range 6 V to 21V Maximum output adjustable up to 45 V 350 kHz to 1 MHz adjustable operating frequency Overvoltage protection OVP up to typical 47 5 V Built in soft start for boost converter Drives up to eight LED current strings LED current adjustable up to 30 mA for each channel Headroom control to maximize efficiency Adjustable dimming frequency 200 Hz to 10 kHz LED open and short fault protection Selectable dimming control interface methods PWM input SMBus serial input Selectable dimming modes Fixed delay PWM dimming control with 8 bit resolution No delay PWM dimming control with 8 bit resolution Direct PWM dimming control DC current dimming control with 8 bit resolution General Thermal shutdown Undervoltage lockout 28 lead 4 mm x 4 mm x 0 75 mm LFCSP WQ APPLICATIONS Notebook PCs UMPCs and monitor displays GENERAL DESCRIPTION The ADD5203 is a white LED driver for backlight applications based on high efficiency current mode step up converter tech nology It is designed with a 0 15 0 2 9 A internal switch and a pin adjustable operating frequency between 350 kHz and 1 MHz The ADD5203 contains eight regulated current sources for uniform brightness intensity Each current source can
13. Bit Name Description LED Panel Display panel using LED backlight Bit 7 1 MFG 3 0 Manufacturer ID Analog Devices ID is 6 REV 2 0 Silicon revision Revision 0 to Revision 7 are allowed for silicon spins Rev 0 Page 16 of 24 EXTERNAL COMPONENT SELECTION GUIDE Inductor Selection The inductor is an integral part of the step up converter It stores energy during the switch on time and transfers that energy to the output through the output diode during the switch off time An inductor in the range of 4 7 uH to 22 is recommended In general lower inductance values result in higher saturation current and lower series resistance for a given physical size However lower inductance results in higher peak current which can lead to reduced efficiency and greater input and or output ripple and noise Peak to peak inductor ripple current at close to 3096 of the maximum dc input current typically yields an optimal compromise The input Vix and output Vour voltages determine the switch duty cycle D which in turn can be used to determine the inductor ripple current Vour ES Vin Vour Use the duty cycle and switching frequency fsw to determine the on time _ ON The inductor ripple current in a steady state is t Vin Xton 1 Solve for the inductance value L fon 41 L Make sure that the peak inductor current that is the maximum input current plus
14. D REGISTER FAULT STATUS REGISTER DEVICE CONTROL REGISTER BRIGHTNESS CONTROL 4 5 4 CURRENT 6 CURRENTSOURCE7 FB6 8 CURRENT SOURCE 8 CURRENT SOURCE CONTROLLER 1 AGND Figure 2 Circuit Diagram Rev 0 Page 3 of 24 REGISTER ADD5203 NC OVP 5 CURRENT SENSE SOFT START R SENSE TSD FAULT OCP FAULT SMBus INTERFACE DUTY GENERATOR OPERATION MODE SELECTION OSCILLATOR 08717 002 ADD5203 SPECIFICATIONS STEP UP SWITCHING REGULATOR SPECIFICATIONS Vm 12 V SHDN high Ta 25 C to 85 C unless otherwise noted Typical values are at Ta 25 Table 1 Parameter Symbol Test Conditions Min Typ Max Unit SUPPLY Input Voltage Range Vin 6 21 V BOOST OUTPUT Output Voltage Vour 45 V SWITCH On Resistance Roson Vin 12V Isw 100 mA 150 210 Leakage Current 44 70 pA Peak Current Limit la Duty cycle D Dmax 2 9 A OSCILLATOR Switching Frequency Re 150 800 1000 1200 kHz fsw Rr 470 350 kHz Maximum Duty Cycle Dmax Rr 470 85 92 SOFT START Soft Start Time tss 1 5 ms OVERVOLTAGE PROTECTION Overvoltage Rising Threshold on OVP Pin Vover 1154 120 1 267 V Overvoltage Falling Threshold on OVP Pin Vover 1 050 1 12 1 188 V LED CURRENT REGULATION SPECIFICATIONS Vm 12 V SHDN high Ta 25 C to 85 C unless otherwise noted Typical valu
15. High DC current SMBus Open DC current PWM Low Direct PWM PWM Rev 0 Page 11 of 24 ADD5203 PWM DIMMING MODE The ADD5203 supports an 8 bit resolution to control brightness therefore the LED dimming duty is generated with 256 steps through the PWM input duty value in the range of 0 to 100 In addition if the PWM input duty cycle is 096 longer than 10 ms the ADD5203 is disabled Note that the ADD5203 has immunity when the PWM input duty cycle is converted to 256 steps Even the PWM input has 0 195 jitter Fixed Delay PWM Dimming Fixed delay PWM mode is selected when SEL1 is open and SEL2 is high for a PWM application or when SELI is high and SEL2 is high for an SMBus application In this mode each current source has a fixed turn on time delay between adjacent strings The fixed delay time is set by the FPWM frequency Each channel delay time is set by the following equation 2 256 D where 1 fewm and is the LED dimming frequency DUTY 60 DUTY 60 torr 08717 015 Figure 15 Fixed Delay PWM Dimming Timing No Delay PWM Dimming No delay PWM mode is selected when SEL1 is open and SEL2 18 low for a PWM application or when SELI is high and SEL2 is low for an SMBus application In this mode each current source turns on and off at the same time without any phase delay DUTY 60 PWMI l DUTY 60 i tw Fe
16. T 300 ns Data Setup Time tsu DAT 250 ns Clock Low Period trow 4 7 us Clock High Period thicH 4 0 50 us Clock Data Fall Time tr 300 ns Clock Data Rise Time tr 1 us 1 These electrical specifications are guaranteed by design 2 After this period the first clock is generated Rev 0 Page 5 of 24 ADD5203 GENERAL SPECIFICATIONS Vin 12 V SHDN high Ta 25 C to 85 C unless otherwise noted Typical values at 25 C Table 4 Parameter Symbol Test Conditions Min Typ Max Unit SUPPLY Input Voltage Range Vin 6 21 V Quiescent Current lo 6V x x 21 V SHDN high 4 2 6 5 mA Shutdown Supply Current Isp 6V lt Vn x 21 V SHDN low 40 160 uA VDD REGULATOR VDD Regulated Output VvoD_REG 6V lt Vn lt 21V 3 18 3 3 3 42 PWM INPUT PWM Voltage High VeWM_HIGH 2 2 5 5 V PWM Voltage Low Vewm_Low 0 8 V PWM Input Range 200 10 000 Hz THERMAL SHUTDOWN Thermal Shutdown Threshold Tsp 160 Thermal Shutdown Hysteresis Tspxys 30 C UVLO Vin Falling Threshold Vin falling 4 2 4 6 V Vin Rising Threshold Vin rising 5 0 5 6 V SHDN CONTROL Input Voltage High Vin 2 0 V Input Voltage Low Vit 1 0 V SHDN Pin Input Current Es SHDN 3 3V 6 uA 1 These electrical specifications are guaranteed by design Rev 0 Page 6 of 24 ABSOLUTE MAXIMUM RATINGS 25 unless otherwise noted Table 5 Parameter Rating VIN 0 3V to 23 SW 0 3V
17. ally 1 5 ms Overvoltage Protection OVP The ADD5203 contains OVP circuits to prevent boost converter damage if the output voltage becomes excessive for any reason To keep a safe output level the integrated OVP circuit monitors the output voltage When the OVP pin voltage is reached by the OVP rising threshold the boost converter stops switching causing the output voltage to drop When the OVP pin voltage goes lower than the OVP falling threshold the boot converter begins switching causing the output to rise There is about 7 596 hysteresis between the rising and falling thresholds The OVP level can be calculated with the following equation Rev 0 Page 12 of 24 V 7 x R1 R2 In general the suitable OVP level is 5 V higher than the nominal boost switching regulator output Large resistors up to 1 can be used for R2 to minimize power loss In addition some applications require C1 to prevent noise interference at the OVP pin in the range of 10 pF to 30 pF R2 El DETECTION COMP R1 C1 OVP R REF 8 Figure 19 Overvoltage Protection Circuit Open Load Protection OLP The ADD5203 contains a headroom control circuit to minimize power loss at each current source Therefore the minimum feedback voltage is achieved by regulating the output voltage of the boost converter If any LED string is opened during normal operation the current source headroom voltage is pulled to
18. be driven up to 30 mA and the LED driving current is pin adjustable by an external resistor The ADD5203 drives up to eight parallel strings of multiple series connected LEDs with a 1 5 current matching between strings The ADD5203 provides various dimming modes Each dimming mode is selectable with an external dimming mode selection pin The LED dimming control interface can be achieved through PWM input and or SMBus The device Rev 0 Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM STEP UP SWITCHING REGULATOR EIGHT CURRENT SOURCES PWM DUTY EXTRACTOR 8 BIT BRIGHTNESS CONTROL LOGIC FIXED DELAY NO DELAY DIRECT PWM DC CURRENT DIMMING CONTROL WITH PWM AND OR SMBus INTERFACE UNDERVOLTAGE LOCKOUT INTERNAL SOFT START THERMAL PROTECTION OVERVOLTAGE PROTECTION AUTODISABLE FOR LED OPEN SHORT 08717 001 Figure 1 provides adjustable output dimming frequency range from 200 Hz to 10 kHz by an external resistor and capacitor The ADD5203 operates over an input voltage range of
19. characteristics of the output capacitor greatly affect the output voltage ripple and stability of the regulator Use a low ESR output capacitor ceramic dielectric capacitors are preferred For very low ESR capacitors such as ceramic capacitors the ripple current due to the capacitance is calculated as follows Because the capacitor discharges during the on time the charge removed from the capacitor Qc is the load current multiplied by the on time Therefore the output voltage ripple AVovr is where Covr is the output capacitance I is the average inductor current Using the duty cycle and switching frequency fsw users can determine the on time with the following equation _ D few The input Vm and output Vour voltages determine the switch duty cycle D with the following equation Vin V OUT t Dz Choose the output capacitor based on the following equation gt I x Vour Vin our XVovr X AVour Capacitor manufacturers include Murata Manufacturing Co Ltd AVX Sanyo and Taiyo Yuden Co Ltd Diode Selection The output diode conducts the inductor current to the output capacitor and loads while the switch is off For high efficiency minimize the forward voltage drop of the diode Schottky diodes are recommended However for high voltage high temperature applications where the Schottky diode reverse leakage current becomes significant and can degrade efficiency
20. efault value is OXFF Device Control Register Address 0x01 This register has three bits Two bits control the operation mode of the device and a single bit controls the backlight on off state This register is both readable and writable for Bit 0 to Bit 2 Bit 0 named BL CTL is used as on off control for the output LEDs Bit 1 and Bit 2 named SEL and MD control the operating mode of the device respectively If the CRT bit is set to 1 the device turns on the backlight within 10 ms after the write cycle If the CRT bit is set to 0 the device turns off the backlight immediately The ADD5203 output operating mode is selected by the combination of Bit 1 and Bit 2 see Table 10 Table 11 Brightness Control Register Address 0x00 Bit Map MSB ADD5203 The PWM MD bit selects the manner in which the PWM input is to be interpreted When this bit is 0 the PWM input reflects a percent change in the current brightness that is DPST mode and should be as follows DPST Brightness Csr x PWM where Cor is the current brightness setting from SMBus without influence from the PWM PWM is the percent duty cycle The PWM signal starts from 100 when operating in DPST mode When PWM_MD is 1 the PWM input has no effect on the brightness setting unless the ADD5203 is in PWM mode In addition when operating in PWM mode this bit is a do not care see Table 10 The PWM_SEL bit determines whether the SMBus
21. es are at Ta 25 Table 2 Parameter Symbol Test Conditions Min Typ Max Unit CURRENT SOURCE Iser Pin Voltage 6 lt lt 21 1 16 12 1 24 V Adjustable LED Current 0 30 mA Constant Current Sink of 20 mA 20 Rset 141 56 19 4 20 20 6 mA Minimum Headroom Voltage Rset 141 56 0 65 0 85 V Current Matching Between Strings Rset 141 56 1 5 1 5 LED Current Accuracy Rset 141 56 3 3 Current Source Leakage Current 1 FPWM GENERATOR Dimming Frequency Range 6 lt lt 21 200 10 000 2 Dimming Frequency fowm Rrewm 50 150 pF 820 1000 1180 Hz LED FAULT DETECTION Open Fault Delay TD_OPENFAULT 6 5 us 1 These electrical specifications are guaranteed by design 2 Tested at Ta 25 C Rev 0 Page 4 of 24 ADD5203 SMBUS SPECIFICATIONS Vin 12 V SHDN high Ta 25 C to 85 C unless otherwise noted Typical values are at Ta 25 C Table 3 Parameter Symbol Test Conditions Min Typ Max Unit SMBus INTERFACE Data Clock Input Low Level Vit 0 8 V Clock Input High Level 2 1 5 5 V Data Clock Output Low Level VoL 0 4 V SMBus TIMING SPECIFICATIONS Clock Frequency 10 100 kHz Bus Free Time Between Stop and Start Condition teur 47 us Hold Time After Start Condition 4 0 us Repeated Start Condition Setup Time tsusta 4 7 us Stop Condition Setup Time tsusto 4 0 us Data Hold Time tHD DA
22. es lead inductance and resistance which in turn reduce noise spikes ringing and resistive losses that produce voltage errors The grounds of the IC input capacitors output capacitors and output diode if applicable should be connected close together directly to a ground plane It is also a good idea to have a ground plane on both sides of the PCB This reduces noise by reducing ground loop errors and by absorbing more of the EMI radiated by the inductor For multilayer boards of more than two layers a ground plane can be used to separate the power plane power traces and com ponents and the signal plane feedback compensation and components for improved performance On multilayer boards the use of vias is required to connect traces and different planes If a trace needs to conduct a significant amount of current from one plane to the other it is good practice to use one standard via per 200 mA of current Arrange the components so that the switching current loops curl in the same direction Due to how switching regulators operate there are two power states one state when the switch is on and one when the switch is off During each state there is a current loop made by the power components currently conducting Place the power components so that the current loop is conducting in the same direction during each of the two states This prevents magnetic field reversal caused by the traces between the two half cycles and reduces
23. functionality Rev 0 7 of 24 ADD5203 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ot On NN 25 SHDN PWMI 1 21 PGND SEL1 2 20 PGND SEL2 3 19 FPWM VDDIO 4 18 R FPWM SDA 5 17 lser SCL 6 16 NC 7 15 FB8 EIEEE NOTES 1 NC NO CONNECT 2 CONNECT THE EXPOSED PADDLE TO GND 08717 003 Figure 3 Pin Configuration Table 7 Pin Function Descriptions Pin No Mnemonic Description 1 PWMI PWM Signal Input 2 SEL 1 Dimming Mode Selection 1 3 SEL2 Dimming Mode Selection 2 4 VDDIO Internal Linear Regulator Output This regulator provides power to the ADD5203 5 SDA Serial Data Input Output 6 SCL Serial Clock Input 7 FB1 Regulated Current Sink Connect the bottom cathode of the LED string to this pin 8 FB2 Regulated Current Sink Connect the bottom cathode of the LED string to this pin 9 FB3 Regulated Current Sink Connect the bottom cathode of the LED string to this pin 10 FB4 Regulated Current Sink Connect the bottom cathode of the LED string to this pin 11 AGND Analog Ground 12 FB5 Regulated Current Sink Connect the bottom cathode of the LED string to this pin If unused connect to GND 13 FB6 Regulated Current Sink Connect the bottom cathode of the LED string to this pin If unused connect to GND 14 FB7 Regulated Current Sink Connect the bottom cathode of the LED string to this pin If unused connect to GND 15 FB8 Regulated C
24. l If the headroom voltage of the current source remains below 200 mV while the boost converter output reaches the OVP level the ADD5203 recognizes that the current source has an open load fault for the current source and the current source is disabled If the headroom voltage of the current source goes above 7 2 V the current source is disabled for short protection If an application requires four LED strings each LED string should be connected using FB1 to FB4 Tie the unused FB pins 5 to FB8 to GND The ADD5203 contains hysteresis to prevent the LED current change that is caused by 0 195 jitter of the PWM input Programming the LED Current As shown in Figure 2 the ADD5203 has an LED current set pin Iser A resistor Rser from this pin to ground adjusts the LED current up to 30 mA LED current level can be set with the following equation _ 2831 SET DIMMING CONTROL INTERFACE The ADD5203 dimming control interface method is selectable between the SMBus serial input and or the external PWM input The LED dimming modes supported by ADD5203 can be controlled externally through these dimming control interfaces The SEL1 and SEL2 pins should be set based on the application conditions see Table 9 Table 9 Brightness Control Mode Selection SEL1 SEL2 Dimming Mode Interface High High Fixed delay PWM SMBus Low No delay PWM SMBus Open High Fixed delay PWM PWM Low No delay PWM PWM Low
25. n the bus direction turns around with the rebroadcast of the slave address with Bit 0 indicating a read cycle The fourth byte contains the data being returned by the backlight controller The byte value in the data byte should reflect the value of the register being queried at the command code index Note the bus directions which are shaded in Figure 21 and are used on cydes where the slaved backlight controller drives the data line other cycles are driven by the host master Write Byte The write byte protocol is only three bytes long The first byte starts with the slave address followed by the command code which translates to the register index being written The third byte contains the data byte that must be written into the register selected by the command code Note the bus directions which are shaded in Figure 22 and are used on cycles where the slaved backlight controller drives the data line All other cycles are driven by the host master Rev 0 Page 13 of 24 ADD5203 Slave Device Address As shown in Figure 23 the ADD5203 address consists of seven is 0x59 address bits plus one read write R W bit If the device is in write mode the LSB is set to 0 and the slave address byte is 0x58 If the Figure 20 SMBus Interface SLAVE ADDRESS WIA COMMAND CODE 5 SLAVE ADDRESS MASTER TO SLAVE SLAVE TO MASTER B Figure 21 Read Byte Protocol 5 SLAVE ADDRESS COMMAND CODE
26. nd customer Therefore if during the engineering development process three silicon spins are needed before the device is released to the factory of the end customer the next available revision ID is used for these three spins The manufacturer ID of Analog Devices Inc is 6 Bit 6 3 0110b In addition the initial value of REVx is 0 and subsequent values are incremented by 1 This register is read only MSB LSB Bit 7 Bit 6 Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Default Value Reserved Reserved 2_CH_SD 1_CH_SDS BL_STAT OV_CURR THRM_SHDN Fault 0x00 Table 16 Fault Status Register Address 0x01 Bit Description Bit Name Description 2_CH_SD_ 1_CH_SD The number of faulted strings is reported in these bits 00 no faults 01 one string fault 11 two or more strings faulted BL_STAT Backlight status 1 backlight on 0 backlight off default OV_CURR Input overcurrent 1 overcurrent condition 0 current ok default THRM_SHDN Thermal shutdown 1 thermal fault 0 thermal ok default Fault Fault occurred Logic OR of all the fault conditions Table 17 Identification Register Address 0x03 Bit Map MSB LSB Bit 7 Bit 6 Bit 5 R Bit 4 R Bit 3 R Bit 2 R Bit 1 R Bit 0 R Default Value LED panel MFG3 MFG2 MFG1 MFGO REV2 REV1 REVO OxBO Table 18 Identification Register Address 0x03 Bit Description
27. nge default PWM SEL Brightness control select 1 control by PWM 0 control by SMBus default BL CTL Backlight on off 1 on 0 off default Fault Status Register Address 0x02 This register has six status bits that allow monitoring of the ADD5203 operating state Bit 0 named fault is a logical OR of all fault codes to simplify error detection In the operation of the ADD5203 Bit 1 named THRM SHDN is set to 1 when a thermal shutdown event occurs Bit 3 named BL STAT is the backlight status indicator This bit is set to 1 whenever the backlight is on and is set to 0 whenever the backlight is off Bit 4 named 1 CH SD is set to 1 if one or more current sources are disabled In addition Bit 5 named 2 SD is set to 1 if two or more current sources are disabled due to an LED open event during normal operation All reserved bits return to 0 when read and ignore the bit value when written All of the bits in this register are read only The default value for Register 0x02 is 0x00 Table 15 Fault Status Register Address 0x02 Bit Map Identification Register Address 0x03 The ID register contains two bit fields to denote the manufacturer and silicon revision of the ADD5203 The bit field widths were chosen to allow up to 16 vendors with up to eight silicon revisions each To ensure that the number of silicon revisions remains low the revision field should not be updated until the part is sent to the factory of the e
28. op stability For most applications the compensation resistor should be in the range of 500 0 to 30 and the compensation capacitor should be in the range of 100 pF to 330 nF VHR R Cc 9 2 a 08717 024 Figure 24 Compensation Components A step up converter produces an undesirable right half plane zero in the regulation feedback loop Capacitor C2 is chosen to cancel the zero introduced by output capacitance ESR Solving for C2 __ Cour 2 For low ESR output capacitance such as with ceramic capacitor C2 is optional LAYOUT GUIDELINES When designing a high frequency switching regulated power supply layout is very important Using a good layout can solve many problems associated with these types of supplies The main problems are loss of regulation at high output current and or large input to output voltage differentials excessive noise on the output and switch waveforms and instability Using the following guidelines can help minimize these problems Make all power high current traces as short direct and thick as possible It is good practice on a standard printed circuit board PCB to make the traces an absolute minimum of 15 mil 0 381 mm per ampere Place the inductor output capacitors and output diode as close to each other as possible This helps reduce the EMI radiated by the power traces that are due to the high switching currents through them This also reduc
29. or PWM input should drive brightness The relationship between these two control bits can be thought of as specifying an operating mode for the ADD5203 The defined modes are shown in Table 10 Note that depending on the setting of some bits other bits have no effect and are do not cares shown as X in Table 10 Table 10 Operating Modes Selected by Device Control Register Bit 1 and Bit 2 PWM SEL Bit 1 MD Bit 2 Mode 1 X PWM mode 0 1 SMBus mode 0 0 SMBus mode with DPST 1X is don t care All reserved bits return to 0 when read and the bits are ignored when written This default value of the register is 0x00 LSB Bit 7 R W Bit6 R W Bit5 R W Bit4 R W Bit3 R W Bit2 R W Bit1 R W BitO R W Default Value BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRTO Table 12 Brightness Control Register Address 0x00 Bit Description Bit Name Description BRT 7 0 256 steps of brightness levels Table 13 Device Control Register Address 0x01 Bit Map MSB LSB Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit 2 R W Bit 1 R W Bit 0 R W Default Value Reserved Reserved Reserved Reserved Reserved PWM MD PWM SEL BL CTL 0x00 Rev 0 Page 15 of 24 ADD5203 Table 14 Device Control Register Address 0x01 Bit Description Bit Name Description PWM MD PWM mode select 1 absolute brightness 0 percent cha
30. radiated EMI Rev 0 Page 18 of 24 ADD5203 Layout Procedure e Place the compensation components as close as possible to To achieve high efficiency good regulation and stability a good the COMP pin PCB layout is required It is recommended that the reference e Place the LED current setting resistors as close as possible board layout be followed as closely as possible because it is to each pin to prevent noise pickup already optimized for high efficiency and low noise e Avoid routing noise sensitive traces near high current Use the following general guidelines when designing PCBs traces and components especially the LED current setting node Iser Keep Cx close to the Viv and GND leads of the ADD5203 e Use a thermal pad size that is the same dimension as the Keep the high current path from through 11 to the exposed pad on the bottom of the package SW and GND leads as short as possible Keep the high current path from Cm through L1 D1 and Heat Sinking Covr as short as possible When using a surface mount power IC or external power Keep high current traces as short and wide as possible switches the PCB can often be used as the heat sink This is Keep nodes connected to SW away from sensitive traces accomplished by using the copper area of the PCB to transfer such as to prevent coupling of the traces If such heat from the device Users should maximize this area to optimize traces need to be run near each o
31. te LI LI L1 L oN torr LI LF Lo L 2 1 LI L LJ L 8 Figure 16 Delay PWM Dimming Timing 08717 016 Direct PWM Dimming Direct PWM mode is selected when SELI is low and SEL2 is low for a PWM application In this mode the PWM input controls the ADD5203 LED dimming logic It turns the current sources on and off without any duty extraction In addition each current source has no phase delay in this mode The LED brightness is changed by the PWM input duty ratio lt DUTY 60 PWM LL mE DUTY 60 7 L uo2 LL LST 22 0 01 ligp8 l Figure 17 Direct PWM Dimming Timing 08717 017 DC Current Dimming DC current mode is selected when SELI is low and SEL2 is open for a PWM application or when SELI is low and SEL2 is high for an SMBus application In this mode the maximum LED current is set by the value of Once the maximum LED current is set the LED current can be changed with 256 steps through PWM input or SMBus DUTY 80 DUTY 60 DUTY 40 DUTY 20 i 1 0 6 0 4 lgpMAx 0 2 08717 018 Figure 18 DC Current Dimming Timing SAFETY FEATURES The ADD5203 contains several safety features to provide stable operation Soft Start The ADD5203 contains an internal soft start function to reduce inrush current at startup The soft start time is typic
32. ther place a ground trace thermal performance between the two as a shield Rev 0 Page 19 of 24 ADD5203 TYPICAL APPLICATION CIRCUITS L1 ViN 10uH 6V TO 21V D1 UP TO 45V R1 0 Yu c Lo x xu ru Yu 2 Y Yu xu xu WA Yu Y ADD5203 T ER 08717 025 Figure 25 Typical Application Circuit for SMBus Interface with No Delay Dimming Mode Rev 0 Page 20 of 24 ADD5203 oem Towel vile l FR yu Yu ar uw Yu Yu Yu Yu f Nc 5 SDA Nc 6 EN EN EN WET 7 2 FB2 8 2 4 4 10 FPWM 5 9 2 FB6 3 R6 FB7 14 20pF di 9 27 FSLCT e Hn Ris 28 7 Ga 08717 026 Figure 26 Typical Application Circuit for PWM Interface with DPWM Dimming Mode Rev 0 Page 21 of 24 ADD5203 Vour TO 21V D1 UP TO 45V 12 A XA WR DA mi WA Yu Yu ar LCS da pu Yu Yu Yu Yu C2 5 E s 1 5 edt Nc 5 SDA ne 6 EN
33. urrent Sink Connect the bottom cathode of the LED string to this pin If unused connect to GND 16 NC No Connection 17 Full Scale LED Current Set A resistor from this pin to ground sets the LED current up to 30 mA 18 R FPWM Dimming frequency adjustment pin with an external resistor 19 C FPWM Dimming frequency adjustment pin with an external capacitor 20 PGND Power Ground 21 PGND Power Ground 22 OVP Overvoltage Protection 23 SW Drain Connection of the Internal Power FET 24 SW Drain Connection of the Internal Power FET 25 SHDN Shutdown Control for PWM Input Operation Mode Active low 26 VIN Supply Input Must be locally bypassed with a capacitor to ground 27 FSLCT Frequency Select A resistor from this pin to ground sets the boost switching frequency from 350 kHz to 1 MHz 28 COMP Compensation for Boost Converter A capacitor and a resistor are connected in series between ground and this pin for stable operation and an optional capacitor can be connected from this pin to ground EP Exposed Paddle Connect the exposed paddle to ground Rev 0 Page 8 of 24 ADD5203 TYPICAL PERFORMANCE CHARACTERISTICS 25 lj gp 20mA 2 BRIGHTNESS 100 20 fgy 600kHz 2 8 PARALLEL x 8 SERIES 2 9 77 75 p 10 PARALLEL x
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ANALOG DEVICES ADD5203: 8 String White LED Driver with SMBus PWM Input for LCD Backlight Application