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ANALOG DEVICES AD7841 handbook

1. JEDEC Industry Standard Soldering eee Rute J STD 020 Io E 24000 V NOTES Stresses above those listed under Absolute Maximum Ratings may cause perma nent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Transient currents of up to 100 mA will not cause SCR latch up 5Vac must not exceed Vpp by more than 0 3 V If it is possible for this to happen during power supply sequencing the following diode protection scheme will ensure protection Vpp Vcc IN4148 HP5082 2811 Vcc AD7841 PIN CONFIGURATION a u Ta o 44 ul a o o a mogqarte usu o 5 5F 5 G ie 25828 ssas FFF Sa SS 44 as a2 41 40 a0 se 37 36 3s aa DUTGND_AB VoutA Vrer AB Vrer AB PIN 1 IDENTIFIER AD7841 TOP VIEW Not to Scale DUTGND GH VourH Vrer GH Vrer GH CLR DB13 DB12 DB11 DB10 DB9 DB8 REV B AD7841 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 DUTGND_AB Device Sense Ground for DACs A and B VourA and VourB are referenced to the voltage applied to this pin 2 44 43 VourA Voy TH DAC Outputs 41 37 35 34 32 3 4 Verer AB Vggg AB Reference Inputs for DAC
2. CCW 4 COMPLIANT TO JEDEC STANDARDS MO 112 AA 1 8 Figure 14 44 Lead Metric Quad Flat Package MQFP S 44 2 Dimensions shown in millimeters ORDERING GUIDE Package Model Linearity Error LSBs DNL LSBs Temperature Range Package Description Option AD7841ASZ 4 0 9 2 40 C to 85 C 44 Lead Metric Quad Flat Package MQFP S 44 2 AD7841ASZ REEL 4 0 9 2 40 C to 85 C 44 Lead Metric Quad Flat Package MQFP S 44 2 AD7841BSZ 2 1 40 C to 85 C 44 Lead Metric Quad Flat Package MQFP S 44 2 AD7841BSZ REEL 2 1 40 C to 85 C 44 Lead Metric Quad Flat Package MOFP S 44 2 EVAL AD7841EBZ Evaluation Board ZZ RoHS Compliant Part REVISION HISTORY 1 11 Rev A to Rev B Changes to Absolute Maximum Ratings Lead Temperature 4 Updated Outline Dimensions sse 13 Moved and Changes to Ordering Guide 13 1999 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09645 0 1 11 B DEVICES www analo g com Rev B Page 13 of 13
3. O Vrer AB EN Vrer AB VourAQ PIN DRIVER VoutBO DUTGND_AB O Vout 2 DEVICE GND DEVICE 7 GND mo WINDOW COMPARATOR TO TESTER ADDITIONAL PINS OMITTED FOR CLARITY Figure 12 ATE Application One of the AD588s is used as a reference for DACs A and B These DACs are used to provide high and low levels for the pin driver The pin driver may have an associated offset This can be nulled by applying an offset voltage to Pin 9 of the AD588 First the code 1000 0000 is loaded into the DACA latch and the pin driver output is set to the DACA output The Vorrser Voltage is adjusted until 0 V appears between the pin driver output and DUTGND This causes both Vggg and Vrer to be offset with respect to GND by an amount equal to TRIMDAC is a registered trademark of Analog Devices Inc REV B Vorrser However the output of the pin driver will vary from 10 V to 10 V with respect to DUTGND as the DAC input code varies from 000 000 to 111 111 The Voggsgr voltage is also applied to the DUTGND pins When a clear is performed on the AD7841 the output of the pin driver will be 0 V with respect to DUTGND The other AD588 is used to provide a reference voltage for DACs G and H These provide the reference voltages for the window comparator shown in the diagram Note that Pin 9 of this AD588 is connected to Device GND This causes Vger GH and Vggg GH to be referenced to Device
4. 5 0 5 0 V min max Vrer t VrerC 2 10 2 10 V min max For Specified Performance Can Go as Low as 0 V but Performance Not Guaranteed DUTGND INPUTS DC Input Impedance 60 60 kQ typ Max Input Current 0 3 0 3 mA typ Per Input Input Range 2 2 2 2 V min max OUTPUT CHARACTERISTICS Output Voltage Swing Vss 2 5 V to Vss 2 5 V to V typ Vout 2 X Vrer Vrer Vrer x D Vpp 2 5V Vpp 2 5 V VpuTGND Short Circuit Current 15 15 mA max Resistive Load 5 5 kQ min To0 V Capacitive Load 50 50 pF max To0 V DC Output Impedance 0 5 0 5 Q max DIGITAL INPUTS Vinu Input High Voltage 2 4 2 4 V min Vint Input Low Voltage 0 8 0 8 V max In Input Current Total for All Pins 25 C ur 1 uA max Tmn to Tmax 10 10 uA max Cm Input Capacitance 10 10 pF max POWER REQUIREMENTS Vec 4 75 5 25 4 75 5 25 V min max For Specified Performance Vpp 15 V 10 15 V 10 V min max For Specified Performance Vss 15V 10 15V 10 V min max For Specified Performance Power Supply Sensitivity AFull Scale AVpp 90 90 dB typ AFull Scale AVss 90 90 dB typ Tec 0 5 0 5 mA max Ving Vcc Vint GND Dynamic Current Ipp 10 10 mA max Outputs Unloaded Typically 8 mA Iss 10 10 mA max Outputs Unloaded Typically 8 mA NOTES Temperature range for A and B Versions 40 C to 85 C Guaranteed by characterization Not production tested See DUTGND Voltage Range section The AD7841 is functional with power supplies of 12 V 10 with reduce
5. CODE TEMPERATURE C TPC 1 Typical INL Plot TPC 2 Typical DNL Plot TPC 3 Typical INL Error vs Temperature 6 Vec 45V 5 Vpp 15V Vss 15V o 4 a a 8 DIGITAL INPUTS i n ZERO SCALE ERROR lt 3 THRESHOLDS _ x I E 9 82 wW 3 z ui a FULL SCALE ERROR DIGITAL INPUTS SUPPLIES 0 1 4 1 40 20 0 20 40 60 80 100 40 20 0 20 40 60 80 100 40 20 0 20 40 60 80 100 TEMPERATURE C TEMPERATURE C TEMPERATURE C TPC 4 Typical DNL Error vs TPC 5 Zero Scale and Full Scale TPC 6 lcc vs Temperature Temperature Error vs Temperature 0 6 0 5 10 19 0 4 0 3 g 10 18 2 E C L O 0 2 z 5 0 1 10 17 0 v 0 1 10 16 0 2 4 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 27 28 29 30 31 32 33 40 20 0 20 40 60 80 100 SETTLING TIME ps TEMPERATURE C TPC 7 Typical Digital to Analog TPC 8 Settling Time 4 TPC 9 lbp Iss vs Temperature Glitch Impulse REV B m AD7841 Unipolar Configuration Figure 2 shows the AD7841 in the unipolar binary circuit configuration The Vggg input of the DAC is driven by the AD586 a 5 V reference Vggg is tied to ground Table II gives the code table for unipolar operation of the AD7841 Other suitable references include the REFO2 a precision 5 V reference and the
6. REF195 a low dropout micropower preci sion 5 V reference 15V 5V Vpp Vec O Vout SIGNAL GND GND ADDITIONAL PINS OMITTED FOR CLARITY Figure 2 Unipolar 10 V Operation Offset and gain may be adjusted in Figure 2 as follows To adjust offset disconnect the Vggg input from 0 V load the DAC with all 0s and adjust the Vggg voltage until Vopr 0 V For gain adjustment the AD7841 should be loaded with all 1s and R1 adjusted until Voyr 2 Vggg 1 LSB 10 V 16383 16384 9 99939 V Many circuits will not require these offset and gain adjustments In these circuits R1 can be omitted Pin 5 of the AD586 may be left open circuit and Pin 2 Vggg of the AD7841 tied to 0 V Table II Code Table for Unipolar Operation Binary Number in DAC Register Analog Output MSB LSB Vout jb dad 111 i 2 Vper 16383 16384 V 10 0000 0000 0000 2 Vggp 8192 16384 V Ol 111 111 1lll 2 Vggg 8191 16384 V 00 0000 0000 0001 2 Vprer 1 16384 V 00 0000 0000 0000 0V NOTES V Vrer Vrzr 0 V for unipolar operation For Vgge 5 V 1 LSB 10 V 2 10 V 16384 610 uV Bipolar Configuration Figure 3 shows the AD7841 set up for 10 V operation The AD588 provides precision 5 V tracking outputs that are fed to the Vggg and Vggg inputs of the AD7841 The code table for bipolar operation of the AD7841 is shown in Table III In Figure 3 full scale and bipolar zero adjustments are provided by
7. third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices DUTGND DUTGND cD AB O Vour NI n VourB L Voute E four Vas VourD und VoutE VourF VourG VourH Vrer Vrer CLR DUTGND DUTGND CDEF CDEF EF GH One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 1999 2011 Analog Devices Inc All rights reserved AD7841 SPECIFI Voge 2 5 V 526 Vpp 15 V 10 Vos 15 V 10 GND DUTGND 0 V R 5 KQ and C 50 pF to GND T4 Ty to Tmax unless otherwise noted CATIONS Parameter Unit Test Conditions Comments ACCURACY Resolution 14 14 Bits Relative Accuracy t t2 LSB max Differential Nonlinearity 0 9 2 1 LSB max Guaranteed Monotonic Over Temperature for All Grades Zero Scale Error 8 8 LSB max Vrer t 5 V Vegp 5 V Typically within 2 LSB Full Scale Error 8 8 LSB max Vrer t 5 V Vegp 5 V Typically within 2 LSB Gain Error 2 LSB typ Vagg 5 V Vagg 5 V Gain Temperature Coefficient 0 5 0 5 ppm FSR C typ 10 10 ppm FSR C max DC Crosstalk 120 120 uV max See Terminology Typically 75 uV REFERENCE INPUTS DC Input Impedance 100 100 MQ typ Input Current 1 1 uA max Per Input Typically 0 03 uA Vrer Range 0 5 0 5 V min max Vererr Range
8. varying the gain and balance on the AD588 R2 varies the gain on the AD588 while R3 adjusts the offset of both the 5 V and 5 V outputs together with respect to ground For bipolar zero adjustment the DAC is loaded with 1000 0000 and R3 is adjusted until Vout 0 V Full scale is adjusted by loading the DAC with all 1s and adjusting R2 until Vour 10 8191 8192 V 9 99878 V When bipolar zero and full scale adjustment are not needed R2 and R3 can be omitted Pin 12 on the AD588 should be con nected to Pin 11 and Pin 5 should be left floating R1 15V 5V O O O Vout 10V TO 10V V SIGNAL GND ADDITIONAL PINS OMITTED FOR CLARITY Figure 3 Bipolar 10 V Operation Table III Code Table for Bipolar Operation Binary Number in DAC Register Analog Output MSB LSB Vout 11 1111 1111 1111 2 Vrer Vrer 16383 16384 V 10 0000 0000 0001 2 VgggC Vrer 8193 16384 V 10 0000 0000 0000 2 VgggC Vrer 8192 16384 V 01 1111 1111 1111 2 Vgge O Vggr 8191 16384 V 00 0000 0000 0001 2 Vrrr Vag 1 16384 V 00 0000 0000 0000 2 VrEK V NOTES Vrer Vrer VrerC For Vapp 5 V and VggeC 5 V Vper 10 V 1 LSB 2 Vapp V 2 4 20 V 16384 1 22 mV CONTROLLED POWER ON OF THE OUTPUT STAGE A block diagram of the output stage of the AD7841 is shown in Figure 4 It is capable of driving a load of 5 kQ in parallel with 50 pF Gi to Gg are transmission gates used t
9. ANALOG DEVICES Octal 14 Bit Parallel Input Voltage Output DAC AD7841 FEATURES Eight 14 Bit DACs in One Package Voltage Outputs Offset Adjust for Each DAC Pair Reference Range of 5 V Maximum Output Voltage Range of 10 V x15 V 10 Operation Clear Function to User Defined Voltage 44 Lead MOFP Package APPLICATIONS Automatic Test Equipment Process Control General Purpose Instrumentation GENERAL DESCRIPTION The AD7841 contains eight 14 bit DACs on one monolithic chip It has output voltages with a full scale range of 10 V from reference voltages of 5 V The AD7841 accepts 14 bit parallel loaded data from the exter nal bus into one of the input registers under the control of the WR CS and DAC channel address pins A0 A2 The DAC outputs are updated on reception of new data into the DAC registers All the outputs may be updated simulta neously by taking the LDAC input low Each DAC output is buffered with a gain of two amplifier into which an external DAC offset voltage can be inserted via the DUTGNDx pins The AD7841 is available in a 44 lead MQFP package FUNCTIONAL BLOCK DIAGRAM Vrer t Vngr C2 Vcc Vss Vpp AB AB AD7841 14 ADDRESS DECODE GND Vrer Vrer GH GH REV B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of
10. GND As DAC G and DAC H input codes vary from 000 000 to 111 111 VourG and VourH vary from 10 V to 10 V with respect to Device GND Device GND is also connected to DUTGND When the AD7841 is cleared Vou 1G and VourtH are cleared to 0 V with respect to Device GND Programmable Reference Generation for the AD7841 in an ATE Application The AD7841 is particularly suited for use in an automated test environment The reference input for the AD7841 octal 14 bit DAC requires three differential references for the eight DACs Programmable references may be a requirement in some ATE applications as the offset and gain errors at the output of a DAC can be adjusted by varying the voltages on the reference pins of the DAC To trim offset errors the DAC is loaded with the digital code 000 000 and the voltage on the Vggg pin is adjusted until the desired negative output voltage is obtained To trim out gain errors first the offset error is trimmed Then the DAC is loaded with the code 111 111 and the voltage on the Vggg pin is adjusted until the desired full scale voltage minus one LSB is obtained It is not uncommon in ATE design to have other circuitry at the output of the AD7841 that can have offset and gain errors of up to say 300 mV These offset and gain errors can be easily removed by adjusting the reference voltages of the AD7841 The AD7841 uses nominal reference values of 5 V to achieve an output span of 10 V Since th
11. ansferred from the external bus to the input register of each DAC on a per channel basis Bringing the CLR line low switches all the signal outputs Voy rA to VoutH to the voltage level on the relevant DUTGND pin When the CLR signal is brought back high the output voltages from the DACs will reflect the data stored in the relevant DAC registers Data Loading to the AD7841 Data is loaded into the AD7841 in straight parallel 14 bit wide words The DAC output voltages VoyrA VourH are updated to reflect new data in the DAC registers The actual input register being written to is determined by the logic levels present on the device s address lines as shown in Table I Table I Address Line Truth Table gt N z gt DAC Selected INPUT REG A DAC A INPUT REG B DAC B INPUT REG C DAC C INPUT REG D DAC D INPUT REG E DAC E INPUT REG F DAC F INPUT REG G DAC G INPUT REG H DAC H e SS OOOO pr OOrrF OO r OroOorOoOro REV B Typical Performance Characteristics AD 7841 Vpp 15V Vss 15V Vrer 5V L VnEr 5V o o a a m 7 5 4 I a a a e 9 Q T g A ui i u z Z Vpp 15V z Vss 15V Vrer 5V Vrer 5V Ta 25 C 1 1 0 2048 4096 6144 8192 10240 12288 14336 16384 0 2048 4096 6144 8192 10240 12288 14336 16384 40 20 0 20 40 60 80 100 CODE
12. d output range Output amplifier requires 2 5 V of head room at the bottom and top ends of the transfer for function At 12 V supplies it is recommended to restrict the reference range to 4 V Specifications subject to change without notice REV B AC PERFORMANCE CHARACTERISTICS AD7841 These characteristics are included for Design Guidance and are not subject to production testing A amp B Parameter Versions Unit Test Conditions Comments DYNAMIC PERFORMANCE Output Voltage Settling Time 31 us typ Full Scale Change to 1 2 LSB DAC Latch Contents Alternately Loaded with All 0s and All 1s Slew Rate 0 7 V us typ Digital to Analog Glitch Impulse 230 nV s typ Measured with Vggg 5 V Vggg 5 V DAC Latch Alternately Loaded with 1FFF Hex and 2000 Hex Not Dependent on Load Conditions Channel to Channel Isolation 99 dB typ See Terminology DAC to DAC Crosstalk 40 nV s typ See Terminology Digital Crosstalk 0 2 nV s typ Feedthrough to DAC Output Under Test Due to Change in Digital Input Code to Another Converter Digital Feedthrough 0 1 nV s typ Effect of Input Bus Activity on DAC Output Under Test Output Noise Spectral Density 1 kHz 200 nV VHz typ All 1s Loaded to DAC Vggg Vggg 0 V Specifications subject to change without notice TIMING SPECIFICATIONS 2 veo 5 v 5 Vop 15 V 10 Vss 15 V 10 GND DUTEND 0 V Parameter Limit at Tmn Tmax Unit Description
13. data in their DAC registers 30 31 Verer GH Vgge GH Reference Inputs for DACs G and H These reference voltages are referred to GND 33 DUTGND_GH Device Sense Ground for DACs G and H VoyrG and VourH are referenced to the voltage applied to this pin 36 DUTGND_EF Device Sense Ground for DACs E and F VoyrE and VourF are referenced to the voltage applied to this pin 39 Vagge CDEF Reference Inputs for DACs C D E and F These reference voltages are referred to GND 40 Vgge 2 CDEF Reference Inputs for DACs C D E and F These reference voltages are referred to GND 42 DUTGND CD Device Sense Ground for DACs C and D VourC and VourD are referenced to the voltage applied to this pin REV B 5 AD7841 TERMINOLOGY Relative Accuracy Relative accuracy or endpoint linearity is a measure of the max imum deviation from a straight line passing through the endpoints of the DAC transfer function It is measured after adjusting for zero scale error and full scale error and is expressed in Least Significant Bits Differential Nonlinearity Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes A specified differential nonlinearity of 1 LSB maximum ensures monotonicity DC Crosstalk Although the common input reference voltage signals are inter nally buffered small IR drops in the individual DAC reference inputs across the die can mean that an update to one cha
14. e AD7841 has a gain of two from the reference inputs to the DAC output adjusting the reference voltages by 150 mV will adjust the DAC offset and gain by 300 mV There are a number of suitable 8 and 10 bit DACs available that would be suitable to drive the reference inputs of the AD7841 such as the AD7804 a quad 10 bit digital to analog converter with serial load capabilities The voltage output from this DAC is in the form of Vgias Vswinc and rail to rail operation is achievable The voltage reference for this DAC can be inter nally generated or provided externally This DAC also contains an 8 bit SUB DAC which can be used to shift the complete trans fer function of each DAC around the Vpyas point This can be used as a fine trim on the output voltage In this application two AD7804s are required to provide programmable reference capabil ity for all eight DACs One AD7804 is used to drive the Vggg pins and the second package used to drive the Vggr pins Another suitable DAC for providing programmable reference capability is the AD8803 This is an octal 8 bit TRIMDAC and provides independent control of both the top and bottom ends of the TRIMDAC This is helpful in maximizing the reso lution of devices with a limited allowable voltage control range 11 AD7841 The AD8803 has an output voltage range of GND to Vpp 0 V provide a positive output voltage and then to level shift that ana to 5 V To trim the Vpgr input th
15. e appropriate trim range log voltage to the required negative range Alternatively these on the AD8803 DAC can be set using the Vggg and Vgggg pins DACs can be operated with supplies of 0 V and 5 V with the allowing 8 bits of resolution between the two points This will Vpp pin connected to 0 V and the GND pin connected to 5 V allow the Vggg pin to be adjusted to remove gain errors Now these can be used to provide the negative reference volt To trim the Vggr voltage some method of providing a trim ages for the Vrer inputs on the AD7841 However the digital voltage in the required negative voltage range is required Neither signals driving the DACs need to be level shifted from the 0 V the AD7804 or the AD8803 can provide this range in normal to 5 V range to the 5 V to 0 V range Figure 15 shows a operation as their output range is 0 V to 5 V There are two typical application circuit to provide programmable reference methods of producing this negative voltage One method is to capabilities for the AD7841 ADDR BUS DAC AO A1 A2 ADDR DECODER 8 10 BIT Vpp Vrer AB VoutA LOGIC LEVEL AD7841 CONTROLLER SHIFT 8 10 BIT DAC DATA BUS ADDITIONAL PINS OMITTED FOR CLARITY Figure 13 Programmable Reference Generation for the AD7841 12 REV B AD7841 OUTLINE DIMENSIONS SEATING PLANE TOP VIEW PINS DOWN COPLANARITY 0 80 BSC LEAD WIDTH VIEW A LEAD PITCH ROTATED 90
16. ence between the supply voltages reaches 10 V the internal power on circuitry opens G and G and closes G4 and Gg configuring the output stage as shown in Figure 9 DUTGND Figure 9 Output Stage Powering Up with CLR High When Vpp gt 7Vand Vss lt 3V AD7841 DUTGND Voltage Range During power on the Vour pins of the AD7841 are connected to the relevant DUTGND pins via G and the 14 KQ thin film resistor The DUTGND potential must obey the max ratings at all times Thus the voltage at DUTGND must always be within the range Vss 0 3 V Vpp 0 3 V However in order that the voltages at the Vour pins of the AD7841 stay within 2 V of the relevant DUTGND potential during power on the voltage applied to DUTGND should also be kept within the range GND 2 V GND 2 V Once the AD7841 has powered on and the on chip amplifiers have settled any voltage that is now applied to the DUTGND pin is subtracted from the DAC output which has been gained up by a factor of two Thus for specified operation the maximum voltage that can be applied to the DUTGND pin increases to the maximum allowable 2 Vggg voltage and the minimum volt age that can be applied to DUTGND is the minimum 2 Vggg voltage After the AD7841 has fully powered on the outputs can track any DUTGND voltage within this minimum maxi mum range Power Supply Sequencing When operating the AD7841 it is important that ground be connected at all times to avoid high cur
17. igital input code to the other converter is defined as the digital crosstalk and is specified in nV secs Digital Feedthrough When the device is not selected high frequency logic activity on the device s digital inputs can be capacitively coupled both across and through the device to show up as noise on the Vour pins This noise is digital feedthrough DC Output Impedance This is the effective output source resistance It is dominated by package lead resistance Full Scale Error This is the error in DAC output voltage when all 1s are loaded into the DAC latch Ideally the output voltage with all 1s loaded into the DAC latch should be 2 Vpgr 1 LSB Zero Scale Error Zero scale error is the error in the DAC output voltage when all Os are loaded into the DAC latch Ideally the output voltage with all Os in the DAC latch should be equal to 2 Vggg Zero scale error is mainly due to offsets in the output amplifier Gain Error Gain Error is defined as Full Scale Error Zero Scale Error GENERAL DESCRIPTION DAC Architecture General Each channel consists of a straight 14 bit R 2R voltage mode DAC The full scale output voltage range is equal to twice the reference span of Vggg Vggg The DAC coding is straight binary all Os produces an output of 2 Vggg all 1s produces an output of 2 Vggg 1 LSB The analog output voltage of each DAC channel reflects the contents of its own DAC register Data is tr
18. nnel can produce a dc output change in one or another of the chan nel outputs The eight DAC outputs are buffered by op amps that share common Vpp and Vss power supplies If the dc load current changes in one channel due to an update this can result in a further dc change in one or another of the channel outputs This effect is most obvious at high load currents and reduces as the load currents are reduced With high impedance loads the effect is virtually impossible to measure Output Voltage Settling Time This is the amount of time it takes for the output to settle to a specified level for a full scale input change Digital to Analog Glitch Impulse This is the amount of charge injected into the analog output when the inputs change state It is specified as the area of the glitch in nV secs It is measured with Vggg 5 V and Vrer 5 V and the digital inputs toggled between IFFFH and 2000H Channel to Channel Isolation Channel to channel isolation refers to the proportion of input signal from one DAC s reference input that appears at the out put of another DAC It is expressed in dBs DAC to DAC Crosstalk DAC to DAC crosstalk is defined as the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog O P change at another converter It is specified in nV secs Digital Crosstalk The glitch impulse transferred to the output of one converter due to a change in d
19. o control the power on voltage present at Vopr On power up G and G are also used in conjunction with the CLR input to set Voy to the user defined voltage present at the DUTGND pin When CLR is taken back high the DAC outputs reflect the data in the DAC registers DUTGND Figure 4 Block Diagram of AD7841 Output Stage REV B AD7841 Power On with CLR Low The output stage of the AD7841 has been designed to allow output stability during power on If CLR is kept low during power on then just after power is applied to the AD7841 the situation is as depicted in Figure 5 G G and Gy are open while G5 G and G are closed G4 DUTGND Figure 5 Output Stage with Vpp lt 7 V or Vss gt 3 V CLR Low Vout is kept within a few hundred millivolts of DUTGND via G and a 14 kQ resistor This thin film resistor is connected in parallel with the gain resistors of the output amplifier The output amplifier is connected as a unity gain buffer via G3 and the DUTGND voltage is applied to the buffer input via G The amplifier s output is thus at the same voltage as the DUTGND pin The output stage remains configured as in Figure 5 until the voltage at Vpp exceeds 7 V and Vss is more negative than 3 V By now the output amplifier has enough headroom to handle signals at its input and has also had time to settle The internal power on circuitry opens Gs and Gs and closes G4 and Gs This situation is shown in Figure 6 Now the
20. output ampli fier is configured in its noise gain configuration via G and Gy The DUTGND voltage is still connected to the noninverting input via G and this voltage appears at Vour G4 DUTGND Figure 6 Output Stage with Vpp gt 7 V and Vss lt 3 V CLR Low Vout has been disconnected from the DUTGND pin by the opening of Gs but will track the voltage present at DUTGND via the configuration shown in Figure 6 When CLR is taken back high the output stage is configured as shown in Figure 7 The internal control logic closes G and opens G3 The output amr fier is connected in a noninverting gain of two configuration The voltage that appears on the Vour pins is determined by the data present in the DAC registers REV B DUTGND Figure 7 Output Stage After CLR Is Taken High Power On with CLR High If CLR is high on the application of power to the device the output stages of the AD7841 are configured as in Figure 8 while Vpp is less than 7 V and Vss is more positive than 3 V G is closed and G is open thereby connecting the output of the DAC to the input of its output amplifier G4 and G are closed while G4 and Gg are open thus connecting the output amplifier as a unity gain buffer Vour is connected to DUTGND via G through a 14 KQ resistor until Vpp exceeds 7 V and Vss is more negative than 3 V DUTGND Figure 8 Output Stage Powering Up with CLR High While Vop lt 7Vor Vss gt 3 V When the differ
21. rent states The recom mended power up sequence is Vpp Vss followed by Vec If Vec can exceed Vpp on power up the diode scheme shown in the absolute maximum ratings section will ensure protection The reference inputs and digital inputs should be powered up last Should the references exceed Vpp Vss on power up current limiting resistors should be inserted in series with the reference inputs to limit the current to 20 mA Logic inputs should not be applied before Vcc Current limiting resistors 470 Q in series with the logic inputs should be inserted if these inputs come up before Vec MICROPROCESSOR INTERFACING Interfacing the AD7841 16 Bit Interface The AD7841 can be interfaced to a variety of 16 bit micro controllers or DSP processors Figure 10 shows the AD7841 interfaced to a generic 16 bit microcontroller DSP processor The lower address lines from the processor are connected to A0 Al and A2 on the AD7841 as shown The upper address lines are decoded to provide a chip select signal or an LDAC signal for the AD7841 The fast interface timing of the AD7841 allows direct interface to a wide variety of microcontrollers and DSPs as shown in Figure 10 10 wCONTROLLER DSP PROCESSOR D13 DATA BUS Do UPPER BITS OF O ADDRESS DECODE AD7841 ADDRESS BUS O ADDITIONAL PINS OMITTED FOR CLARITY Figure 10 Parallel Interface APPLICATIONS Power Supply Bypassing and Grounding In any circuit where accurac
22. s A and B These reference voltages are referred to GND 5 38 Vpp Positive Analog Power Supply 15 V 10 for specified performance 6 Vss Negative Analog Power Supply 15 V 10 for specified performance 7 LDAC Load DAC Logic Input active low When this logic input is taken low the contents of the registers are transferred to their respective DAC registers LDAC can be tied permanently low enabling the outputs to be updated on the rising edge of WR 8 9 10 A2 Al AO Address inputs AO Al and A2 are decoded to select one of the eight input registers for a data transfer 11 CS Level Triggered Chip Select Input active low The device is selected when this input is low 12 WR Level Triggered Write Input active low used in conjunction with CS to write data to the AD7841 data registers Data is latched into the selected input register on the rising edge of WR 13 Voc Logic Power Supply 5 V 5 14 GND Ground 15 28 DB0 DBI2 Parallel Data Inputs The AD7841 can accept a straight 14 bit parallel word on DBO to DB13 where DB13 is the MSB and DBO is the LSB 29 CLR Asynchronous Clear Input level sensitive active low When this input is low all analog outputs are switched to the externally set potential on the relevant DUTGND pin The con tents of input registers and DAC registers A to H are not affected when the CLR pin is taken low When CLR is brought back high the DAC outputs revert to their original outputs as determined by the
23. to each other This reduces the effects of feedthrough through the board A micro strip technique is by far the best but not always possible with a double sided board In this technique the component side of the board is dedicated to ground plane while signal traces are placed on the solder side REV B AD7841 The AD7841 should have ample supply bypassing located as close to the package as possible ideally right up against the device Figure 11 shows the recommended capacitor values of 10 uF in parallel with 0 1 uF on each of the supplies The 10 uF capacitors are the tantalum bead type The 0 1 uF capacitor should have low Effective Series Resistance ESR and Effective Series Inductance ESD such as the common ceramic types which provide a low impedance path to ground at high frequen cies to handle transient currents due to internal logic switching Figure 11 Recommended Decoupling Scheme for AD7841 Automated Test Equipment The AD7841 is particularly suited for use in an automated test environment Figure 12 shows the AD7841 providing the neces sary voltages for the pin driver and the window comparator in a typical ATE pin electronics configuration AD588s are used to provide reference voltages for the AD7841 In the configuration shown the AD588s are configured so that the voltage at Pin 1 is 5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the voltage at Pin 9 15V 15V VoFFSET Q
24. ty 15 ns min Address to WR Setup Time ty 0 ns min Address to WR Hold Time t 50 ns min CS Pulsewidth Low ty 50 ns min WR Pulsewidth Low ts 0 ns min CS to WR Setup Time te 0 ns min WR to CS Hold Time t 20 ns min Data Setup Time tg 0 ns min Data Hold Time to 31 us typ Settling Time tio 300 ns max CLR Pulse Activation Time tu 50 ns min LDAC Pulsewidth Low NOTES AII input signals are specified with tr tf 5 ns 10 to 90 of 5 V and timed from a voltage level of 1 6 V Rise and fall times should be no longer than 50 ns Specifications subject to change without notice AO A1 A2 REV B tio Figure 1 Timing Diagram AD7841 ABSOLUTE MAXIMUM RATINGS T4 25 C unless otherwise noted Vee to GND vti eek teo 0 3 V 7 V or Vpp 0 3 V Whichever Is Lower Vpp TO GN DD i eoo REN 0 3 V 17 V Vesto GND 4 eed rne ER m eh A 0 3 V 17 V Digital Inputs to GND 0 3 V Vcc 0 3 V Vagge to Veer oo eee 0 3 V 18 V Vrer to GND Vagg to GND DUTGND to GND Vout A H to GND Operating Temperature Range Industrial A Version Storage Temperature Range Vss 0 3 V Vpp 0 3 V Vss 0 3 V Vpp 0 3 V Vss 0 3 V Vpp 0 3 V Vss 0 3 V Vpp 0 3 V 40 C to 85 C 65 C to 150 C Junction Temperature MQEFP Package Power Dissipation Oja Thermal Impedance 005 95 C W Lead Temperature
25. y is important careful consideration of the power supply and ground return layout helps to ensure the rated performance The printed circuit board on which the AD7841 is mounted should be designed such that the analog and digital sections are separated and confined to certain areas of the board This facilitates the use of ground planes that can be easily separated A minimum etch technique is generally best for ground planes as it gives the best shielding Digital and ana log ground planes should be joined at only one place The GND pin of the AD7841 should be connected to the AGND of the system If the AD7841 is in a system where multiple devices require an AGND to DGND connection the connection should be made at one point only a star ground point that should be established as close as possible to the AD7841 Digital lines running under the device should be avoided as these will couple noise onto the die The analog ground plane should be allowed to run under the AD7841 to avoid noise coupling The power supply lines of the AD7841 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line Fast switching signals like clocks should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the analog inputs Avoid crossover of digital and analog signals Traces on opposite sides of the board should run at right angles

ANALOG DEVICES AD7841 handbook

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