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ANALOG DEVICES AD1980 handbook3

1. 1Ch Record Gain X X X LIM3 LIM2 LIMI LIMO IMRM X X X RIM RIM2 RIMI RIMO 8000h For AC 97 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set Bit D7 has no effect registers not shown and bits containing an X are assumed to be reserved Refer to Table VI for examples RIM 3 0 Right Input Mixer Gain Control Each LSB represents 1 5 dB 0000 0 dB and the gain range is 0 dB to 22 5 dB RM Right Channel Mute Once enabled by the MSPLT bit in Register 76h this bit mutes the right channel separately from the IM bit Otherwise this bit will always read 0 and will have no effect when set to 1 LIM 3 0 Left Input Mixer Gain Control Each LSB represents 1 5 dB 0000 0 dB and the gain range is 0 dB to 22 5 dB IM Input Mute When this bit is set to 1 both the left and the right channels are muted unless the MSPLT bit in Register 76h is set to 1 in which case this mute bit will affect only the left channel Table VI Settings for Record Gain Register Control Bits Reg 76h Record Gain 1Ch Left Channel Input Mixer D 11 8 Right Channel Input Mixer D 3 0 MSPLT D15 WRITE READBACK Function D7 WRITE READBACK Function 0 0 1111 1111 22 5 dB Gain x 1111 1111 2
2. This read write Sample Rate Control Register contains 16 bit unsigned value representing the rate of operation in Hz This register sets the sample rate for the surround DAC This register s reset default is to be locked to the PCM front DAC sample rate register 2 Ch To unlock this register Bit SRU in Register 76h must be asserted SRS 15 0 Sample Rate The sampling frequency range is from 7 kHz 1B58h to 48 kHz BB80h in 1 Hz increments If zero is written to VRA bit then the sample rate is reset to 48 kHz PCM LFE and CENTER DAC Rate Register Index 30h No Name D15 D14 D12 D11 D10 D9 D8 D7 D6 05 D4 D3 D2 00 Default 30h LFE SRCLI5 SRCL14 SRCL13 SRCL12 SRCL11 SRCL10 SRCL9 SRCL8 SRCL7 SRCL6 SRCL5 SRCLA SRCL3 SRCL2 SRCL1 SRCL0 BB80h C DAC Rate This read write sample rate control register contains 16 bit unsigned value representing the rate of operation in Hz This register sets the sample rate for the LFE DAC and Center DAC This register s reset default is to be locked to the PCM Front DAC sample rate register 2 Ch To unlock the register bit SRU in Register 76h must be asserted SRCL 15 0 Sample Rate The sampling frequency range is from 7 kHz 1B58h to 48 kHz BB80h in 1 Hz increments If zero is written to VRA then the sample rate is reset to 48 kHz PCM ADC Rate Register
3. 0 LDAC SDAC CDAC DSA1 DSAO X 5 DRA VRA X3C7h The extended audio ID register identifies which extended audio features are supported A nonzero extended audio ID value indicates one or more of the extended audio features are supported All registers not shown and bits containing an X are assumed to be reserved VRA Variable Rate PCM Audio Support Read Only This bit returns a 1 when read to indicate that the Variable Rate PCM Audio is supported DRA Double Rate Audio Read Only This bit returns a 1 when read to indicate that the optional Double Rate RCM Audio is supported for POM L and PCM R SPDIF SPDIF Support Read Only This bit returns a 1 when read to indicate that the SPDIF transmitter is supported IEC958 This bit is also used to validate that the SPDIF transmitter output is actually enabled The SPDIF bit is only allowed to be set high if the SPDIF pin 48 is pulled down at power up enabling the codec transmitter logic If the SPDIF pin is floating or pulled high at power up the transmitter logic is disabled and therefore this bit returns a low indicating that the SPDIF transmitter is not available This bit must always be read back to verify that the SPDIF transmitter is actually enabled DSA 1 0 DAC Slot Assignments Read Write Reset Default 00 00 DACs 1 2 4 DACs 3
4. Unit TCASE Case Temperature in Power Supplies PD Power Dissipation in W Digital DVpp 0 5 43 6 V Thermal Resistance Junction to Ambient Analog AVpp 0 3 6 0 V Thermal Resistance Junction to Case Input Current Except Supply Pins 10 0 mA Analog Input Voltage Signal Pins 0 3 AVpp 0 3 V Digital Input Voltage Signal Pins 0 3 DVpp 0 3 V Package 6j Ambient Temperature Operating 0 70 C LQFP 50 1 C W 17 8 C W Storage Temperature 65 150 measurements per EIA JESD51 with 252 Stresses greater than those listed under Absolute Maximum Ratings may cause test board per EIA JESD51 7 permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ORDERING GUIDE Model Temperature Range Package Description Package Option AD1980JST 0 C to 70 C 48 Lead LQFP ST 48 ST Low Profile Quad Flatpack CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the WARN NG S AD1980 features proprietary ESD protection circuitry permanent damage may occur on devices
5. subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE PIN CONFIGURATION 48 Lead LQFP A 5 5 amp 3 E E 5 9 8 e GE 225 Bz 55 2 929 29 2 48 144 43 42 37 36 LINE OUT R FRONT R 35 LINE OUT L FRONT 1 AVpp4 AVss4 32 LFE_OUT AD1980 31 CENTER_OUT TOP VIEW Not to Scale AFILT2 29 AFILT1 28 VREFouT VREF 26 551 25 AVppt NC NOCONNECT 2 3 45 5 8255 5 5825 w 3 7 0 2 2 2 3 Ir o 4 lt 2 z 9 zz REV 0 l T AD1980 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic I O Function DIGITAL INPUT OUTPUT 2 XTL IN I Crystal Input 24 576 MHz or External Clock In 24 576 MHz 14 31818 MHz or 48000 MHZ 3 XTL OUT Crystal Output 5 SDATA OUT I AC Link Serial Data Output AD1980 Input Stream 6 BIT CLK AC Link Bit Clock 12 288 MHz serial data clock Input pin for Secondary mode only 8 SDATA IN AC Link Serial Data Input AD1980 Output Stream 10 SYNC I AC Link Frame Sync 11 RESET I AC Link Reset AD1980 Master H W Reset 48 SPDIF O SPDIF Output CHIP SELECTS CLOCK STRAPPING 45 IDO I Chip Select Input 0 Active Low This pin can also be
6. 76th Misc DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIXO SPRD 2CMIC LOSEL SRU VREFH VREFD 90 0000 Control Bits MBG 1 0 MIC Boost Gain Select Register These two bits allow changing the MIC preamp gain from the nominal 20 dB gain Both MICI MIC2 and MIC2 preamps will be set to the same selected gain Note that this gain takes effect only while Bit D6 M20 on the MIC volume register 0Eh is set to 1 otherwise the MIC boost block has a gain of 0 dB 00 20 dB gain reset default 01 10 dB gain 10 30 dB gain 11 reserved VREFD Vngrovr Disable Disables placing it into High Z out mode Note that this bit overrides the VREFH bit selection see below 0 Vrerour pin is driven by the internal reference reset default 1 Vngrovr pin is placed into High Z out mode VREFH Vngrovr High Changes Vgggour from 2 25 V to 3 70 V for PC2001 compliant MIC bias applications 0 pin is set to 2 25 V output reset default 1 pin is set to 3 70 V output SRU Sample Rate Unlock Controls DAC sample rate locking 0 All DAC Sample Rates are locked to the front sample rate reset default 1 DAC sample rates can be set independently for front surround and LFE LOSEL LINE OUT Amplifiers Input Select This bit allows the LINE OUT output amplifiers to be driven by the mixer or the surround D
7. INTS Interrupt Mode Select This bit selects the JS interrupt implementation path 0 Bit 0 SLOT 12 modem interrupt reset default 1 Slot 6 Valid Bit MIC ADC interrupt LBKS 1 0 Loop Back Selection These bits select the internal digital loop back path when LPBK bit is active see Register 20h 00 Loop back through the front DACs reset default 01 Loop back through the surround DACs 10 Reserved 11 Loop back through the center and LFE DACs Center DAC loops back from the ADC left channel the LFE DAC from the ADC right channel CHEN Chain Enable This bit enables chaining of a slave codec SDATA_IN stream into the IDO pin Pin 45 0 Disable chaining reset default 1 Enable chaining into IDO pin DRF DAC Request Force This allows the AD1980 to synchronize DAC requests with the AD1981A B 0 Normal DAC requesting sequence reset default 1 Synchronize to AD1981A B DAC requests REGM3 Slave 3 Codec Register Mask REGMO Master Codec Register Mask Slave 1 Codec Register Mask REGM2 Slave 2 Codec Register Mask SLOTI16 Enable 16 Bit Slot Mode SLOT16 makes all ac link slots 16 bits in length formatted into 16 slots This is a preferred mode for DSP serial port interfacing 26 REV 0 AD1980 Miscellaneous Control Bit Register Index 76h Reg De No Name 015 014 D13 12 D8 D7 Ds D4 D2 Di DO fault
8. 0 The MSPLT bit enables separate mute bits for the left and right AD1980 Reset Register Index 00h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Di D0 Default 00h Reset X SE4 SE3 SE2 SEI SEO ID9 ID8 ID7 ID6 ID5 IDA ID3 ID2 IDO 0090h NOTES All registers not shown and bits containing an X are assumed to be reserved Writing any value to this register performs a register reset which causes all registers to revert to their default values except 74h which forces the serial configuration Reading this register returns the ID code of the part and a code for the type of 3D Stereo Enhancement ID 9 0 Identify Capability The ID decodes the capabilities of AD1980 based on the following Bit 1 Function AD1980 IDO Dedicated Mic PCM In Channel 0 Modem Line Codec Support 0 ID2 Bass and Treble Control 0 ID3 Simulated Stereo Mono to Stereo 0 1 4 Headphone Out Support 1 ID5 Loudness Bass Boost Support 0 ID6 18 Bit DAC Resolution 0 ID7 20 Bit DAC Resolution 1 ID8 18 Bit ADC Resolution 0 ID9 20 Bit ADC Resolution 0 SE 4 0 Stereo Enhancement The AD1980 does not provide hardware 3D stereo enhancement All bits are zeros Master Volume Register Index 02h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8
9. Output Leakage Current 10 10 uA POWER SUPPLY Power Supply Range Analog AVpp 4 75 5 25 V Power Supply Range Digital DVpp 3 15 3 45 V Power Dissipation 5 V 3 3 V 563 mW Analog Supply Current 5 V AVpp 70 mA Digital Supply Current 3 3 DVpp 53 mA Power Supply Rejection 100 mV p p Signal 4 1 kHz 40 dB At Both Analog and Digital Supply Pins Both ADCs and DACs Guaranteed but not tested Specifications subject to change without notice REV 0 Eg AD1980 Parameter PR K I PR 6 0 DVpp Typ AVpp Typ Unit POWER DOWN STATES Fully Active 000 000 0000 53 70 mA ADC 000 000 0001 44 66 mA FRONT DAC 000 000 0010 46 61 mA SURROUND DAC 010 000 0000 46 61 mA CENTER LFE DAC 101 000 0000 46 61 mA ADC ALL DACs 111 000 0011 12 33 mA Mixer 000 000 0100 52 44 mA ADC Mixer 000 000 0101 45 39 mA ALL DACs Mixer 111 000 0110 31 14 mA ADC ALL DACs Mixer 111 000 0111 12 8 mA Standby 111 011 1111 0 0 mA Headphone Standby 000 100 0000 52 65 mA NOTES IPR bits are controlled in Reg 2Ah and 26h Values presented with Vpgrout loaded Specifications subject to change without notice Parameter Min Typ Max Unit CLOCK SPECIFICATIONS Input Clock Frequency XTAL Mode or Clock Oscillator 24 576 MHz Input Clock Frequency Reference Clock Mode 14 31818 MHz Input Clock Frequency USB Clock Mode 48 000 MHz Recommended Clock Duty Cycle 40 50 60 Guaranteed but not tested
10. 0 1 2 02 V S T NI 32
11. 00 1111 22 5 dB Gain x 00 1111 00 1111 22 5 dB Gain 0 0 01 1111 01 1111 46 5 dB Gain 01 1111 011111 46 5 0 0 Ixxxxx 01 1111 46 5 dB Gain 1 011111 46 5 0 1 XX XX XXXX dB Gain Muted X XX XXXX XX XXXX dB Gain Muted 1 0 Ixxxxx 01 1111 46 5 dB Gain 1 XX XXXX XX XXXX dB Gain only Right Muted 1 1 XX XXXX XX XXXX dB Gain Left only Muted 0 XX XXXX XX XXXX 46 5 dB Gain 1 1 XX XXXX XX XXXX dB Gain Left Muted 1 XX XXXX XX XXXX dB Gain Right Muted For AC 97 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set Bit D7 has no effect x in the above table is don t care Mono Volume Register Index 06h Reg Name D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 Di DO Default 06h Mono Volume MVM X X X X X X X X X MV5 MV4 MV2 MV1 MVO 8000h Refer to Table II for examples This register controls the Mono output volume and mute bit The volume register contains five bits generating 32 volume levels with 31 steps of 1 5 dB each Because 97 defines 6 bit volume registers to maintain compatibility whenever the D5 bit is set to 1 their respective lower five vol ume
12. Index 32h No Name D15 D14 D13 012 D11 D10 09 D8 D7 D6 D5 D4 D3 D2 D1 Default 32h POM L R 5 15 SRAI4 SRAI3 SRAI2 5 11 SRAIO SRA9 SRA8 SRA7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRA0 BB80h ADC Rate This read write sample rate control register contains 16 bit unsigned value representing the rate of operation in Hz SRA 15 0 Sample Rate The sampling frequency range is from 7 kHz 1B58h to 48 kHz BB80h 1 Hz increments If zero is written to VRA then the sample rate is reset to 48 kHz 20 REV 0 AD1980 CENTER LFE Volume Control Register Index 36h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 36h Center LFE LM X LFE5 LFE4 LFE3 LFE2 LFE1 LFEO CM X CNT5 CNT4 CNT3 CNT2 CNT1 CNTO 8080h Volume All registers not shown and bits containing an X are assumed to be reserved Refer to Table VII for examples This register controls the LFE output volume and mute bit The volume registers contain five bit generating 32 volume levels with 31 steps of 1 5 dB each If MSPLT is not set Bit D7 has no effect Because 97 defines 6 bit volume registers to maintain compatibility whenever the D5 or D13 bit is set to 1 its respective lower five volume bits are automati cally set to 1 by
13. Sample Rate SPSR 1 0 00 Transmit Sample Rate 44 1 kHz SPSR 1 0 01 Reserved SPSR 1 0 10 Transmit Sample Rate 48 kHz default SPSR 1 0 11 Not supported V Validity This bit affects the Validity flag Bit 28 transmitted in each SPDIF L R subframe and enables the SPDIF transmitter to maintain connection during error or mute conditions 1 Each SPDIF subframe L R has Bit 28 set to 1 This tags both samples as invalid V 0 Each SPDIF subframe L R has Bit 28 set to 0 for valid data and 1 for invalid data error condition Note that when V 0 asserting the VFORCE bit D15 in Register 2Ah Ext d Audio Stat Ctrl will force the Va lidity flag low marking both samples as valid 22 REV 0 AD1980 EQ Control Register Index 60h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 60h EQ CTRL EQM X X X X X X X SYM CHS 5 BCA4 2 BCA1 BCAO 8080h All registers not shown and bits containing an X are assumed to be reserved Register 60h is a read write register that controls the Equalizer functionality and data setup This register also contains the Biquad and Coefficient Address pointer which is used in conjunction with the EQ Data Register 78h to set up the equalizer coefficients The reset default disables the Equali
14. and the CFDO bit is the LSB Jack Sense Audio Interrupt Status Register Index 72h No Name D15 D14 D13 D12 Dil D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 72h Jack 151 181 150 JS JS JS Js Jso Js1 180 151 150 151 150 151 180 0000h Sense SPRD DMX DMX MT2 MT1 TMR TMR MD MD ST ST INT INT All register bits are read write except for JSOST and JS1ST which are read only JSOINT Indicates Pin 80 has generated an interrupt Remains set until the software services JSO interrupt i e JSO ISR should clear this bit by writing a 0 to it Note that the interrupt to the system is actually an OR combination of this bit and JSIINT Also note that the actual interrupt implementation is selected by the INTS bit Register 76h It is also possible to generate a software system interrupt by writing a 1 to this bit JSIINT Indicates Pin JS1 has generated an interrupt Remains set until the software services JS1 interrupt i e 751 ISR should clear this bit by writing a 0 to it See the JSOINT description for additional details JSOST JSO STATE This bit always reports the logic state of JSO pin JSIST JS1 STATE This bit always reports the logic state of JS1 pin JS0MD JS0 Mode This bit selects the operation mode for the 150 pin 0 Jack Sense Mode reset default
15. bits are automatically set to 1 by the codec logic On readback all lower five bits will read 1s whenever this bit is set to 1 registers not shown and bits containing an X are assumed to be reserved MV 5 0 Mono Volume Control The least significant bit represents 1 5 dB This register controls the output from 0 dB to a maximum attenuation of 46 5 dB MVM Mono Volume Mute When this bit is set to 1 the channel is muted Table II Volume Settings for Mono Control Bits D 4 0 for Mono 06h D15 WRITE READBACK Function 0 0 0000 0 0000 0 dB Gain 0 0 1111 0 1111 22 5 dB Gain 0 11111 11111 46 5 dB Gain 1 X XXXX X XXXX dB Gain Muted x in the above table is a wild card and has no effect on the value REV 0 11 AD1980 Phone in Volume Register Index 0Ch Reg No Name D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default Phone_in Volume PHM X X X X X X X X X X PHV4 PHV3 PHV2 PHV1 PHVO 8008h All registers not shown and bits containing an X are assumed to be reserved Refer to Table III for examples PHV 4 0 Phone Volume Allows setting the Phone Volume attenuator in 32 volume levels with 31 steps of 1 5 dB each The LSB represents 1 5 dB and the gain range is 12 dB to 34 5 dB The default value is 0 dB with the mute bit enabled PHM Phone Mute
16. interrupt infrastructure In that case S W could poll the interrupt status after initiating a sense cycle and waiting for Sense Cycle Max Delay to determine if an inter rupting event has occurred I4 INTERRUPT STATUS R W This bit provides interrupt status and clear capability 0 Interrupt is Clear 1 Interrupt was Generated Interrupt event is cleared by writing a 1 to this bit The interrupt bit will change regardless of condition of inter rupt enable 10 status An interrupt in the GPI in slot 12 in the AC link will follow this bit change when interrupt enable I0 is unmasked 16 REV 0 AD1980 Power Down Control Status Register Index 26h Reg No Name D15 D14 D13 D12 D11 D10 D D8 D7 DS D4 D3 D2 DO Default 26h Power Down EAPD PR6 PR5 PRA PR2 PRI PRO X X X X DAC ADC NA Control Status The ready bits are read only writing to REF ANL DAC ADC will have no effect These bits indicate the status for the AD1980 subsections If the bit is a 1 then that subsection is ready Ready is defined as the subsection able to perform in its nominal state All registers not shown and bits containing an X are assumed to be reserved ADC ADC Sections Ready to Transmit Data DAC DAC Sections Ready to Transmit Data ANL Analog Amplifiers Attenuators and Mixers Ready REF
17. 1 46 5 dB Gain Not Applicable 1 XX XXXX XX XXXX Muted Muted SPDIF Control Register Index 3Ah Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Default 3Ah SPDIF V X SPSRI SPSRO L CC6 5 4 2 PRE COPY AUD PRO 2000h Control All registers not shown and bits containing an X are assumed to be reserved Register 3Ah is a read write register that controls SPDIF functionality and manages bit fields propagated as channel status or subframe in the V case With the exception of V this register should only be written to when the SPDIF transmitter is disabled SPDIF Bit in Register 2Ah is 0 This ensures that control and status information starts up correctly at the beginning of SPDIF transmission PRO Professional 1 indicates professional use of channel status 0 indicates consumer AUD Non Audio 1 indicates data is non PCM format 0 indicates data is PCM COPY Copyright 1 indicates copyright is asserted 1 indicates copyright is not asserted PRE Pre emphasis 1 indicates filter pre emphasis is 50 us 15 us 0 indicates pre emphasis is none CC 6 0 Category Code Programmed according to IEC standards or as appropriate L Generation Level Programmed according to IEC standards or as appropriate SPSR 1 0 SPDIF Transmit
18. 2 5 dB Gain 0 0 0000 0000 0 dB Gain x 0000 0000 0 dB Gain 0 1 XXXX XXXX dB Gain Muted X XXXX XXXX dB Gain Muted 1 0 1111 1111 22 5 dB Gain 1 XXXX XXXX dB Gain Right Only Muted 1 1 XXXX XXXX dB Gain 0 1111 1111 22 5 dB Gain Left Only Muted 1 1 XXXX dB Gain 1 XXXX XXXX 0 dB Gain Right Muted Left Muted For AC 97 compatibility Bit D7 RM is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set Bit D7 has no effect x is don t care REV 0 15 AD1980 General Purpose Register Index 20h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Default 20h General Purpose X x X X DRSS1 550 X 5 LPBK X X X X X X 0000h This register should be read before writing to generate a mask for only the bit s that need to be changed All registers not shown and bits containing an X are assumed to be reserved LPBK Loopback Control This bit enables the digital internal loopback from the ADC to the Front DAC This feature is normally used for test and troubleshooting 0 No Loopback Default 1 Loopback PCM digital data from ADC output to DAC See LBKS bit in Register 0x74 for changing the loopback path to use the Surround or Center LFE DACs MS MIC Select Selects
19. 4 7 and 8 DACs 5 6 6 and 9 01 DACs1 2 7and8 DACs 3 4 9 DACs 5 6 disabled 10 DACs1 2 6and9 DACs 3 4 disabled DACs 5 6 disabled 11 Reserved CDAC PCM CENTER DAC Support Read Only This bit returns a 1 when read to indicate that PCM center DAC is supported SDAC PCM Surround DAC Support Read Only This bit returns a 1 when read to indicate that PCM surround left and right DACs are supported LDAC PCM LFE DAC Support Read Only This bit returns a 1 when read to indicate that PCM LFE DAC is supported AMAP Slot DAC Mappings Based on Codec ID Read Only This bit returns a 1 when read to indicate that slot DAC mappings based on codec ID are supported REV 1 0 REV 1 0 01 indicates codec is 97 revision 2 2 compliant Read Only ID 1 0 Indicates Codec Configuration Read Only 00 Primary 01 10 11 Secondary 18 REV 0 AD1980 Extended Audio Status and Control Register Index 2Ah Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Di Default 2Ah Extended Audio VFORCE X PRK PRI SPCV X ELDAC ESDAC ECDAC SPSAI SPSAO0 X ESPDIF EDRA EVRA 0 Stat Ctrl The extended audio status and control register is a read write register that provides status and control of the extended audio features All registers not shown and bits containing an X are assumed to be reser
20. ACs The main purpose for this is to allow swapping of the front and surround channels to make better use of the SURR HP OUT output amplifiers This bit should normally be used in tandem with the HPSEL bit see below 0 LINE OUT amplifiers are driven by the mixer outputs reset default 1 LINE OUT amplifiers are driven by the surround DAC outputs 2CMIC 2 Channel MIC Select This bit enables simultaneous recording from MICI and inputs using a stereo microphone array Note that this register works in conjunction with the MS bit in Register 20h 0 MICI or MIC2 determined by MS bit is routed to the record selector s left and right MIC channels as well as to the mixer reset default 1 MICI is routed to the record selector s left MIC channel and is routed to the record selector s right MIC channel Note that in this mode the MS bit should be set low and MICI can still be enabled into the mixer SPRD SPREAD Enable This bit enables spreading of 2 channel media to all six output channels This function is imple mented in the analog section by using the output selector controls line for the center LFE surround and Line out output channels Note that the Jack Sense pins can also be set up to control gate this function depending on the JSSPRD bit see Register 72h 0 No spreading occurs unless activated by the Jack Senses and JSSPRD bits reset default 1 The SPRD selector drives the center and LFE outputs f
21. ANALOG DEVICES FEATURES AC 97 2 3 COMPATIBLE FEATURES 6 DAC Channels for 5 1 Surround S PDIF Output Integrated Stereo Headphone Amplifier Variable Rate Audio Double Rate Audio fs 96 kHz Greater than 90 dB Dynamic Range 20 Bit PCM DACs Line Level Mono Phone Input High Quality CD Input Selectable MIC Input with Preamp AUX and Line In Stereo Inputs External Amplifier Power Down Control Power Management Modes 48 Lead LOFP Package AC 97 SoundMAX Codec AD1980 ENHANCED FEATURES Integrated Parametric Equalizer Stereo MIC Preamp Support Integrated PLL for System Clocking Variable Sample Rate 7 kHz to 96 kHz Jack Sense Auto Topology Switching Software Controlled VREF OUT for MIC Bias Software Enabled Outputs for Jack Sharing Auto Down Mix and Channel Spreading Modes FUNCTIONAL BLOCK DIAGRAM VREFOUT VREF AD1980 MIC PREAMP XTL OUT XTL SPDIF VOLTAGE REFERENCE CODEC CORE PCM L R ADC RATE tc a Te To PCM LFE DAC RATE Q RESET Q SYNC AC 97 INTERFACE G GAIN A ATTENUATION MUTE BITCLK PCM FRONT SDATA_OUT DAC RATE SDATA_IN SURR OUT L EQ COEF STORAGE AC 97 CONTROL REGISTERS REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents
22. AVM X X LAV4 LAV3 LAV2 LAVO AVRM X X RAV4 RAV3 RAV2 RAVI RAVO 8808h 18h PCM Out Vol OM X X LOV4 LOV3 LOV2 LOVI LOVO OMRM X X ROV4 ROV3 ROV2 ROVI 8808h 1Ah Record Select X X X X X LS2 LS1 150 X X X X X RS2 RS1 RSO 0000h 1Ch Record Gain IM X X X LIM3 LIM2 LIMI LIMO X X X RIM2 RIMI RIMO 8000h 20h General Purpose X X X X DRSS1 DRSSO X MS LPBK X X X X X X X 0000h 24h Audio Int 14 X X X 10 X X X X X X X PG3 PG2 PG1 PGO XXXX and Paging 26h Power Down EAPD PR6 PR5 PRA PR3 PR2 PRI PRO X X X X REF ANL ADC Ctrl Stat 28h Ext d Audio ID IDI IDO X X REVO AMAP LDAC SDAC CDAC DSA1 DSA0 X SPDIF DRA VRAS x3C7h 2Ah Ext d Audio VFORCE X PRK PRJ PRI SPCV X ELDAC ESDAC ECDAC SPSAI 8 0 X ESPDIF EDRA EVRA Oxx0h Stat Ctrl 2Ch PCM Front SRFI5 SRF14 SRF13 SRF12 SRF11 5 0 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 SRF3 SRF2 SRF1 SRFO BB80h DAC Rate 2Eh PCM Surr 86815 86814 86513 86812 SRS11 SRS10 5859 SRS8 SRS7 SRS6 5855 5854 SRS3 SRS2 5651 5850 BB80h DAC Rate 30h PCM C LFE SRCLI15 SRCL14 SRCL13 SRCLI2 SRCLI1 SRCLIO SRCL9 SRCL8 SRCL7 SRCL6 SRCLS SRCLA SRCL3 SRCL2 SRCLI SRCLO BB80h DAC Rate 32h PCM 15 8 14 SRA13 5 13 SRA11 SRAIO SRA9 SRA8 SRAT7 SRA6 SRA5 SRA4 SRA3 SRA2 SRA1 SRAO BB80h ADC Rate 36h Center LFE LM X LFE5 LFE4 LFE3 LFE2 LFE1 LFEO X CNT5 CN
23. D7 D6 Ds D3 D2 D1 DO Default 02h Master X 5 LMV4 LMV3 LMV2 LMV1 LMV0 MMRM X RMV5 RMV4 RMV3 RMV2 RMV1 0 8000 Volume NOTES Refer to Table I for examples This register controls the Line Out volume controls for both stereo channels and mute bit Each volume subregister contains five bits generating 32 volume levels with 31 steps of 1 5 dB each Because AC 97 defines 6 bit volume registers to maintain compatibility whenever the D5 or D13 bits are set to 1 their respective lower five volume bits are automatically set to 1 by the codec logic On readback all lower five bits will read 1s whenever these bits are set to 1 For AC 797 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set bit D7 has no effect All registers not shown and bits containing an X are assumed to be reserved Note that depending on the state of the AC97NC bit in Register 0x76 this register has the following additional functionality For AC97NC 0 the register controls the Line_out output Attenuators only For AC97NC 1 the register controls the Line_out Center and LFE output Attenuators 5 0 Right Master Volume Control The least significant bit represents 1 5 dB This register controls the output from 0 dB to a maximum attenuation of 46 5 dB RM Right Channel
24. Interrupt Mode JSIMD JS1 Mode This bit selects the operation mode for the JS1 pin 0 Jack Sense Mode reset default Interrupt Mode JSOTMR JSO Timer Enable If this bit is set to a 1 JSO must be high for greater than 278 ms to be recognized JSITMR JS1 Timer Enable If this bit is set to a 1 JS1 must be high for greater than 278 ms to be recognized JSOEQB JSO EQ Bypass Enable This bit enables JSO to control the EQ bypass When this bit is set to 1 JSO 1 will cause the EQ to be bypassed JSIEQB JS1 EQ Bypass Enable This bit enables JS1 to control the EQ bypass When this bit is set to 1 JS1 1 will cause the EQ to be bypassed JSMT 2 0 JS Mute Enable Selector These three bits select and enable the Jack Sense muting action see Table IX JSODMX JSO Down Mix Control Enable This bit enables JSO to control the Down Mix function This function allows a digital mix of six channels of audio into 2 channel audio The mix can then be routed to the stereo Line_out or HP_out jacks When this bit is set to 1 JSO 1 will activate the Down Mix conversion See the DMIX description in Register 76h The DMIX bits select the Down Mix implementation type and can also force the function to be activated JSIDMX JS1 Down Mix Control Enable This bit enables 2 channel to 6 channel audio Spread function when both Jack Senses are active logic state 1 Note that the SPRD bit can also force the S
25. LS 1 DVppl I Digital Vpp 3 3 V 4 DVssl I Digital GND 7 DVss2 I Digital GND 9 DVpp2 I Digital Vpp 3 3 V 25 AVppl I Analog Vpp 5 0V 26 AVss1 I Analog GND 33 AVss4 I Analog GND 34 AVpp4 I Analog Vpp 5 0 V 38 AVpp2 I Analog Vpp 5 0 V 40 AVss2 I Analog GND 43 AVpp3 I Analog Vpp 5 0 V 44 AVss3 I Analog GND NO CONNECTS 12 NC No Connect 42 NC No Connect REV 0 Indexed Control Registers AD1980 Reg Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Default 00h Reset X SE4 SE3 SE2 SE1 SEO ID9 ID8 ID7 ID6 ID5 2 IDO 0090h 02h Master Volume MM X LMV5 LMV4 LMV3 LMV2 LMVI LMV0 MMRM X RMV5 RMV4 RMV3 2 RMVI RMVO 8000h 04h Headphone HPM X LHV5 LHV4 LHV3 LHV2 LHVI LHV0 HPRM X RHV5 RHV4 RHV3 RHV2 RHVO 8000h Volume 06h Mono Volume MVM X X X X X X X X X MV4 MV2 2 MVI MVO 8000h OCh Phone Volume PHM X X X X X X X X X X PHV4 PHV3 2 PHV1 8008h OEh Mic Volume MCM X X X X X X X X M20 X MCV4 MCV3 2 MCV1 MCVO 8008h 10h Line In Volume X X LLV4 LLV3 LLV2 LLVI LLVO LVRM X X RLV4 RLV3 RLV2 RLVO 8808h 12h CD Volume CVM X X LCV4 LCV3 LCV2 LCV0 CDRM X X RCV4 RCV3 RCV2 RCVI RCVO 8808h 16h AUX Volume
26. M Out Volume Mute When this bit is set to 1 both the left and the right channels are muted unless the MSPLT bit in Register 76h is set to 1 in which case this mute bit will affect only the left channel REV 0 AD1980 PCM Out Volume Register Index 18h Reg No Name 015 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Di Default 18h PCM Out Volume OM X X LOV4 LOV3 LOV2 LOV1 LOVO OMRM X X 4 ROV3 ROV2 ROVI ROVO 8808h For AC 97 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set Bit D7 has no effect All registers not shown and bits containing an X are assumed to be reserved Refer to Table IV for examples Note that depending on the state of the AC97NC bit in Register 76h this register has the following additional functionality For AC87NC 0 the register also controls the Surround Center and LFE DAC Gain Attenuators For AC97NC 1 the register controls the PCM Out Volume only ROV 4 0 Right PCM Out Volume Allows setting the PCM right channel attenuator in 32 volume levels The LSB represents 1 5 dB and the gain range is 12 dB to 34 5 dB The default value is 0 dB mute enabled RM Right Channel Mute Once enabled by the MSPLT bit in Register 76h this bit mutes the right chan
27. Mono MIC input 0 Select MICI 1 Select MIC2 See 2CMIC bit in Register 76h to enable stereo microphone recording DRSS 1 0 Double Rate Slot Select The DRSS bits specify the slots for the n 1 sample outputs PCM L n 1 and n 1 data are by default provided in output slots 10 and 11 00 PCM L n 1 Data is on Slots 10 11 reset default 01 PCM L Rn 1 Data is on Slots 7 8 10 Reserved 11 Reserved Audio Interrupt and Paging Mechanism Register Index 24h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 DS D4 D3 D2 D1 DO Default 24h Audio Interrupt 14 X X X 10 X X X X X X X PG3 PG2 PGI PGO xxxxh and Paging This register controls the Audio Interrupt and Paging mechanism All registers not shown and bits containing an X are assumed to be reserved PG 3 0 Page Selector Read Only This register is used to describe Page Selector capability for extended features Reading these bits returns 0h which describes Page Selection as vendor specific only IO INTERRUPT ENABLE R W This enables interrupt generation 0 Interrupt Generation is Masked Default 1 Interrupt Generation is Unmasked The S W should not unmask the interrupt unless ensured by the 797 controller that no conflict is possible with Modem slot 12 GPI functionality 77 2 2 compliant controllers will not likely support audio codec
28. Mute Once enabled by the MSPLT bit in Register 76h this bit mutes the right channel separately from the MM bit Otherwise this bit will always read 0 and will have no effect when set to 1 LMV 5 0 Left Master Volume Control The least significant bit represents 1 5 dB This register controls the output from 0 dB to a maximum attenuation of 46 5 dB MM Headphones Volume Mute When this bit is set to 1 both the left and the right channels muted unless the MSPLT bit in Register 76h is set to 1 10 REV 0 AD1980 Headphones Volume Register Index 04h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 Di DO Default 04h Headphones HPM X LHV5 LHV4 LHV3 LHV2 LHVI LHV0 HPRM X 5 RHV4 RHV3 2 RHVO 8000h Volume For AC 97 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set Bit D7 has no effect Table I Volume Settings for Master and Headphone Control Bits Reg 76h Master Volume 02h and Headphone Volume 04h Left Channel Volume D 13 8 Right Channel Volume D 5 0 MSPLT D15 WRITE READBACK Function D7 WRITE READBACK Function 0 0 00 0000 00 0000 0 dB Gain 00 0000 00 0000 0 dB Gain 0 0 00 1111
29. Specifications subject to change without notice Tl M NG PARAMETERS Guaranteed over Operating Temperature Range Parameter Symbol Min Typ Max Unit RESET Active Low Pulsewidth trsT LOW 1 0 us RESET Inactive to BIT_CLK Startup Delay tRST2CLK 162 8 400 000 ns SYNC Active High Pulsewidth tsyNC HIGH 1 3 us SYNC Low Pulsewidth tsyNC LOW 19 5 us SYNC Inactive Startup Delay tsyNC2CLK 162 8 ns BIT CLK Frequency 12 288 MHz BIT CLK Frequency Accuracy 51 0 ppm BIT CLK Period PERIOD 81 4 ns Output Jitter 750 ps CLK High Pulsewidth tcLK HIGH 40 41 7 ns CLK Low Pulsewidth tcLK LOW 39 7 41 4 ns SYNC Frequency 48 0 kHz SYNC Period tsyNC PERIOD 20 8 Us Setup to Falling Edge of BIT_CLK tsETUP 4 ns Hold from Falling Edge of BIT CLK tuorp 3 ns Rise Time trIsECLK 2 4 6 ns Fall Time tFALLCLK 2 4 6 ns SYNC Rise Time tRISESYNC 2 4 6 ns SYNC Fall Time tFALLSYNC 2 4 6 ns SDATA IN Rise Time tRISEDIN 2 4 6 ns SDATA IN Fall Time tFALLDIN 2 4 6 ns SDATA OUT Rise Time tRISEDOUT 2 4 6 ns SDATA OUT Fall Time tFALLDOUT 2 4 6 ns End of Slot 2 to BIT CLK SDATA IN Low 152 PDOWN 0 1 0 us Setup to RESET Inactive SYNC SDATA_OUT tsETUP2RST 15 ns Rising Edge of RESET to Hi Z Delay torr 25 ns Propagation Delay 15 ns RESET Rise Time 50 ns Output Valid Delay from BIT_CLK Rising 15 ns NOTES Guaranteed but not tested Output jitter directly dependent on crystal input jitter Specifica
30. T4 CNT3 CNT2 CNT1 CNTO 8080h Volume 38h Surround Volume MUTE_L X LSR5 LSR4 LSR3 LSR2 LSR1 1560 MUTER X RSR5 RSRA RSR3 RSR2 RSRI RSRO 8080h 3Ah SPDIF Control X SPSR1 SPSRO L CC6 CC5 CC4 CC3 CC2 0 PRE AUD PRO 2000h 60h EQ CTRL EQM X X X X X X X SYM CHS 5 BCA4 2 BCA1 BCAO 8080h 62h EQ DATA CFD15 CFD14 CFD13 CFDI2 CFDI1 CFD10 9 CFD8 CFD7 CFD6 5 4 CFD3 CFD2 CFD1 CFDO 0000h 72h JACK SENSE JJS1 151 150 15 18 18 151 150 151 150 151 150 151 180 181 180 0000h SPRD DMX DMX MT2 MTI MTO EQB EQB TMR TMR MD MD ST ST INT INT 74h Serial SLOT 16 REGM2 REGMI REGMO REGM3 DRF X CHEN X LBK1 LBKO INTS X SPAL SPDZ SPLNK 1001h Configuration 76h Misc Control DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIXI DMIX0 SPRD 2CMIC LOSEL SRU VREFH VREFD MBGI MBG0 0000h Bits 7Ch Vendor ID1 F7 F6 F5 F4 F3 F2 Fl FO S7 S6 55 54 53 52 51 50 4144h 7Eh Vendor ID2 T7 T6 T5 T4 T3 T2 Tl TO REV7 REV6 REV5 REV4 REV2 REVI REVO 5370h NOTES All registers not shown and bits containing an X are assumed to be reserved Odd register addresses are aliased to the next lower even address Reserved registers should not be written to Zeros should be written to reserved bits For AC 97 compatibility Bit D7 is only available by setting the MSPLT bit Register 76h channels If MSPLT is not set Bit D7 has no effect REV
31. Voltage References Vggg and up to Nominal Level PR 6 0 Codec Power Down Modes The first three bits are to be used individually rather than in combination with each other PR3 can be used in combination with PR2 or by itself The mixer and reference cannot be powered down via PR3 unless the ADCs and DACs are also powered down Nothing else can be powered up until the reference is up PR5 has no effect unless all ADCs DACs and the AC Link are powered down The reference and the mixer can be either up or down but all power up sequences must be allowed to run to completion before PR5 and are both set In multiple codec systems the master codec s PR5 and 4 bits control the slave codec PR5 is also effective in the slave codec if the master s PR5 bit is clear but the PR4 bit has no effect except to enable or disable PR5 EAPD External Audio Power Down Control Controls the state of the EAPD pin EAPD 0 sets the EAPD pin low enabling an external power amplifier reset defaults EAPD 1 sets the EAPD pin high shutting off the external power amplifier REV 0 17 AD1980 PRO 1 1 1 2 1 1 ADCs OFF DACs OFF PRO PR1 READY 1 COLD Figure 8 One Example of AC 97 Power Down Power Up Flow Extended Audio ID Register Index 28h Reg No Name D15 D14 D13 D12 D11 1 D9 D8 D7 D6 D5 D4 D2 D1 DO Default 28h Ext d Audio ID1 IDO X X
32. When this bit is set to 1 the Phone channel is muted MIC Volume Register Index 0Eh Reg No Name 015 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 Default OEh MIC Volume X X X X X X X X M20 X MCV4 MCV3 MCV2 MCVI MCVO 8008h All registers not shown and bits containing an X are assumed to be reserved Refer to Table III for examples MCV 4 0 MIC Volume Gain Allows setting the MIC Volume attenuator in 32 volume levels The LSB represents 1 5 dB and the gain range is 12 dB to 34 5 dB The default value is 0 dB with mute enabled M20 MIC Gain Boost This bit allows setting additional MIC gain to increase the microphone sensitivity The nominal gain boost by default is 20 dB however Bits DO and D1 MBG 1 0 on the miscellaneous control bits register 76h allow changing the gain boost to 10 dB or 30 dB if necessary 0 Disabled Gain 0 dB 1 Enabled Default Gain 20 dB see Register 76h Bits DO D1 MCM MIC Mute When this bit is set to 1 the channel is muted Table Volume Settings for Phone and Control Bits D 4 0 Phone 0Ch and MIC 0Eh D15 WRITE READBACK Function 0 0 0000 0 0000 12 dB Gain 0 0 1000 0 1000 0 dB Gain 0 11111 11111 34 5 dB Gain 1 X XXXX X XXXX dB Gain Muted x in the above table is a wild card and has no effect on the va
33. ad 6 coefb2 BCA 5 0 111010 CHS Channel Select CHS 0 selects left channel coefficients data block CHS 1 selects right channel coefficients data block SYM Symmetry When set to 1 this bit indicates that the left and right channel coefficients are equal This shortens the coeffi cients setup sequence since only the left channel coefficients need to be addressed and set up The right channel coefficients are fetched from the left channel memory EOM Equalizer Mute When set to 1 this bit disables the equalizer function allows all data pass through The reset default sets this bit to 1 disabling the equalizer function until the biquad coefficients can be properly set REV 0 23 AD1980 EQ Data Register Index 62h Reg No Name D15 014 D13 D12 Dii 010 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 62h DATA CFD15 CFD14 CFD13 CFD12 CFDII CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h This read write register is used to transfer EQ biquad coefficients into memory The register data is transferred to or retrieved from the address pointed to by the BCA Bits in the EQ CNTRL register 60h Data will only be written to memory if the EQM bit Register 60h Bit 15 is asserted CFD 15 0 Coefficient Data The biquad coefficients are fixed point format values with 16 bits of resolution The CFD15 bit is the MSB
34. and 10 IN 1 OUT 0 0 1 0 ACTIVE ACTIVE ACTIVE FMUTE enables HP OUT 11 IN D IN 0 0 1 0 ACTIVE ACTIVE ACTIVE FMUTE and C LFE Standard 6 channel config no swap 12 OUT 0 OUT 0 0 1 1 Reserved 13 OUT 0 IN 110 1 1 14 IN 1 OUT 0 0 1 1 i d 15 IN D IN 0 0 1 1 ae mm ae 16 OUT 0 OUT 0 1 0 0 ACTIVE FMUTE FMUTE ACTIVE JS0 0 and JS1 0 17 OUT 0 IN 1 1 0 0 ACTIVE ACTIVE ACTIVE FMUTE enables mono 18 IN l OUT 0 1 0 0 ACTIVE FMUTE FMUTE FMUTE JSI enables front 19 D IN 1 1 0 0 ACTIVE FMUTE FMUTE FMUTE only JSO 1 enables all rear 6 chan config with front jack wrap back 20 OUT 0 OUT 0 1 0 1 FMUTE FMUTE FMUTE ACTIVE 150 no mute action 21 OUT 0 IN 1 1 0 1 FMUTE FMUTE FMUTE FMUTE JS1 mutes mono and 22 IN 1 OUT 0 1 0 1 ACTIVE ACTIVE ACTIVE FMUTE enables LINE_OUT 23 IN 1 IN 1 0 1 ACTIVE ACTIVE ACTIVE FMUTE HP_OUT C LFE Standard 6 channel config swapped HP_OUT and LINE_OUT 24 OUT 0 OUT 0 1 1 0 oe ae du Reserved 25 OUT 0 IN 1 1 1 0 m TOM TOM 26 IN 1 OUT 0 1 1 0 X 27 IN IN 1 1 0 28 0 0 1 1 1 me To TE Reserved 29 OUT 0 IN D 1 1 1 XR X RE 30 IN 1 OUT 0 1 1 1 xd T uro 31 IN 0 IN D i i FMUTE Output is forced to m
35. channel media to use the higher power headphone amplifiers available on the SURR HP_OUT outputs the other is to allow spreading of 2 channel media to the surround outputs Together with the LOSEL bit see above this bit also provides for analog swapping of the mixer front and sur round outputs 0 SURR_out HP_out outputs are driven by the surround DACs reset default 1 SURR_out HP_out outputs are driven by the mixer outputs CLDIS Center and LFE Disable Disables the center and LFE output pins placing them into High Z mode so that the assigned output audio jack s can be shared for MIC inputs or other functions 0 Center and LFE output pins have normal audio drive capability reset default 1 Center and LFE output pins are placed into High Z mode LODIS Line_out Disable Disables the Line_out pins L R placing them into High Z mode so that the assigned output audio jack can be shared for Line Input function 0 Line_out pins have normal audio drive capability reset default 1 Line_out pins are placed into High Z mode MSPLT Mute Split Allows separate mute control bits for master HP Line_in CD PCM OUT and record volume gain control registers 0 Both left and right channel mutes are controlled by Bit D15 in the respective registers reset default 1 Bit D15 affects only the left channel mute and Bit D7 affects only the right channel mute AC 97 No Compatibility Mode This bit allows the surround cente
36. enables separate mute bits for the left and right channels If MSPLT is not set RM Bit has no effect x in the above table is don t care Record Select Control Register Index 1Ah Reg No Name D15 D14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 1Ah Record Select X X X X X 152 LS1 150 X X X X X RS2 RS1 RSO 0000h All registers not shown and bits containing an X are assumed to be reserved Refer to Table V for examples Used to select the record source independently for the right and left channels For single MIC recording see MS bit Register 20h for MICI and MIC2 input selection For dual MIC recording see 2CMIC bit Register 76h to enable simultaneous recording into the left and the right channels default value is 0000h which corresponds to MIC input for both channels RS 2 0 Right Record Select LS 2 0 Left Record Select 14 REV 0 AD1980 Table V Settings for Record Select Control LS 10 8 Left Record Source RS 2 0 Right Record Source 000 MIC 000 MIC 001 CDL 001 CD 010 Muted 010 Muted 011 AUX_L 011 AUX R 100 LINE INL 100 LINE IN R 101 Stereo Mix L 101 Stereo Mix R 110 Mono Mix 110 Mono Mix 111 PHONE IN 111 PHONE IN Record Gain Register Index 1Ch Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D5 D4 D3 D2 Di Default
37. h Primary w SPDIF 3 and 4 7 and 8 6 and 9 default 10 and 11 00 6 Ch Primary w SPDIF 3and4 7 and 8 6 and 9 10 and 11 default 01 2 Ch Secondary w SPDIF 3and4 7 and 8 6 and 9 default 01 4 Ch Secondary w SPDIF and 4 7 and 8 6 and 9 10 and 11 default 10 2 Ch Secondary w SPDIF 4 7 and 8 6 and 9 default 10 4 Ch Secondary w SPDIF 3 and 4 7 and 8 6 and 9 10 and 11 default 11 2 Ch Secondary w SPDIF 3 and 4 7 and 8 6 and 9 10 and 11 default PCM Front DAC Rate Register Index 2Ch No Name D15 014 D13 D12 D11 D10 D9 08 D7 D6 D5 D4 D3 D2 D1 Default 2Ch PCM Front SRF15 SRF14 SRF13 5 12 SRF11 SRF10 SRF9 SRF8 SRF7 SRF6 SRF5 SRF4 5 SRF2 SRF1 SRFO BB80h DAC Rate This read write Sample Rate Control Register contains 16 bit unsigned value representing the rate of operation in Hz SRF 15 0 Sample Rate The sampling frequency range is from 7 kHz 1B58h to 48 kHz BB80h 1 Hz increments If zero is written to VRA then the sample rate is reset to 48 kHz PCM Surround DAC Rate Register Index 2Eh Reg 015 014 D13 D12 D11 D10 09 DS D7 D6 D5 D4 D3 D2 D1 D0 Default 2 PCM Surr SRS15 SRS14 SRS13 SRS12 SRS11 SRS10 5659 SRS8 SRS7 SRS6 SRS5 SRS4 SRS3 SRS2 SRS1 SRSO BB80h DAC Rate
38. hannels are muted unless the MSPLT bit in Register 76h is set to 1 in which case this mute bit will only affect the left channel CD Volume Register Index 12h Reg No Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 12h CD Volume CVM X X LCV4 LCV3 LCV2 LCVI LCVO CDRM X X RCV4 RCV3 RCV2 RCVI RCVO 8808h For AC 97 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set the Bit D7 has no effect All registers not shown and bits containing an X are assumed to be reserved Refer to Table IV for examples RCV 4 0 Right CD Volume Allows setting the CD right channel attenuator in 32 volume levels with 31 steps of 1 5 dB each The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled RM Right Channel Mute Once enabled by the MSPLT bit in Register 76h this bit mutes the Right channel separately from the bit Otherwise this bit will always read 0 and will have no effect when set to 1 LCV 4 0 Left CD Volume Allows setting the CD left channel attenuator in 32 volume levels with 31 steps of 1 5 dB each The LSB represents 1 5 dB and the range is 12 dB to 24 5 dB The default value is 0 dB mute enabled CVM CD Volume Mute When t
39. his bit is set to 1 both the left and the right channels are muted unless the MSPLT bit in Register 76h is set to 1 in which case this mute bit will affect only the left channel AUX Volume Register Index 16h Reg No Name D15 DI4 D13 D12 011 D10 D9 D8 D7 D6 DS D4 D3 D2 DO Default 16h AUX Volume AVM X X LAV4 LAV3 LAV2 LAV1 LAVO AVRM X X RAV4 RAV3 RAV2 RAVI RAVO 8808h For AC 97 compatibility Bit D7 is only available by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set Bit D7 has no effect All registers not shown and bits containing an X are assumed to be reserved Refer to Table IV for examples RAV 4 0 Right AUX Volume Allows setting the AUX right channel attenuator in 32 volume levels with 31 steps of 1 5 dB each The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled RM Right Channel Mute Once enabled by the MSPLT bit in Register 76h this bit mutes the right channel separately from the AVM bit Otherwise this bit will always read 0 and will have no affect when set to 1 LAV 4 0 Left PCM Out Volume Allows setting the PCM left channel attenuator in 32 volume levels The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled AVM PC
40. ister is ASCII encoded to D Reg No Name D15 Di4 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Default 7Eh VendorID2 T7 716 T5 4 T3 2 TO REV7 REV6 REV5 REV4 REV3 REV2 REVO 5370h T 7 0 This register is ASCII encoded to S REV 7 0 This register is set to 70h identifying the AD1980 Codec ID and Clock Selection Table XTL IN ID1 IDO Codec ID Codec Clocking Source GND 0 0 SECONDARY ID 3 12 288 MHz BIT_CLK from Primary Codec GND 0 1 SECONDARY ID 2 12 288 MHz BIT_CLK from Primary Codec GND 1 0 SECONDARY ID 1 12 288 MHz BIT_CLK from Primary Codec XTAL 1 1 PRIMARY ID 0 24 576 MHz Local XTAL or External CLK into XTL_IN CLK INPUT 0 0 PRIMARY ID 0 14 3181 MHz External into XTL_IN CLK INPUT 0 1 PRIMARY ID 0 48 00 MHz External into XTL_IN CLK INPUT 1 X RESERVED RESERVED Note that internally the ID pins have weak pull ups and are inverted REV 0 29 AD1980 OUTLINE DIMENSIONS 48 Lead Plastic Quad Flatpack LQFP 1 4 mm Thick ST 48 Dimensions shown in millimeters 1 60 MAX PING 0 75 INDICATOR 0 60 9 00 BSC 545 Y SEATING 1 45 PLANE 140 0 20 TOP VIEW IE PINS DOWN zv y 7 4 a 3 5 0 15 0 0 05 SEATING 0 08 PLANE COPLANARITY VIEW A ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS 5 026 30 REV 0 342 0 20 LL
41. istortion THD LINE_OUT AVpp 5 0 V 90 Total Harmonic Distortion THD HP OUT AVpp 5 0 V 73 Total Harmonic Distortion THD AVpp 5 0 V 82 5 Dynamic Range 60 dB Input THD N Referenced to FS A Weighted 90 dB AVpp 5 0V Signal to Intermodulation Distortion CCIF Method 88 dB Gain Error Full Scale Span Relative to Nominal Input Voltage 10 Interchannel Gain Mismatch Difference of Gain Errors 0 7 dB DAC Crosstalk Input L Zero R Read LINE_OUT_R Input R 80 Zero L Read LINE OUT 1 10 kQ Load Total Audible Out of Band Energy Measured from 0 6 X fs to 20 kHz 40 ANALOG OUTPUT Full Scale Output Voltage LINE OUT MONO OUT CENTER OUT LFE OUT 1 V rms 2 83 V p p Output Impedance 800 Q External Load Impedance LINE OUT CENTER OUT LFE OUT MONO OUT 10 kQ Output Capacitance 15 pF External Load Capacitance 100 pF Full Scale Output Voltage HP_OUT 0 dB Gain 1 V rms External Load Impedance HP_OUT 32 Q VREF 2 05 2 25 2 45 V Vrer ovr 0 2 25 V Vngr ovr Vreru 1 3 65 V out Current Drive 5 mA Mute Click Muted Output Minus Unmuted Midscale DAC Output 5 mV STATIC DIGITAL SPECIFICATIONS High Level Input Voltage Vim Digital Inputs 0 65 X DVpp V Low Level Input Voltage 0 35 X DVpp V High Level Output Voltage Voy 2 mA 0 9 X DVpp V Low Level Output Voltage Voz Io 2 mA 0 1 X DVpp V Input Leakage Current 10 10 uA
42. lue 2 REV 0 AD1980 Line In Volume Register Index 10h Reg No Name D15 14 D13 D12 D11 D10 D8 D7 D6 D5 D4 D3 D2 D1 D0 Default 10h Line In Volume LVM X X LLV4 LLV3 LLV2 LLV1 LLVO LVRM X X RLV4 RLV3 RLV2 RLVO 8808h For AC 97 compatibility Bit D7 is available only by setting the MSPLT bit Register 76h The MSPLT bit enables separate mute bits for the left and right channels If MSPLT is not set the Bit D7 has no effect All registers not shown and bits containing an X are assumed to be reserved Refer to Table IV for examples RLV 4 0 Right Line In Volume Allows setting the Line In Right channel attenuator in 32 volume levels with 31 steps of 1 5 dB each The LSB represents 1 5 dB and the range is 12 dB to 34 d dB The default value is 0 dB mute enabled RM Right Channel Mute Once enabled by the MSPLT bit in Register 76h this bit mutes the right channel separately from the LIM bit Otherwise this bit will always read 0 and will have no effect when set to 1 LLV 4 0 Left Line In Volume Allows setting the Line In left channel attenuator in 32 volume levels with 31 steps of 1 5 dB each The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled LVM Line In Mute When this bit is set to 1 both the left and the right c
43. nel separately from the bit Otherwise this bit will always read 0 and will have no affect when set to 1 LOV 4 0 Left PCM Out Volume Allows setting the PCM left channel attenuator in 32 volume levels The LSB represents 1 5 dB and the range is 12 dB to 34 5 dB The default value is 0 dB mute enabled OM PCM Out Volume Mute When this bit is set to 1 both the left and the right channels are muted unless the MSPLT bit in Register 76h is set to 1 in which case this mute bit will affect only the left channel Table IV Volume Settings for Line In CD Volume AUX and PCM Out Control Bits Reg 76h Line In 10h CD 12h AUX 16h and PCM Out 18h Left Channel Volume D 12 8 Right Channel Volume D 4 0 MSPLT D15 WRITE READBACK Function D7 WRITE READBACK Function 0 0 00000 0 0000 12 dB Gain x 00000 00000 12 dB Gain 0 0 01000 0 1000 0 dB Gain x 01000 01000 0 dB Gain 0 0 11111 11111 34 5 dB Gain x 11111 11111 34 5 dB Gain 0 1 X XXXX X XXXX dB Gain Muted x X XXXX X XXXX dB Gain Muted 1 0 11111 11111 34 5 Gain 1 X XXXX X XXXX dB Gain Right Only Muted 1 1 X XXXX X XXXX dB Gain 0 11111 1 1111 34 5 dB Gain Left Only Muted 1 1 X XXXX X XXXX dB Gain Left Muted 1 X XXXX X XXXX dB Gain Right Muted For AC 97 compatibility Bit D7 is only available by setting the MSPLT bit Register 76h The MSPLT bit
44. nsmitter subsystem enabling the driver to determine if the currently programmed SPDIF configuration is supported SPCV is always valid indepen dent of the SPDIF enable bit status SPCV 0 indicates current SPDIF configuration SPSA SPSR DAC slot rate DRS is not valid not supported SPCV 1 indicates current SPDIF configuration SPSA SPSR DAC slot rate DRS is valid supported PRI Center DAC Power Down Read Write PRJ 1 turns off the PCM Center DAC PRJ Surround DACs Power Down Read Write PRJ 1 turns off the PCM surround DACs PRK LFE DAC Power Down Read Write PRJ 1 turns off the PCM LFE DAC VFORCE Validity Force Bit Reset Default 0 When asserted this bit forces the SPDIF stream validity flag Bit 28 within each SPDIF L R subframe to be con trolled by the V bit D15 in Register 3Ah SPDIF control register VFORCE 0 and V 0 the Validity Bit is managed by the codec error detection logic VFORCE 0 and 1 the Validity Bit is forced high indicating subframe data is invalid VFORCE 1 and 0 the Validity Bit is forced low indicating subframe data is valid VFORCE 1 and V 1 the Validity Bit is forced high indicating subframe data is invalid REV 0 19 AD1980 97 2 2 Compliant Default SPDIF Slot Assignments Codec ID Function SPSA 00 SPSA 01 SPSA 10 SPSA 11 00 2 Ch Primary w SPDIF 3 and 4 7 and 8 default 6 and 9 10 and 11 00 4 C
45. ono Out Surround Out Center LFE 1 5 Output Attenuation Range Span 46 5 dB Mute Attenuation of 0 dB Fundamental 80 dB PROGRAMMABLE GAIN AMPLIFIER ADC Step Size 0 dB to 22 5 dB 1 5 dB PGA Gain Range Span 22 5 dB ANALOG MIXER INPUT GAIN AMPLIFIERS ATTENUATORS Signal to Noise Ratio SNR CD to LINE OUT 90 dB LINE AUX PHONE to LINE OUT 90 dB MICI or MIC2 Note MIC Gain of 0 dB to LINE OUT 90 dB Step Size Mixer Inputs 1 5 dB Input Gain Attenuation Range All Mixer Inputs 46 5 dB DIGITAL DECIMATION AND INTERPOLATION FILTERS Pass Band 0 0 4 X fs Hz Pass Band Ripple 0 09 Transition Band 0 4 X fs 0 6 X fs Hz Stop Band 0 6 X fs Hz Stop Band Rejection 74 Group Delay 16 6 Group Delay Variation over Pass Band 0 us REV 0 AD1980 Parameter Min Typ Max Unit ANALOG TO DIGITAL CONVERTERS Resolution 16 Bits Total Harmonic Distortion THD AVpp 5 0 V 78 Dynamic Range 60 dB Input THD N Referenced to FS A Weighted 82 dB AVpp 5 0V Signal to Intermodulation Distortion CCIF Method 84 dB ADC Crosstalk Line Inputs Input L Ground R Read R Input R Ground L Read L 95 90 LINE IN to Other 90 85 Gain Error Full Scale Span Relative to Nominal Input Voltage t10 Interchannel Gain Mismatch Difference of Gain Errors 0 5 dB ADC Offset Error 0 dB Gain HPF On 10 mV DIGITAL TO ANALOG CONVERTERS Resolution 20 Bits Total Harmonic D
46. or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies 20 BIT X A DAC PCM SURR DAC RATE ANALOG MIXING CONTROL LOGIC 5 2 150 451 EAPD One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2002 Analog Devices Inc All rights reserved 01980 5 0 5 STANDARD TEST CONDITIONS UNLESS OTHERWISE DAC Test Conditions NOTED Calibrated Temperature 25 C Digital Supply DVpp 3 3V 0 dB Input Analog Supply AVpp 5 0 V 3 dB Attenuation Relative to Full Scale 10 Output Load LINE OUT MONO OUT Sample Rate fs 48 kHz CENTER_OUT and LFE_OUT Input Signal 1008 Hz 32 Q Output Load HP_OUT Analog Output Pass Band 20 Hz to 20 kHz ADC Test Conditions Calibrated 0 dB Gain Input 3 0 dB Relative to Full Scale Parameter Min Typ Max Unit ANALOG INPUT Input Voltage rms Values Assume Sine Wave Input LINE_IN CD AUX PHONE_IN 1 V rms 2 83 V p p MIC IN with 30 dB Preamp 0 032 V rms 0 089 V p p MIC IN with 20 dB Preamp 0 1 V rms 0 283 V p p MIC IN with 10 dB Preamp 0 316 V rms 0 894 V p p MIC IN with 0 dB Gain 1 V rms 2 83 V p p Input Impedance 20 Input Capacitance 5 MASTER VOLUME Step Size Line Out M
47. pread function without being gated by the Jack Senses See this bit s description in Register 76h for a better understanding of the Spread function JSSPRD JS Spread Control Enable This bit enables 2 channel to 6 channel audio Spread function when both Jack Senses are active logic state 1 Note that the SPRD bit can also force the Spread function without being gated by the Jack Senses See this bit s description in Register 76h for a better understanding of the Spread function 24 REV 0 AD1980 Table IX Jack Sense Mute Select JSMT 2 0 HP LINE C LFE MONO REF JS1 80 JSMT2 JSMT1 JSMTO OUT OUT OUT OUT NOTES 0 OUT 0 OUT 0 0 0 0 ACTIVE ACTIVE ACTIVE ACTIVE 160 and JS1 ignored 1 OUT 0 IN 110 0 0 ACTIVE ACTIVE ACTIVE ACTIVE 2 IN 1 OUT 0 0 0 0 ACTIVE ACTIVE ACTIVE ACTIVE 3 IN 1 IN 110 0 0 ACTIVE ACTIVE ACTIVE ACTIVE 4 OUT 0 OUT 0 0 0 1 ACTIVE FMUTE FMUTE ACTIVE JSO no mute action 5 OUT 0 IN 110 0 1 ACTIVE FMUTE FMUTE ACTIVE 51 mutes mono 6 IN 1 OUT 0 0 0 1 ACTIVE ACTIVE ACTIVE ACTIVE enables LINE OUT 7 IN 1 IN 110 0 1 ACTIVE ACTIVE ACTIVE ACTIVE and C LFE Standard 6 channel config swapped HP OUT and LINE OUT 8 OUT 0 OUT 0 0 1 0 FMUTE ACTIVE FMUTE ACTIVE 150 no mute action 9 OUT 0 IN 710 1 0 FMUTE ACTIVE FMUTE ACTIVE 1651 mutes Mono
48. r LFE volume control registers and output attenuators to operate in a more functional mode than defined by the 97 2 2 spec This is called ADI compatibility mode In AC 97 compatibility mode the DAC Gain Attenuators for the surround center and LFE are controlled by Register 18h PCM volume The output pin attenuators for the surround are controlled by Register 38h and the output pin attenuators for the center and LFE are controlled by Register 36h In ADI compatibility mode the Surround DAC Gain Attenuators are controlled by Register 38h and the Center LFE DAC are controlled by Register 36h output pin attenuators for Center LFE are controlled by Register 02h Master Volume and the output pin attenuators for Surround are controlled by Register 04h 0 AC97 compatibility mode reset default 1 ADI compatibility mode DACZ DAC Zero Fill Determines DAC data fill under starved condition 0 DAC data is repeated when DACs are starved for data reset default 1 DAC data is zero filled when DACs are starved for data 28 REV 0 AD1980 Vendor ID Register Index 7Ch 7Eh Reg No Name D15 D13 D12 D11 1 DI D8 D7 D6 DS D4 D3 D2 D1 DO Default 7Ch Vendor ID1 F7 Fo F5 FA F3 F2 Fl FO S7 S6 55 54 53 52 51 50 4144h S 7 0 This register is ASCII encoded to A F 7 0 This reg
49. rom the OUT the HPSEL selector drives the SURR HP OUT outputs from the mixer outputs and the LOSEL selector drives the LINE OUT outputs also from the mixer outputs Note that the SPRD bit overrides the current output selector control lines set up by bits LOSEL and HPSEL as follows LOSEL 0 and HPSEL 1 REV 0 27 AD1980 DMIX 1 0 Down Mix Mode Select Provides analog down mixing of the center LFE and or surround channels into the mixer channels This allows the full content of 5 1 or quad media to be played through stereo headphones or speakers Note that the Jack Sense pins can also be set up to control gate this function depending on the JSODMX and JSIDMxX Bits see Register 72h The upper bit allows forcing the down mix function DMIX 1 0 no down mix unless activated by the Jack Sense and JSxDMxX bits default DMIX 1 1 forces down mix function lower bit selects the down mix type 0 0 selects 6 to 4 down mix The center and LFE channels are summed equally into the mixer left and right channels default 0 1 selects 6 to 2 down mix The surround left and right channels are summed into the mixer left and right channels Default for DMIX 1 0 is 00 HPSEL Headphone Amplifier Input Select This bit allows the headphone power amps to be driven from the surround DACs or from the mixer outputs There are two reasons for this one is to allow 2
50. ster controls the surround volume controls for both stereo channels and mute bits Each volume subregister contains five bits generating 32 volume levels with 31 steps of 1 5 dB each Because AC 97 defines 6 bit volume registers to maintain compatibility whenever the D5 or D13 Bit is set to 1 its respective lower five volume bits are automatically set to 1 by the coded logic On readback all lower five bits will read 1s whenever these bits are set to 1 Note that depending on the state of the AC97NC bit in Register 0x76 this register operates as follows For AC97NC 0 the register controls the surround output pin Attenuators Range is 0 dB to 46 5 dB For AC97NC 1 the register controls the surround DAC Gain Attenuators Range is 12 dB to 34 5 dB RSR 5 0 Right Surround Volume Control MUTE_R Right Surround Volume Mute When this bit is set to 1 the right channel is muted LSR 5 0 Left Surround Volume Control MUTE_L Left Surround Volume Mute When this bit is set to 1 the left channel is muted REV 0 21 AD1980 Table VIII Settings for Surround Register Control Bits Surround Volume 38h Left Surround D 13 8 Right Surround D 5 0 D15 D7 WRITE READBACK Function with AC97NC 0 Function with AC97NC 1 0 00 0000 00 0000 0 dB Gain 12 dB Gain 0 00 1111 00 1111 22 dB Gain 10 5 dB Gain 0 011111 011111 46 5 dB Gain 34 5 dB Gain 0 lx xxxx 01 111
51. the codec logic On readback all lower five bits will read 1 s whenever this bit is set to 1 Note that depending on the state of the AC97NC bit in register 76h this register operates as follows For AC97NC 0 the register controls the center and LFE output pin Attenuators Range is 0 dB to 46 5 dB For AC97NC 1 the register controls the center and LFE DAC Gain Attenuators Range is 12 dB to 34 5 dB CNT 5 0 Center Volume Control CM Center Volume Mute When this bit is set to 1 the channel is muted LFE 5 0 LFE Volume Control LM LFE Volume Mute When this bit is set to 1 the channel is muted Table VII Settings for Center LFE Register Control Bits CENTER and LFE Volume 36h CENTER D 5 0 and LFE D 13 8 D15 D7 WRITE READBACK Function with AC97NC 0 Function with AC97NC 1 0 00 0000 00 0000 0 dB Gain 12 dB Gain 0 00 1111 00 1111 22 dB Gain 10 5 dB Gain 0 01 1111 01 1111 46 5 dB Gain 34 5 dB Gain 0 lx xxxx 01 1111 46 5 dB Gain Not Applicable 1 XX XXXX XX XXXX Muted Muted Surround Volume Control Register Index 38h Reg No Name D15 D14 D13 12 D11 D10 D9 D7 D6 D5 D4 D3 2 D1 Default 38h Surround MUTE L X LSR5 1864 1563 1862 LSR1 LSRO MUTE R X RSR5 RSR4 RSR3 RSR2 RSR1 RSRO 8080h Volume Refer to Table VIII for examples This regi
52. tions subject to change without notice REV 0 AD1980 46 trst2cLk trrractv e BIT_CLK trractv SDATA IN M 2 Figure 1 Cold Reset Timing Codec is Supplying the Bit CLK Signal E tsync_HIGH e 2 gt SYNC BIT CLK Figure 2 Warm Reset Timing Low SLOT 1 SLOT 2 SYNC BIT_CLK BIT_CLK HIGH 4t cLk PERIOD WRITE TO 0x26 SDATA OUT H tsync Low gt t gt 52 PDOWN SYNC SDATA IN gt NOT TO SCALE 44 tsync PERIOD Figure 5 AC Link Low Power Mode Timing Figure 3 Clock Timing 4 gt je SDATA I SYN trisesyNC gt gt l lraALLSYNC SYNC x o ON SDATA O Figure 6 AC Link Low Power Mode Timing SDATA IN Jd 4 gt j lt trallo RESET 7 SDATA OUT 10 trisepout gt lrALLDOUT SDATA OUT 4 gt Figure 4 Signal Rise Fall Times SDATA IN BIT CLK EAPD SPDIF OUT AND DIGITAL I O Hi Z gt tor 4 Figure 7 ATE Test Mode REV 0 AD1980 ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL CONDITIONS Ambient Temperature Rating Parameter Min
53. used as the chain input from a secondary Codec 46 IDI I Chip Select Input 1 Active Low JACK SENSE AND EAPD 47 EAPD O EAPD Output 17 150 Jack Sense 0 Input 16 JS1 I Jack Sense 1 Input ANALOG INPUT OUTPUT 13 PHONE IN I Monaural Line Level Input 14 AUX I Auxiliary Input Left Channel 15 AUX I Auxiliary Input Right Channel 18 CDL I CD Audio Left Channel 19 CD GND REF I CD Audio Analog Ground Reference for Differential CD Input 20 CD R I CD Audio Right Channel 21 MICI I Microphone 1 Input Left Channel when 2 Channel Mode Selected 22 MIC2 I Microphone 2 Input Right Channel when 2 Channel Mode Selected 23 LINE IN L I Line In Left Channel 24 LINE IN R I Line In Right Channel 31 CENTER OUT Center Channel Output 32 LFE OUT Low Frequency Enhanced Output 35 LINE OUT L Line Out Front Left Channel 36 LINE OUT R Line Out Front Right Channel 37 MONO OUT Monaural Output to Telephone Subsystem Speakerphone 39 SURR OUT I HP OUT L O Surround or Front Headphone Left Channel Output 41 SURR OUT OUT O Surround or Front Headphone Right Channel Output FILTER REFERENCE 27 VREF O Voltage Reference Filter 28 VREFOUT O Voltage Reference Output 5 mA Drive intended for MIC bias 29 AFILTI Antialiasing Filter Capacitor ADC Right Channel 30 AFILT2 Antialiasing Filter Capacitor ADC Left Channel REV 0 AD1980 Pin Number Mnemonic I O Function POWER AND GROUND SIGNA
54. ute independent of the respective Volume Register setting ACTIVE Output is not muted and its status is dependent on the respective Volume Register setting OUT Nothing plugged into the jack and therefore the JS status is 0 via the load resistor pull down IN Jack has plug inserted and therefore the JS status is 1 via the codec JS internal pull up REV 0 25 AD1980 Serial Configuration Register Index 74h Reg No Name D15 014 D13 D12 D11 D10 D9 D8 D7 D6 05 D4 D3 D2 DO Default 74h Serial SLOT16 REGM2 REGMO REGM3 DRF X CHEN X LBKSI LBKSO INTS X SPAL SPDZ SPLNK 1001h Configuration All registers not shown and bits containing an X are assumed to be reserved Note that this register is not reset when the reset register 0x00 is written to soft reset SPLNK SPDIF Link This bit enables the SPDIF to link with the front DACs for data requesting 0 SPDIF and DAC are not linked 1 SPDIF and DAC are linked and receive the same data requests reset default SPDZ SPDIF DACZ 0 Repeat last sample out of the SPDIF stream if FIFO under runs reset default 1 Forces midscale sample out the SPDIF stream if FIFO under runs SPAL SPDIF ADC Loop around 0 SPDIF transmitter is connected to the AC Link stream reset default 1 SPDIF transmitter is connected to the digital ADC stream not the AC Link
55. ved EVRA Variable Rate Audio Read Write VRA 0 sets fixed sample rate audio at 48 kHz Reset Default VRA 1 enables variable rate audio mode enables sample rate registers and SLOTREQ signaling EDRA Double Rate Audio DRA 1 enables double rate audio mode in which data from PCM L and PCM R in output slots 3 and 4 is used in conjunction with PCM L n 1 and PCM R n 1 data to provide DAC streams at twice the sample rate desig nated by the PCM front sample rate control register When using the double rate audio only the front DACs are supported and all other DACs surround center and LFE are automatically powered down Note that DRA can be used without VRA in that case the converter rates are forced to 96 kHz if DRA 1 ESPDIF SPDIF Transmitter Subsystem Enable Disable Bit Read Write SPDIF 1 enables the SPDIF transmitter SPDIF 0 disables the SPDIF transmitter default SPSA 1 0 SPDIF Slot Assignment Bits Read Write These bits control the SPDIF slot assignment and respective defaults depending on the codec ID configuration See the following table ECDAC Center DAC Status Read Only CDAC 1 indicates the PCM center DAC is ready ESDAC Surround DAC status Read Only SDAC 1 indicates the PCM surround DACs are ready ELDAC LFE DAC status Read Only 1 indicates the PCM LFE DAC is ready SPCV SPDIF Configuration Valid Read Only Indicates the status of the SPDIF tra
56. zer function until the coeffi cients can be properly set up by the software and sets the Symmetry Bit to allow equal coefficients for the left and right channels BCA 5 0 Biquad and Coefficient Address Pointer biquad 0 coefa0 BCA 5 0 011011 biquad 0 coefal 5 0 011010 biquad 0 coefa2 BCA 5 0 011001 biquad 0 1 BCA 5 0 011101 biquad 0 coefb2 BCA 5 0 011100 biquad 1 coefa0 BCA 5 0 100000 biquad 1 coefal BCA 5 0 011111 biquad 1 coefa2 5 0 011110 biquad 1 coefbl BCA 5 0 100010 biquad 1 coefb2 BCA 5 0 100001 biquad 2 coefa0 BCA 5 0 100101 biquad 2 coefal 5 0 100100 biquad 2 coefa2 BCA 5 0 100011 biquad 2 coefbl BCA 5 0 100111 biquad 2 coefb2 BCA 5 0 100110 biquad 3 coefa0 5 0 101010 biquad coefal BCA 5 0 101001 biquad 3 coefa2 BCA 5 0 101000 biquad 3 coefbl BCA 5 0 101100 biquad 3 coefb2 BCA 5 0 101011 biquad 4 coefa0 BCA 5 0 101111 biquad 4 coefal BCA 5 0 101110 biquad 4 coefa2 BCA 5 0 101101 biquad 4 1 BCA 5 0 110001 biquad 4 coefb2 BCA 5 0 110000 biquad 5 coefa0 5 0 110100 biquad 5 coefal BCA 5 0 110011 biquad 5 coefa2 5 0 110010 biquad 5 coefbl BCA 5 0 110110 biquad 5 coefb2 BCA 5 0 110101 biquad 6 coefa0 BCA 5 0 111001 biquad 6 coefal 5 0 111000 biquad 6 coefa2 BCA 5 0 110111 biquad 6 coefbl BCA 5 0 111011 biqu

ANALOG DEVICES AD1980 handbook3

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