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ANALOG DEVICES AD9516-5 handbook

1. 120 110 125 120 130 gt E 135 D _130 140 2 o G 140 145 a 4 I a 150 150 155 160 160 a 10 100 1k 10k 100k 1M 40M 100m amp 10 100 1k 10k 100k 1M 10M 100M FREQUENCY Hz g FREQUENCY Hz 2 Figure 23 Phase Noise Additive LVPECL at 245 76 MHz Divide by 1 Figure 26 Phase Noise Additive LVDS at 200 MHz Divide by 1 100 110 N 5 120 o o 2 130 o 4 I a 140 150 ML 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY Hz g FREQUENCY Hz Figure 24 Phase Noise Additive LVPECL at 200 MHz Divide by 5 Figure 27 Phase Noise Additive LVDS at 800 MHz Divide by 2 100 110 V N o 120 o o z 130 ul 7 4 a 140 150 3 10 100 1k 10k 100k 1M 10M 100M 10 100 1k 10k 100k 1M 10M 100M FREQUENCY Hz S FREQUENCY Hz Figure 25 Phase Noise Additive LVPECL at 1600 MHz Divide by 1 Figure 28 Phase Noise Additive CMOS at 50 MHz Divide by 20 Rev A Page 21 of 76 AD9516 5 PHASE NOISE dBc Hz 10 100 1k 10k 100k 1M FREQUENCY Hz Figure 29 Phase Noise Additive CMOS at 250 MHz Div
2. 1 10 15 Even Even Even 5096 Nx1 Mx Nx2 Mx Odd Even Even 50 Nx1 Mx Nx2 Mx Even Odd Even 5096 Mx 1 Nx2 Mx Odd Odd Even 50 1 Nx2 Mx Even Odd Odd 5096 Mx 1 Mx2 Nx2 1 Odd 3 Odd Odd 6Nx1Nx2 9Nx Mx 1 Mx2 Nx2 1 9Nx2 13 X96 3 2Nx 3 2Nx2 3 Odd 5 Odd Odd 10NxiNx2 15 1 2 Ny 3 1 15Nx2 22 5 2 3 2 Nx2 3 Input Clock Duty Output Cycle Nx Mx 2 Nx2 Mx2 2 Duty Cycle 5096 Bypassed Bypassed 5096 5096 Even Bypassed 5096 Mx X96 Bypassed Bypassed X96 high X96 Even Bypassed 5096 Mx 5096 Odd Bypassed 5096 1 X96 Odd Bypassed Nx 1 1 2 3 Odd Bypassed 1 X 1 231 3 50 Even Even 50 Nx1 Mx Nx2 Mx X Even Even 50 Nx1 Mx Nx2 Mx 5096 Odd Even 50 Mx1 Nxit 1 Mx X Odd Even 50 Nx 1 1 Mx 50 Odd Odd 50 Nx 1 Mx2 Nx2 1 X Odd Odd 2Nx1Nx2 3Nx1 Mxiz Nxi 1 Mx2 Nx2 1 3Nx2 4 2Nx1 3 2Nx2 3 Phase Offset or Coarse Time Delay Divider 3 and Divider 4 Divider 3 and Divider 4 can be set to have a phase offset or delay The phase offset is set by a combination of the bits in the phase offset and
3. SERIAL CONTROL PORT Table 10 Parameter Min Typ Max Unit Test Conditions Comments CS INPUT CS has an internal 30 pull up resistor Input Logic 1 Voltage 2 0 V Input Logic 0 Voltage 0 8 V Input Logic 1 Current 3 uA Input Logic 0 Current 110 uA Input Capacitance 2 pF SCLK INPUT SCLK has an internal 30 kQ pull down resistor Input Logic 1 Voltage 2 0 V Input Logic 0 Voltage 0 8 V Input Logic 1 Current 110 uA Input Logic 0 Current 1 uA Input Capacitance 2 pF SDIO WHEN INPUT Input Logic 1 Voltage 2 0 V Input Logic 0 Voltage 0 8 V Input Logic 1 Current 10 nA Input Logic 0 Current 20 nA Input Capacitance 2 pF SDIO SDO OUTPUTS Output Logic 1 Voltage 2 7 V Output Logic 0 Voltage 0 4 V TIMING Clock Rate SCLK 1 tscix 25 MHz Pulse Width High tuu 16 ns Pulse Width Low tiow 16 ns SDIO to SCLK Setup tps 2 ns SCLK to SDIO Hold tox 1 1 ns SCLK to Valid SDIO and SDO tov 8 ns CS to SCLK Setup and Hold ts tu 2 ns CS Minimum Pulse Width High tew 3 ns PD RESET AND SYNC PINS Table 11 Parameter Min Typ Max Unit Test Conditions Comments INPUT CHARACTERISTICS Each of these pins has an internal 30 kO pull up resistor Logic 1 Voltage 2 0 V Logic 0 Voltage 0 8 V Logic 1 Current 110 uA Logic 0 Current 1 uA Capacitance 2 pF RESET TIMING Pulse Width Low 50 ns SYNCTIMING Pulse Width Low 1 5 High speed High speed clock is CLK input signal clock cycles Rev A Page 10 of 76 LD STATUS AND REFMON P
4. Rev A Page 62 of 76 AD9516 5 Reg Addr Hex Bits Name Description 4 4 OUTA invert Sets the output polarity 0 noninverting default 1 inverting 3 2 OUTALVPECL Sets the LVPECL output differential voltage Vo differential 3 2 Van mV voltage 400 O 1 600 1 O 780 default 1 1 960 1 0 OUT4 LVPECL power down modes power down 1 o Mode Output 0 0 Normal operation On O 1 Partial power down reference on use only if there are no external load resistors Off 1 O Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off OxOF5 4 5 invert Sets the output polarity 0 noninverting default 1 inverting 3 2 OUTS LVPECL Sets the LVPECL output differential voltage Vor differential 3 2 mV voltage o 0 400 O 1 600 1 O 780 default 1 1 960 1 0 OUTS LVPECL power down modes powerdown 4 9 Mode Output 0 0 Normal operation On 0 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down default Off 1 1 Total power down reference off use only if there are no external load resistors Off Rev A Page 63 of 76 AD9516 5 Tabl
5. 1 PLL is locked Rev A Page 58 of 76 Table 50 Fine Delay Adjust OUT6 to OUT9 AD9516 5 Reg Addr Hex Bits Name Description 0x0A0 0 OUT6 delay Bypasses or uses the delay function bypass 0 uses the delay function 1 bypasses the delay function default OxOA1 5 3 OUT6 ramp Selects the number of ramp capacitors used by the delay function The combination of the number of capacitors capacitors and the ramp current sets the full scale delay 5 4 3 Number of Capacitors O O O 4 default 00 10 113 0 11013 0111112 1101013 14101112 1111012 1111111 2 0 OUT6 ramp Ramp current for the delay function The combination of the number of capacitors the ramp current current sets the full scale delay 2 1 O Current pA O O O 200 default 0 0 1 400 O 11101 600 01111 800 110 0 1000 110 1 1200 111 0 1400 1 1 1 1600 2 5 0 OUT6 delay Selects the fraction of the full scale delay desired 6 bit binary A setting of 000000b gives zero delay fraction Only delay values of up to 47 decimals 101111b 2 are supported default 0x00 0 OUT7 delay Bypasses or uses the delay function bypass 0 uses the delay function 1 bypasses the delay function default Ox0A4 5 3 OUT7 ramp Selects the number of ramp capacitors used by the delay function The combination of the number of the capaci
6. unless otherwise noted Minimum and maximum values are given over full Vs and 40 C to 85 C variation POWER SUPPLY REQUIREMENTS Table 1 Parameter Min Typ Max Unit Test Conditions Comments Vs 3 135 3 3 3 465 V 3 3V 5 Vs iveECL 2 375 VS V Nominally 2 5 V to 3 3 V 596 Vee Vs 525 V Nominally 3 3 V to 5 0 V 596 RSET Pin Resistor 4 12 kQ Sets internal biasing currents connect to ground CPRSET Pin Resistor 2 7 5 1 10 kQ Sets internal CP current range nominally 4 8 mA CP_Isb 600 actual current can be calculated CP Isb 3 06 CPRSET connect to ground PLL CHARACTERISTICS Table 2 Parameter Min Typ Max Unit Test Conditions Comments REFERENCE INPUTS Differential Mode REFIN REFIN Differential mode can accommodate single ended input by ac grounding undriven input Input Frequency 0 250 MHz Frequencies below about 1 MHz should be dc coupled be careful to match Vem self bias voltage Input Sensitivity 250 mV p p PLL figure of merit FOM increases with increasing slew rate see Figure 13 Self Bias Voltage REFIN 1 35 1 60 1 75 V Self bias voltage of REFIN Self Bias Voltage REFIN 1 30 1 50 160 V Self bias voltage of REFIN Input Resistance REFIN 4 0 4 8 5 9 KO Self biased Input Resistance REFIN 44 5 3 64 kO Self biased Dual Single Ended Mode REF1 REF2 Two single ended CMOS compatible inputs Input Frequency AC Coupled 20 250 MHz Slew rate 50 V us In
7. Figure 58 SNR and ENOB vs Analog Input Frequency See the AN 756 Application Note Sampled Systems and the Effects of Clock Phase Noise and Jitter and the AN 501 Application Note Aperture Uncertainty and ADC System Performance at www analog com Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB Distributing a single ended clock on a noisy PCB may result in coupled noise on the sample clock Differential distribution has inherent common mode rejection that can provide superior clock performance in a noisy environment The AD9516 features both LVPECL and LVDS outputs that provide differential clock outputs which enable clock solutions that maximize converter SNR performance The input requirements of the ADC differential or single ended logic level and termination should be considered when selecting the best clocking converter solution Rev A Page 71 of 76 AD9516 5 LVPECL CLOCK DISTRIBUTION The LVPECL outputs of the AD9516 provide the lowest jitter clock signals that are available from the AD9516 The LVPECL outputs because they are open emitter require a dc termination to bias the output transistors The simplified equivalent circuit in Figure 47 shows the LVPECL output stage In most applications an LVPECL far end Thevenin termination see Figure 59 or Y termination see Figure 60 is recommended In each case the Vs of th
8. Rev A Page 70 of 76 AD9516 5 APPLICATIONS INFORMATION FREQUENCY PLANNING USING THE AD9516 The AD9516 is a highly flexible PLL When choosing the PLL settings and version of the AD9516 keep in mind the following guidelines The AD9516 has the following four frequency dividers the reference or R divider the feedback or N divider the VCO divider and the channel divider When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division some of the frequency division can be done by either the VCO divider or the channel divider thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth Within the AD9516 family lower VCO frequencies generally result in slightly lower jitter The difference in integrated jitter from 12 kHz to 20 MHz offset for the same output frequency is usually less than 150 fs over the entire VCO frequency range 1 45 GHz to 2 95 GHz of the AD9516 family If the desired frequency plan can be achieved with a version of the AD9516 that has a lower VCO frequency choosing the lower frequency part results in the lowest phase noise and the lowest jitter However choosing a higher VCO frequency may result in more flexibility in frequency planning Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and
9. 10N 15 4 2 requires 1 Rev Page 36 of 76 Table 32 Channel Divider Output Duty Cycle When the VCO Divider Is Not Used Input Clock Dx Output Duty Cycle DutyCyde N M 2 DCCOFF 1 DCCOFF 0 Any Channel 1 divider Same as input divider bypassed duty cycle bypassed Any Even 1 50 requires M N 2 5096 Odd 1 5096 requires M N 2 M N 1 X Odd N 1 N 4 1 X99 2 X N 4 3 M N 2 requires M N 1 If the CLK input is routed directly to the output the duty cycle of the output is the same as the CLK input Phase Offset or Coarse Time Delay 0 1 and 2 Each channel divider allows for a phase offset or a coarse time delay to be programmed by setting register bits see Table 33 These settings determine the number of cycles successive rising edges of the channel divider input frequency by which to offset or delay the rising edge of the output of the divider This delay is with respect to a nondelayed output that is with a phase offset of zero The amount of the delay is set by five bits loaded into the phase offset PO register plus the start high SH bit for each channel divider When the start high bit is set the delay is also affected by the number of low cycles M that are programmed for the divider The sync function must be used to make phase offsets effective see the Synchronizing the Outputs SYNC Function
10. 3 counter bypass B counter bypass This is valid only when operating the prescaler in FD mode 0 normal default 1 B counter is set to divide by 1 This allows the prescaler setting to determine the divide for the N divider Rev A Page 53 of 76 AD9516 5 Reg Addr Hex Bits Name Description 2 0 Prescaler P Prescaler DM dual modulus and FD fixed divide 2 1 0 Mode Prescaler Divide by 1 0 0 1 FD Divide by 2 DM Divide by 2 2 3 mode 0 1 1 DM Divide by 4 4 5 mode 1 0 0 DM Divide by 8 8 9 mode 1 0 1 DM Divide by 16 16 17 mode 1 110 DM Divide by 32 22 23 mode default 1 1 1 FD Divide by 3 0x017 7 2 STATUS pin Selects the STATUS pin signal control Level or Dynamic 71615 4 3 2 Signal Signal at STATUS Pin 0 0 0 0 0 0 LVL Ground dc default 0 0 0 0 0 1 DYN N divider output after the delay 0 0 0 0 1 0 DYN R divider output after the delay o 1 1 DYN A divider output 0 0 1 0 DYN Prescaler output 1 0 1 DYN PFD up pulse 1 1 0 PFD down pulse 0 X X X X X LVL Ground for all other cases of OxOXXXX not specified The selections that follow are the same as for 1 0 0 0 0 0 LVL Ground dc 1 0 0 0 0 1 DYN REF1 clock differential reference when in differential mode 1 0 0 0 1 0 DYN REF2 clock not available in differential mode 1 0 0 0 1 1 DYN Selected
11. R A Bcounters 7 6 Action SYNC pin reset 0 0 Does nothing on SYNC default 0 1 Asynchronous reset 1 0 Synchronous reset 1 1 Does nothing on SYNC 5 3 R path delay R path delay default 0x0 see Table 2 2 0 N path delay N path delay default 2 0x0 see Table 2 Rev A Page 55 of 76 AD9516 5 Reg Addr Hex Bits Name Description 6 Reference Sets the reference REF 1 REF2 frequency monitor s detection threshold frequency This does not affect the CLK frequency frequency monitor s detection threshold see Table 12 REF1 REF2 and CLK frequency status monitor parameter monitor 0 frequency valid if frequency is above the higher frequency threshold default threshold 1 frequency valid if frequency is above the lower frequency threshold 5 0 LD pin control Selects the LD pin signal Level or Dynamic 5 4 3 2 1 0 Signal Signal at LD Pin 0 0101010101 LVL Digital lock detect high lock low unlock default 0 01010101 DYN P channel open drain lock detect analog lock detect 0 1 N channel open drain lock detect analog lock detect 0 010101 1 HIZ High Z LD pin 0 01011 O O CUR Current source lock detect 110 uA when DLD is true 0 l LVL Ground dc for all other cases of OxOXXXX not specified The selections that follow are the same as for REFMON 1 0101010101 LVL Ground dc 1 010
12. CMOS OUT7 LVDS O O O Noninverting Inverting Noninverting O 1 0 Noninverting Noninverting Noninverting default 1 0 O inverting Inverting Noninverting 1 1 O Inverting Noninverting Noninverting O 10 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT7 CMOS B In CMOS mode turns on off the CMOS B output This has no effect in LVDS mode 0 turns off the CMOS B output default 1 turns on the CMOS B output 3 OUT7 select LVDS CMOS Selects LVDS or CMOS logic levels 0 LVDS default 1 CMOS 2 1 OUT7 LVDS output current Sets output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination 10 1 75 100 0 1 3 5 100 default 1 0 5 25 50 1 1 7 50 Rev A Page 64 of 76 AD9516 5 Reg Addr Hex Bits Name Description 0 OUT7 power down Power down output LVDS CMOS 0 powers on 1 powers off default 0x142 7 5 OUT8 output polarity In CMOS mode Bits 7 5 select the output polarity of each CMOS output In LVDS mode only Bit 5 determines LVDS polarity 7 6 5 OUT8A CMOS OUTS8B CMOS OUTS LVDS 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting default 1 0 0 Inverting Inver
13. Charge Pump Characteristics at VCP 3 3 V 0 05 10 15 20 25 30 35 40 45 5 0 VOLTAGE ON CP PIN V Figure 11 Charge Pump Characteristics at Ve 5 0 V 140 145 150 155 160 165 170 0 1 1 10 100 PFD FREQUENCY MHz 07972 011 07972 012 Figure 12 PFD Phase Noise Referred to PFD Input vs PFD Frequency 07972 013 PLL FIGURE OF MERIT dBc Hz DIFFERENTIAL OUTPUT V DIFFERENTIAL OUTPUT V 0 0 5 1 0 1 5 2 0 2 5 SLEW RATE V ns Figure 13 PLL Figure of Merit vs Slew Rate at REFIN REFIN 1 0 0 2 1 0 e o e M 1 e 0 5 10 15 20 TIME ns Figure 14 LVPECL Output Differential at 100 MHz N a NOD UNE CA 0 1 TIME ns Figure 15 LVPECL Output Differential at 1600 MHz N DIFFERENTIAL OUTPUT V 07972 136 DIFFERENTIAL OUTPUT V 5 07972 014 DIFFERENTIAL OUTPUT V 07972 015 Rev A Page 19 of 76 0 4 2 0 4 2 8 0 8 5 10 15 TIME ns Figure 16 LVDS Output Differential at 100 MHz AD9516 5 20 o TIME ns Figure 17 LVDS Output Differential at 800 MHz 20 40 60 TIME ns Figure 18 CMOS Output at 25 MHz 100 07972 016 07972 017 07972 018 AD9516 5
14. DETAILED BLOCK DIAGRA REF SEL vs GND RSET REFMON CPRSET VCP Q DISTRIBUTION REFERENCE LD LOCK DETECT R PROGRAMMABLE DIVIDER R DELAY STATUS REFIN REF1 REFIN REF2 61 STATUS n eae i PHASE CHARGE 1 1 PROGRAMMABLE FREQUENCY PUMP PRESCALER COUNTERS 1 N DELAY DETECTOR 1 1 N DIVIDER PLL REFERENCE DIVIDE BY STATUS 2 3 4 5 OR 6 CLK CLK QO OUTO DIVIDE BY O OUTO pp d 4 32 OUT1 DIGITAL SYNC LOGIC OUT RESET QO OUT2 DIVIDE BY OUT2 1TO 32 sc K OUT3 SDIO OUT3 5 C CS O OUT4 DIVIDE BY O OUT4 1TO 32 Q OUTS OUTS OUT6 OUT6A OUT6 OUT6B DIVIDE BY DIVIDE BY 1TO 32 1TO 32 OUT OUT7A Q OUT OUT7B OUTS OUT8A OUTS OUT8B DIVIDE BY DIVIDE BY 1TO 32 1TO 32 AD9516 5 OUT9 OUT9A O OUTS OUT9B Figure 32 Detailed Block Diagram Rev A Page 24 of 76 07972 002 THEORY OF OPERATION REF SEL DISTRIBUTION REFERENCE AD9516 5 REFMON Em CPRSET VCP REFERENCE SWITCHOVER E REFIN REF1 REFIN REF2 P P 1 PRESCALER DIVIDE BY 2 3 4 5 OR6 UAR DIGITAL RESET D SCLK SERIAL De CONTROL SDO PORT cs DIVIDE BY 1TO32 DIVIDE BY 1TO32 AD9516 5 Ht LOCK DETECT PLL REFERENCE HOLD CHARGE PUMP PHASE FREQUENCY DETECTOR DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 3
15. Figure 64 CMOS Output with Far End Termination Because of the limitations of single ended CMOS clocking consider using differential outputs when driving high speed signals over long traces The AD9516 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters Rev A Page 73 of 76 AD9516 5 OUTLINE DIMENSI PIN 1 INDICATOR UNS 9 00 0 60 MAX BSC SQ 0 60 MAX PIN 1 L NN UUUUUU L INDICATOR 2 0 49 B 0 50 6 35 TOP VIEW BSC EXPOSED PAD 6 20 SQ BOTTOM VIEW 0 50 0 40 32 1 0 30 aaaanaanannnnnn 7 50 100 12 0 80 MAK __ d 0 85 0 65 TYP FOR PROPER CONNECTION OF pm TTL THE PIN CONFIGURATION AND i DTH Li 002 FUNCTION DESCRIPTIONS SEXTING SECTION OF THIS DATA SHEET PLANE 0 20 REF 2 COMPLIANT TO JEDEC STANDARDS MO 220 VMMD 4 8 Figure 65 64 Lead Lead Frame Chip Scale Package LFCSP VQ 9 mm x 9 mm Body Very Thin Quad CP 64 4 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option AD9516 5BCPZ 40 C to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP CP 64 4 AD9516 5BCPZ REEL7 40 C to 85 C 64 Lead Lead Frame Chip Scale Package LFCSP_VQ CP 64 4 AD9516 5 PCBZ Evaluation Board 17 RoHS Compliant Part Re
16. Long Delay Range Zero Scale 0 3 5 Full Scale 0 24 5 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature 2 Corresponding CMOS drivers set to OUTxA for noninverting and OUTXB for inverting x 6 7 8 or 9 3 The maximum delay that can be used is a little less than one half the period of the clock A longer delay disables the output Incremental delay does not include propagation delay 5 All delays between zero scale and full scale can be estimated by linear interpolation Rev A Page 13 of 76 AD9516 5 Timing Diagrams tox DIFFERENTIAL gt lt 07972 060 g temos Figure 2 CLK CLK to Clock Output Timing Divider 1 Figure 4 LVDS Timing Differential DIFFERENTIAL SINGLE ENDED 07972 061 e 2 1 trc 14 1 Figure 3 LVPECL Timing Differential Figure 5 CMOS Timing Single Ended 10 pF Load Rev A Page 14 of 76 07972 062 07972 063 ABSOLUTE MAXIMUM RATINGS Table 15 Parameter Rating VS VS LVPECL to GND 0 3V to 3 6V VCP to GND 0 3V to 45 8 V REFIN REFIN to GND 0 3 V to VS 0 3 V REFIN to REFIN 3 3 V to 3 3 V RSET to GND 0 3V to VS 0 3 V CPRSET to GND 0 3V to VS 0 3 V CLK CLK to GND 0 3V to VS 0 3 V CLK to CLK 1 2 V to 1 2 V SCLK SDIO SDO CS to GND 0 3 V to VS 0 3 V OUTO OUTO OUT1
17. SWITCHOVER REFIN REF1 REFIN REF2 REFMON CPRSET VCP O O LD LOCK DETECT PROGRAMMABLE R DELAY PHASE FREQUENCY CHARGE PUMP DETECTOR PROGRAMMABLE N DELAY L STATUS 07972 064 Figure 35 PLL Functional Blocks The AD9516 includes on chip PLL blocks that can be used with an external VCO or VCXO to create a complete phase locked loop The PLL requires an external loop filter which usually consists of a small number of capacitors and resistors The configuration and components of the loop filter help to establish the loop bandwidth and stability of the PLL The AD9516 PLL is useful for generating clock frequencies from a supplied reference frequency This includes conversion of reference frequencies to much higher frequencies for subsequent division and distribution In addition the PLL can be exploited to clean up jitter and phase noise on a noisy reference The exact choices of PLL parameters and loop dynamics are very application specific The flexibility and depth of the PLL allow the part to be tailored to function in many different applications and signal environments Configuration of the PLL Configuration of the PLL is accomplished by programming the various settings for the R divider N divider PFD polarity and charge pump current The combination of these settings determines the PLL loop bandwidth These are managed through programm
18. input of the channel dividers VCO divider out or CLK When a divider is bypassed Dx 1 Otherwise Dx N 1 M 1 N M 2 This allows each channel divider to divide by any integer from 2 to 32 Duty Cycle and Duty Cycle Correction 0 1 and 2 The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions e What are M and N values for the channel s 5 the DCC enabled s Isthe VCO divider used e What is the CLK input duty cycle vco Dx Output Duty Cycle Divider N M 2 DCCOFF 1 DCCOFF 0 Even 1 divider 5096 5096 bypassed Odd 3 1 divider 33 396 50 bypassed Odd 5 1 divider 40 50 bypassed Even Even N 1 50 requires N Odd 2 Even Odd 1 5096 requires 1 Odd 2 Table 31 Duty Cycle with VCO Divider Input Duty Cycle Is X vco Dx Output Duty Cycle Divider N M 2 DCCOFF 1 DCCOFF 0 Even 1 divider 50 50 bypassed Odd 3 1 divider 33 3 1 X 3 bypassed Odd 5 1 divider 40 2 5 bypassed Even Even 1 50 2 Odd 1 50 2 requires 1 Odd 3 Even 1 50 2 Odd Odd 1 3N 4 X96 6N 9 2 requires 1 5 Even 1 50 2 requires 5 Odd 1 5N 7 X
19. 1 of the Divider 4 2 input during which the Divider 4 2 output stays high A value of 0x7 means that the divider is low for eight input clock cycles default Ox1 Ox1A1 5 Bypass Divider 4 2 Bypasses and powers down 4 2 divider logic routes clock to 4 2 output 0 does not bypass default 1 bypasses 4 Bypass Divider 4 1 Bypasses and powers down 4 1 divider logic routes clock to 4 1 output 0 does not bypass default 1 bypasses 3 Divider 4 nosync No sync 0 obeys chip level SYNC signal default 1 ignores chip level SYNC signal Rev A Page 68 of 76 AD9516 5 Reg Addr Hex Bits Name Description 2 Divider 4 force high Forces Divider 4 output high Requires that the Divider 4 nosync bit Bit 3 also be set 0 forces low default 1 forces high 1 Start High Divider 4 2 Divider 4 2 starts high low 0 starts low default 1 starts high 0 Start High Divider 4 1 Divider 4 1 starts high low 0 starts low default 1 starts high Ox1A2 0 Divider 4 DCCOFF Duty cycle correction function 0 enables duty cycle correction default 1 disables duty cycle correction Table 55 VCO Divider and CLK Input Reg Addr Hex Bits Name Description 2 0 VCO divider 2 1 0 Divide 0 0 0 2 0 0 1 3 0 1 0 4 default 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 Output static 1 1 1 Output static Ox1E1 4 Power dow
20. 2 Soft reset Soft reset 1 soft reset restores default values to internal registers Not self clearing Must be cleared to Ob to complete reset operation 1 LSB first MSB or LSB data orientation 0 data oriented MSB first addressing decrements default 1 data oriented LSB first addressing increments 0 SDO active Selects unidirectional or bidirectional data transfer mode 0 SDIO pin used for write and read SDO set to high impedance bidirectional mode default 1 SDO used for read SDIO used for write unidirectional mode 0x003 7 0 Part ID read only Uniquely identifies the dash version 0 through 5 of the AD9516 AD9516 0 0 01 AD9516 1 0x41 AD9516 2 0x81 AD9516 3 0x43 AD9516 4 0xC3 AD9516 5 0xC1 0x004 0 Read back active registers Selects register bank used for a readback 0 reads back buffer registers default 1 reads back active registers Rev A Page 52 of 76 Table 49 PLL AD9516 5 Reg Addr Hex Bits Name Description 0x010 7 PFD polarity Sets the PFD polarity 0 positive higher control voltage produces higher frequency default 1 negative higher control voltage produces lower frequency 6 4 CP current Charge pump current with CPRSET 5 1 6 5 4 ICP mA 0 0 0 0 6 0 0 1 1 2 0 1 0 1 8 0 1 1 2 4 1 0 0 3 0 1 0 1 3 6 1 1 0 42 1 1 1
21. 4 8 default 3 2 CP mode Charge pump operating mode 3 2 Charge Pump Mode 0 0 High impedance state 0 1 Force source current pump up 1 0 Force sink current pump down 1 1 Normal operation default 1 0 PLLpower down PLLoperating mode 1 0 Mode 0 0 Normal operation 0 1 Asynchronous power down default 1 0 Normal operation 1 1 Synchronous power down 0x011 7 0 14 bit R divider R divider LSBs lower eight bits default 0x01 Bits 7 0 LSB 0x012 5 0 14 bit R divider R divider MSBs upper six bits default 0x00 Bits 13 8 MSB 0x013 5 0 6 bit A counter A counter part of N divider default 0x00 0x014 7 0 13 bit B counter B counter part of N divider lower eight bits default 0x03 Bits 7 0 LSB 0x015 4 0 13 bit B counter B counter part of N divider upper five bits default 0x00 Bits 12 8 MSB 0x016 7 Set CP pin Sets the CP pin to one half of the Vcp supply voltage to Vcp 2 0 CP normal operation default 1 CP pin set to Vcp 2 6 Reset R counter Resets R counter R divider This bit is not self clearing 0 normal default 1 holds the R counter in reset 5 Reset AandB Resets A and B counters part of N divider counters 0 normal default This bit is not self clearing 1 holds the A and B counters in reset 4 Reset all counters Resets R A and B counters This bit is not self clearing 0 normal default 1 holds the R A and B counters in reset
22. 50 Even Even Nx Mx Even 5090 Nx2 Mx Odd Even Nx Mx Even 50 Nx2 Mx Even Odd Mx Nxi 1 Even 50 Nx2 Mx Odd Odd Mx Nxi 1 Even 50 Nx2 Mx Even Odd Nx 1 Odd 50 Nx2 1 Odd Odd Nxi 1 Odd 50 Nx2 1 vco Dx Divider Nx Mx 2 Nx2 Mx2 2 Output Duty Cycle Even Bypassed Bypassed 5096 Odd 3 Bypassed Bypassed 33 3 Odd 5 Bypassed Bypassed 40 Even Even odd Bypassed 1 Mx 2 Odd Even odd Bypassed 1 Mx 2 Even Even odd Even odd Nx2 1 Nx2 2 Even odd Even odd 1 Nx2 Mx2 2 Rev A Page 38 of 76 Table 38 Divider 3 and Divider 4 Duty Cycle Divider Used Duty Cycle Correction On DCCOFF 0 VCO Divider Input Duty Cycle X AD9516 5 Table 39 Divider 3 and Divider 4 Duty Cycle VCO Divider Not Used Duty Cycle Correction On DCCOFF 0 Dx vco Output Divider 2 2 Duty Cycle Even Bypassed Bypassed 5096 Odd 23 Bypassed Bypassed 1 X96 3 5 Bypassed 2 5 Even Even Bypassed 5096 Nx1 Mx Odd Even Bypassed 5096 Mx Even Odd Bypassed 5096 Mx 1 Odd Odd Bypassed 4 X 1 6 9 Odd 5 Odd Bypassed bNxa 7 X
23. MHz Register Description 0x1E1 0 1b Bypass the VCO divider as source for distribution section 0x010 1 0 200b normal operation PLL on along with other appropriate PLL settings in Register 0x010 to Register The register settings shown in Table 21 are the default values of these registers at power up or after a reset operation If the contents of the registers are altered by prior programming after power up or reset these registers can also be set intentionally to these values Table 21 Default Settings of Some PLL Registers An external VCO VCXO requires an external loop filter that must be connected between CP and the tuning pin of the VCO VCXO This loop filter determines the loop bandwidth and stability of the PLL Ensure that the correct PFD polarity is selected for the VCO VCXO that is being used Table 20 Setting the PFD Polarity Register Description 0x010 1 0 01b PLL asynchronous power down PLL off 0x1E0 2 0 0106 Set VCO divider 4 0x1E1 0 Ob Use the VCO divider When using the internal PLL with an external VCO the PLL must be turned on Table 22 Settings When Using an External VCO Register Description Register Description 0x010 7 0b PFD polarity positive higher control voltage produces higher frequency PFD polarity negative higher control voltage produces lower frequency 0x010 7 1b After the appropriate register va
24. O H 7 Clock Output Absolute Time Jitter Clock Generation Using External VCXO 8 Clock Output Additive Time Jitter VCO Divider Not Used 8 Clock Output Additive Time Jitter VCO Divider Used 9 Delay Block Additive Time Jitter sss 9 Serial Control Port T 10 PD RESET and SYNC Pius icu 10 LD STATUS REFMON 1 Power SIS Re 1 Timing Characteristics ettet 13 Absolute Maximum Ratings 15 Thermal Resistance ESD Caution ERUNT E 15 Pin Configuration and Function Descriptions 16 Typical Performance Characteristics 18 Terminology iie iioii a e E A RO RES bs 23 Detailed Block Diagram 24 Theory 20f ODGratiOn ect eR GIUM 25 Operational Configurations eerte 25 oot tte E es 31 Clock Distribution reete eee teet 35 Reset Modes 43 Power Down Modes 43 Serial Control Port pec 44 Serial Control Port Pin 44 General Operation of Serial Control 44 Instruction Word 16 Bits sss 45 MSB LSB First Transfers Thermal Performance essere 48 Maps RR EP 49 Register Map Overview 49 Register Map Descriptions esee 52 Applications Information 71 Frequency Planni
25. OUTPUT V DIFFERENTIAL SWING mV p p o 1600 1400 1200 1000 0 1 2 N 2 4 6 8 10 1 TIME ns Figure 19 CMOS Output at 250 MHz FREQUENCY GHz Figure 20 LVPECL Differential Swing vs Frequency Using a Differential Probe Across the Output Pair 07972 019 07972 020 DIFFERENTIAL SWING mV p p OUTPUT SWING V Rev A Page 20 of 76 LI 500 e 0 100 200 300 400 500 600 70 8 FREQUENCY MHz Figure 21 LVDS Differential Swing vs Frequency Using a Differential Probe Across the Output Pair 0 100 200 300 400 500 600 OUTPUT FREQUENCY MHz Figure 22 CMOS Output Swing vs Frequency and Capacitive Load 07972 021 07972 133 AD9516 5 PHASE NOISE dBc Hz PHASE NOISE dBc Hz PHASE NOISE dBc Hz
26. Only Bits A9 A0 are needed to cover the range of the 0x232 registers used by the AD9516 Bits A12 A10 must always be set to 0b For multibyte transfers this address is the starting byte address In MSB first mode subsequent bytes decrement the address MSB LSB FIRST TRANSFERS The AD9516 instruction word and byte data can be MSB first or LSB first Any data written to Register 0x000 must be mirrored the upper four bits Bits 7 4 must mirror the lower four bits Bits 3 0 This makes it irrelevant whether LSB first or MSB first is in effect As an example of this mirroring see the default setting for this register 0x000 which mirrors Bit 4 and Bit 3 This sets the long instruction mode which is the default and the only mode that is supported The default for the AD9516 is MSB first When LSB first is set by Register 0x000 1 and Register 0 000 6 it takes effect immediately because it affects only the operation of the serial control port and does not require that an update be executed When MSB first mode is active the instruction and data bytes must be written from MSB to LSB Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte Subsequent data bytes must follow in order from high address to low address In MSB first mode the serial control port internal address generator decrements for each data byte of the multibyte transfer cyc
27. Register 0x232 0 1 to take effect CHANNEL DIVIDER CHANNEL DIVIDER OUTPUT STATIC OUTPUT CLOCKING SYNC PIN OUTPUT OF CHANNEL DIVIDER T 1 1 pe 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT 1 CYCLE AT VCO DIVIDER INPUT 07972 073 Figure 45 SYNC Timing When VCO Divider Is Used CLK or VCO Is Input CHANNEL DIVIDER OUTPUT CLOCKING CHANNEL DIVIDER OUTPUT STATIC CHANNEL DIVIDER OUTPUT CLOCKING gu neces 1 1 1 INPUT J UU U U FLU LT LT LU LT LT L L L L L L L LU L LL L L LT L INPUT TO CHANNEL DIVIDER 1 2 3 4 SYNC PIN CHANNEL DIVIDER 1 1 1 14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT 1 CYCLE AT CLK INPUT zuo 07972 074 Figure 46 SYNC Timing When VCO Divider Is Not Used CLK Input Only Rev A Page 41 of 76 AD9516 5 A sync operation brings all outputs that have not been excluded by the nosync bit to a preset condition before allowing the outputs to begin clocking in synchronicity The preset condition takes into account the settings in each of the channel s start high bit and its phase offset These settings govern both the static state of each output when the sync operation is happening and the state and relative phase of the outputs when they begin clocking again upon completion of the sync operation Between outputs and after synchronization this allows for the setting of phase offsets The AD9516 outputs are i
28. between CP and the tuning pin of the VCO This loop filter determines the loop bandwidth and stability of the PLL Ensure that the correct PFD polarity is selected for the VCO that is being used Table 23 Setting the PFD Polarity Register Description 0x010 7 0b PFD polarity positive higher control voltage produces higher frequency PFD polarity negative higher control voltage produces lower frequency 0x010 7 1b After the appropriate register values are programmed Register 0x232 must be set to 0x01 for the values to take effect Rev A Page 26 of 76 AD9516 5 REF_SEL vs GND RSET REFMON CPRSET VCP O O O DISTRIBUTION REFERENCE REFERENCE SWITCHOVER REF1 p R DELAY PLL REFERENCE REFIN REF1 REFIN REF2 PHASE PROGRAMMABLE FREQUENCY CHARGE N DELAY DETECTOR DIVIDE BY O STATUS 2 3 4 5 OR 6 DIVIDE BY O OUTO DO 1 32 LVPECL SYNC Till DIGITAL RESET OUT2 DIVIDE BY OUT2 1TO 32 SCLK QO OUT3 SERIAL Q OUT3 SDI0 CONTROL 500 PORT DIVIDE BY OUT4 4 32 OUT6 OUT6A C OUT6 OUT6B DIVIDE BY DIVIDE BY 1TO 32 1TO 32 OUT7 OUT7A OUT7 OUT7B DIVIDE BY DIVIDE BY 1TO32 1TO32 AD9516 5 OUTS OUT9A 07972 029 Figure 34 High Frequency Clock Distribution CLK or External VCO 1600 MHz Mode 2 Rev A Page 27 of 76 AD9516 5 Phase Locked Loop PLL REF_SEL vs Q O O Q REFERENCE
29. chip level SYNC signal default 1 ignores chip level SYNC signal Rev A Page 66 of 76 AD9516 5 Reg Addr Hex Bits Name Description Divider 1 force high Forces divider output to high This operation requires that the Divider 1 nosync bit Bit 6 also be set This bit has no effect if the Divider 1 bypass bit Bit 7 is set 0 normal operation default 1 divider output forced to the setting of the Divider 1 start high bit Divider 1 start high Selects clock output to start high or start low 0 starts low default 1 starts high 3 0 Divider 1 phase offset Phase offset default 0x0 0x195 Divider 1 direct to output Connects OUT2 and OUT3 to Divider 1 or directly to CLK input 0 OUT2 and OUT3 are connected to Divider 1 default 1 If Register 0x1E1 0 Ob the CLK is routed directly to OUT2 and OUT3 If Register 1b this has no effect Divider 1 DCCOFF Duty cycle correction function 0 enables duty cycle correction default 1 disables duty cycle correction 0x196 Divider 2 low cycles Number of clock cycles minus 1 of the Divider 2 input during which the Divider 2 output stays low A value of 0x7 means that the divider is low for eight input clock cycles default 0x0 Divider 2 high cycles Number of clock cycles minus 1 of the Divider 2 input during which the Divider 2 output stays high A value of 0x7 mea
30. fs rms Calculated from SNR of ADC method DCC not used Divider 16 for even divides CLK 500 MHz 100 MHz 245 fs rms Calculated from SNR of ADC method DCC on Divider 5 LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL uses rising edge of clock signal CLK 1 6 GHz LVDS 800 MHz Divider 2 85 fs rms Bandwidth 12 kHz to 20 MHz VCO Divider Not Used CLK 1 GHz LVDS 200 MHz Divider 5 113 fs rms Bandwidth 12 kHz to 20 MHz CLK 1 6 GHz LVDS 100 MHz Divider 16 280 fs rms Calculated from SNR of ADC method DCC not used for even divides CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL uses rising edge of clock signal CLK 1 6 GHz CMOS 100 MHz Divider 16 365 fs rms Calculated from SNR of ADC method DCC not used for even divides Rev A Page 8 of 76 CLOCK OUTPUT ADDITIVE TIME JITTER VCO DIVIDER USED AD9516 5 Table 8 Parameter Min Typ Unit Test Conditions Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL uses rising edge of clock signal CLK 2 4 GHz VCO Div 2 LVPECL 100 MHz 210 fsrms Calculated from SNR of ADC method Divider 12 Duty Cycle Correction Off LVDS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL uses rising edge of clock signal CLK 2 4 GHz VCO Div 2 LVDS 100 MHz 285 fsrms Calculat
31. if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down default Off 1 1 Total power down reference off use only if there are no external load resistors Off OxOF2 4 OUT2 invert Sets the output polarity 0 noninverting default 1 inverting 3 2 OUT2LVPECL Sets the LVPECL output differential voltage Vor differential 3 2 Van mV voltage 400 O 1 600 1 O 780 default 1 1 960 1 0 OUT2 LVPECL power down modes power down 1 o Mode Output 0 0 Normal operation default On O 1 Partial power down reference on use only if there are no external load resistors Off 1 O Partial power down reference on safe LVPECL power down Off 1 1 Total power down reference off use only if there are no external load resistors Off OxOF3 4 OUT3 invert Sets the output polarity 0 noninverting default 1 inverting 3 2 OUT3LVPECL Sets the LVPECL output differential voltage Vor differential 3 2 Vo mV voltage 400 O 1 600 1 O 780 default 1 1 960 1 0 OUT3 LVPECL power down modes power down 1 o Mode Output 0 0 Normal operation On O 1 Partial power down reference on use only if there are no external load resistors Off 1 0 Partial power down reference on safe LVPECL power down default Off 1 1 Total power down reference off use only if there no external load resistors Off
32. in the clock signal at that output D uos HS vco BYPASS CLK DIVIDER FINE DELAY ADJUST OUTPUT DRIVERS BYPASS CMOS OUTN LVDS OUTN FINE DELAY ADJUST Figure 44 Fine Delay OUT6 to OUT9 The amount of delay applied to the clock signal is determined by programming four registers per output see Table 41 Table 41 Setting Analog Fine Delays 07972 072 OUTPUT Ramp Ramp Delay Delay LVDS CMOS Capacitors Current Fraction Bypass OUT6 0x0A1 5 3 Ox0A1 2 0 OxOA2 5 0 OxOAO O OUT7 Ox0A4 5 3 OxOA4 2 0 0 0 5 5 0 OxOAS3 O OUT8 0x0A7 5 3 0 0 7 2 0 0 0 8 5 0 OxOAG O OUT9 5 3 OxOAA 2 0 OxOAB 5 0 OxOA9 O Rev A Page 40 of 76 The following values and equations are used to calculate the delay of the delay block Tramp uA 200 x Ramp Current 1 Number of Capacitors Number of Bits 0 in Ramp Capacitors 1 Example 101 1 1 2 110 1 1 2 100 2 1 3 001 2 1 3 111 0 1 1 Delay Range ns 200 No of Caps 3 Inaur 1 3286 No of Caps E E x6 RAMP Offset ns 0 34 1600 I pamp 10 4 Delay Full Scale ns Delay Range Offset Fine Delay ns Delay Range x Delay Fraction x 1 63 Offset Note that only delay fraction values up to 47 decimal 101111b 0x02F are supported In no case can the fine delay exceed one half o
33. mode the charge pump stays in a high impedance state as long as there is no reference clock present As in the external holdover mode the B counter in the N divider is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event This helps to align the edges out of the R and N dividers for faster settling of the PLL and reduce frequency errors during settling Because the prescaler is not reset this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out After leaving holdover the loop then reacquires lock and the LD pin must charge if Register 0x01D 3 1 before it can re enter holdover CP high impedance The holdover function always responds to the state of the currently selected reference Register 0 01 If the loop loses lock during a reference switchover see the Reference Switchover section holdover is triggered briefly until the next reference clock edge at the PFD AD9516 5 PLL ENABLED LOOP OUT OF LOCK DIGITAL LOCK DETECT SIGNAL GOES LOW WHEN THE LOOP LEAVES LOCK AS DETERMINED BY THE PHASE DIFFERENCE AT THE INPUT OF THE PFD ANALOG LOCK DETECT PIN INDICATES LOCK WAS PREVIOUSLY ACHIEVED REGISTER 0x1D 3 1 USE LD PIN VOLTAGE WITH HOLDOVER REGISTER 0x1D 3 0 IGNORE LD PIN VOLTAGE TREAT LD PIN AS ALWAYS HIGH WAS LD PIN HIGH WHEN DLD WENT LOW CHARGE PUMP
34. output of the R divider goes to of the PFD inputs to be compared with the VCO frequency divided by the N divider The frequency applied to the PFD must not exceed the maximum allowable frequency which depends on the antibacklash pulse setting see Table 2 The R counter has its own reset The R counter can be reset via the shared reset bit of the R A and B counters It can also be reset by a SYNC operation VCXO VCO Feedback Divider N P A B The N divider is a combination of a prescaler P and two counters A and B The total divider value is where P can 2 4 8 16 or 32 Prescaler The prescaler of the AD9516 allows for two modes of operation a fixed divide FD mode of 1 2 or 3 and a dual modulus DM mode where the prescaler divides by P and P 1 2 and 3 4 and 5 8 and 9 16 and 17 or 32 and 33 The prescaler modes of operation are given in Table 49 Register 0x016 2 0 Not all modes are available at all frequencies see Table 2 When operating the AD9516 in dual modulus mode P P 1 the equation used to relate the input reference frequency to the VCO output frequency is fvco fas R x P x A frer x N R However when operating the prescaler in FD Mode 1 FD Mode 2 or FD Mode 3 the A counter is not used A 0 and the equation simplifies to fvco frer R x P x B frer x N R When A 0 the divide is a fixed divide of P 2 4 8 16 32 in which case the
35. previous equation also applies By using combinations of DM and FD modes the AD9516 can achieve values of N all the way down to N 1 and up to N 26 2175 Table 24 shows how a 10 MHz reference input can be locked to any integer multiple of N Table 24 Using a 10 MHz Reference to Generate Different VCO Frequencies frer MHz P A B N fvco MHz Mode Conditions Comments 10 1 1 X 1 1 10 FD 1 1 B counters are bypassed 10 1 2 x 1 2 20 FD 2 1 B counters are bypassed 10 1 1 x 3 3 30 FD A counter is bypassed 10 1 1 x 4 4 40 FD A counter is bypassed 10 1 1 x 5 5 50 FD A counter is bypassed 10 1 2 x 3 6 60 FD A counter is bypassed 10 1 2 0 3 6 60 DM 10 1 2 1 3 7 70 DM Maximum frequency into prescaler in P 2 2 3 mode is 200 MHz If N 7 or N 11 is desired for prescaler input frequency of 200 MHz to 300 MHz use 1 and N 7 or 11 respectively 10 1 2 2 3 8 80 DM 10 1 2 1 4 9 90 DM 10 1 8 6 18 150 1500 DM 10 1 8 7 18 151 1510 DM 10 1 16 7 9 151 1510 DM 10 10 32 6 47 1510 1510 DM 10 1 8 0 25 200 2000 DM 10 1 16 14 16 270 2700 DM 8 is not allowed 2700 8 gt 300 MHz P 32 is not allowed A gt B not allowed 10 10 32 22 84 2710 2710 DM P 32 A 22 B 84 16 is also permitted 1X don t care Rev A Page 30 of 76 AD9516 5 Note that the same value of N can be derived in different ways as illustrated by
36. reference to PLL differential reference when in differential mode 1 0 0 1 0 0 DYN Unselected reference to PLL not available in differential mode 1 0 0 1 0 1 LVL Status of selected reference status of differential reference active high 1 0 0 1 1 0 LVL Status of unselected reference not available in differential mode active high 1 1 1 1 LVL Status of REF1 frequency active high 1 0 1 0 O LVL Status of REF2 frequency active high 1 0 1 0 0 1 LVL Status of REF1 frequency AND status of REF2 frequency 1 0 1 0 1 0 LVL DLD AND status of selected reference AND status of CLK 1 0 1 0 1 1 LVL Status of CLK frequency active high 1 0 1 1 0 0 LVL Selected reference low REF1 high REF2 1 0 1 1 0 1 LVL Digital lock detect DLD active high 1 0 1 1 1 0 LVL Holdover active active high 1 0 1 1 1 1 LVL LD pin comparator output active high 1 1 0 0 O LVL VS PLL supply 1 1 0 0 0 1 DYN REF1 clock differential reference when in differential mode 1 1 0 0 1 0 DYN REF2 clock not available in differential mode 1 1 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 110 1 0 0 Unselected reference to PLL not available when in differential mode 1 1 0 1 0 1 LVL Status of selected reference status of differential reference active low 1 110 1 1 0 LVL Status of unselected reference not available in differential mode active low 1 1 0 1 1 1 LVL Status of REF1 frequency active lo
37. sleep mode AD9516 5 When the AD9516 is ina PD power down the chip is in the following state e The PLL is off asynchronous power down e The CLK input buffer is off e All dividers are off s All LVDS CMOS outputs are off e outputs are in safe off mode e The serial port is active and responds to commands If the AD9516 clock outputs must be synchronized to each other a SYNC is required upon exiting power down see the Synchronizing the Outputs SYNC Function section PLL Power Down The PLL section of the AD9516 can be selectively powered down There are three PLL operating modes that are set by Register 0x010 1 0 as shown in Table 49 In asynchronous power down mode the device powers down as soon as the registers are updated In synchronous power down mode the PLL power down is gated by the charge pump to prevent unwanted frequency jumps The device goes into power down on the occurrence of the next charge pump event after the registers are updated Distribution Power Down The distribution section can be powered down by writing to Register 0x230 1 1b This turns off the bias to the distribution section If the LVPECL power down mode is normal operation 00b it is possible for a low impedance load on that LVPECL output to draw significant current during this power down If the LVPECL power down mode is set to 11b the LVPECL output is not protected from reverse bias and can be damaged
38. start high registers see Table 40 Table 40 Setting Phase Offset and Division for Divider 3 and Divider 4 Start Phase Low High Divider High SH Offset PO CyclesM Cycles N 3 3 1 Ox19C 0 0x19A 3 0 0x199 7 4 0x199 3 0 3 2 0x19C 1 Ox19A 7 4 Ox19B 7 4 Ox19B 3 0 4 41 0x1A1 0 Ox19F 3 0 Ox19E 7 4 Ox19E 3 0 4 2 OXIAT 1 Ox19F 7 4 Ox1A0 7 4 Ox1A0 3 0 Note that the value stored in the register is equal to the number of cycles minus 1 For example Register 0x199 7 4 0001b equals two low cycles M 2 for Divider 3 1 Rev A Page 39 of 76 AD9516 5 Calculating the Fine Delay Let A delay in seconds 16 x SH 0 8 x PO 3 4 x PO 2 2 x PO 1 1 x PO 0 Tx period of the clock signal at the input to Dx in seconds Tx period of the clock signal at the input to Dx in seconds Case 1 When 15 and x2 lt 15 At Ox2 x Case 2 When lt 15 and gt 16 At x x Txa x2 16 Mx2 1 x Tx2 Case 3 When Ox gt 16 and x lt 15 At Oxi 16 Mxi 1 x Txi 0x x Tx2 Case 4 When x gt 16 and gt 16 Mx 16 1 Txi Ox 16 1 x Tx2 Fine Delay Adjust Divider 3 and Divider 4 Each AD9516 LVDS CMOS output OUT6 to 9 includes an analog delay element that can be programmed to give variable time delays
39. the Motorola SPI and Intel SSR protocols The serial control port allows read write access to all registers that configure the AD9516 Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats The AD9516 serial control port can be configured for a single bidirectional I O pin SDIO only or for two unidirectional I O pins SDIO SDO By default the AD9516 is in bidirectional mode long instruction long instruction is the only instruction mode supported SERIAL CONTROL PORT PIN DESCRIPTIONS SCLK serial clock is the serial shift clock This pin is an input SCLK is used to synchronize serial control port reads and writes Write data bits are registered on the rising edge of this clock and read data bits are registered on the falling edge This pin is internally pulled down by a 30 resistor to ground SDIO serial data input output is a dual purpose pin that acts as either an input only unidirectional mode or as both an input output bidirectional mode The AD9516 defaults to the bidirectional I O mode Register 0x000 0 0b SDO serial data output is used only in the unidirectional I O mode Register 0x000 0 1b as a separate output pin for reading back data CS chip select bar is an active low control that gates the read and write cycles When CS is high SDO and SDIO are in a high impedance state This pin is internally pulled up by a 30 resistor to VS SC
40. the case of N 12 The user can choose a fixed divide mode of P 2 with B 6 use the dual modulus mode of 2 3 with A 0 B 6 or use the dual modulus mode of 4 5 with A 0 B 3 A and Counters The B counter must be 23 or bypassed and unlike the R counter A 0 is actually zero When the prescaler is in dual modulus mode the A counter must be less than the B counter The maximum input frequency to the A or B counter is reflected in the maximum prescaler output frequency 300 MHz that is specified in Table 2 This is the prescaler input frequency external VCO or CLK divided by P For example a dual modulus mode of P 8 9 mode is not allowed if the external VCO frequency is greater than 2400 MHz because the frequency going to the A or B counter is too high When the B counter is bypassed B 1 the A counter should be set to 0 and the overall resulting divide is equal to the prescaler setting P The possible divide ratios in this mode are 1 2 3 4 8 16 and 32 This mode is useful only when an external VCO VCXO is used because the frequency range of the internal VCO requires an overall feedback divider that is greater than 32 Although manual reset is not normally required the A and B counters have their own reset bit Alternatively the A and B counters can be reset using the shared reset bit of the R A and B counters Note that these reset bits are not self clearing R A and B Counters SYNC Pin Reset The
41. thus allows the designer to fine tune the PLL loop bandwidth in either direction ADIsimCLK is a powerful PLL modeling tool that can downloaded from www analog com It is a very accurate tool for determining the optimal loop filter for a given application USING THE AD9516 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of its sampling clock An ADC can be thought of as a sampling mixer and any noise distortion or timing jitter on the clock is combined with the desired signal at the analog to digital output Clock integrity requirements scale with the analog input frequency and resolution with higher analog input frequency applications at 214 bit resolution being the most stringent The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored the available SNR can be expressed approximately by SNR dB 20 x log 2a where fais the highest analog frequency being digitized tj is the rms jitter on the sampling clock Figure 58 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits ENOB 110 i 305 SNR 20log 90 80 70 SNR dB ENOB 60 50 40 30 07972 044 fa MHz
42. x PD Tj Tease x PD where is the junction temperature is the case temperature C measured by the user at the top center of the package where is the ambient temperature Values of Oja are provided for package comparison and PCB design considerations can be used for a first order approximation of T by the following equation Values of are provided for package comparison and design considerations yr is the value from Table 46 PD is the power dissipation of the device see Table 13 Rev A Page 48 of 76 design considerations when an external heat sink is required Values of Tin are provided for package comparison and PCB REGISTER MAPS REGISTER MAP OVERVIEW Register addresses that are not listed in Table 47 as well as ones marked unused are not used and writing to those registers has no effect The user should write the default value only to the register addresses marked reserved Table 47 Register Map Overview AD9516 5 Ref Default Addr Value Hex Parameter Bit 7 MSB Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Hex Serial Port Configuration 0x000 Serial port SDO active LSB first Soft reset Long Long Soft reset LSB first SDO active 0x18 configuration instruction
43. 1 Number of clock cycles minus 1 of the Divider 3 1 input during which the Divider 3 1 output stays low A value of 0x7 means that the divider is low for eight input clock cycles default 0x2 3 0 High Cycles Divider 3 1 Number of clock cycles minus 1 of the Divider 3 1 input during which the Divider 3 1 output stays high A value of 0x7 means that the divider is low for eight input clock cycles default 0x2 Ox19A 7 4 Phase Offset Divider 3 2 Refers to LVDS CMOS channel divider function description default 0x0 3 0 Phase Offset Divider 3 1 Refers to LVDS CMOS channel divider function description default 0x0 0x19B 7 4 Low Cycles Divider 3 2 Number of clock cycles minus 1 of the Divider 3 2 input during which the Divider 3 2 output stays low A value of 0x7 means that the divider is low for eight input clock cycles default 0x1 3 0 High Cycles Divider 3 2 Number of clock cycles minus 1 of the Divider 3 2 input during which the Divider 3 2 output stays high A value of 0x7 means that the divider is low for eight input clock cycles default 0x1 0 19 5 55 Divider 3 2 Bypasses and powers down 3 2 divider logic routes clock to 3 2 output 0 does not bypass default 1 bypasses 4 Bypass Divider 3 1 Bypasses and powers down 3 1 divider logic routes clock to 3 1 output 0 does not bypass default 1 bypasses 3 Divider 3 nosync No sync 0 obeys chip level SYNC signal default 1 ignores chi
44. 10101 REF1 clock differential reference when in differential mode 1 1 DYN REF2 clock not available in differential mode 1 0101011 1 Selected reference to PLL differential reference when in differential mode 1 01011 0 O DYN Unselected reference to PLL not available in differential mode 1 01011 0 1 LVL Status of selected reference status of differential reference active high 1 01011 LVL Status of unselected reference not available in differential mode active high 1 LVL Status of REF1 frequency active high 1 Status of REF2 frequency active high 1 0 1 01011 LVL Status of REF1 frequency AND status of REF2 frequency 1 0 1 O 110 LVL DLD AND status of selected reference AND status of CLK 1 Status of CLK frequency active high 1 0 1 1 1 LVL Selected reference low REF1 high 2 1 0 1 1 0 1 LVL Digital lock detect DLD active high 1 0 1 1 1 0O LVL Holdover active active high 1 0 1 1 1 1 LVL Not available do not use 1 VS PLL supply 1 REF1 clock differential reference when in differential mode 1 1 0 REF2 clock not available in differential mode 1 1 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 1 0 1 0 0 DYN Unselected reference to PLL not available when in differential mode 1 1 0 1 0 1 LVL Status
45. 2 OUT6 OUT6A r3 gt OUT6 OUT6B DIVIDE BY LVDS CMOS 1T032 OUT7 OUT7A Q gt pa OUT7 OUT7B OUT8 OUT8A OUTS OUT8B LVDS CMOS DIVIDE BY 1TO 32 OUTS OUT9A bum OUTS OUT9B 07972 028 Figure 33 Clock Distribution or External VCO 1600 MHz Mode 1 OPERATIONAL CONFIGURATIONS The AD9516 can be configured in several ways These configurations must be set up by loading the control registers see Table 47 and Table 48 through Table 57 Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers Mode 1 Clock Distribution or External VCO lt 1600 MHz Mode 1 bypasses the VCO divider Mode 1 can be used only with an external clock source of 1600 MHz due to the maximum input frequency allowed at the channel dividers For dock distribution applications where the external clock is less than 1600 MHz use the register settings shown in Table 18 Table 18 Settings for Clock Distribution 1600 MHz Register Description 0x010 1 0 01b PLL asynchronous power down PLL off 0x1E1 0 1b Bypass the VCO divider as source for distribution section When using the internal PLL with an external VCO of lt 1600 MHz the PLL must be turned on Rev A Page 25 of 76 AD9516 5 Table 19 Settings for Using an Internal PLL with an External VCO lt 1600
46. 516 5 Parameter Min Typ Max Unit Test Conditions Comments POWER DELTAS INDIVIDUAL FUNCTIONS Power delta when a function is enabled disabled VCO Divider 30 mW VCO divider bypassed REFIN Differential 20 mW All references off to differential reference enabled REF1 REF2 Single Ended 4 mW All references off to REF1 or REF2 enabled differential reference not enabled PLL 75 mW PLL off to PLL on normal operation no reference enabled Channel Divider 30 mW Divider bypassed to divide by 2 to divide by 32 LVPECL Channel Divider Plus Output Driver 120 mW output on to one LVPECL output on that is enabling OUTO with OUT off Divider 0 enabled independent of frequency LVPECL Driver 90 mW Second LVPECL output turned on same channel that is enabling OUTO with OUT1 already on LVDS Channel Divider Plus Output Driver 140 mW LVDS output on to one LVDS output on that is enabling OUT8 with OUT off with Divider 4 1 enabled and Divider 4 2 bypassed see Figure 8 for dependence on output frequency LVDS Driver 50 mW Second LVDS output turned on same channel that is enabling 8 with OUT9 already on CMOS Channel Divider Plus Output Driver 100 mW Static no CMOS output on to one CMOS output on that is enabling OUT8A starting with OUT8 and OUTO off see Figure 9 for variation over output frequency CMOS Driver Second in Pair 0 mW Static second CMOS output same pair turned o
47. 9516 The first part writes a 16 bit instruction word into the AD9516 coincident with the first 16 SCLK rising edges The instruction word provides the AD9516 serial control port with information regarding the data transfer which is the second part of the communication cycle The instruction word defines whether the upcoming data transfer is a read or a write the number of bytes in the data transfer and the starting register address for the first byte of the data transfer Write If the instruction word is for a write operation the second part is the transfer of data into the serial control port buffer of the AD9516 Data bits are registered on the rising edge of SCLK The length of the transfer 1 2 or 3 bytes or streaming mode is indicated by two bits W1 W0 in the instruction byte When the transfer is 1 2 or 3 bytes but not streaming CS can be raised after each sequence of eight bits to stall the bus except after the last byte where it ends the cycle When the bus is stalled the serial transfer resumes when CS is lowered Raising CS on a nonbyte boundary resets the serial control port During a write streaming mode does not skip over reserved or unused registers therefore the user must know the correct bit pattern to write to the reserved registers to preserve proper operation of the part Refer to the register map see Table 47 to determine if the default value for reserved registers is nonzero It does not matter w
48. ANALOG DEVICES 14 Output Clock Generator AD9516 5 FEATURES Low phase noise phase locked loop PLL External VCO VCXO to 2 4 GHz optional 1 differential or 2 single ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover holdover modes Accepts LVPECL LVDS or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect selectable Six 1 6 GHz LVPECL outputs arranged in 3 groups Each group shares a 1 to 32 divider with coarse phase delay Additive output jitter 225 fs rms Channel to channel skew paired outputs of lt 10 ps Four 800 MHz LVDS outputs arranged in 2 groups Each group has 2 cascaded 1 to 32 dividers with coarse phase delay Additive output jitter 275 fs rms Fine delay adjust At on each LVDS output Each LVDS output can be reconfigured as two 250 MHz CMOS outputs Automatic synchronization of all outputs on power up Manual output synchronization available Available in 64 lead LFCSP APPLICATIONS Low jitter low phase noise clock distribution 10 40 100 Gb sec networking line cards including SONET Synchronous Ethernet OTU2 3 4 Forward error correction G 710 Clocking high speed ADCs DACs DDSs DDCs DUCs MxFEs High performance wireless transceivers ATE and high performance instrumentation GENERAL DESCRIPTION The AD9516 5 provides a multi output clock distribution function with subpicosecond jitter performance along wit
49. CL Output One Side of a Differential Output 42 LVPECL OUT2 LVPECL Output One Side of a Differential LVPECL Output 43 LVPECL OUT2 LVPECL Output One Side of a Differential LVPECL Output 45 LVDS or CMOS OUT7 OUT7B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 46 LVDS or CMOS OUT7 OUT7A LVDS CMOS Output One Side of a Differential LVDS Output or Single Ended CMOS Output 47 LVDS or CMOS OUT6 OUT6B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 48 LVDS or CMOS OUT6 OUT6A LVDS CMOS Output One Side of a Differential LVDS Output or Single Ended CMOS Output 52 LVPECL OUT LVPECL Output One Side of a Differential LVPECL Output 53 LVPECL OUT1 LVPECL Output One Side of a Differential Output 55 LVPECL OUTO LVPECL Output One Side of a Differential LVPECL Output 56 LVPECL OUTO LVPECL Output One Side of a Differential LVPECL Output 58 Current set RSET A resistor connected to this pin sets internal bias currents Nominal value 4 12 resistor 62 Current set CPRSET A resistor connected to this pin sets the CP current range Nominal value 5 1 resistor This resistor can be omitted if the PLL is not used 63 Reference REFIN REF2 Along with REFIN this pin is the differential input for the PLL reference input Alternatively this pin is a single ended input for REF2 Thi
50. CL outputs is 1 to 32 The LVDS CMOS outputs allow a range of divisions up to a maximum of 1024 The AD9516 5 is available in a 64 lead LFCSP and can be operated from a single 3 3 V supply An external VCO which requires an extended voltage range can be accommodated by connecting the charge pump supply Vcr to 5 5 V A separate LVPECL power supply can be from 2 375 V to 3 6 V nominal The AD9516 5 is specified for operation over the industrial range of 40 C to 85 C For applications requiring an integrated EEPROM or needing additional outputs the AD9520 5 and AD9522 5 are available 1 AD9516 is used throughout the data sheet to refer to all members of the AD9516 family However when AD9516 5 is used it refers to that specific member of the AD9516 family One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2009 2011 Analog Devices Inc All rights reserved AD9516 5 TABLE OF CONTENTS Features oce eoe LU Le uer 1 Applications iiie venen bei ten e rie CURIE 1 General Descriptio iesita iS RE S RES 1 Functional Block Diagram seen 1 REVISION History 3 Sp cifications eee ettet e re ERE 4 Power Supply Requirement 4 PLL Ch racteristiCs ete tete rette 4 Clock Inputs cn etre e SDN EN 6 Clock Outputs iore Ele bn ES 6 Clock Output Additive Phase Noise Distribution Only VCO Divider Not
51. Differential Selects the PLL reference mode differential or single ended Single ended must be selected for the automatic reference reference switchover or REF1 and REF2 to work 0 single ended reference mode default 1 differential reference mode Rev A Page 57 of 76 AD9516 5 Reg Addr Hex Bits Name Description 0x01D 4 PLL status Disables the PLL status register readback register disable 0 PLL status register enable default 1 PLL status register disable 3 LD pin Enables the LD pin voltage comparator This function is used with the LD pin current source lock detect mode When in comparator the internal automatic holdover mode this function enables the use of the voltage on the LD pin to determine if the enable PLL was previously in a locked state see Figure 41 Otherwise this function can be used with the REFMON and STATUS pins to monitor the voltage on the LD pin 0 disables LD pin comparator internal automatic holdover controller treats this pin as true high default 1 enables LD pin comparator 2 Holdover enable Along with Register 0 010 0 enables the holdover function 0 holdover disabled default 1 holdover enabled 1 External Enables the external hold control through the SYNC pin This disables the internal holdover mode holdover control 0 automatic holdover mode holdover controlled by automatic holdover circuit default 1 external holdover mo
52. External Loop Filter for PLL PLL Reference Inputs The AD9516 features a flexible PLL reference input circuit that allows a fully differential input or two separate single ended inputs The input frequency range for the reference inputs is specified in Table 2 Both the differential and the single ended inputs are self biased allowing for easy ac coupling of input signals The differential input and the single ended inputs share two pins REFIN REF1 and REFIN REF2 The desired reference input type is selected and controlled by Register 0x01C see Table 47 and Table 49 When the differential reference input is selected the self bias level of the two sides is offset slightly see Table 2 to prevent chattering of the input buffer when the reference is slow or missing The specification for this voltage level is found in Table 2 The input hysteresis increases the voltage swing required of the driver to overcome the offset The differential reference input can be driven by either ac coupled LVDS or ac coupled LVPECL signals The single ended inputs can be driven by either a dc coupled CMOS level signal or an ac coupled sine wave or square wave Each single ended input can be independently powered down when not needed to increase isolation and reduce power Either a differential or a single ended reference must be specifically enabled All PLL reference inputs are off by default The differential reference input is powered down whe
53. INS AD9516 5 Table 12 Parameter Min Typ Max Unit Test Conditions Comments OUTPUT CHARACTERISTICS When selected as a digital output CMOS there are other modes in which these pins are not CMOS digital outputs see Table 49 Register 0x017 Register 0x01A and Register 0x01B Output Voltage High Vou 2 7 V Output Voltage Low 0 4 V MAXIMUM TOGGLE RATE 100 MHz Applies when muxis set to any divider or counter output or PFD up down pulse also applies in analog lock detect mode usually debug mode only beware that spurs may couple to output when any of these pins are toggling ANALOG LOCK DETECT Capacitance 3 pF On chip capacitance used to calculate RC time constant for analog lock detect readback use a pull up resistor REF1 REF2 AND CLK FREQUENCY STATUS MONITOR Normal Range 1 02 MHz Frequency above which the monitor always indicates the presence of the reference Extended Range 8 kHz Frequency above which the monitor always indicates the presence of the reference LD PIN COMPARATOR Trip Point 1 6 V Hysteresis 260 mV POWER DISSIPATION Table 13 Parameter Min Unit Test Conditions Comments POWER DISSIPATION CHIP The values in this table include all power supplies unless otherwise noted the power deltas for individual drivers are at dc see Figure 7 Figure 8 and Figure 9 for power dissipation vs output frequency Power On Default 1 0 1 2 No clock no programming def
54. IS MADE HIGH IMPEDANCE PLL COUNTERS CONTINUE OPERATING NORMALLY HIGH IMPEDANCE CHARGE PUMP CHARGE PUMP REMAINS HIGH IMPEDANCE UNTIL THE REFERENCE HAS RETURNED REFERENCE EDGE AT PFD YES YES TAKE CHARGE PUMP OUT OF RELEASE CHARGE PUMP HIGH IMPEDANCE PLL CAN HIGH IMPEDANCE NOW RESETTLE WAIT FOR DLD TO GO HIGH THIS TAKES 5 TO 255 CYCLES PROGRAMMING OF THE DLD DELAY COUNTER WITH THE REFERENCE AND FEEDBACK CLOCKS INSIDE THE LOCK WINDOW AT THE PFD THIS ENSURES THAT THE HOLDOVER FUNCTION WAITS FOR THE PLL TO SETTLE AND LOCK BEFORE THE HOLDOVER FUNCTION CAN BE RETRIGGERED 07972 069 Figure 41 Flowchart of Automatic Internal Holdover Mode Rev A Page 33 of 76 AD9516 5 The following registers affect the internal automatic holdover function e Register 0x018 6 5 lock detect counter These bits change how many PFD cycles with edges inside the lock detect window are required for the DLD indicator to indicate lock This impacts the time required before the LD pin can begin to charge as well as the delay from the end of a holdover event until the holdover function can be reengaged e Register 0x018 3 disable digital lock detect This bit must be set to Ob to enable the DLD circuit Internal automatic holdover does not operate correctly without the DLD function enabled e Register 0x01A 5 0 lock detect pin output select Set this to 000100b to put it in the current source lock detect mo
55. ISTER DATA REGISTER N 1 DATA 07972 038 Figure 52 Serial Control Port Write MSB First 16 Bit Instruction Two Bytes of Data DON T CARE DON T CARE soo BONT GARE eee oo vo for os os 04 os veo vo o7 Josee vo 16 INSTRUCTION HEADER REGISTER DATA REGISTER N 1 DATA REGISTER 2 DATA REGISTER N 3 DATA poN T 07972 039 Figure 53 Serial Control Port Read MSB First 16 Bit Instruction Four Bytes of Data SCLK DON T CARE DON T CARE SDIO DON T CARE DON T CARE 07972 040 tov nm prs DATA BIT N DATA BIT N 1 Figure 55 Timing Diagram for Serial Control Port Register Read 07972 041 pontoane AD A2 A4 As A7 46 wo Je ox vs 07 v1 2 OTK DONT CARE 16 BIT INSTRUCTION HEADER REGISTER N DATA REGISTER N 1 DATA 07972 042 Figure 56 Serial Control Port Write LSB First 16 Bit Instruction Two Bytes of Data Rev A Page 46 of 76 SCLK SDIO AD9516 5 ts tc 07972 043 Figure 57 Serial Control Port Timing Write Table 45 Serial Control Port Timing Parameter Description tps Setup time between data and the rising edge of SCLK toH Hold time between data and the rising edge of SCLK tak Period of the clock t
56. L output stages there is the possibility of electrical overstress and breakdown under certain power down conditions For this reason the LVPECL outputs have several power down modes This includes a safe power down mode that continues to protect the output devices while powered down although it consumes somewhat more power than a total power down If the LVPECL output pins are terminated it is best to select the safe power down mode If the pins are not connected unused it is acceptable to use the total power down mode LVDS CMOS Outputs OUT6 to OUT9 OUT6 to OUT can be configured as either an LVDS differential output or as a pair of CMOS single ended outputs The LVDS outputs allow for selectable output current from 1 75 mA to 7 mA 07972 034 Figure 48 LVDS Output Simplified Equivalent Circuit with 3 5 mA Typical Current Source The LVDS output polarity can be set as noninverting or inverting which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change Each LVDS output can be powered down if not needed to save power OUT6 to OUT can also be CMOS outputs Each LVDS output can be configured to be two CMOS outputs This provides for up to eight CMOS outputs OUT6A OUT6B OUT7A OUT7B OUT8B OUT9A and OUT9B When an output is configured as CMOS the CMOS Output A is automatically turned on The CMOS Output B can be turned on or off independ
57. LD Vour O COMPARATOR REFMON OR STATUS 07972 068 Figure 39 Current Source Lock Detect External VCXO VCO Clock Input CLK CLK CLK is a differential input that can be used to drive the AD9516 clock distribution section This input can receive up to 2 4 GHz The pins are internally self biased and the input signal should be ac coupled via capacitors CLOCK INPUT STAGE vs CLK CLK O 2 5kO 2 5 07972 032 Figure 40 Equivalent Input Circuit The CLK CLK input can be used either as a distribution only input with the PLL off or as a feedback input for an external VCO VCXO using the PLL The CLK CLK input can be used for frequencies up to 2 4 GHz Holdover The AD9516 PLL has a holdover function Holdover is implemented by putting the charge pump into a high impedance state This is useful when the PLL reference clock is lost Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock Without this function the charge pump is placed into a constant pump up or pump down state resulting in a large VCO frequency shift Because the charge pump is placed in a high impedance state any leakage that occurs at the charge pump output or the VCO tuning node causes a drift of the VCO frequency This can be mitigated by using a loop filter that contains a large capacitive component because this drift is limited by the current leakage induced slew rate Ir
58. LK G AD9516 5 cs SERIAL SDO 1 CONTROL ssa 07972 036 Figure 50 Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9516 is initiated by pulling CS low CS stall high is supported in modes where three or fewer bytes of data plus instruction data are transferred see Table 42 In these modes CS can temporarily return high on any byte boundary allowing time for the system controller to process the next byte CS can go high on byte boundaries only and during either part instruction or data of the transfer During this period the serial control port state machine enters a wait state until all data is sent If the system controller decides to abort the transfer before all of the data is sent the state machine must be reset either by completing the remaining transfers or by returning the CS low for at least one complete SCLK cycle but less than eight SCLK cycles Raising the CS on a nonbyte boundary terminates the serial transfer and flushes the buffer In streaming mode see Table 42 any number of data bytes can be transferred in a continuous stream The register address is automatically incremented or decremented see the MSB LSB First Transfers section CS must be raised at the end of the last byte to be transferred thereby ending the stream mode Communication Cycle Instruction Plus Data There are two parts to a communication cycle with the AD
59. LL Reference Inputs and Reference Switchover SOCHONS ooo BOR S REIR OQ RE RT 29 AD9516 5 Changes to A and B Counters Digital Lock Detect DLD and Current Source Digital Lock Detect CSDLD Sections 31 Change to Holdover Section see Changes to Automatic Internal Holdover Mode Changes to Clock Distribution Section sss Changes to Channel Dividers LVDS CMOS Outputs SOCUOM EE 37 Change to the Instruction Word 16 Bits Section 45 Change to Figure P 46 Changes to Oja and Parameters Table 46 48 Changes to Register Address 0x003 and Register Address 0 01 Table 47 sss 49 Changes to Register Address 0x003 Table 48 52 Changes to Register Address 0x016 Bits 2 0 Table 49 54 Changes to Register Address 0x01C Bits 4 3 Table 49 57 Changes to Register Address 0x191 Register Address 0x194 and Register Address 0x197 Bit 5 Table 53 Added Frequency Planning Using the AD9516 Section Changes to LVPECL Clock Distribution and LVDS Clock Distribution Sections Changes to Figure 59 Figure 60 and lano ge ERE 72 1 09 Revision 0 Initial Version Rev A Page 3 of 76 AD9516 5 SPECIFICATIONS Typical is given for Vs Vs 3 3 V 596 Vs lt 5 25 V Ta 25 C 4 12 CPrser 5 1
60. OUT1 OUT2 OUT2 0 3 V to VS 0 3 V OUT3 OUT3 OUTA OUTA OUT5 5 OUT6 OUT6 OUT7 OUT7 OUT8 OUTS OUT9 OUT9 to GND SYNC to GND 0 3 V to VS 0 3 V REFMON STATUS LD to GND 0 3V to VS 0 3 V Temperature Junction Temperature 150 Storage Temperature Range 65 C to 150 Lead Temperature 10 sec 300 C AD9516 5 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability THERMAL RESISTANCE Table 16 Package Osa Unit 64 Lead LFCSP CP 64 4 22 C W 1 Thermal impedance measurements were taken on a 4 layer board in still air in accordance with EIA JESD51 2 ESD CAUTION ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge 4 without detection Although this product features patented or proprietary protection circuitry damage A may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality 1 See Table 16 for Rev A Page 15 of 76 AD9516 5 PIN CONFIGURATION AND FUNCTION DESCRIPTION
61. Offset 157 dBc Hz At 1 MHz Offset 160 dBc Hz 510 MHz Offset 163 dBc Hz CLOCK OUTPUT ABSOLUTE TIME JITTER CLOCK GENERATION USING EXTERNAL VCXO Table 6 Parameter Min Typ Max Unit Test Conditions Comments LVPECL OUTPUT ABSOLUTE TIME JITTER Application example based on a typical setup using an external 245 76 MHz VCXO Toyocom TCO 21 12 reference 15 36 MHz 1 LVPECL 245 76 MHz PLL LBW 125 Hz 54 fs rms Integration bandwidth 200 kHz to 5 MHz 77 fsrms Integration bandwidth 200 kHz to 10 MHz 109 fsrms Integration bandwidth 12 kHz to 20 MHz LVPECL 122 88 MHz PLL LBW 125 Hz 79 fs rms Integration bandwidth 200 kHz to 5 MHz 114 fsrms Integration bandwidth 200 kHz to 10 MHz 163 fsrms Integration bandwidth 12 kHz to 20 MHz LVPECL 61 44 MHz PLL LBW 125 Hz 124 fsrms Integration bandwidth 200 kHz to 5 MHz 176 fsrms Integration bandwidth 200 kHz to 10 MHz 259 fsrms Integration bandwidth 12 kHz to 20 MHz CLOCK OUTPUT ADDITIVE TIME JITTER VCO DIVIDER NOT USED Table 7 Parameter Min Max Unit Test Conditions Comments LVPECL OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL uses rising edge of clock signal CLK 622 08 MHz LVPECL 622 08 MHz 40 fs rms Bandwidth 12 kHz to 20 MHz Divider 1 CLK 622 08 MHz LVPECL 155 52 MHz 80 fs rms Bandwidth 12 kHz to 20 MHz Divider 2 4 CLK 1 6 GHz LVPECL 100 MHz 215
62. P to pump up or pump down to charge or discharge the integrating node part of the loop filter The integrated and filtered CP current is transformed into a voltage that drives the tuning node of the external VCO to move the VCO frequency up or down The CP can be set via Register 0x010 6 4 for high impedance allows holdover operation for normal operation attempts to lock the PLL loop for pump up or for pump down test modes The CP current is programmable in eight steps from nominally 600 uA to 4 8 mA The exact value of the CP current LSB is set by the CPRSET resistor which is nominally 5 1 If the value of the resistor connected to the CP RSET pin is doubled the resulting charge pump current range becomes 300 to 2 4 mA Rev A Page 28 of 76 PLL External Loop Filter An example of an external loop filter for a PLL is shown in Figure 36 A loop filter must be calculated for each desired PLL configuration The values of the components depend on the VCO frequency the Kvco the PFD frequency the charge pump current the desired loop bandwidth and the desired phase margin The loop filter affects the phase noise loop settling time and loop stability A basic knowledge of PLL theory is helpful for under standing loop filter design ADIsimCLK can help with calculation of a loop filter according to the application requirements AD9516 5 EXTERNAL VCOIVCXO CHARGE PUMP C3 07972 065 Figure 36 Example of
63. R A and B counters can also be reset simultaneously via the SYNC pin This function is controlled by Register 0x019 7 6 see Table 49 The SYNC pin reset is disabled by default Rand N Divider Delays Both the R and N dividers feature a programmable delay cell These delays can be enabled to allow adjustment of the phase relationship between the PLL reference clock and the VCO or CLK Each delay is controlled by three bits The total delay range is about 1 ns See Register 0x019 in Table 49 LOCK DETECT Digital Lock Detect DLD By selecting the proper output through the mux on each pin the DLD function can be made available at the LD STATUS and REFMON pins The DLD circuit indicates a lock when the time difference of the rising edges at the PFD inputs is less than a specified value the lock threshold The loss of a lock is indicated when the time difference exceeds a specified value the unlock threshold Note that the unlock threshold is wider than the lock threshold which allows some phase error in excess of the lock window to occur without chattering on the lock indicator The lock detect window timing depends on three settings the digital lock detect window bit Register 0x018 4 the antibacklash pulse width setting Register 0x017 1 0 see Table 2 and the lock detect counter Register 0x018 6 5 A lock is not indicated until there is a programmable number of consecutive PFD cycles with a time difference that
64. Register 0x017 1 0 006 01b 11b Register 0 018 4 1b High Range ABP 1 3 ns 2 9 ns 15 ns Register 0x017 1 0 006 016 11b Register 0 018 4 Ob High Range ABP 6 0 ns 11 ns Register 0x017 1 0 10b Register 0x018 4 Ob The REFIN and REFIN self bias points are offset slightly to avoid chatter on an open input condition For reliable operation of the digital lock detect the period of the PFD frequency must be greater than the unlock after lock time Rev A Page 5 of 76 AD9516 5 CLOCK INPUTS Table 3 Parameter Min Typ Max Unit Test Conditions Comments CLOCK INPUTS CLK CLK Differential input Input Frequency 0 24 GHz High frequency distribution VCO divider enabled 0 1 6 GHz Distribution only VCO divider bypassed this is the frequency range supported by the channel divider Input Sensitivity Differential 150 mVp p Measured at 2 4 GHz jitter performance is improved with slew rates 1 V ns Input Level Differential 2 Vp p Larger voltage swings may turn on the protection diodes and may degrade jitter performance Input Common Mode Voltage Va 1 3 1 57 1 8 V Self biased enables ac coupling Input Common Mode Range 1 3 1 8 V With 200 mV p p signal applied dc coupled Input Sensitivity Single Ended 150 mVp p CLKac coupled CLK ac bypassed to RF ground Input Resistance 3 9 4 7 5 7 kQ Self biased Input Capacitance 2 pF 1 Below about 1 MHz the input should b
65. S 4 uu o ee a zzo E ve xe STTS oss eee gt gt gt gt gt gt gt D D OD O O 1O 10 10 10 1 10 10 10 10 10 LEE uq LVPECL LVPECL VS 1 HO RN ed 48 OUTS 0 REFMON 2H INDICATOR _ 47 OUT6 OUT6B LD 3H 54 46 OUT7 OUT7A VCP 4H 88 45 OUT7 OUT7B 5H Zw H44 GND STATUS 6H 43 our2 REF SEL 7 AD9516 5 E amp H 42 ouT2 SYNC 8H ZOP VIEW 3 H 41 VS_LVPECL NC 9 FH Not to Scale R 40 OUT3 NC 10 H 5 39 OUT3 vs 11 H sa 38 VS VS 12 H ad 37 GND CLK 13 H 2r 36 OUTS OUT9B CLK 14 H Sa 11935 OUTS OUT9A NC 15 H 9A 34 OUTS OUT8B SCLK 16 29 JH OUTS OUT8A LVPECL LVPECL _ 1 cO st 10 G c OQ ON WN CON 82220 nalo 22u2 2 alo r4 gt m S NOTES 1 NC NO CONNECT DO NOT CONNECT TO THIS PIN 2 EXPOSED DIE PAD MUST BE CONNECTED TO GND Table 17 Pin Function Descriptions 07972 003 Figure 6 Pin Configuration Input Pin No Output Pin Type Mnemonic Description 1 11 12 30 I Power VS 3 3 V Power Pins 31 32 38 49 50 51 57 60 61 2 3 3 V CMOS REFMON Reference Monitor Output This pin has multiple selectable outputs see Table 49 Register 0x01B 3 3 3 V CMOS LD Lock Detect Output This pin has multi
66. Unselected reference to PLL not available when in differential mode 1 0 1 0 1 LVL Status of selected reference status of differential reference active low 1 0 1 1 0 LVL Status of unselected reference not available in differential mode active low 1 0 1 1 1 LVL Status of REF1 frequency active low 1 1 0 0 0 LVL Status of REF2 frequency active low 1 1 Status of REF 1 frequency AND status of REF2 frequency 1 DLD AND status of selected reference AND status of CLK 1 1 0 1 1 LVL Status of CLK frequency active low 1 1 1 0 0 LVL Selected reference low REF2 high 1 1 1 1 0 1 LVL Digital lock detect DLD active low 1 1 1 1 0 LVL Holdover active active low 1 1 1 1 1 LVL LD pin comparator output active low 0 01 7 Disable Disables or enables the switchover deglitch circuit switchover 0 enables switchover deglitch circuit default deglitch 1 disables switchover deglitch circuit 6 Select REF2 If Register 0 01 5 0 selects reference for PLL 0 select REF1 default 1 select REF2 5 Use REF_SEL pin If Register 0x01C 4 0 manual sets method of PLL reference selection 0 uses Register 0x01C 6 default 1 uses REF_SEL pin Reserved 0 default 3 Reserved 0 default 2 REF2 This bit turns the REF2 power on power on 0 REF2 power off default 1 REF2 power on 1 REF1 This bit turns the REF1 power on power on 0 REF1 power off default 1 REF1 power on 0
67. V CMOS compatible Whenever single ended CMOS clocking is used some general guidelines should be followed Point to point nets should be designed such that a driver has only one receiver on the net if possible This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net Series termination at the source is generally required to provide transmission line matching and or to reduce current transients at the driver The value of the resistor is dependent on the board design and timing requirements typically 10 to 100 is used 5 outputs are also limited in terms of the capacitive load or trace length that they can drive Typically trace lengths less than 3 inches are recommended to preserve signal rise fall times and preserve signal integrity AD9516 5 60 40 1 0 INCH 100 MICROSTRIP 07972 076 Figure 63 Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option The CMOS outputs of the AD9516 do not supply enough current to provide a full voltage swing with a low impedance resistive far end termination as shown in Figure 64 The far end termination network should match the PCB trace impedance and provide the desired switching point The reduced signal swing may still meet receiver input requirements in some applications This can be useful when driving long trace lengths on less critical nets 07972 077
68. able register settings see Table 47 and Table 49 and by the design of the external loop filter Successful PLL operation and satisfactory PLL loop performance are highly dependent upon proper configuration of the PLL settings The design of the external loop filter is crucial to the proper operation of the PLL A thorough knowledge of PLL theory and design is helpful ADIsimCLK V1 2 or later is a free program that can help with the design and exploration of the capabilities and features of the AD9516 including the design of the PLL loop filter It is available at www analog com clocks Phase Frequency Detector PFD The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them The PFD includes a programmable delay element that controls the width of the antibacklash pulse This pulse ensures that there is no dead zone in the PFD transfer function and minimizes phase noise and reference spurs The antibacklash pulse width is set by Register 0x017 1 0 An important limit to keep in mind is the maximum frequency allowed into the PFD which in turn determines the correct anti backlash pulse setting The antibacklash pulse setting is specified in the phase frequency detector PFD parameter of Table 2 Charge Pump CP The charge pump is controlled by the PFD The PFD monitors the phase and frequency relationship between its two inputs and tells the C
69. ally reported as a series of values whose units are dBc Hz at a given offset in frequency from the sine wave carrier The value is a ratio expressed in decibels dB of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency For each measurement the offset from the carrier frequency is also given Itis meaningful to integrate the total power contained within some interval of offset frequencies for example 10 kHz to 10 MHz This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval Phase noise has a detrimental effect on the performance of ADCs DACs and RF mixers It lowers the achievable dynamic range of the converters and mixers although they are affected in somewhat different ways AD9516 5 Time Jitter Phase noise is a frequency domain phenomenon In the time domain the same effect is exhibited as time jitter When observing a sine wave the time of successive zero crossings varies In a square wave the time jitter is a displacement of the edges from their ideal regular times of occurrence In both cases the variations in timing from the ideal are the time jitter Because these variations are random in nature the time jitter is specified in units of seconds root mean square rms or 1 sigma of the Gaussian distribution Time jitter that occurs on a sampli
70. ank OUTO OUTO LVPECL OUTO power down 0x08 invert differential voltage OxOF1 OUTI Blank OUT1 OUT1 LVPECL OUT power down invert differential voltage OxOF2 OUT2 Blank OUT2 OUT2 LVPECL OUT2 power down 0x08 invert differential voltage OxOF3 OUT3 Blank OUT3 OUT3 LVPECL OUT3 power down invert differential voltage OxOFA OUT4 Blank OUT4 OUT4 LVPECL OUT4 power down 0x08 invert differential voltage OxOF5 5 Blank OUT5 5 LVPECL 5 power down invert differential voltage OxOF6 Blank to Ox13F LVDS CMOS Outputs 0x140 OUT6 OUT6 CMOS OUT6 OUT6 select OUT6 LVDS OUT6 0x42 output polarity CMOS B LVDS CMOS output current power down 0x141 OUT7 OUT7 CMOS OUT7 OUT7 select OUT7 LVDS OUT7 0x43 output polarity CMOS B LVDS CMOS output current power down 0x142 OUT8 OUT8 CMOS OUT8 OUTS select OUT8 LVDS OUT8 0x42 output polarity CMOS B LVDS CMOS output current power down 0x143 OUT9 OUT9 CMOS OUT9 OUT select OUT9 LVDS OUT9 0x43 output polarity CMOS B LVDS CMOS output current power down 0 144 Blank to Ox18F Rev A Page 50 of 76 AD9516 5 Ref Default Addr Value Hex Parameter Bit 7 MSB Bit6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB Hex LVPECL C
71. ault register values does not include power dissipated in external resistors this configuration has the following blocks already powered up VCO divider six channel dividers three LVPECL drivers and two LVDS drivers Full Operation CMOS Outputs at 225 MHz 1 5 2 1 W 2 25 GHz VCO divider 2 all channel dividers on six LVPECL outputs at 562 5 MHz eight CMOS outputs 10 pF load at 225 MHz all four fine delay blocks on maximum current does not include power dissipated in external resistors Full Operation LVDS Outputs at 225 MHz 1 5 2 1 W 2 25 GHz VCO divider 2 all channel dividers on six LVPECL outputs at 562 5 MHz four LVDS outputs at 225 MHz all four fine delay blocks on maximum current does not include power dissipated in external resistors PD Power Down 75 185 mW PD pin pulled low does not include power dissipated in terminations PD Power Down Maximum Sleep 31 mW PD pin pulled low PLL power down Register 0x010 1 0 01b SYNC power down Register 0x230 2 1b REF for distribution power down Register 0x230 1 1b Vce Supply 4 4 8 mW PLLoperating typical closed loop configuration this number is included in all other power measurements AD9516 Core 220 mW AD9516 core only all drivers off PLL off VCO divider off and delay blocks off the power consumption of the configuration of the user can be derived from this number and the power deltas that follow Rev A Page 11 of 76 AD9
72. by momentarily pulling RESET low A reset restores the chip registers to the default settings It is recommended that the user not toggle SCLK for 20 ns after RESET goes high Soft Reset via Register 0x000 2 A soft reset is executed by writing Register 0x000 2 and Register 0 000 5 1b This bit is not self clearing therefore it must be cleared by writing Register 0x000 2 and Register 0x000 2 Ob to reset it and complete the soft reset operation soft reset restores the default values to the internal registers The soft reset bit does not require an update registers command Register 0x232 0x01 to be issued POWER DOWN MODES Chip Power Down via PD The AD9516 can be put into a power down condition by pulling the PD pin low Power down turns off most of the functions and currents inside the AD9516 The chip remains in this power down state until PD is brought back to logic high When the AD9516 wakes up it returns to the settings programmed into its registers prior to the power down unless the registers are changed by new programming while the PD pin is held low The PD power down shuts down the currents on the chip except the bias current that is necessary to maintain the LVPECL outputs in a safe shutdown mode This is needed to protect the LVPECL output circuitry from damage that can be caused by certain termination and load configurations when tristated Because this is not a complete power down it can be called
73. channel divider result in a non 5096 duty cycle A non 5096 duty cycle can also result with an even division if M N The duty cycle correction function automatically corrects non 50 duty cycles at the channel divider output to 5096 duty cycle Duty cycle correction requires the following channel divider conditions e An even division must be set as M e An odd division must set as M N 1 When not bypassed or corrected by the DCC function the duty cycle of each channel divider output is the numerical value of 1 N M 2 expressed as a percentage 96 Table 30 to Table 32 list the duty cycles at the output of the channel dividers for various configurations Table 30 Duty Cycle with VCO Divider Input Duty Cycle Is 50 Low Cycles High Cycles Divider M N Bypass DCCOFF 0 0x190 7 4 0x190 3 0 0x191 7 0x192 0 1 0x193 7 4 0x193 3 0 0x194 7 0x195 0 2 0x196 7 4 0x196 3 0 0x197 7 0x198 0 Note that the value stored in the register of cycles minus 1 For example 0x190 7 4 0001b equals two low cycles M 2 for Divider 0 Channel Frequency Division 0 1 and 2 For each channel where the channel number is x 0 1 or 2 the frequency division Dx is set by the values of M and N four bits each representing Decimal 0 to Decimal 15 where Number of Low Cycles M 1 Number of High Cycles N 1 The cycles are cycles of the clock signal currently routed to the
74. current current sets the full scale delay 2 1 O Current pA O O O 200 default 0 1 400 600 01111 800 10 0 1000 110 1 1200 1 1 0 1400 1 1 1 1600 Ox0A8 5 0 OUT8 delay Selects the fraction of the full scale delay desired 6 bit binary A setting of 000000b gives zero delay fraction Only delay values of up to 47 decimals 101111b 2 are supported default 0x00 0x0A9 0 OUT delay Bypasses or uses the delay function bypass 0 uses the delay function 1 bypasses the delay function default Rev A Page 60 of 76 AD9516 5 Reg Addr Hex Bits Name Description 5 3 OUT9 ramp Selects the number of ramp capacitors used by the delay function The combination of the number of capacitors capacitors and the ramp current sets the full scale delay 5 4 Number of Capacitors O O O 4 default 00 10 113 0 11013 0111112 1101013 14101112 1111012 11111411 2 0 9 ramp Ramp current for the delay function The combination of the number of capacitors and the ramp current current sets the full scale delay 2 1 0 Current Value pA O O O 200 default O 0 1 400 O 11101 600 0 1 1 800 1 0 0 1000 1 1200 1 1 0 1400 1 1 1 1600 5 0 OUT9 delay Selects the fraction of the full scale delay desired 6 bit binary A set
75. de holdover controlled by SYNC pin 0 Holdover enable Along with Register OxO1D 2 enables the holdover function 0 holdover disabled default 1 holdover enabled 5 Holdover active Read only register Indicates if the part is in the holdover state see Figure 41 This is not the same as holdover enabled 0 not in holdover 1 holdover state active 4 REF2 selected Read only register Indicates which PLL reference is selected as the input to the PLL 0 REF1 selected or differential reference if in differential mode 1 REF2 selected 3 CLK frequency Read only register Indicates if the CLK frequency is greater than the threshold see Table 12 REF1 REF2 and CLK threshold frequency status monitor 0 CLK frequency is less than the threshold 1 CLK frequency is greater than the threshold 2 REF2 Read only register Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by frequency Register 0x01A 6 threshold 0 REF2 frequency is less than threshold frequency 1 REF2 frequency is greater than threshold frequency 1 REF1 Read only register Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by frequency Register 0x01A 6 threshold 0 REF1 frequency is less than threshold frequency 1 REF1 frequency is greater than threshold frequency 0 Digital Read only register Digital lock detect lock detect 0 PLL is not locked
76. de if using the LD pin comparator Load the LD pin with a capacitor of an appropriate value e Register 0x01D 3 LD pin comparator enable 1b enable Ob disable When disabled the holdover function always senses the LD pin as high e Register OxOID 1 external holdover control e Register 0x01D 0 and Register 0x01D 2 holdover enable If holdover is disabled both external and automatic internal holdover are disabled For example to use automatic holdover with the following e Digital lock detect PFD cycles high range window e Automatic holdover using the LD pin comparator Set the following registers in addition to the normal PLL registers e Register 0x018 6 5 00b lock detect counter five cycles e Register 0x018 4 0b lock detect window high range REF SEL vs GND RSET Q O O I Er STATUS e REFIN REF1 Q gt lla REFIN REF2 DIVIDE BY 2 3 4 5 6 il S DISTRIBUTION REFERENCE PROGRAMMABLE R DELAY PROGRAMMABLE N DELAY CLK FREQUENCY e Register 0x018 3 0b DLD normal operation e Register 0x01A 5 0 000100b current source lock detect mode e Register 0x01B 7 0 7 set REFMON pin to status of REFI active low e Register 0x01C 2 1 11b enable REF1 and REF2 input buffers e Register 0x01D 3 1b enable LD pin comparator e Register 0x01D 2 1b enable holdover function e Register 0x01D 1 Ob use internal automatic h
77. der that divides the clock frequency that is applied to its input The LVPECL channel dividers can divide by any integer from 2 to 32 or the divider can be bypassed to achieve a divide by 1 Each LVDS CMOS channel divider contains two of these divider blocks in a cascaded configuration The total division of the channel is the product of the divide value of the cascaded dividers This allows divide values of 1 to 32 x 1 to 32 or up to 1024 note that this is not all values from 1 to 1024 but only the set of numbers that are the product of the two dividers The VCO divider can be set to divide by 2 3 4 5 or 6 and must be used if the external clock signal connected to the CLK input is greater than 1600 MHz The channel dividers allow for a selection of various duty cycles depending on the currently set division That is for any specific division D the output of the divider can be set to high for N 1 input clock cycles and low for M 1 input clock cycles where D N M 2 For example a divide by 5 can be high for one divider input cycle and low for four cycles or a divide by 5 can be high for three divider input cycles and low for two cycles Other combinations are also possible The channel dividers include a duty cycle correction function that can be disabled In contrast to the selectable duty cycle just described this function can correct a non 50 duty cycle caused by an odd division However this requires that the div
78. e 52 LVDS CMOS Outputs Reg Addr Hex Bits Name Description 0x140 7 5 OUT6 output polarity In CMOS mode Bits 7 5 select the output polarity of each CMOS output In LVDS mode only Bit 5 determines LVDS polarity 7 6 5 OUT6A CMOS OUT6B CMOS OUT6 LVDS O O 0 Noninverting Inverting Noninverting O 1 0 Noninverting Noninverting Noninverting default 1 0 O Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 O 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 O 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT6 CMOS B In CMOS mode turns on off the CMOS B output This has no effect in LVDS mode 0 turns off the CMOS B output default 1 turns on the CMOS B output 3 OUT6 select LVDS CMOS Selects LVDS or CMOS logic levels 0 LVDS default 1 CMOS 2 1 OUT6 LVDS output current Sets output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination 0 0 1 75 100 0 1 3 5 100 default 1 0 5 25 50 1 1 7 50 0 OUT6 power down Power down output LVDS CMOS 0 powers on default 1 powers off 0x141 7 5 OUT7 output polarity In CMOS mode Bits 7 5 select the output polarity of each CMOS output In LVDS mode only Bit 5 determines LVDS polarity 7 6 5 OUT7A CMOS OUT7B
79. e Divider 0 nosync bit Bit 6 also be set This bit has no effect if the Divider O bypass bit Bit 7 is set 0 normal operation default 1 divider output forced to the setting of the Divider O start high bit 4 Divider 0 start high Selects clock output to start high or start low 0 starts low default 1 starts high 3 0 Divider 0 phase offset Phase offset default 0x0 0 192 1 Divider 0 direct to output Connects OUTO and OUTI to Divider 0 or directly to CLK input 0 OUTO and OUT1 are connected to Divider 0 default 1 If Register 0x1E1 0 Ob the CLK is routed directly to OUTO and OUT1 If Register 0x1E1 0 1b there is no effect 0 Divider 0 DCCOFF Duty cycle correction function 0 enables duty cycle correction default 1 disables duty cycle correction 0x193 7 4 Divider 1 low cycles Number of clock cycles minus 1 of the Divider 1 input during which the Divider 1 output stays low A value of 0 7 means that the divider is low for eight input clock cycles default OxB 3 0 Divider 1 high cycles Number of clock cycles minus 1 of the Divider 1 input during which the Divider 1 output stays high A value of 0x7 means that the divider is low for eight input clock cycles default OxB 0x194 7 Divider 1 55 Bypasses and powers down the divider routes input to divider output 0 uses divider default 1 bypasses divider 6 Divider 1 nosync No sync 0 obeys
80. e dc coupled Care should be taken to match CLOCK OUTPUTS Table 4 Parameter Min Typ Max Unit Test Conditions Comments LVPECL CLOCK OUTPUTS Termination 50 to Vs 2 V OUTO OUT1 OUT2 OUT3 OUT4 Differential OUT OUT 5 Output Frequency Maximum 2400 MHz Using direct to output see Figure 20 for peak to peak differential amplitude Output High Voltage 1 12 098 Vs vera 0 84 V Measured at dc using the default amplitude setting see Figure 20 for amplitude vs frequency Output Low Voltage Voi Vs veea 2 03 1 77 Vs wea 1 49 V Measured at dc using the default amplitude setting see Figure 20 for amplitude vs frequency Output Differential Voltage 550 790 980 mV Va for each leg of a differential pair for default amplitude setting with driver not toggling see Figure 20 for variation over frequency LVDS CLOCK OUTPUTS Differential termination 100 at 3 5 mA OUT6 OUT7 OUT8 OUT9 Differential OUT OUT Output Frequency Maximum 800 MHz The AD9516 outputs can toggle at higher frequencies but the output amplitude may not meet the Vop specification see Figure 21 Differential Output Voltage 247 360 454 mV measurement across a differential pair at the default amplitude setting with output driver not toggling see Figure 21 for variation over frequency Delta 25 mV This is the absolute value of the difference between Von wh
81. e receiving buffer should match the Vs eect If it does not match ac coupling is recommended see Figure 61 The resistor network is designed to match the transmission line impedance 50 and the switching threshold Vs 1 3 V Vs Vs LvPECL Vs 500 SINGLE ENDED NOT COUPLED 500 Figure 59 DC Coupled 3 3 V LVPECL Far End Thevenin Termination 07972 045 07972 147 Vs Vs 1000 DIFFERENTIAL COUPLED 1000 0 1nF TRANSMISSION LINE 07972 046 Figure 61 AC Coupled LVPECL with Parallel Transmission Line LVPECL Y termination is an elegant termination scheme that uses the fewest components and offers both odd and even mode impedance matching Even mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter follower LVPECL driver This can be an important consideration when driving long trace lengths but is usually not an issue In the case shown in Figure 60 where Vs 2 5 V the 50 termination resistor connected to ground should be changed to 19 Thevenin equivalent termination uses a resistor network to provide 50 termination to a dc voltage that is below Vor of the LVPECL driver In this case Vs on the AD9516 should equal Vs of the receiving buffer Although the resistor combination shown in Figure 60 r
82. eads the data that is in the serial control port buffer area or the data that is in the active registers see Figure 51 Readback of the buffer or active registers is controlled by Register 0 004 0 The AD9516 supports only the long instruction mode therefore Register 0x000 4 3 must be set to 11b This register uses mirrored bits Long instruction mode is the default at power up or reset The AD9516 uses Register Address 0x000 to Register Address 0x232 CONTROL PORT 2 SCLK 7 t 5010 9 500 E vs UPDATE 5 SERIAL REGISTERS F D am lt WRITE REGISTER 0x232 0x01 TO UDATE REGISTERS 07972 037 Figure 51 Relationship Between Serial Control Port Buffer Registers and Active Registers of the AD9516 INSTRUCTION WORD 16 BITS The MSB of the instruction word is R W which indicates whether the instruction is a read or a write The next two bits W1 W0 indicate the length of the transfer in bytes The final 13 bits are the address A12 A0 at which to begin the read or write operation For a write the instruction word is followed by the number of bytes of data indicated by Bits W1 W0 see Table 42 Table 42 Byte Transfer Count w1 wo Bytes to Transfer 0 0 1 0 1 2 1 0 3 1 1 Streaming mode AD9516 5 The 13 bits found in Bits A12 A0 select the address within the register map that is written to or read from during the data transfer portion of the communications cycle
83. ects the signal that is connected to the REFMON pin control Level or Dynamic 4 3 2 1 O Signal Signal at REFMON Pin 0 0 0 0 0 LVL Ground dc default 0 0 0 0 1 DYN REF1 clock differential reference when in differential mode 0 0 0 1 0 DYN REF2 clock not available in differential mode 0 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 0 0 1 0 0 DYN Unselected reference to PLL not available in differential mode 0 0 1 0 1 LVL Status of selected reference status of differential reference active high 0 0 1 1 0 LVL Status of unselected reference not available in differential mode active high 0 0 1 1 LVL Status of REF1 frequency active high 0 1 O LVL Status of REF2 frequency active high 0 1 0 0 1 LVL Status of REF1 frequency AND status of REF2 frequency 0 1 0 1 0 LVL DLD AND status of selected reference AND status of CLK 0 1 0 1 1 LVL Status of CLK frequency active high 0 1 1 0 0 LVL Selected reference low REF1 high 2 0 1 1 0 1 LVL Digital lock detect DLD active low 0 1 1 1 0 LVL Holdover active active high 0 1 1 1 1 LVL LD pin comparator output active high 1 LVL VS supply 1 0 010 1 DYN REF1 clock differential reference when in differential mode DYN REF2 clock not available in differential mode 1 0 0 1 1 DYN Selected reference to PLL differential reference when in differential mode 1 0 1 0 0 DYN
84. ed from SNR of ADC method Divider 12 Duty Cycle Correction Off CMOS OUTPUT ADDITIVE TIME JITTER Distribution section only does not include PLL uses rising edge of clock signal CLK 2 4 GHz VCO Div 2 CMOS 100 MHz 350 fsrms Calculated from SNR of ADC method Divider 12 Duty Cycle Correction Off DELAY BLOCK ADDITIVE TIME JITTER Table 9 Parameter Min Typ Unit Test Conditions Comments DELAY BLOCK ADDITIVE TIME JITTER Incremental additive jitter 100 MHz Output Delay 1600 uA 0x1C Fine Adjust 000000b 0 54 ps rms Delay 1600 Ox1C Fine Adjust 101111b 0 60 ps rms Delay 800 pA 0x1C Fine Adjust 0000006 0 65 ps rms Delay 800 pA Ox1C Fine Adjust 101111b 0 85 ps rms Delay 800 pA 4 Fine Adjust 0000006 0 79 ps rms Delay 800 pA 4 Fine Adjust 101111b 1 2 ps rms Delay 400 pA 4 Fine Adjust 000000b 1 2 ps rms Delay 400 pA 4 Fine Adjust 101111b 2 0 ps rms Delay 200 uA 0x1C Fine Adjust 0000006 1 3 ps rms Delay 200 pA Ox1C Fine Adjust 101111b 2 5 ps rms Delay 200 uA 4 Fine Adjust 0000006 1 9 ps rms Delay 200 pA 4 Fine Adjust 101111b 3 8 ps rms This value is incremental that is it is in addition to the jitter of the LVDS or CMOS output without the delay To estimate the total jitter the LVDS or CMOS output jitter should be added to this value using the root sum of the squares RSS method Rev A Page 9 of 76 AD9516 5
85. en the normal output is high vs when the complementary output is high Output Offset Voltage Vos 1 125 1 24 1 375 V Vo 2 across a differential pair at the default amplitude setting with output driver not toggling Delta Vos 25 mV This is the absolute value of the difference between Vos when the normal output is high vs when the complementary output is high Short Circuit Current Isa Iss 14 24 mA Output shorted to GND CMOS CLOCK OUTPUTS OUT6A OUT6B OUT7A OUT7B Single ended termination 10 pF OUT8A OUT8B OUT9A OUT9B Output Frequency 250 MHz See Figure 22 Output Voltage High Vou Vs 0 1 V At 1 mA load Output Voltage Low 0 1 V At 1 mA load Rev A Page 6 of 76 AD9516 5 CLOCK OUTPUT ADDITIVE PHASE NOISE DISTRIBUTION ONLY VCO DIVIDER NOT USED Table 5 Parameter Min Typ Max Unit Test Conditions Comments CLK TO LVPECL ADDITIVE PHASE NOISE Distribution section only does not include PLL input CLK 1 GHz Output 1 GHz slew rate gt 1 V ns Divider 1 At 10 Hz Offset 109 dBc Hz At 100 Hz Offset 118 dBc Hz At 1 kHz Offset 130 dBc Hz At 10 kHz Offset 139 dBc Hz At 100 kHz Offset 144 dBc Hz At 1 MHz Offset 146 dBc Hz At 10 MHz Offset 147 dBc Hz At 100 MHz Offset 149 dBc Hz CLK 1 GHz Output 200 MHz Input slew rate gt 1 V ns Divider 5 At 10 Hz Offset 120 dBc Hz At 100 Hz Offset 126 dBc Hz At 1 kHz Offset 139 dBc Hz At 10 kHz Off
86. ently The relative polarity of the CMOS outputs can also be selected for any combination of inverting and noninverting See Table 52 Register 0x140 7 5 Register 0x141 7 5 Register 0x142 7 5 and Register 0x143 7 5 Each LVDS CMOS output can be powered down as needed to save power The CMOS output power down is controlled by the same bit that controls the LVDS power down for that output This power down control affects both CMOS Output A and CMOS Output B However when CMOS Output A is powered up CMOS Output B output can be powered on or off separately ce 33 zi 07972 035 Figure 49 CMOS Equivalent Output Circuit Rev A Page 42 of 76 RESET MODES The AD9516 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active Power On Reset Start Up Conditions When VS Is Applied power on reset POR is issued when the VS power supply is turned on The POR pulse duration is 100 ms and initializes the chip to the power on conditions that are determined by the default register settings These are indicated in the Default Value Hex column of Table 47 At power on the AD9516 also executes a SYNC operation which brings the outputs into phase alignment according to the default settings It is recommended that the user not toggle SCLK during the reset pulse Asynchronous Reset via the RESET Pin An asynchronous hard reset is executed
87. esults in a dc bias point of Vs verger 2 V the actual common mode voltage is Vs 1 3 V because additional current flows from the AD9516 LVPECL driver through the pull down resistor The circuit is identical when Vs 2 5 V except that the pull down resistor is 62 5 and the pull up resistor 15 250 LVDS CLOCK DISTRIBUTION The AD9516 provides four clock outputs OUT6 to OUT9 that are selectable as either CMOS or LVDS level outputs LVDS is a differential output option that uses a current mode output stage The nominal current is 3 5 mA which yields a 350 mV output swing across 100 resistor An output current of 7 mA is also available in cases where a larger output swing is required The LVDS output meets or exceeds all ANSI TIA EIA 644 specifications recommended termination circuit for the LVDS outputs is shown in Figure 62 Vs Vs 1000 DIFFERENTIAL COUPLED 1000 1 CJ 07972 047 Figure 62 LVDS Output Termination See the AN 586 Application Note LVDS Data Outputs for High Speed Analog to Digital Converters for more information on LVDS Rev A Page 72 of 76 CMOS CLOCK DISTRIBUTION The AD9516 provides four clock outputs OUT6 to OUT9 that are selectable as either CMOS or LVDS level outputs When selected as CMOS each output becomes a pair of CMOS outputs each of which can be individually turned on or off and set as noninverting or inverting These outputs are 3 3
88. f the output clock period If a delay longer than half of the clock period is attempted the output stops clocking The delay function adds some jitter that is greater than that specified for the nondelayed output This means that the delay function should be used primarily for clocking digital chips such as FPGA ASIC DUC and DDC An output with this delay enabled may not be suitable for clocking data converters The jitter is higher for long full scales because the delay block uses a ramp and trip points to create the variable delay A slower ramp time produces more time jitter Synchronizing the Outputs SYNC Function The AD9516 clock outputs can be synchronized to each other Outputs can be individually excluded from synchronization Synchronization consists of setting the nonexcluded outputs to a preset set of static conditions and subsequently releasing these outputs to continue clocking at the same instant with the preset conditions applied This allows for the alignment of the edges of two or more outputs or for the spacing of edges according to the coarse phase offset settings for two or more outputs Synchronization of the outputs is executed in several ways By forcing the SYNC pin and then releasing it manual sync By setting and then resetting any one of the following three bits the soft SYNC bit Register 0x230 0 the soft reset bit Register 0x000 2 mirrored or the power down distribution reference bit Regis
89. gister 0x199 7 4 0001b equals two low cycles M 2 for Divider 3 1 Rev A Page 37 of 76 AD9516 5 Channel Frequency Division Divider 3 and Divider 4 The division for each channel divider is set by the bits in the registers for the individual dividers X Y 3 1 3 2 4 1 and 4 2 Number of Low Cycles Mxy 1 Number of High Cycles Nyy 1 When both X 1 and 2 are bypassed Dx 1x 1 1 When only 2 is bypassed Dx Nxi 2 x 1 When both X 1 and X 2 are not bypassed Dx 2 x Nx2 Mx 2 By cascading the dividers channel division up to 1024 can be obtained However not all integer value divisions from 1 to 1024 are obtainable only the values that are the product of the separate divisions of the two dividers Dx x Dx can be realized If only one divider is needed when using Divider 3 and Divider 4 use the first one X 1 and bypass the second one X 2 Do not bypass X 1 and use X 2 Duty Cycle and Duty Cycle Correction Divider 3 and Divider 4 The same duty cycle and DCC considerations apply to Divider 3 and Divider 4 as to Divider 0 Divider 1 and Divider 2 see the Duty Cycle and Duty Cycle Correction 0 1 and 2 section however with these channel dividers the number of possible configurations is more complex Duty cycle correction on Divider 3 and Divider 4 requires the following channel divider conditions s Aneven must be set as Mxy Nxx low cycle
90. h an on chip PLL that can be used with an external VCO VCXO of up to 2 4 GHz The AD9516 5 emphasizes low jitter and phase noise to maximize data converter performance and it can benefit other applications with demanding phase noise and jitter requirements Rev A Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM cP a 2E 92 Ea 22 0 DIVIO LVPECL gt out ere OUT2 DIVIO LVPECL I 9 ours SA Ss 5 DIVIO LVPECL PS Q OUTS AD9516 5 At Q SERIAL CONTROL PORT d AND ju DIGITAL LOGIC Figure 1 07972 001 The AD9516 5 features six LVPECL outputs in three pairs and four LVDS outputs in two pairs Each LVDS output can be reconfigured as two CMOS outputs The LVPECL outputs operate to 1 6 GHz the LVDS outputs operate to 800 MHz and the CMOS outputs operate to 250 MHz Each pair of outputs has dividers that allow both the divide ratio and coarse delay or phase to be set The range of division for the LVPE
91. hannel Dividers 0x190 Divider 0 Divider 0 low cycles Divider 0 high cycles 0x00 0x191 PECL Divider 0 Divider 0 Divider 0 Divider 0 Divider 0 phase offset 0x80 bypass nosync force high start high 0x192 Blank Divider 0 Divider 0 0x00 direct to DCCOFF output 0x193 Divider 1 Divider 1 low cycles Divider 1 high cycles OxBB 0x194 PECL Divider 1 Divider 1 Divider 1 Divider 1 Divider 1 phase offset 0x00 bypass nosync force high start high 0x195 Blank Divider 1 Divider 1 0x00 direct to DCCOFF output 0x196 Divider 2 Divider 2 low cycles Divider 2 high cycles 0x00 0x197 PECL Divider 2 Divider 2 Divider 2 Divider 2 Divider 2 phase offset 0x00 bypass nosync force high start high 0x198 Blank Divider 2 Divider 2 0x00 direct to DCCOFF output LVDS CMOS Channel Dividers 0x199 Divider 3 Low Cycles Divider 3 1 High Cycles Divider 3 1 0x22 0 19 LVDS CMOS Phase Offset Divider 3 2 Phase Offset Divider 3 1 0x00 Ox19B Low Cycles Divider 3 2 High Cycles Divider 3 2 0x11 0x19C Reserved Bypass Bypass Divider 3 Divider 3 Start High Start High 0x00 Divider 3 2 Divider 3 1 nosync force high Divider 3 2 Divider 3 1 0x19D Blank Divider 3 0x00 DCCOFF 0 19 Divider 4 Low Cycles Divider 4 1 High Cycles Divider 4 1 0x22 ox19F LVDS CMOS Phase Offset Divider 4 2 Phase Offset Divider 4 1 0x00 0x1A0 Low Cycles Divider 4 2 High Cycles Divider 4 2 0x11 Ox1A1 Reserved Bypass Bypass Divider 4 Divider 4 Start High Start High 0x00 Divider 4 2 Divider 4 1 nosy
92. hat data is written to blank or unused registers Because data is written into a serial control port buffer area and not directly into the actual control registers of the AD9516 an additional operation is needed to transfer the serial control port buffer contents to the actual control registers of the AD9516 thereby causing them to become active The update registers operation consists of setting Register 0x232 0 1b this bit is self clearing Any number of bytes of data can be changed before executing an update registers The update registers operation simultaneously actuates all register changes that have been written to the buffer since any previous update Rev A Page 44 of 76 Read If the instruction word is for a read operation the next N x 8 SCLK cycles clock out the data from the address specified in the instruction word where N is 1 to 3 as determined by W1 W0 If N 4 the read operation is in streaming mode continuing until CS is raised Streaming mode does not skip over reserved or blank registers The readback data is valid on the falling edge of SCLK The default mode of the AD9516 serial control port is the bidirectional mode In bidirectional mode both the sent data and the readback data appear on the SDIO pin It is also possible to set the AD9516 to unidirectional mode via the SDO active bit Register 0x000 0 1b In unidirectional mode the readback data appears on the SDO pin A readback request r
93. he CMOS B output 3 OUT select LVDS CMOS Selects LVDS or CMOS logic levels 0 LVDS default 1 CMOS Rev A Page 65 of 76 AD9516 5 Reg Addr Hex Bits Name Description 2 1 OUT9 LVDS output current Sets output current level in LVDS mode This has no effect in CMOS mode 1 Current mA Recommended Termination 1 75 100 3 5 100 default 5 25 50 7 50 0 OUT9 power down Power down output LVDS CMOS 0 powers on 1 powers off default N 00 Table 53 LVPECL Channel Dividers Reg Addr Hex Bits Name Description 0x190 7 4 Divider 0 low cycles Number of clock cycles minus 1 of the Divider 0 input during which the Divider 0 output stays low A value of 0x7 means that the divider is low for eight input clock cycles default 0 0 3 0 Divider 0 high cycles Number of clock cycles minus 1 of the Divider 0 input during which the Divider 0 output stays high A value of 0x7 means that the divider is low for eight input clock cycles default 0x0 0x191 7 Divider 0 bypass Bypasses and powers down the divider routes input to the divider output 0 uses the divider 1 bypasses the divider default 6 Divider 0 nosync No sync 0 obeys chip level SYNC signal default 1 ignores chip level SYNC signal 5 Divider 0 force high Forces divider output to high This operation requires that th
94. ide by 4 120 PHASE NOISE dBc Hz L A 1k 10 100k 1M 10M 100M FREQUENCY Hz Figure 30 Phase Noise Absolute External VCXO Toyocom TCO 21 12 INPUT JITTER AMPLITUDE UI 07972 132 07972 140 at 245 76 MHz PFD 15 36 MHz LBW 250 Hz LVPECL Output 245 76 MHz Rev A Page 22 of 76 NOTE 375UI MAX AT 10Hz OFFSET IS THE MAXIMUM JITTER THAT CAN BE GENERATED BY THE TEST EQUIPMENT FAILURE POINT IS GREATER THAN 375UI 0 1 1 10 100 JITTER FREQUENCY kHz Figure 31 GR 253 Jitter Tolerance Plot 07972 148 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0 to 360 for each cycle Actual signals however display a certain amount of variation from ideal phase progression over time This phenomenon is called phase jitter Although many causes can contribute to phase jitter one major cause is random noise which is characterized statistically as being Gaussian normal in distribution This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain producing a continuous power spectrum This power spectrum is usu
95. instruction 0x001 Blank 0x002 Reserved 0x003 Part ID Part ID read only 0x01 0x004 Readback Blank Read back 0x00 control active registers PLL 0x010 PFD and PFD Charge pump current Charge pump mode PLL power down 0x7D charge pump polarity 0x011 R Counter 14 bit R divider Bits 7 0 LSB 0x01 0x012 Blank 14 bit R divider Bits 13 8 MSB 0x00 0x013 A counter Blank 6 bit A counter 0x00 0x014 B counter 13 bit B counter Bits 7 0 LSB 0x03 0x015 Blank 13 bit B counter Bits 12 8 MSB 0x00 0x016 PLL Control 1 Set CP pin Reset R ResetAand Reset all B counter Prescaler P 0x06 to Vcp 2 counter B counters counters bypass 0x017 PLL Control 2 STATUS pin control Antibacklash pulse width 0x00 0x018 Control3 Reserved Lock detect counter Digital Disable Reserved 0x06 lock detect digital window lock detect 0x019 PLL Control 4 R A B counters R path delay N path delay 0x00 SYNC pin reset Control 5 Reserved Reference LD pin control 0x00 frequency monitor threshold 0x01B PLL Control 6 CLK 2 1 REFIN REFMON pin control 0x00 frequency REFIN frequency monitor frequency monitor monitor 0x01C PLLControl7 Disable Select Use Reserved REF2 REF1 Differential 0x00 switchover REF2 REF_SEL pin power on power on reference deglitch 0x01D PLL Control 8 Reserved PLL status LD pin Holdover External Holdover 0x00 register comparator enable holdover enable disable enable control PLL Cont
96. is less than the lock detect threshold The lock detect circuit continues to indicate a lock until a time difference greater than the unlock threshold occurs on a single subsequent cycle For the lock detect to work properly the period of the PFD frequency must be greater than the unlock threshold The number of consecutive PFD cycles required for lock is programmable Register 0x018 6 5 Analog Lock Detect ALD The AD9516 provides an ALD function that can be selected for use at the LD pin There are two versions of ALD as follows e N channel open drain lock detect This signal requires a pull up resistor to the positive supply VS The output is normally high with short low going pulses Lock is indicated by the minimum duty cycle of the low going pulses e P channel open drain lock detect This signal requires a pull down resistor to GND The output is normally low with short high going pulses Lock is indicated by the minimum duty cycle of the high going pulses The analog lock detect function requires an R C filter to provide a logic level indicating lock unlock VS 3 3V AD9516 5 ALD 4 07972 067 Figure 38 Example of Analog Lock Detect Filter Using N Channel Open Drain Driver Current Source Digital Lock Detect CSDLD During the PLL locking sequence it is normal for the DLD signal to toggle a number of times before remaining steady when the PLL is completely locked and stable There may be applications whe
97. ision be set by M N 1 In addition the channel dividers allow a coarse phase offset or delay to be set Depending on the division selected the output can be delayed by up to 31 input clock cycles The divider outputs can also be set to start high or start low Operating Modes There are two clock distribution operating modes These operating modes are shown in Table 25 It is not necessary to use the VCO divider if the CLK frequency is less than the maximum channel divider input frequency 1600 MHz otherwise the VCO divider must be used to reduce the frequency going to the channel dividers Table 25 Clock Distribution Operating Modes CLK Direct to LVPECL Outputs It is possible to connect the CLK directly to the LVPECL outputs OUTO to OUTS However the LVPECL outputs may not be able to provide full a voltage swing at the highest frequencies To connect the LVPECL outputs directly to the CLK input the VCO divider must be selected as the source to the distribution section even if no channel uses it Table 26 Settings for Routing VCO Divider Input Directly to LVPECL Outputs Register Setting Selection 0x1E1 0 Ob VCO divider selected 0x192 1 1b Direct to OUTO OUT1 outputs 0x195 1 1b Direct to OUT2 OUT3 outputs 0x198 1 1b Direct to OUT4 OUT5 outputs Clock Frequency Division The total frequency division is a combination of the VCO divider when used and the channel divider When the VCO d
98. ivider is used the total division from the VCO or CLK to the output is the product of the VCO divider 2 3 4 5 and 6 and the division of the channel divider Table 27 and Table 28 indicate how the frequency division for a channel is set For the LVPECL outputs there is only one divider per channel For the LVDS CMOS outputs there are two dividers X 1 X 2 cascaded per channel Table 27 Frequency Division for Divider 0 to Divider 2 vco Channel CLK Direct Divider Divider to Output Frequency Setting Setting Setting Division 2to6 Don t care Enable 1 2to6 Bypass Disable 2 to 6 x 1 2to6 2to32 Disable 2 to 6 x 2 to 32 VCO Divider Bypass No 1 Bypassed VCO Divider 2to32 No 2to32 Bypassed Table 28 Frequency Division for Divider 3 and Divider 4 VCO Divider Channel Divider Setting Resulting Frequency Setting X 1 X 2 Division 2to6 Bypass Bypass 2 to 6 x 1 x 1 2to6 2 to 32 Bypass 2 to 6 x 2 to 32 x 1 2to6 2 to 32 2 to 32 2 to 6 x 2 to 32 x 2 to 32 Bypass 1 1 1 Bypass 2 to 32 1 2 to 32 x 1 Bypass 2 to 32 2 to 32 2 to 32 x 2 to 32 Mode 0x1E1 0 VCO Divider 2 0 Used 1 1 Not used The channel dividers feeding the LVPECL output drivers contain one 2 to 32 frequency divider This divider provides for division by 2 to 32 Division by 1 is accomplished by bypassing the divider The dividers also provide for a programmable duty cycle with
99. le When LSB first is active the instruction and data bytes must be written from LSB to MSB Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes The internal byte address generator of the serial control port increments for each byte of the multibyte transfer cycle The AD9516 serial control port register address decrements from the register address just written toward 0x000 for multibyte I O operations if the MSB first mode is active default If the LSB first mode is active the register address of the serial control port increments from the address just written toward Register 0x232 for multibyte I O operations Streaming mode always terminates when it hits Address 0x232 Note that unused addresses are not skipped during multibyte I O operations Table 43 Streaming Mode No Addresses Are Skipped Write Mode Address Direction Stop Sequence LSB first Increment 0x230 0x231 0x232 stop MSB first Decrement 0x001 0x000 0x232 stop Rev A Page 45 of 76 AD9516 5 Table 44 Serial Control Port 16 Bit Instruction Word MSB First MSB LSB SDIO Ao a7 Ae as as A2 at ao p7 oe ps pa 02 01 po pe 05 ps 02 bo K DoNT CARE 16 BIT INSTRUCTION HEADER REG
100. lues are programmed Register 0x232 must be set to 0x01 for the values to take effect Mode 2 High Frequency Clock Distribution CLK or External VCO 1600 MHz The AD9516 power up default configuration has the PLL powered off and the routing of the input set so that the CLK CLK input is connected to the distribution section through the VCO divider divide by 2 divide by 3 divide by 4 divide by 5 divide by 6 This is a distribution only mode that allows for an external input of up to 2400 MHz see Table 4 For divide ratios other than 1 the maximum frequency that can be applied to the channel dividers is 1600 MHz Therefore the VCO divider must be used to divide down input frequencies that are greater than 1600 MHz before the channel dividers can be used for further division This input routing can also be used for lower input frequencies but the minimum divide is 2 before the channel dividers When the PLL is enabled this routing also allows the use of the PLL with an external VCO or VCXO with a frequency of lt 2400 MHz In this configuration the external VCO VCXO feeds directly into the prescaler 0x010 1 0 00b PLL normal operation PLL on 0x010 to 0x01D PLL settings Select and enable a reference input Set R P A PFD polarity and lc according to the intended loop configuration CLK selected as the source 0x1E1 1 Ob An external VCO requires an external loop filter that must be connected
101. n that is enabling OUT8A with OUT8B already CMOS Driver First in Second Pair 30 mW Static first output second pair turned on that is enabling OUT9A with OUT9B off and OUT8A and already on Fine Delay Block 50 mW Delay block off to delay block enabled maximum current setting Rev A Page 12 of 76 TIMING CHARACTERISTICS AD9516 5 Table 14 Parameter Min Typ Max Unit Test Conditions Comments LVPECL Termination 50 to Vs vera 2 V default amplitude setting 810 mV Output Rise Time tar 70 180 ps 2096 to 8096 measured differentially Output Fall Time tre 70 180 ps 8096 to 2096 measured differentially PROPAGATION DELAY CLK TO LVPECL OUTPUT High Frequency Clock Distribution Configuration 835 995 1180 ps See Figure 34 Clock Distribution Configuration 773 933 1090 ps See Figure 33 Variation with Temperature 0 8 ps C OUTPUT SKEW LVPECL OUTPUTS LVPECL Outputs That Share the Same Divider 5 15 ps LVPECL Outputs on Different Dividers 13 40 ps All LVPECL Outputs Across Multiple Parts 220 ps LVDS Termination 100 differential 3 5 mA setting Output Rise Time ta 170 350 ps 2096 to 8096 measured differentially Output Fall Time te 160 350 ps 2096 to 8096 measured differentially PROPAGATION DELAY tios CLK TO LVDS OUTPUT Delay off on all outputs OUT6 OUT7 OUT8 OUT9 For All Divide Values 1 4 1 8 2 1 ns Variation with Temperature 1 25
102. n clock input Powers down the clock input section including CLK buffer VCO divider and CLK tree section 0 normal operation default 1 powers down 0 Bypass VCO divider Bypasses or uses the VCO divider 0 uses VCO divider default 1 bypasses VCO divider Table 56 System Reg Addr Hex Bits Name Description 230 2 Power down SYNC Powers down the sync function 0 normal operation of the sync function default 1 powers down the SYNC circuitry 1 Power down distribution Powers down the reference for distribution section reference 0 normal operation of the reference for the distribution section default 1 powers down the reference for the distribution section 0 Soft SYNC The soft SYNC bit works the same as the SYNC pin except that the polarity of the bit is reversed that is a high level forces selected channels into a predetermined static state and a 1 to 0 transition triggers a SYNC 0 same as SYNC high default 1 same as SYNC low Rev A Page 69 of 76 AD9516 5 Table 57 Update All Registers Reg Addr Hex Bits Name Description 0x232 0 Update all registers This bit must be set to 1 to transfer the contents of the buffer registers into the active registers which happens on the next SCLK rising edge This bit is self clearing that is it does not have to be set back to 0 1 updates all active registers to the contents of the buffer registers self clearing
103. n pairs sharing a channel divider per pair two pairs of pairs four outputs in the case of CMOS The synchronization conditions apply to both outputs of a pair Each channel a divider and its outputs can be excluded from any sync operation by setting the nosync bit of the channel Channels that are set to ignore SYNC excluded channels do not set their outputs static during a sync operation and their outputs are not synchronized with those of the nonexcluded channels Clock Outputs The AD9516 offers three output level choices LVPECL LVDS and CMOS OUTO to OUTS are LVPECL differential outputs and OUT6 to are LVDS CMOS outputs These outputs can be configured as either LVDS differential or as pairs of single ended CMOS outputs LVPECL Outputs OUTO to OUT5 The LVPECL differential voltage VOD is selectable from 400 mV to 960 mV see Register 0 0 0 3 2 to Register 0 0 5 3 2 The LVPECL outputs have dedicated pins for power supply VS LVPECL allowing a separate power supply to be used Vs can range from 2 5 V to 3 3 V 3 3V GND Figure 47 LVPECL Output Simplified Equivalent Circuit 07972 033 The LVPECL output polarity can be set as noninverting or inverting which allows for the adjustment of the relative polarity of outputs within an application without requiring a board layout change Each LVPECL output can be powered down or powered up as needed Because of the architecture of the LVPEC
104. nc force high Divider 4 2 Divider 4 1 2 Blank Divider 4 0x00 DCCOFF 0x1A3 Reserved read only Ox1A4 Blank to Ox1DF VCO Divider and CLK Input VCO divider Blank VCO divider 0x02 Ox1E1 Input CLKs Reserved Power Reserved Bypass 0x00 down VCO divider clock input section Ox1E2 Blank to 0x22A System 0x230 Power down Reserved Power Power Soft SYNC 0x00 and SYNC down down SYNC distribution reference 0x231 Blank 0x00 Update All Registers 0x232 Update all Blank Update all 0x00 registers registers self clearing Rev A Page 51 of 76 AD9516 5 REGISTER MAP DESCRIPTIONS Table 48 through Table 57 provide a detailed description of each of the control register functions The registers are listed by hexadecimal address A range of bits for example from Bit 5 through Bit 2 is indicated using a colon and brackets as follows 5 2 Table 48 Serial Port Configuration Reg Addr Hex Bits Name Description 0x000 7 4 Mirrored Bits 3 0 Bits 7 4 should always mirror Bits 3 0 so that it does not matter whether the part is in MSB or LSB first mode see Bit 1 Register The user should set the bits as follows Bit 7 Bit 0 Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 3 Long instruction Short long instruction mode This part uses long instruction mode only so this bit should always be set to 1b 0 8 bit instruction short 1 16 bit instruction long default
105. nel Divider 3 and Channel Divider 4 each drive a pair of LVDS outputs giving four LVDS outputs OUT6 to OUT9 Alternatively each of these LVDS differential outputs can be configured individually as a pair A and B of CMOS single ended outputs providing for up to eight CMOS outputs By default the B output of each pair is off but can be turned on as desired Channel Divider 3 and Channel Divider 4 each consist of two cascaded 2 to 32 frequency dividers The channel frequency division is Dx x Dx or up to 1024 Divide by 1 is achieved by bypassing one or both of these dividers Both of the dividers also have DCC enabled by default but this function can be disabled if desired by setting the DCCOFF bit of the channel A coarse phase offset or delay is also programmable see the Phase Offset or Coarse Time Delay Divider 3 and Divider 4 section The channel dividers operate up to 1600 MHz The features and settings of the dividers are selected by programming the appropriate setup and control registers see Table 47 and Table 48 through Table 57 Table 34 Setting Division Dx for Divider 3 and Divider 4 Divider M N Bypass DCCOFF 3 3 1 0x199 7 4 0x199 3 0 0x19C 4 0x19D 0 3 2 Ox19B 7 4 0x19B 3 0 Ox19C 5 0x19D 0 4 4 1 0x19E 7 4 Ox19E 3 0 0x1A1 4 Ox1A2 0 4 2 0x1A0 7 4 0x1A0 3 0 0x1A1 5 Ox1A2 0 1 Note that the value stored in the register of cycles minus 1 For example Re
106. never the PLL is powered down or when the differential reference input is not selected The single ended buffers power down when the PLL is powered down and when their individual power down registers are set When the differential mode is selected the single ended inputs are powered down AD9516 5 In differential mode the reference input pins are internally self biased so that they can be ac coupled via capacitors It is possible to dc couple to these inputs If the differential REFIN is driven by a single ended signal the unused side REFIN should be decoupled via a suitable capacitor to a quiet ground Figure 37 shows the equivalent circuit of REFIN Vs 85 07972 066 Figure 37 REFIN Equivalent Circuit Reference Switchover The AD9516 supports dual single ended CMOS inputs as well as a single differential reference input In dual single ended reference mode automatic and manual PLL reference clock switching between REF1 Pin REFIN and REF2 Pin REFIN is supported This feature supports networking and other applications that require smooth switching of redundant references When used in conjunction with the automatic holdover function the AD9516 can achieve a worst case reference input switchover with an output frequency disturbance as low as 10 ppm When using reference switchover the single ended reference inputs should be dc coupled CMOS levels that are never allowed to go to high impedance If the i
107. ng Using the 9516 71 Using the AD9516 Outputs for ADC Clock Applications 71 LVPECL Clock Distribution seen 72 LVDS Clock Distribution 72 CMOS Clock Distribution 73 Outline Dimensions sses renei ee e teretes 74 Ordering Gilde eret tunt 74 Rev A Page 2 of 76 REVISION HISTORY 8 11 Rev 0 to Rev A Changes to Features Applications and General Description 1 Changes to CPRSET Pin Resistor Parameter Table 1 4 Change to P 2 DM 2 3 Parameter Table 2 iu Changes Test Conditions Comments Table 4 6 Moved Table 5 to End of Specifications and Renumbered Sequentially sd 13 Change to Shortest Delay Range Parameter Test Conditions Comments Table 14 sss 13 Moved Timing Diagrams 14 Change to Endnote Table 16 sse 15 Change to Caption Figure 8 sse 18 Change to Captions Figure 20 and Figure 21 20 Moved Figure 23 and Figure 24 sse 21 Added Figure 31 Renumbered Sequentially 22 Change to Mode 1 Clock Distribution or External VCO 1600 MHz Section seer errer 25 Changes to Mode 2 High Frequency Clock Distribution CLK or External VCO 1600 MHz Change to Table 22 Change to Charge Pump CP Section sss Changes to P
108. ng clock for a DAC or an ADC decreases the signal to noise ratio SNR and dynamic range of the converter A sampling clock with the lowest possible jitter provides the highest performance from a given converter Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured The phase noise of any external oscillators or clock sources is subtracted This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources each of which contributes its own phase noise to the total In many cases the phase noise of one element dominates the system phase noise When there are multiple contributors to phase noise the total is the square root of the sum of squares of the individual contributors Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured The time jitter of any external oscillators or clock sources is subtracted This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources each of which contributes its own time jitter to the total In many cases the time jitter of the external oscillators and clock sources dominates the system time jitter Rev A Page 23 of 76 AD9516 5
109. nputs are allowed to go to high impedance noise may cause the buffer to chatter causing false detection of the presence of a reference Reference switchover can be performed manually or automatically Manual switchover is performed either through Register 0x01C or by using the REF SEL pin Manual switchover requires the presence ofa clock on the reference input that is being switched to or that the deglitching feature be disabled Register 0x01C 7 The reference switching logic fails if this condition is not met and the PLL does not reacquire Rev A Page 29 of 76 AD9516 5 Automatic revertive switchover relies on the REFMON pin to indicate when REF1 disappears By programming Register 0x01B OxF7 and Register 0x01C 0x26 the REFMON pin is programmed to be high when REF1 is invalid which commands the switch to REF2 When REF1 is valid again the REFMON pin goes low and the part again locks to REF1 The STATUS pin can also be used for this function and REF2 can be used as the preferred reference A switchover deglitch feature ensures that the PLL does not receive rising edges that are far out of alignment with the newly selected reference Automatic nonrevertive switching is not supported Reference Divider R The reference inputs are routed to the reference divider R R a 14 bit counter can be set to any value from 0 to 16 383 by writing to Register 0x011 and Register 0x012 Both R 0 and 1 give divide by 1 The
110. ns that the divider is low for eight input clock cycles default 0x0 0x197 Divider 2 bypass Bypasses and powers down the divider route input to divider output 0 uses divider default 1 bypasses divider Divider 2 nosync No sync 0 obeys chip level SYNC signal default 1 ignores chip level SYNC signal Divider 2 force high Forces divider output to high This operation requires that the Divider 2 nosync bit Bit 6 also be set This bit has no effect if the Divider 2 bypass bit Bit 7 is set 0 normal operation default 1 divider output forced to the setting of the Divider 2 start high bit Divider 2 start high Selects clock output to start high or start low 0 starts low default 1 starts high 3 0 Divider 2 phase offset Phase offset default 0x0 0x198 Divider 2 direct to output Connects OUTA and OUTS to Divider 2 or directly to CLK input 0 OUT4 and OUTS are connected to Divider 2 default 1 if OXTE1 0 Ob the CLK is routed directly to OUT4 and OUTS If OXTE1 0 1b there is no effect Divider 2 DCCOFF Duty cycle correction function 0 enables duty cycle correction default 1 disables duty cycle correction Rev A Page 67 of 76 AD9516 5 Table 54 LVDS CMOS Channel Dividers Reg Addr Hex Bits Name Description 0x199 7 4 Low Cycles Divider 3
111. of selected reference status of differential reference active low 1 1 0 1 1 0 LVL Status of unselected reference not available in differential mode active low 1 1 011 1 1 LVL Status of REF1 frequency active low 1 1 1 0 0 0 Status of REF2 frequency active low Status of REF1 frequency AND status of REF2 frequency 1 1 1 DLD AND status of selected reference AND status of CLK 1 1 1 0 1 1 LVL Status of CLK frequency active low 1 1 1 1 1 LVL Selected reference low REF2 high REF1 1 1 1 1 0 1 LVL Digital lock detect DLD active low 1 1 1 1 1 0 LVL Holdover active active low 1 1 1 1 1 1 LVL Not available do not use 0x01B 7 CLK frequency Enables disables CLK frequency monitor monitor 0 disables CLK frequency monitor default 1 enables CLK frequency monitor 6 REF2 REFIN Enables or disables REF2 frequency monitor frequency 0 disables REF2 frequency monitor default monitor 1 enables REF2 frequency monitor 5 REF1 REFIN REF1 REFIN frequency monitor enable this is for both REF1 single ended and REFIN differential inputs as selected frequency by differential reference mode monitor 0 disables REF1 REFIN frequency monitor default 1 enables REF1 REFIN frequency monitor Rev A Page 56 of 76 AD9516 5 Reg Addr Hex Bits Name Description 4 0 REFMON pin Sel
112. oldover mode e Register 0x01D 0 1b enable holdover function complete VCO calibration before enabling this bit e Register 0x232 0x01 update all registers And finally e Connect REFMON pin to REFSEL pin Frequency Status Monitors The AD9516 contains three frequency status monitors that are used to indicate if the PLL reference or references in the case of single ended mode and the VCO have fallen below a threshold frequency Figure 42 is a diagram that shows their location in the PLL The PLL reference frequency monitors have two threshold frequencies normal and extended see Table 12 The reference frequency monitor thresholds are selected in Register 0x01B 7 5 The reference frequency monitor status can be found in Register 0x01F 3 1 REFMON CPRSET VCP QO Q s LOCK DETECT PLL REFERENCE PHASE FREQUENCY CHARGE DETECTOR 07972 070 Figure 42 Reference and CLK Status Monitors Rev A Page 34 of 76 AD9516 5 CLOCK DISTRIBUTION A clock channel consists of a pair or double pair in the case of CMOS of outputs that share a common divider A clock output consists of the drivers that connect to the output pins The clock outputs have either LVPECL or LVDS CMOS signal levels at the pins The AD9516 has five clock channels three channels are LVPECL six outputs two channels are LVDS CMOS up to four LVDS outputs or up to eight CMOS outputs Each channel has its own programmable divi
113. optional duty cycle correction when the divide ratio is odd Rev A Page 35 of 76 AD9516 5 A phase offset or delay in increments of the input clock cycle is selectable The channel dividers operate with a signal at their inputs up to 1600 MHz The features and settings of the dividers are selected by programming the appropriate setup and control registers see Table 47 through Table 57 VCO Divider The VCO divider provides frequency division between the external CLK input and the clock distribution channel dividers The VCO divider can be set to divide by 2 3 4 5 or 6 see Table 55 Register Ox1EO0 2 0 Channel Dividers LVPECL Outputs Each pair of LVPECL outputs is driven by a channel divider There are three channel dividers 0 1 and 2 driving six LVPECL outputs OUTO to OUTS Table 29 lists the register locations used for setting the division and other functions of these dividers The division is set by the values of M and N The divider can be bypassed equivalent to divide by 1 divider circuit is powered down by setting the bypass bit The duty cycle correction can be enabled or disabled according to the setting of the DCCOFF bits Table 29 Setting Dx for Divider 0 Divider 1 and Divider 2 The DCC function is enabled by default for each channel divider However the DCC function can be disabled individually for each channel divider by setting the DCCOFF bit for that channel Certain M and N values for a
114. ort Unidirectional Serial Data Output 22 1 0 3 3 V CMOS SDIO Serial Control Port Bidirectional Serial Data Input Output 23 3 3 V CMOS Chip Reset Active Low This pin has an internal 30 pull up resistor 24 3 3 V CMOS PD Chip Power Down Active Low This pin has an internal 30 pull up resistor 25 LVPECL OUT4 LVPECL Output One Side of a Differential Output 26 LVPECL OUT4 LVPECL Output One Side of a Differential LVPECL Output 27 41 54 Power VS LVPECL Extended Voltage 2 5 V to 3 3 V LVPECL Power Pins 28 LVPECL OUT5 LVPECL Output One Side of a Differential LVPECL Output 29 LVPECL OUTS LVPECL Output One Side of a Differential LVPECL Output 33 LVDS or CMOS OUT8 OUT8A LVDS CMOS Output One Side of a Differential LVDS Output or Single Ended CMOS Output 34 LVDS or CMOS OUT8 OUT8B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 35 LVDS or CMOS OUT9 OUT9A LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 36 LVDS or CMOS OUT9 OUT9B LVDS CMOS Output One Side of a Differential LVDS Output or a Single Ended CMOS Output 37 44 59 GND GND Ground Pins Including External Paddle EPAD The external die paddle on the EPAD bottom of the package must be connected to ground for proper operation 39 LVPECL OUT3 LVPECL Output One Side of a Differential LVPECL Output 40 LVPECL OUT3 LVPE
115. p level SYNC signal 2 Divider 3 force high Forces Divider 3 output high Requires that the Divider 3 nosync bit Bit 3 also be set 0 forces low default 1 forces high 1 Start High Divider 3 2 Divider 3 2 starts high low 0 starts low default 1 starts high 0 Start High Divider 3 1 Divider 3 1 starts high low 0 starts low default 1 starts high Ox19D 0 Divider 3 DCCOFF Duty cycle correction function 0 enables duty cycle correction default 1 disables duty cycle correction Ox19E 7 4 Low Cycles Divider 4 1 Number of clock cycles minus 1 of the Divider 4 1 input during which the Divider 4 1 output stays low A value of 0x7 means that the divider is low for eight input clock cycles default 0x2 3 0 High Cycles Divider 4 1 Number of clock cycles minus 1 of the Divider 4 1 input during which the Divider 4 1 output stays high A value of 0x7 means that the divider is low for eight input clock cycles default 0x2 Ox19F 7 4 Phase Offset Divider 4 2 Refers to LVDSCMOS channel divider function description default 0 0 3 0 Phase Offset Divider 4 1 Refers to LVDSCMOS channel divider function description default 0 0 Ox1A0 7 4 Low Cycles Divider 4 2 Number of clock cycles minus 1 of the Divider 4 2 input during which the Divider 4 2 output stays low A value of 0x7 means that the divider is low for eight input clock cycles default Ox1 3 0 High Cycles Divider 4 2 Number of clock cycles minus
116. ple selectable outputs see Table 49 Register 0x01A 4 Power VCP Power Supply for Charge Pump CP VS lt VCP lt 5 25 V 5 Loop filter CP Charge Pump Output This pin connects to an external loop filter This pin can be left unconnected if the PLL is not used 6 3 3 V CMOS STATUS Status Output This pin has multiple selectable outputs see Table 49 Register 0x017 7 3 3 V CMOS REF SEL Reference Select Selects REF1 low REF2 high This pin has an internal 30 pull down resistor 8 3 3 V CMOS SYNC Manual Synchronizations and Manual Holdover This pin initiates a manual synchronization and is also used for manual holdover Active low This pin has an internal 30 pull up resistor 9 10 15 18 N A NC NC No Connection These pins can be left floating 19 20 13 Differential CLK Along with CLK this is the differential input for the clock distribution section clock input 14 Differential CLK Along with CLK this is the differential input for the clock distribution section clock input If a single ended input is connected to the CLK pin connect a 0 1 uF bypass capacitor from CLK to ground Rev A Page 16 of 76 AD9516 5 Input Pin No Output Pin Type Mnemonic Description 16 3 3 V CMOS SCLK Serial Control Port Data Clock Signal 17 3 3 V CMOS Serial Control Port Chip Select Active Low This pin has an internal 30 pull up resistor 21 3 3 V CMOS SDO Serial Control P
117. ps C OUTPUT SKEW LVDS OUTPUTS Delay off on all outputs LVDS Outputs That Share the Same Divider 6 62 ps LVDS Outputs on Different Dividers 25 150 ps All LVDS Outputs Across Multiple Parts 430 ps CMOS Termination open Output Rise Time trc 495 1000 ps 20 to 80 10 pF Output Fall Time tec 475 985 ps 80 to 20 10 pF PROPAGATION DELAY tcmos CLK TO CMOS OUTPUT Fine delay off For All Divide Values 1 6 2 1 2 6 ns Variation with Temperature 2 6 ps C OUTPUT SKEW CMOS OUTPUTS Fine delay off CMOS Outputs That Share the Same Divider 4 66 ps All CMOS Outputs on Different Dividers 28 180 ps All CMOS Outputs Across Multiple Parts 675 ps DELAY ADJUST LVDS and CMOS Shortest Delay Range Register 1 4 0x0A7 Bits 5 0 1011116 Zero Scale 50 315 680 ps Register 2 0x0A5 8 Bits 5 0 000000b Full Scale 540 880 1180 ps Register 2 5 8 OxOAB Bits 5 0 2 101111b Longest Delay Range Register OxOA1 4 0x0A7 Bits 5 0 0000006 Zero Scale 200 570 950 ps Register 2 0x0A5 8 Bits 5 0 000000b Quarter Scale 1 72 2 31 2 89 ns Register 2 5 8 OxOAB Bits 5 0 001100b Full Scale 5 7 8 0 10 1 ns Register 2 5 8 OxOAB Bits 5 0 101111b Delay Variation with Temperature Short Delay Range Zero Scale 0 23 ps C Full Scale 0 02 ps C
118. put Frequency DC Coupled 0 250 MHz Slew rate 50 V us CMOS levels Input Sensitivity AC Coupled 0 8 V p p Should not exceed Vs p p Input Logic High 2 0 V Input Logic Low 0 8 V Input Current 100 100 pA Input Capacitance 2 pF Each pin REFIN REFIN REF1 REF2 PHASE FREQUENCY DETECTOR PFD PFD Input Frequency 100 MHz Antibacklash pulse width 1 3 ns 2 9 ns 45 MHz Antibacklash pulse width 6 0 ns Antibacklash Pulse Width 1 3 ns Register 0x017 1 0 2 O1b 2 9 ns Register 0x017 1 0 00b Register 0x017 1 0 11b 6 0 ns Register 0x017 1 0 10b CHARGE PUMP CP Sink Source Programmable High Value 4 8 mA With 5 1 Low Value 0 60 mA Absolute Accuracy 2 5 90 CPv Vce 2 CPRSET Range 24 10 kQ Ice High Impedance Mode Leakage 1 nA Sink and Source Current Matching 2 0 5 lt CPv lt Vo 0 5 V lce vs CPv 1 5 96 0 5 lt lt 0 5 V lce vs Temperature 2 96 VCP 2V Rev A Page 4 of 76 AD9516 5 Parameter Min Typ Max Unit Test Conditions Comments PRESCALER PART OF N DIVIDER See the VCXO VCO Feedback Divider N P A B section Prescaler Input Frequency P 1FD 300 MHz P 2FD 600 MHz P 3FD 900 MHz P 2 DM 2 3 200 MHz P 4 DM 4 5 1000 MHz P 8 DM 8 9 2400 MHz 16 16 17 3000 MHZ 32 32 33 3000 MHZ Prescaler Output Frequency 300 MHz A B counter input frequency prescaler input frequency divided by P PLL DIVIDER DELAYS Regis
119. re it is desirable to have DLD asserted only after the PLL is solidly locked This is made possible by using the current source lock detect function This function is set when it is selected as the output from the LD pin control Register 0x01A 5 0 The current source lock detect provides a current of 110 pA when DLD is true and it shorts to ground when DLD is false Ifa capacitor is connected to the LD pin it charges at a rate that is determined by the current source during the DLD true time but is discharged nearly instantly when DLD is false By monitoring the voltage at the LD pin top of the capacitor it is possible to get a logic high level only after the DLD has been true for a sufficiently long time Any momentary DLD false resets the charging By selecting a properly sized capacitor it is possible to delay a lock detect indication until the PLL is locked in a stable condition and the lock detect does not chatter Rev A Page 31 of 76 AD9516 5 The voltage on the capacitor can be sensed by an external comparator connected to the LD pin However there is an internal LD pin comparator that can be read at the REFMON pin control Register 0x01B 4 0 or the STATUS pin control Register 0x017 7 2 as an active high signal It is also available as an active low signal REFMON Register 0x01B 4 0 and STATUS Register 0x017 7 2 The internal LD pin comparator trip point and hysteresis are listed in Table 12 AD9516 5 110pA
120. rol 9 Reserved 0x00 readback Reserved Holdover REF2 CLK REF2 REF1 Digital N A read only active selected frequency gt frequency frequency lock detect threshold threshold threshold 0x020 Blank to Ox04F Rev A Page 49 of 76 AD9516 5 Ref Default Addr Value Hex Parameter Bit 7 MSB Bit6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 LSB Hex Fine Delay Adjust OUT6 to OUT9 OUT6 delay Blank OUT6 delay 0x01 bypass bypass 1 OUT6 delay Blank OUT6 ramp capacitors OUT6 ramp current 0x00 full scale 0x0A2 OUT6 delay Blank OUT6 delay fraction 0x00 fraction OUT7 delay Blank OUT7 delay 0x01 bypass bypass 4 OUT7 delay Blank OUT7 ramp capacitors OUT7 ramp current 0x00 full scale 0x0A5 OUT7 delay Blank OUT7 delay fraction 0x00 fraction 0x0A6 8 delay Blank OUTS delay 0x01 bypass bypass 7 8 delay Blank OUTS8 ramp capacitors 8 ramp current 0x00 full scale Ox0A8 8 delay Blank OUTS delay fraction 0x00 fraction 0x0A9 OUTO delay Blank OUT delay 0x01 bypass bypass OUTO delay Blank OUT ramp capacitors OUT ramp current 0x00 full scale OUT9 delay Blank OUT delay fraction 0x00 fraction OxOAC Blank to OxOEF LVPECL Outputs OxOFO OUTO Bl
121. s high cycles s Anodd Dxy must be set as Mxy Nxy 1 number of low cycles must be one greater than the number of high cycles s If only one divider is bypassed it must be the second divider X 2 s Ifonly one divider has an even divide by it must be the second divider X 2 The possibilities for the duty cycle of the output clock from Divider 3 and Divider 4 are shown in Table 35 through Table 39 Table 35 Divider 3 and Divider 4 Duty Cycle VCO Divider Used Duty Cycle Correction Off DCCOFF 1 Table 36 Divider 3 and Divider 4 Duty Cycle VCO Divider Not Used Duty Cycle Correction Off DCCOFF 1 Input Dxa Dx2 Clock Duty Output Cycle 2 Nx2 Mx2 2 Duty Cycle 5096 Bypassed Bypassed 5096 X Bypassed Bypassed X 50 Even odd Bypassed 1 Nx 2 X Even odd Bypassed 1 Nx 2 50 Even odd Even odd Nx2 1 Nx2 Mx2 2 X Even odd Even odd Nx2 1 Nx2 Mx2 2 Table 37 Divider 3 and Divider 4 Duty Cycle VCO Divider Used Duty Cycle Correction On DCCOFF 0 VCO Divider Input Duty Cycle 50 vco Dx Output Divider 2 2 Duty Cycle Even Bypassed Bypassed 5096 Odd Bypassed Bypassed 5096 Even Even Nx Mx Bypassed 5090 Even Nx Mx Bypassed 50 Even Odd Mx 1 Bypassed 5096 Odd Odd Mx 1 Bypassed
122. s Setup time between the CS falling edge and the SCLK rising edge start of communication cycle tc Setup time between the SCLK rising edge and the CS rising edge end of communication cycle tHicH Minimum period that SCLK should be in a logic high state trow Minimum period that SCLK should be in a logic low state tov SCLK to valid SDIO and SDO see Figure 55 Rev A Page 47 of 76 AD9516 5 THERMAL PERFORMANCE Table 46 Thermal Parameters for 64 Lead LFCSP Symbol Thermal Characteristic Using a JEDEC JESD51 7 Plus JEDEC JESD51 5 2S2P Test Board Value C W Junction to ambient thermal resistance natural convection JEDEC JESD51 2 still air 22 0 Oma Junction to ambient thermal resistance 1 0 m sec airflow per JEDEC JESD51 6 moving air 19 2 Oma Junction to ambient thermal resistance 2 0 m sec airflow per JEDEC JESD51 6 moving air 17 2 Junction to board characterization parameter 1 0 m sec airflow JESD51 6 moving air 11 6 and JEDEC JESD51 8 Junction to case thermal resistance die to heat sink per MIL Std 883 Method 1012 1 1 3 Vy Junction to top of package characterization parameter natural convection per JEDEC JESD51 2 still air 0 1 The AD9516 is specified for a case temperature Tcasz To ensure that Tcasc is not exceeded an airflow source can be used Use the following equation to determine the junction temperature on the application PCB T Ta
123. s pin can be left unconnected when the PLL is not used 64 Reference REFIN REF1 Along with REFIN this pin is the differential input for the PLL reference input Alternatively this pin is a single ended input for REF1 This pin can be left unconnected when the PLL is not used Rev A Page 17 of 76 AD9516 5 TYPICAL PERFORMA CURRENT mA CURRENT mA CURRENT mA Figure 7 Current vs Frequency Direct to Output LVPECL Outputs 180 160 140 120 100 240 220 200 180 160 140 120 100 Figure 9 Current vs Frequency CMOS Outputs with 10 pF Load 3 CHANNELS 6 LVPECL 3 CHANNELS 3 LVPECL 2 CHANNELS 2 LVPECL 1 CHANNEL 1 LVPECL 500 1000 1500 2000 2500 3000 FREQUENCY MHz 2 CHANNELS 4 LVDS 2 CHANNELS 2 LVDS 1 CHANNEL 1 LVDS 200 400 600 800 FREQUENCY MHz Figure 8 Current vs Frequency LVDS Outputs Includes Clock Distribution Current Draw 2 CHANNELS 8 CMOS 2 CHANNELS 2 CMOS 1 CHANNEL 2 CMOS 1 CHANNEL 1 CMOS 50 100 150 200 250 FREQUENCY MHz NCE CHARACTERISTICS 07972 007 07972 008 PFD PHASE NOISE REFERRED TO PFD INPUT 07972 009 Rev A Page 18 of 76 CURRENT FROM CP PIN mA CURRENT FROM CP PIN mA dBc Hz UMP DOWN 0 0 5 1 0 1 5 2 0 2 5 3 0 VOLTAGE PIN V Figure 10
124. section Table 33 Setting Phase Offset and Division for Divider 0 Divider 1 and Divider 2 Start Phase Low High Divider High SH Offset PO Cycles M Cycles N 0 0x191 4 0x191 3 0 0x190 7 4 0x190 3 0 1 0x194 4 0x194 3 0 0x193 7 4 0x193 3 0 2 0x197 4 0x197 3 0 0x196 7 4 0x196 3 0 1 Note that the value stored in the register of cycles minus 1 For example Register 0x190 7 4 0001b equals two low cycles M 2 for Divider 0 Let delay in seconds A delay in cycles of clock signal at input to Dx Tx period of the clock signal at the input of the divider Dx in seconds 16 x SH 4 8 x PO 3 4 x PO 2 2 x PO 1 1 x PO 0 The channel divide by is set as N high cycles and M low cycles AD9516 5 Case 1 For lt 15 A x Tx 2 For gt 16 16 1 Ac AV Tx By giving each divider a different phase offset output to output delays can be set in increments of the channel divider input clock cycle Figure 43 shows the results of setting such a coarse offset between outputs 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CHANNEL DIVIDER INPUT gt CHANNEL DIVIDER 5 DIV 4 DUTY 50 SH 0 DIVIDER 0 po lt 0 1 SH 0 PO 1 SH 0 DIVIDER 2 pg 2 1x Tx 5 2xTx B Figure 43 Effect of Coarse Phase Offset or Delay Channel Dividers LVDS CMOS Outputs Chan
125. set 150 dBc Hz At 100 kHz Offset 155 dBc Hz At 1 MHz Offset 157 dBc Hz 510 MHz Offset 157 dBc Hz CLK TO LVDS ADDITIVE PHASE NOISE Distribution section only does not include input slew CLK 1 6 GHz Output 800 MHz rate 1 V ns Divider 2 At 10 Hz Offset 103 dBc Hz At 100 Hz Offset 110 dBc Hz At 1 kHz Offset 120 dBc Hz At 10 kHz Offset 127 dBc Hz At 100 kHz Offset 133 dBc Hz At 1 MHz Offset 138 dBc Hz At 10 MHz Offset 147 dBc Hz At 100 MHz Offset 149 dBc Hz CLK 1 6 GHz Output 400 MHz Input slew rate gt 1 V ns Divider 4 At 10 Hz Offset 114 dBc Hz At 100 Hz Offset 122 dBc Hz At 1 kHz Offset 132 dBc Hz At 10 kHz Offset 140 dBc Hz At 100 kHz Offset 146 dBc Hz At 1 MHz Offset 150 dBc Hz 510 MHz Offset 155 dBc Hz CLK TO CMOS ADDITIVE PHASE NOISE Distribution section only does not include PLL input CLK 1 GHz Output 250 MHz slew rate 1 V ns Divider 4 At 10 Hz Offset 110 dBc Hz At 100 Hz Offset 120 dBc Hz At 1 kHz Offset 127 dBc Hz At 10 kHz Offset 136 dBc Hz At 100 kHz Offset 144 dBc Hz At 1 MHz Offset 147 dBc Hz gt 10 MHz Offset 154 dBc Hz Rev A Page 7 of 76 AD9516 5 Parameter Min Typ Max Unit Test Conditions Comments CLK 1 GHz Output 50 MHz Input slew rate gt 1 V ns Divider 20 At 10 Hz Offset 124 dBc Hz At 100 Hz Offset 134 dBc Hz At 1 kHz Offset 142 dBc Hz At 10 kHz Offset 151 dBc Hz At 100 kHz
126. set the channel dividers to ignore the SYNC pin at least after an initial SYNC event If the dividers are not set to ignore the SYNC pin the distribution outputs turn off each time SYNC is taken low to put the part into holdover Rev A Page 32 of 76 Automatic Internal Holdover Mode When enabled this function automatically puts the charge pump into a high impedance state when the loop loses lock The assumption is that the only reason that the loop loses lock is due to the PLL losing the reference clock therefore the holdover function puts the charge pump into a high impedance state to maintain the VCO frequency as close as possible to the original frequency before the reference clock disappears See Figure 41 for a flowchart of the internal automatic holdover function operation The holdover function senses the logic level of the LD pin asa condition to enter holdover The signal at LD can be from the DLD ALD or current source LD CSDLD mode It is possible to disable the LD comparator Register 0x01D 3 which causes the holdover function to always sense LD as high If DLD is used it is possible for the DLD signal to chatter somewhat while the PLL is reacquiring lock The holdover function may retrigger thereby preventing the holdover mode from ever terminating Use of the current source lock detect mode is recommended to avoid this situation see the Current Source Digital Lock Detect section When in holdover
127. ter 0x019 R Bits 5 3 N Bits 2 0 see Table 49 000 Off ps 001 330 ps 010 440 ps 011 550 ps 100 660 ps 101 770 ps 110 880 ps 111 990 ps NOISE CHARACTERISTICS In Band Phase Noise of the Charge The PLL in band phase noise floor is estimated by Pump Phase Frequency Detector measuring the in band phase noise at the output of In Band Is Within the LBW of the PLL the VCO and subtracting 20 log N where N is the value of the N divider At 500 kHz PFD Frequency 165 dBc Hz At 1 MHz PFD Frequency 162 dBc Hz At 10 MHz PFD Frequency 151 dBc Hz At 50 MHz PFD Frequency 143 dBc Hz PLL Figure of Merit FOM 220 dBc Hz Reference slew rate gt 0 25 V ns FOM 10 log ferp is an approximation of the PFD CP in band phase noise in the flat region inside the PLL loop bandwidth when running closed loop the phase noise as observed at the VCO output is increased by 20 log N PLL DIGITAL LOCK DETECT WINDOW Signal available at the LD STATUS and REFMON pins when selected by appropriate register settings Required to Lock Coincidence of Edges Selected by Register 0x017 1 0 and Register 0 018 4 Low Range ABP 1 3 ns 2 9 ns 3 5 ns Register 0x017 1 0 006 016 11b Register 0x018 4 1b High Range ABP 1 3 ns 2 9 ns 7 5 ns Register 0x017 1 0 00b 01b 11b Register Ox018 4 Ob High Range ABP 6 0 ns 3 5 ns Register 0x017 1 0 10b Register Ox018 4 Ob To Unlock After Lock Hysteresis Low Range ABP 1 3 ns 2 9 ns 7 ns
128. ter 0x230 1 By executing synchronization of the outputs as part of the chip power up sequence By forcing the RESET pin low then releasing it chip reset By forcing the PD pin low then releasing it chip power down The most common way to execute the SYNC function is to use the SYNC pin to do a manual synchronization of the outputs This requires a low going signal on the SYNC pin which is held low and then released when synchronization is desired The timing of the SYNC operation is shown in Figure 45 using VCO divider and Figure 46 VCO divider not used There is an uncertainty of up to one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9516 The delay from the SYNC rising edge to the beginning of synchronized output clocking is CHANNEL DIVIDER OUTPUT CLOCKING INPUT TO CHANNEL DIVIDER AD9516 5 between 14 and 15 cycles of clock at the channel divider input plus either one cycle of the VCO divider input see Figure 45 or one cycle of the CLK input see Figure 46 depending on whether the VCO divider is used Cycles are counted from the rising edge of the signal Another common way to execute the SYNC function is by setting and resetting the soft SYNC bit at Register 0x230 0 see Table 47 through Table 57 for details Both the setting and resetting of the soft SYNC bit require an update all registers operation
129. ting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 O 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT8 CMOS B In CMOS mode turns on off the CMOS B output There is no effect in LVDS mode 0 turns off the CMOS B output default 1 turns on the CMOS B output 3 OUTS select LVDS CMOS Selects LVDS or CMOS logic levels 0 LVDS default 1 CMOS 2 1 OUT8 LVDS output current Sets output current level in LVDS mode This has no effect in CMOS mode 2 1 Current mA Recommended Termination 1 75 100 0 1 3 5 100 default 1 0 5 25 50 1 1 7 50 0 OUT8 power down Power down output LVDS CMOS 0 powers on default 1 powers off 0x143 7 5 OUT9 output polarity In CMOS mode Bits 7 5 select the output polarity of each CMOS output In LVDS mode only Bit 5 determines LVDS polarity 7 6 5 OUT9A CMOS OUT9B CMOS OUT9 LVDS 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting default 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting O 1 Inverting Noninverting Inverting O 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting 4 OUT9 CMOS B In CMOS mode turns on off the CMOS B output This has no effect in LVDS mode 0 turns off the CMOS B output default 1 turns on t
130. ting of 000000b gives zero delay fraction Only delay values of up to 47 decimals 101111b 2 are supported default 0x00 Table 51 LVPECL Outputs Reg Addr Hex Bits Name Description OxOFO 4 OUTO invert Sets the output polarity 0 noninverting default 1 inverting 3 2 OUTOLVPECL Sets the LVPECL output differential voltage Vor differential 3 2 Van mV voltage 400 O 1 600 1 O 780 default 1 1 960 1 0 OUTO LVPECL power down modes power down 1 o Mode Output 0 0 Normal operation default On O 1 Partial power down reference on use only if there are no external load resistors Off 1 O Partial power down reference on safe LVPECL power down off 1 1 Total power down reference off use only if there are no external load resistors Off Rev A Page 61 of 76 AD9516 5 Reg Addr Hex Bits Name Description OxOF1 4 OUT1 invert Sets the output polarity 0 noninverting default 1 inverting 3 2 OUT1 LVPECL Sets the LVPECL output differential voltage Vor differential 2 Van mV voltage 400 O 1 600 1 O 780 default 1 1 960 1 0 OUT1 LVPECL power down modes power down 1 o Mode Output 0 0 Normal operation On O 1 Partial power down reference on use only
131. tors capacitors and the ramp current sets the full scale delay 5 4 Number of Capacitors O O O 4 default 00 10 113 0 11013 0111112 1101013 14101112 1111012 11111411 Rev 59 of 76 AD9516 5 Reg Addr Hex Bits Name Description Ox0A4 2 0 OUT7 ramp Ramp current for the delay function The combination of the number of capacitors and the ramp current current sets the full scale delay 2 1 0 Current pA O O O 200 default O 10111 400 600 01111 800 10 0 1000 110 1 1200 1 1 0 1400 1 1 1 1600 Ox0A5 5 0 OUT7 delay Selects the fraction of the full scale delay desired 6 bit binary A setting of 000000b gives zero delay fraction Only delay values of up to 47 decimals 101111b 2 are supported default 0x00 0x0A6 0 OUTS delay Bypasses or uses the delay function bypass 0 uses the delay function 1 bypasses the delay function default OxOA7 5 3 OUT8 ramp Selects the number of ramp capacitors used by the delay function The combination of the number of capacitors capacitors and the ramp current sets the full scale delay 5 4 3 Number of Capacitors O O O 4 default 00 10 113 0111013 0111112 1101013 14101112 1111012 1111111 2 0 OUT8 ramp Ramp current for the delay function The combination of the number of capacitors and the ramp
132. under certain termination conditions Individual Clock Output Power Down Any ofthe clock distribution outputs can be powered down individually by writing to the appropriate registers The register map details the individual power down settings for each output The LVDS CMOS outputs can be powered down regardless of their output load configuration The LVPECL outputs have multiple power down modes see Table 53 that give some flexibility in dealing with the various output termination conditions When the mode is set to 10b the LVPECL output is protected from reverse bias to 2 VBE 1 V If the mode is set to 11b the LVPECL output is not protected from reverse bias and can be damaged under certain termination conditions This setting also affects the operation when the distribution block is powered down with 0x230 1 Ib see the Distribution Power Down section Individual Circuit Block Power Down Other AD9516 circuit blocks such as CLK REF1 and REF2 can be powered down individually This gives flexibility in configuring the part for power savings whenever certain chip functions are not needed Rev A Page 43 of 76 AD9516 5 SERIAL CONTROL PORT The AD9516 serial control port is a flexible synchronous serial communications port that allows an easy interface with many industry standard microcontrollers and microprocessors The AD9516 serial control port is compatible with most synchronous transfer formats including both
133. v A Page 74 of 76 AD9516 5 NOTES Rev A Page 75 of 76 AD9516 5 NOTES 2009 2011 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D07972 0 8 11 A DEVICES www analo g com Rev A Page 76 of 76
134. w 1 1 1 0 0 0 LVL Status of REF2 frequency active low LVL Status of REF1 frequency AND status of REF2 frequency DLD AND status of selected reference AND status of CLK 1 1 1 0 1 1 LVL Status of CLK Frequency active low 1 1 1 1 0 0 LVL Selected reference low REF2 high 1 1 1 1 1 0 1 LVL Digital lock detect DLD active low 1 1 1 1 1 0 LVL Holdover active active low 1 1 1 1 1 1 LVL LD pin comparator output active low Rev A Page 54 of 76 AD9516 5 Reg Addr Hex Bits Name Description 1 0 Antibacklash 1 0 Antibacklash Pulse Width ns pulse width 0 2 9 default 0 1 1 3 1 0 6 0 1 1 2 9 0x018 6 5 Lock detect Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked counter condition 6 5 PFD Cycles to Determine Lock 0 0 5 default 0 1 16 1 0 64 1 1 255 4 Digital lock If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time the digital detect window lock detect flag is set The flag remains set until the time difference is greater than the loss of lock threshold 0 high range default 1 low range 3 Disable digital Digital lock detect operation lock detect 0 normal lock detect operation default 1 disables lock detect 0 019 7 6
135. zax C of the VCO control voltage For most applications the frequency is sufficient for 3 sec to 5 sec Both a manual holdover mode using the SYNC pin and an automatic holdover mode are provided To use either function the holdover function must be enabled Register 0x01D 0 and Register OxO1D 2 Manual Holdover Mode A manual holdover mode can be enabled that allows the user to place the charge pump into a high impedance state when the SYNC pin is asserted low This operation is edge sensitive not level sensitive The charge pump enters a high impedance state immediately To take the charge pump out of a high impedance state take the SYNC pin high The charge pump then leaves the high impedance state synchronously with the next PFD rising edge from the reference clock This prevents extraneous charge pump events from occurring during the time between SYNC going high and the next PFD event This also means that the charge pump stays in a high impedance state as long as there is no reference clock present The B counter in the N divider is reset synchronously with the charge pump leaving the high impedance state on the reference path PFD event This helps align the edges out of the Rand N dividers for faster settling of the PLL Because the prescaler is not reset this feature works best when the B and R numbers are close because this results in a smaller phase difference for the loop to settle out When using this mode

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