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ANALOG DEVICES AD9550 handbook

1. 100M 09057 005 09057 006 09057 007 MAGNITUDE dB MAGNITUDE dB MAGNITUDE dB JITTER TRANSFER 25 75 100 125 150 175 50 FREQUENCY OFFSET Hz 10 100 1k FREQUENCY OFFSET Hz Figure 9 Jitter Transfer Loop Bandwidth 170 Hz 1k 10k 100k 1M FREQUENCY OFFSET Hz Figure 10 Jitter Transfer Loop Bandwidth 20 kHz JITTER TRANS JITTER PEAKING 30 40 50 60 FREQUENCY OFFSET kHz 30 10k 100k 1M FREQUENCY OFFSET Hz Figure 11 Jitter Transfer Loop Bandwidth 75 kHz 09057 008 SUPPLY CURRENT mA SUPPLY CURRENT mA 09057 110 09057 009 OUTPUT VOLTAGE V p p Rev 0 Page 9 of 20 AD9550 LVPECL 0 100 200 300 400 500 600 700 800 900 FREQUENCY MHz Figure 12 Supply Current vs Output Frequency LVPECL and LVDS 10 pF Load 30 20pF 25 10pF 20 5pF 15 10 0 100 200 300 400 500 600 FREQUENCY MHz Figure 13 Supply Current vs Output Frequency CMOS 10 pF Load 0 100 200 300 400 500 600 FREQUENCY MHz Figure 14 Peak to Peak Output Voltage vs Frequency CMOS 09057 010 09057 011 09057 0
2. A3 to AO free MHz Divide by 5 x2 R Decimal 0000 Not used 0001 0 008 Bypassed On 1 0010 1 536 Bypassed Bypassed 96 0011 2 048 Bypassed Bypassed 128 0100 16 384 Bypassed Bypassed 1024 0101 19 44 Bypassed Bypassed 1215 0110 25 Bypassed On 3125 0111 38 88 Bypassed Bypassed 2430 1000 61 44 Bypassed Bypassed 3840 1001 77 76 Bypassed Bypassed 4860 1010 122 88 Bypassed Bypassed 7680 1011 125 On On 3125 1100 1 544 Bypassed On 193 11013 155 52 Bypassed Bypassed 59 1110 25 77 76 Bypassed Bypassed 16 1111 200 3 Bypassed Bypassed 5000 For divide by 5 and x2 frequency scalers on indicates active Using to AO 0110 to yield a 25 MHz to 125 MHz conversion provides a loop bandwidth of 170 Hz An alternate 25 MHz to 125 MHz conversion uses to 0 1110 which provides a loop bandwidth of 20 kHz 3 to AO 1101 only works with Y5 to YO 101101 through 110010 A3to AO 1110 only works with Y5 to YO 110011 or 111111 Table 7 Pin Configured Output Frequency Yx Pins Y5 to YO fico MHz four MHz four MHz P P P 000000 Not used 000001 3686 4 245 76 245 76 5 3 3 000010 3686 4 245 76 122 88 5 3 6 000011 3686 4 245 76 61 44 5 3 12 000100 3686 4 245 76 16 384 5 3 45 000101 3686 4 245 76 2 048 5 3 360 000110 3686 4 245 76 1 536 5 3 480 000111 3686 4 122 88 122 88 5 6 6 001000 3686 4 122 88 61 44 5 6 12 001001 3686 4 122 88 16 384 5 6 45 001010 3686 4 122 88 2 048 5 6 360 00101
3. 4 fo 4 6 4 4 110011 3732 48 622 08 622 08 6 1 1 110100 to 111110 Undefined 111111 3750 125 25 5 6 30 1 fo 39 191 04 59 MHz Table 8 Pin Configuration vs PLL Feedback Divider Value and Charge Pump Value A3 to Y5 to YO 0001 to 1100 000001 010101 230 400 121 010110 to 011011 234 375 121 011100 100001 233 280 121 100010 to 100110 230 400 121 100111 to 101011 225 000 121 101100 231 600 121 101101 to 111111 Undefined 1101 000001 to 101100 Undefined 101101 to 110010 1512 255 110010 to 111111 Undefined 1110 000001 to 110010 Undefined 110011 768 121 110100 to 111110 Undefined 111111 2400 121 1111 000001 to 010101 276 480 145 010110 to 011011 281 250 145 011100 to 100001 279 936 145 100010 to 100110 276 480 145 100111 to 101011 270 000 145 101100 277 920 145 101101 to 111111 Undefined 1 PLL feedback divider value decimal Charge pump value decimal Multiply by 3 5 pA to yield Rev 0 Page 14 of 20 AD9550 DESCRIPTION OF FUNCTIONAL BLOCKS Input Frequency Prescaler Divide by 5 The divide by 5 prescaler provides the option to reduce the input reference frequency by a factor of five Note that the pre scaler physically precedes the x2 frequency multiplier This allows the prescaler to bring a high frequency reference clock down to a frequency that is within the range of the x2 frequency multiplier Input x2 Frequency Multiplier The x2 frequency multiplier doubles the frequency at it
4. 42 mA CMOS Configured Output 29 34 mA Pin 28 LVDS Configured Output 35 41 mA LVPECL Configured Output 36 42 mA CMOS Configured Output 29 34 mA LOGIC INPUT PINS Input Characteristics Logic 1 Voltage 1 02 V For the CMOS inputs a static Logic 1 results from either a pull up resistor or no connection Logic 0 Voltage V 0 64 V Logic 1 Current l 3 yA Logic 0 Current 17 LOGIC OUTPUT PINS Output Characteristics Tested at 1 mA load current Output Voltage High Vo 2 7 V Output Voltage Low Vo 0 19 V RESET Pin Input Characteristics Input Voltage High V 1 96 V Input Voltage Low Vi 0 85 V Input Current High ly 0 3 12 5 pA Input Current Low ly 31 43 Minimum Pulse Width Low 150 us Tested with an active source driving the RESET pin REFERENCE CLOCK INPUT CHARACTERISTICS CMOS Single Ended Input Input Frequency Range 0 008 200 MHz Input High Voltage 1 62 V Input Low Voltage 0 52 V Input Threshold Voltage 1 0 V When ac coupling to the input receiver the user must dc bias the input to 1 V Input High Current 0 04 uA Input Low Current 0 03 uA Input Capacitance 3 pF Duty Cycle Pulse width high and pulse width low establish the bounds for duty cycle Pulse Width Low 2 ns Pulse Width High 2 ns Rev 0 Page 3 of 20 AD9550 Parameter Min Typ Max Unit Test Conditions Comments x2 Frequency Multiplier 125 MHz To avoid excessive reference spurs the x2 multiplier requires 4896 to 5296 duty cycle ref
5. MODE Differential Output Voltage Swing Output driver static for dynamic performance see Figure 15 Balanced Vop 297 398 mV Voltage swing between output pins output driver static Unbalanced 8 3 mV Absolute difference between voltage swing of normal pin and inverted pin output driver static Offset Voltage Common Mode Vos 1 17 1 35 V Output driver static Common Mode Difference 7 3 mV Voltage difference between output pins output driver static Short Circuit Output Current 17 24 mA Frequency Range 0 810 MHz Duty Cycle 40 60 96 Up to 805 MHz output frequency Rise Fall Time 2096 to 80 285 355 ps 100 O termination between both pins of the output driver Rev 0 Page 4 of 20 AD9550 Parameter Min Typ Max Unit Test Conditions Comments CMOS MODE Output Voltage High Vo Output driver static log 10 mA 2 8 V lg 1 mA 2 8 V Output Voltage Low Vo Output driver static lg 10 mA 0 5 V lg 1 mA 0 3 V Frequency Range 0 200 MHz 3 3 V CMOS output toggle rates in excess of the maximum are possible but with reduced amplitude see Figure 14 Duty Cycle 45 55 96 At maximum output frequency Rise Fall Time 20 to 80 500 745 ps 3 3 V CMOS 10 pF load The listed values are for the slower edge rise or fall JITTER CHARACTERISTICS Table 3 Parameter Min Typ Max Unit Test Conditions Comments JITTER GENERATION Output 12 kHz to 20 MHz LVPECL 1 31 ps rms Input 122 88 MHz o
6. Type Description 29 30 31 YO Y1 2 Control Pins These pins select one of 52 preset output frequency combinations for OUT1 and 32 1 2 Y4 Y5 OUT2 Each pin has an internal 100 pull up resistor 3 4 5 6 AO 1 2 Control Pins These pins select one of 15 preset input reference frequencies Each pin has internal 100 kQ pull up resistor 7 REF Reference Clock Input Connect this pin to a single ended active clock input signal 8 11 24 25 GND Ground 9 10 NC No Connection Make no external connection to these pins Do not connect to GND or VDD 12 13 14 OM2 Control Pins These pins select one of eight preset output configurations see Table 10 Each pin OMO has an internal 40 pull up resistor 15 RESET Reset Internal Logic This is digital input pin This pin is active low with 100 internal pull up resistor and resets the internal logic to default states see the Automatic Power On Reset section 16 FILTER 1 0 Loop Filter Node for the PLL Connect external loop filter components see Figure 24 from this pin to Pin 17 LDO 17 19 LDO P O LDO Decoupling Pins Connect a 0 47 uF decoupling capacitor from each of these pins to ground 18 21 28 VDD P Power Supply Connection 3 3 V Supply Pin 21 supplies the OUT2 driver and Pin 28 supplies the OUTI driver 20 LOCKED Locked Status Indicator for the PLL Active high 26 22 OUT1 OUT2 Complementary Square Wave Clock
7. the frequency at OUT2 The P and P dividers are each programmable over a range of 1 to 1023 which results in a frequency at OUT1 or OUT2 that is an integer submultiple of the frequency at the output of the P divider Output Driver Mode Control Three mode control pins OMI and OM2 establish the logic family and pin function of the output drivers The logic families include LVDS LVPECL and CMOS see Table 10 Table 10 Logic Family Assignment via the OMx Pins Logic Family Pin OMx OUT1 OUT2 000 LVPECL LVPECL 001 LVPECL LVDS 010 LVDS LVPECL 011 LVPECL CMOS 100 LVDS LVDS 101 LVDS CMOS 110 CMOS LVDS 111 CMOS CMOS Because both output drivers support the LVDS and LVPECL logic families each driver has two pins to handle the differential signals associated with these two logic families The OUT1 driver uses the OUT1 and OUTI pins and the OUT2 driver uses the OUT2 and OUT2 pins When the OMx pins select the CMOS logic family the signal at the OUT1 pin is a phase aligned replica of the signal at the OUTI pin and the signal at the OUT2 pin is a phase aligned replica of the signal at the OUT2 pin JITTER TOLERANCE Jitter tolerance is the ability of the AD9550 to maintain lock in the presence of sinusoidal jitter The AD9550 meets the input jitter tolerance mask per Telcordia GR 253 CORE see Figure 25 The acceptable jitter tolerance is the region above the mask 1000 2 Qa 5 100 AD9
8. 1 3686 4 122 88 1 536 5 6 480 001100 3686 4 61 44 61 44 5 12 12 001101 3686 4 61 44 16 384 5 12 45 001110 3686 4 61 44 2 048 5 12 360 001111 3686 4 61 44 1 536 5 12 480 010000 3686 4 16 384 16 384 5 45 45 010001 3686 4 16 384 2 048 5 45 360 010010 3686 4 16 384 1 536 5 45 480 010011 3686 4 2 048 2 048 5 360 360 010100 3686 4 2 048 1 536 5 360 480 010101 3686 4 1 536 1 536 5 480 480 010110 3750 156 25 156 25 6 4 4 010111 3750 156 25 125 6 4 5 011000 3750 156 25 25 6 4 25 011001 3750 125 125 6 5 5 011010 3750 125 25 6 5 25 011011 3750 25 25 6 25 25 011100 3732 48 155 52 155 52 6 4 4 Rev 0 Page 13 of 20 AD9550 Y5 to YO fvco MHz four MHz fours MHz P P 011101 3732 48 155 52 77 76 6 4 8 011110 3732 48 155 52 19 44 6 4 32 011111 3732 48 77 76 77 76 6 8 8 100000 3732 48 77 76 19 44 6 8 32 100001 3732 48 19 44 19 44 6 32 32 100010 3686 4 153 6 153 6 6 4 4 100011 3686 4 153 6 122 88 6 4 5 100100 3686 4 153 6 61 44 6 4 10 100101 3686 4 153 6 2 048 6 4 300 100110 3686 4 153 6 1 536 6 4 400 100111 3600 100 100 6 6 6 101000 3600 100 50 6 6 12 101001 3600 100 25 6 6 24 101010 3600 50 50 6 12 12 101011 3600 50 25 6 12 24 101100 3705 6 1 544 1 544 6 400 400 101101 3985 53 fj fj 6 1 1 101110 3985 53 fo fo 2 6 1 2 101111 3985 53 fo fo 4 6 1 4 110000 3985 53 fo 2 fo 2 6 2 2 110001 3985 53 fo 2 fj 4 6 2 4 110010 3985 53 fo
9. 12 AD9550 DUTY CYCLE OUTPUT VOLTAGE mV p p DUTY CYCLE 26 1800 1600 1400 gt e N e e e e e PL LVDS 0 100 200 300 400 500 600 700 800 FREQUENCY MHz Figure 15 Peak to Peak Output Voltage vs Frequency LVPECL and LVDS 100 Q Load 900 10pF 20pF 5pF 0 100 200 300 400 500 600 FREQUENCY MHz Figure 16 Duty Cycle vs Output Frequency CMOS LVPECL LVDS 0 100 200 300 400 500 600 700 800 900 FREQUENCY MHz Figure 17 Duty Cycle vs Output Frequency LVPECL and LVDS 100 Q Load 09057 013 09057 014 09057 015 Rev 0 Page 10 of 20 200mV DIV Figure 18 Typical Output Waveform LVPECL 800 MHz 500ps DIV 125mV DIV 500ps DIV Figure 19 Typical Output Waveform LVDS 800 MHz 3 5 mA Drive Current 500mV DIV 1 25ns DIV Figure 20 Typical Output Waveform CMOS 250 MHz 10 pF Load 09057 016 09057 017 09057 018 AD9550 INPUT OUTPUT TERMINATION RECOMMENDATIONS AD9550 Biol AD9550 DOWNSTREAM DOWNSTREAM 3 3V DIFFERENTIAL IMPEDANCE 3 3V DIFFERENTIAL OUTPUT INPUT DEVICE OUTPUT DEVICE LVDS OR 0 1yF LVDS OR LVPECL MODE x LVPECL MODE Figure 21 AC Coupled L
10. 51 6 moving air Junction to ambient thermal 32 6 C W resistance 2 5 m sec airflow per JEDEC JESD51 6 moving air Junction to board thermal 24 2 C W resistance 0 m sec airflow per JEDEC JESD51 8 still air Junction to board characterization 22 9 C W parameter 0 m sec airflow per JEDEC JESD51 6 still air Junction to case thermal resistance 4 8 C W Ye Junction to top of package 0 5 C W characterization parameter 0 m sec airflow per JEDEC JESD51 2 still air 1 Results are from simulations The PCB is a JEDEC multilayer type Thermal performance for actual applications requires careful inspection of the conditions in the application to determine whether they are similar to those assumed in these calculations Rev 0 Page 17 of 20 AD9550 OUTLINE DIMENSIONS 0 30 0 25 j PIN 1 0 18 INDICATOR PIN 1 INDICATOR 0 50 1 BSC EXPOSED 3 25 Ep RA nus 3 10 50 2 95 TOP VIEW 252 EE EM 0 30 FOR PROPER CONNECTION OF 0 80 THE EXPOSED PAD REFER TO 0 75 THE PIN CONFIGURATION AND 0 75 0 05 FUNCTION DESCRIPTIONS 0 70 eer j 0 02 NOM SECTION OF THIS DATA SHEET N i COPLANARITY SEATING PLANE 0 20 REF COMPLIANT JEDEC STANDARDS MO 220 WHHD Figure 27 32 Lead Lead Frame Chip Scale Package LFCSP_WQ 5mm x 5 mm Body Very Very Thin Quad CP 32 7 Dimensions shown in millimeters ORDERING GUIDE Model Temperatur
11. 550 2 E a 10 tc MASK 5 5 1 a z 0 1 0 01 0 1 1 10 100 1M 10M 09057 021 JITTER FREQUENCY kHz Figure 25 Jitter Tolerance LOW DROPOUT LDO REGULATORS The AD9550 is powered from a single 3 3 V supply and contains on chip LDO regulators for each function to eliminate the need for external LDOs To ensure optimal performance each LDO output should have 0 47 capacitor connected between its access pin and ground AUTOMATIC POWER ON RESET The AD9550 has an internal power on reset circuit see Figure 26 At power up an 800 pF capacitor momentarily holds a Logic 0 at the active low input of the reset circuitry This ensures that the device is held in a reset state 250 us until the capacitor charges sufficiently via the 100 pull up resistor and 200 series resistor Note that when using a low impedance source to drive the RESET pin be sure that the source is either tristate or Logic 0 at power up otherwise the device may not calibrate properly AD9550 RESET CIRCUITRY Figure 26 Power On Reset 09057 022 Provided an input reference signal is present at the REF pin the device automatically performs a VCO calibration during power up If the input reference signal is not present VCO calibration fails and the PLL does not lock As soon as an input reference signal is present the user must reset the device to initiate the automatic VCO calibration process Any change to
12. AD9550 is It accepts a single ended input reference signal at the REF input implemented in a strictly CMOS process The AD9550 is pin programmable providing a matrix of The AD9550 operates over the extended industrial temperature standard input output frequency translations from a list of range of 40 C to 85 C Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result fromits use Specifications subject to change without notice No One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A license is granted by implication or otherwise under any patent or patent rights of Analog Devices Tel 781 329 4700 www analog com Trademarks and registered trademarks are the property of their respective owners Fax 781 461 3113 2010 Analog Devices Inc All rights reserved AD9550 TABLE OF CONTENTS V 1 Input Output Termination Recommendations 1 Applications e p De e eR 1 Th orysot Operations eee n obe E eitis 12 Basic Block DJIagram i esiste tei ded 1 12 General DesCfiption eere aep p quieti 1 Preset Frequencies isssssssssncsssssscveisissevesssvsnsssssssevssvastevesssssnsestsess 12 R vision History races e e i Dre Re eia 2 Descripti
13. ANALOG Integer N Clock Translator DEVICES for Wireline Communications AD9550 FEATURES BASIC BLOCK DIAGRAM Converts preset standard input frequencies to standard output frequencies Input frequencies from 8 kHz to 200 MHz Output frequencies up to 810 MHz LVPECL and LVDS REF LR um 200 MHz CMOS Preset pin programmable frequency translation ratios On chip VCO PIN DECODER Single ended CMOS reference input Two output clocks independently programmable as LVDS AD9550 8 LVPECL or CMOS 8 Single supply 3 3 V Figure 1 Very low power lt 450 mW under most conditions Small package size 5 mm x 5 mm Exceeds Telcordia GR 253 CORE jitter generation transfer and tolerance specifications APPLICATIONS Cost effective replacement of high frequency VCXO OCXO and SAW resonators Flexible frequency translation for wireline applications such as Ethernet T1 E1 SONET SDH GPON xDSL Wireless infrastructure Test and measurement including handheld devices GENERAL DESCRIPTION The AD9550 is a phase locked loop PLL based clock translator 15 possible input frequencies to a list of 52 possible output designed to address the needs of wireline communication and frequency pairs OUT1 and OUT2 base station applications The device employs an integer N PLL The AD9550 output is compatible with LVPECL LVDS or to accommodate the applicable frequency translation requirements single ended CMOS logic levels although the
14. FFSET FROM CARRIER Hz Figure 5 Phase Noise frer 61 44 MHz 122 88 MHz CAL PERFORMANCE CHARACTERISTICS PHASE NOISE dBc Hz 09057 103 PHASE NOISE dBc Hz 09057 023 PHASE NOISE dBc Hz 09057 004 Rev 0 Page 8 of 20 JITTER BANDWIDTH JITTER rms 12kHz TO 20MHz 0 73ps 50kHz TO 80MHz 0 51ps 100 110 120 130 140 150 160 100 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER Hz Figure 6 Phase Noise frer 77 76 MHz 622 08 MHz 12kHz TO 20MHz 1 26ps 50kHz TO 80MHz 0 49ps 100M JITTER BANDWIDTH JITTER rms 10 100 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER Hz Figure 7 Phase Noise frer 19 44 MHz four 155 52 MHz 12kHz TO 20MHz 1 27ps 50kHz TO 80MHz 0 54ps 100M JITTER BANDWIDTH JITTER rms 10 100 1k 10k 100k 1M 10M FREQUENCY OFFSET FROM CARRIER Hz Figure 8 Phase Noise frer 8 kHz Foy 155 52 MHZ
15. PLL to synchronize the VCO output signal with the reference signal applied to the PFD Selection of the VCO frequency band as well as gain adjustment occurs automatically as part of the automatic VCO calibration process of the device which initiates at power up or reset VCO calibration centers the dc operating point of the VCO control signal During VCO calibration the output drivers provide a static dc signal The feedback divider N divider sets the frequency multiplication factor of the PLL in integer steps over a 20 bit range Note that the N divider has a lower limit of 32 Loop Filter The charge pump in the PFD delivers current to the loop filter see Figure 24 The components primarily responsible for the bandwidth of the loop filter are external and connect between Pin 16 and Pin 17 The internal portion of the loop filter has two configurations one is for low loop bandwidth applications 170 Hz and the other is for medium 20 kHz high 75 kHz bandwidth applications The low loop bandwidth condition applies when the feedback divider value N is 2 16 384 or greater Otherwise the medium high loop bandwidth configuration is in effect The feedback divider value depends on the configuration of the Ax and Yx pins per Table 8 AD9550 CONTROL LOGIC 170pF BUFFER SWITCHES CHANGE STATE FOR N 2 16384 FILTER R c2 09057 029 C1 Figure 24 External Loop Filter The bandwidth of the loop fil
16. VDS or LVPECL Output Driver Figure 22 DC Coupled LVDS or LVPECL Output Driver Rev 0 Page 11 of 20 AD9550 THEORY OF OPERATION LOCKED LOCK DETECT PRECONFIGURED DIVIDER SETTINGS A3TO A0 Y5TO YO AD9550 3350MHz TO 4050MHz 09057 019 Figure 23 Detailed Block Diagram OVERVIEW The AD9550 accepts one input reference clock REF The input clock path includes an optional divide by 5 prescaler an optional x2 frequency multiplier and a 14 bit programmable divider R The output of the R divider drives the input to the PLL The PLL translates the R divider output to a frequency within the operating range of the VCO 3 35 GHz to 4 05 GHz based on the value of the feedback divider N The VCO prescaler P reduces the VCO output frequency by an integer factor from 5 to 11 resulting in an intermediate frequency in the range of 305 MHz to 810 MHz The 10 bit P and P dividers can further reduce the P output frequency to yield the final output clock frequencies at OUT1 and OUT2 respectively Thus the frequency translation ratio from the reference input to the output depends on the selection of the divide by 5 prescalers the x2 frequency multipliers the values of the three R dividers the N divider and the P P and P dividers These parameters are set automatically via the preconfigured divider settings per the Ax and Yx pins see the Preset Frequencies section PRESET FREQUENCIES The frequency selecti
17. devices and circuit boards can discharge Supply Voltage VDD 3 6V 4 without detection Although this product features Maximum Digital Input Voltage 0 5 V to VDD 0 5 V patented or proprietary protection circuitry damage _ o 4 may occur on devices subjected to high energy ESD 2101998 Temperature Range 65 C to 150 C Ata Therefore proper ESD precautions should be taken to Operating Temperature Range 40 C to 85 C avoid performance degradation or loss of functionality Lead Temperature Soldering 10 sec 300 C Junction Temperature 150 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Rev 0 Page 6 of 20 AD9550 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 5 Pin Function Descriptions 85g eo 55000 Nr Q Q9 QN Y4 1 T 24 GND Y5 2 23 OUT2 3 INDICATOR 22 9075 A1 4 AD9550 21 VDD A2 5 TOP VIEW 20 LOCKED A36 Not to Scale 19 LDO REF 7 18 VDD GND 8 17 LDO NOTES 1 NC NO CONNECT 2 EXPOSED DIE PAD MUST BE CONNECTED TO GND Figure 2 Pin Configuration 09057 002 Pin No Mnemonic
18. e Range Package Description Package Option AD9550BCPZ 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 7 AD9550BCPZ REEL7 40 C to 85 C 32 Lead Lead Frame Chip Scale Package LFCSP_WQ CP 32 7 AD9550 PCBZ Evaluation Board 17 RoHS Compliant Part Rev 0 Page 18 of 20 AD9550 NOTES Rev 0 Page 19 of 20 AD9550 NOTES 2010 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09057 0 8 10 0 DEVICES www analo g com Rev 0 Page 20 of 20
19. erence clock input frequencies greater than 125 MHz require the use of the divide by 5 prescaler VCO CHARACTERISTICS Frequency Range 3350 4050 MHz VCO Gain 45 MHz V VCO Tracking Range 300 ppm PLL Lock Time Using the pin selected frequency settings lock time is from the rising edge of the RESET pin to the rising edge of the LOCKED pin Low Bandwidth Setting 170 Hz Applies for Pin A3 to Pin AO 0001 to 1100 or for Pin A3 to Pin AO 1111 13 3 kHz PFD Frequency 214 ms 16 kHz PFD Frequency 176 ms Medium Bandwidth Setting 20 kHz Applies for Pin A3 to Pin AO 1110 and Pin Y5 to Pin YO 111111 1 5625 MHz PFD Frequency 2 ms High Bandwidth Setting 75 kHz Applies for Pin to Pin AO 1101 to 1110 2 64 MHz PFD Frequency 1 50 ms 4 86 MHz PFD Frequency 0 89 ms The to AO and Y5 to YO pins have 100 internal 2 The RESET pin has a 100 internal pull up resistor OUTPUT CHARACTERISTICS resistors The OM2 to pins have 40 pull up resistors Table 2 Parameter Min Typ Max Unit Test Conditions Comments LVPECL MODE Differential Output Voltage Swing 690 800 890 mV Output driver static for dynamic performance see Figure 15 Common Mode Output Voltage VDD 1 66 VDD 1 34 VDD 1 01 V Output driver static Frequency Range 0 810 MHz Duty Cycle 40 60 96 Up to 805 MHz output frequency Rise Fall Time 2096 to 8096 255 305 ps 100 O termination between both pins of the output driver LVDS
20. ing Outputs 27 23 OUT1 OUT2 Square Wave Clocking Outputs N A EP Exposed Die Pad The exposed die pad must be connected to GND lis input is input output is output P is power and P O is power output 2 N A means not applicable Rev 0 Page 7 of 20 AD9550 TYPI PHASE NOISE dBc Hz PHASE NOISE dBc Hz PHASE NOISE dBc Hz JITTER BANDWIDTH JITTER rms 40 12kHz TO 20MHz 0 89ps B 50kHz TO 80MHz 0 58ps 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET FROM CARRIER Hz Figure 3 Phase Noise frer 25 MHz 125 MHz JITTER BANDWIDTH JITTER rms 40 12kHz 20MHz 1 32ps 50kHz TO 80MHz 0 41ps 10 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET FROM CARRIER Hz Figure 4 Phase Noise frer 25 MHz 156 25 MHz JITTER BANDWIDTH JITTER rms 40 12kHz TO 20MHz 1 25ps 50kHz TO 80MHz 0 63ps 10 100 1k 10k 100k 1M 10M 100M FREQUENCY O
21. on of Functional Blocks sss 15 Specifications era erae 3 Jitter Tole rane sete rie e exeun ines 16 Output Characteristics rettet b trente 4 Low Dropout LDO Regulators eee 16 Jitter Characteristics essent tette tette 5 Automatic Power On 16 Absolute Maximum Ratings sentent 6 Applications Information 17 ESD Caution cete i Ode eios 6 Thermal Performance eerte 17 Pin Configuration and Function 7 Outline DImernsions tem Re e 18 Typical Performance Characteristics 8 Ordering Guilde oe a E RECHERCHER 18 REVISION HISTORY 8 10 Revision 0 Initial Version Rev 0 Page 2 of 20 SPECIFICATIONS AD9550 Minimum min and maximum max values apply for the full range of supply voltage and operating temperature variations Typical typ values apply for VDD 3 3 V T 25 C unless otherwise noted Table 1 Parameter Min Typ Max Unit Test Conditions Comments SUPPLY VOLTAGE 3 135 330 3 465 V Pin 18 Pin 21 and Pin 28 POWER CONSUMPTION Tested with both output channels active at maximum output frequency LVPECL and LVDS outputs use a 100 O termination between both pins of the output driver Total Current 162 185 mA VDD Current By Pin Pin 18 93 106 mA Pin 21 LVDS Configured Output 35 41 mA LVPECL Configured Output 36
22. on pins A3 to A0 and Y5 to allow the user to hardwire the device for preset input and output frequencies based on the pin logic states see Figure 23 The pins decode ground or open connections as Logic 0 or Logic 1 respectively The A3 to A0 pins allow the user to select one of 15 input reference frequencies as shown in Table 6 The device sets the appropriate divide by 5 5 multiply by 2 x2 and input divider R values based on the logic levels applied to the Ax pins The divide by 5 x2 and R values cause the PLL input frequency to be either 16 KHz or 40 3 kHz There are two exceptions The first is for A3 to 1101 which yields a PLL input frequency of 155 52 59 MHz The second is for A3 to AO 1110 which yields a PLL input frequency of either 1 5625 MHz or 4 86 MHz depending on the Y5 to pins The Y5 to YO pins allow the user to select one of 52 output frequency combinations and foyr per Table 7 The device sets the appropriate P P and P settings based on the logic levels applied to the Yx pins Note however that selecting 101101 through 110010 require A3 to AO 1101 and selecting 110011 requires A3 to AO 1110 The value N of the PLL feedback divider and the control setting for the charge pump current CP depend on a combi nation of both the Ax and Yx pin settings as shown in Table 8 Rev 0 Page 12 of 20 Table 6 Pin Configured Input Frequency Ax Pins AD9550
23. s input thereby taking advantage of a higher frequency at the input to the PLL This provides greater separation between the frequency generated by the PLL and the modulation spur associated with frequency at the PLL input PLL PFD Charge Pump VCO Feedback Divider The PLL see Figure 23 consists of a phase frequency detector PFD a partially integrated analog loop filter see Figure 24 an integrated voltage controlled oscillator VCO and a 20 bit programmable feedback divider The PLL generates a 3 35 GHz to 4 05 GHz clock signal that is phase locked to the input reference signal and its frequency is the phase detector frequency multiplied by the feedback divider value The PFD of the PLL drives a charge pump that increases decreases or holds constant the charge stored on the loop filter capacitors both internal and external The stored charge results in a voltage that sets the output frequency of the VCO The feedback loop of the PLL causes the VCO control voltage to vary in such a way as to phase lock the PFD input signals The PLL has a VCO with 128 frequency bands spanning a range of 3350 MHz to 4050 MHz 3700 MHz nominal However the actual operating frequency within a particular band depends on the control voltage that appears on the loop filter capacitor The control voltage causes the VCO output frequency to vary linearly within the selected band This frequency variability allows the control loop of the
24. ter primarily depends on three external components R C1 and C2 There are two sets of recom mended values for these components corresponding to the low and medium high loop bandwidth configurations see Table 9 Table 9 External Loop Filter Components Loop A3 to AO Pins R C1 C2 Bandwidth 0001 to 1100 and 1111 68kO 47nF 1 0 17 kHz 1110 12 51pF 220nF 20 kHz 1101 to 1110 12 51pF 220nF 75 kHz 20 kHz loop bandwidth case only applies when the pin to A0 pin 1110and the Y5 pin to YO pin 111111 To achieve the best jitter performance in applications requiring a loop bandwidth ofless than 1 KHz C1 and C2 must have an insulation resistance of at least 500 PLL Locked Indicator The PLL provides a status indicator that appears at Pin 20 LOCKED When the PLL acquires phase lock the LOCKED pin switches to a Logic 1 state When the PLL loses lock however the LOCKED pin returns to a Logic 0 state Rev 0 Page 15 of 20 AD9550 Output Dividers The output divider section consists of three dividers P P and The P divider or VCO frequency prescaler accepts the VCO frequency and reduces it by an integer factor of 5 to 11 thereby reducing the frequency to a range between 305 MHz and 810 MHz The output of the P divider independently drives the P divider and the P divider The P divider establishes the frequency at OUT and the P divider establishes
25. the preset frequency selection pins requires the user to reset the device This is necessary to initiate the automatic VCO calibration process Rev 0 Page 16 of 20 APPLICATIONS INFORMATION THERMAL PERFORMANCE The AD9550 is specified for case temperature T oase To ensure that Tease is not exceeded use an airflow source The following equation determines the junction temperature on the application printed circuit board PCB T Tease Ppr x Pp where is the junction temperature C T case is the case temperature C measured by the customer at the top center of the package Y is the value indicated in Table 11 Py is the power dissipation see Table 1 for the power consumption parameters Values of 6 are provided for package comparison and PCB design considerations 6 can be used for a first order approximation of T using the following equation T T 0 x Pp where T is the ambient temperature C Values of are provided for package comparison and PCB design considerations when an external heat sink is required Values of are provided for package comparison and PCB design considerations AD9550 Table 11 Thermal Parameters for the 32 Lead LFCSP Symbol Description Value Unit Oy Junction to ambient thermal 41 6 C W resistance 0 m sec airflow per JEDEC JESD51 2 still air Junction to ambient thermal 36 4 C W resistance 1 0 m sec airflow per JEDEC JESD
26. utput 155 52 MHz 1 28 ps rms Input 19 44 MHz output 245 76 MHz 0 89 ps rms Input 25 MHz output 125 MHz Pin A3 to Pin AO 1110 Pin Y5 to Pin YO 111111 see Figure 3 LVDS Output 1 32 ps rms Input 122 88 MHz output 155 52 MHz 1 29 ps rms Input 19 44 MHz output 245 76 MHz CMOS Output 1 24 ps rms Input 122 88 MHz output 155 52 MHz 1 26 ps rms Input 19 44 MHz output 245 76 MHz see Figure 14 regarding CMOS toggle rates above 250 MHz 50 kHz to 80 MHz Input 122 88 MHz output 155 52 MHz LVPECL 0 44 ps rms Input 122 88 MHz output 155 52 MHz 0 75 ps rms Input 19 44 MHz output 245 76 MHz 0 58 ps rms Input 25 MHz output 125 MHz Pin A3 to Pin AO 1110 Pin Y5 to Pin YO 111111 see Figure 3 LVDS 0 45 ps rms Input 122 88 MHz output 155 52 MHz 0 76 ps rms Input 19 44 MHz output 245 76 MHz CMOS 0 39 ps rms Input 122 88 MHz output 155 52 MHz 0 44 ps rms Input 19 44 MHz output 245 76 MHz see Figure 14 regarding CMOS toggle rates above 250 MHz JITTER TRANSFER BANDWIDTH See the Typical Performance Characteristics section Bandwidth Setting Low 170 Hz Medium 20 kHz High 75 kHz JITTER TRANSFER PEAKING See the Typical Performance Characteristics section Bandwidth Setting Low 1 3 dB Medium 0 dB High 0 08 dB Rev 0 Page 5 of 20 AD9550 ABSOLUTE MAXIMUM RATINGS ESD CAUTION Parameter Rating ESD electrostatic discharge sensitive device Charged

ANALOG DEVICES AD9550 handbook

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