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ANALOG DEVICES AD1380 handbook

1. 15V 00764 004 Figure 4 Zero Offset Adjustment Circuit 0 3 FSR An alternate offset adjustment circuit which contributes a negligible offset temperature coefficient if metal film resistors temperature coefficient 100 ppm C are used is shown in Figure 5 AD1380 OFFSET 10 ADJ TO 100kQ 00764 005 Figure 5 Low Temperature Coefficient Zero Adjustment Circuit In either adjustment circuit the fixed resistor connected to Pin 5 should be located close to this pin to keep the pin connection runs short Pin 5 is quite sensitive to external noise pickup and should be guarded by ANALOG COMMON TIMING The timing diagram is shown in Figure 6 Receipt of a CONVERT START signal sets the STATUS flag indicating conversion in progress This in turn removes the inhibit applied to the gated clock permitting it to run through 17 cycles All the SAR parallel bits STATUS flip flops and the gated clock inhibit signal are initialized on the trailing edge of the CONVERT START signal At time to Bi is reset and B to Bis are set unconditionally At ti the Bit 1 decision is made keep and Bit 2 is reset unconditionally This sequence continues until the Bit 16 LSB decision keep is made at tic The STATUS flag is reset indicating that the conversion is complete and the parallel output data is valid Resetting the STATUS flag restores the gated clock inhibit signal forcing the clock output to the low Logic 0 state Note
2. Page 11 of 12 AD1380 OUTLINE DIMENSIONS 43 89 M 32 17 1 102 27 99 1 079 27 41 1 16 PIN 1 INDICATOR 0 025 0 64 NOTE 1 0 015 0 38 0 192 4 88 Um Tryin 0 206 5 23 0 015 0 38 0 152 3 86 0 186 4 72 0 910 23 11 0 008 0 20 0 025 0 64 0 120 3 05 0 890 22 61 MIN E f 0 225 5 72 MAX 0 100 2 54 BSC 0 070 1 78 0 023 0 58 0 030 om 0 014 0 36 NOTES 1 INDEX AREA IS INDICATED BY A NOTCH OR LEAD ONE IDENTIFICATION MARK LOCATED ADJACENT TO LEAD ONE 2 CONTROLLING DIMENSIONS ARE IN INCHES MILLIMETER DIMENSIONS IN PARENTHESES ARE ROUNDED OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 15 32 Lead Bottom Brazed Ceramic DIP for Hybrid BBDIP DH 32E Dimensions shown in inches and millimeters ORDERING GUIDE Model Max Linearity Error Temperature Range Package Option AD1380JD 0 00696 FSR 0 C to 70 C Ceramic DH 32E AD1380KD 0 003 FSR 0 C to 70 C Ceramic DH 32E 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners www analo g com 0 La DEVICES Rev D Page 12 of 12
3. 0 00061 V adjust zero for digital output 11111111111110 Zero is now calibrated Set analog input to FSR 2 LSB 9 99878 V adjust gain for 00000000000001 digital output code full scale gain is now calibrated Half scale calibration check set analog input to 5 00000 V digital output code should be 01111111111111 10 V to 10 V Range Set analog input to 9 99878 V adjust zero for 1111111111110 digital output complementary offset binary code Set analog input to 9 99756 V adjust gain for 00000000000001 digital output complementary offset binary code Half scale calibration check set analog input to 0 00000 V digital output complementary offset binary code should be 01111111111111 Other Ranges Representative digital coding for 0 V to 10 V and 10 V to 10 V ranges is given in the 0 V to 10 V Range section and 10 V to 10 V Range section Coding relationships and calibration points for 0 V to 5 V 2 5 V to 42 5 V and 5 V to 5 V ranges can be found by halving proportionally the corresponding code equivalents listed for the 0 V to 10 V and 10 V to 10 V ranges respectively as indicated in Table 4 Zero and full scale calibration can be accomplished to a precision of approximately 1 2 LSB using the static adjustment procedure described above By summing a small sine or triangular wave voltage with the signal applied to the analog input the output can be cycled through each of the calibration codes
4. Inputs Pin 6 Pin 7 Pin 31 Vs Digital Input 0 3 V to Voo 0 3 V Output Short Circuit Duration to Ground Sample Hold Indefinite Data 1 secfor any one output Junction Temperature 175 Storage Temperature 65 C to 150 C Lead Temperature Soldering 10 sec 300 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality AD1380 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability ED ESD SENSITIVE DEVICE Rev D Page 5 of 12 AD1380 THEORY OF OPERATION A 16 bit ADC partitions the range of analog inputs into 2 discrete ranges or quanta All analog values within a given quantum are represented by the same digital code usually assigned to the nominal midrange value There is an inherent
5. as close to the AD1380 as possible A large value such as 1 uF capacitor in parallel with a 0 1 uF capacitor is usually sufficient Analog supplies are to be bypassed to the ANALOG COMMON analog power return Pin 30 and the logic supply is bypassed to DIGITAL COMMON logic power return Pin 8 The metal cover is internally grounded with respect to the power supplies grounds and electrical signals Do not externally ground the cover Rev D Page 9 of 12 AD1380 15V 16 BIT SUCCESSIVE 10ko 01380 APPROMIXATION REGISTER TO RERRREAAAAAL REF 15V 16 BIT DAC 0 01 uF CONTROL 7 5kQ los 1 3mA Q 75 3 75 4 can TO 10V 00764 009 NOTE ANALOG V7 AND DIGITAL a GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY Figure 9 Analog and Power Connections for Unipolar 0 V to 10 V Input Range 415V AD1380 16 BIT SUCCESSIVE 300 APPROMIXATION REGISTER T 10KO GAIN Fa rv vui 111 9 15V 16 BIT DAC 0 01uF CONTROL 7 5 15V 1uF los 1 75 3 75 15V A 4 10V TO 10V 10ko ZERO ZER NOTE 15V ANALOG X7 AND DIGITAL L GROUNDS ARE NOT TIED INTERNALLY AND MUST BE CONNECTED EXTERNALLY 00764 010 Figure 10 Analog and Power Connections for Bipolar 10 V to 10 V Input Range Rev D Page 10 of 12 APPLICATIONS High pe
6. decision to keep or reject each bit is then made at the completion of each bit comparison period depending on the state of the comparator at that time GAIN ADJUSTMENT The gain adjustment circuit consists of a 100 ppm C poten tiometer connected across Vs with its slider connected through a 300 resistor to Pin 3 GAIN ADJ as shown in Figure 3 If no external trim adjustment is desired Pin 5 COMPARATOR IN and Pin 3 may be left open 15V 10kQ 100 1 TO mE 0 01 nF 15V i Figure 3 Gain Adjustment Circuit 0 2 FSR ZERO OFFSET ADJUSTMENT The zero offset adjustment circuit consists of a 100 ppm C potentiometer connected across Vs with its slider connected through a 1 8 resistor to Pin 5 for all ranges As shown in Figure 4 the tolerance of this fixed resistor is not critical a carbon composition type is generally adequate Using a carbon composition resistor having a 1200 ppm C temperature coefficient contributes a worst case offset temperature coefficient of 32 LSBi x 61 ppm LSBi x 1200 ppm C 2 3 ppm C of FSR if the offset adjustment potentiometer is set at either end of its adjustment range Since the maximum offset adjustment required is typically more than 16 LSBu use of a carbon composition offset summing resistor typically contributes no more than 1 ppm C of FSR offset temperature coefficient 300kQ 00764 003 15V 10kQ 1 8MQ TO AD1 100kQ 380
7. types of drift error over temperature offset gain and linearity Offset drift causes a shift of the transfer characteristic left or right on the diagram over the operating temperature range Gain drift causes a rotation of the transfer characteristic about the zero for unipolar ranges or the minus full scale point for bipolar ranges The worst case accuracy drift is the summation of all three drift errors over temperature Statistically however the drift error behaves as the root sum squared RSS and can be shown as RSS E where gain drift error ppm C o offset drift error ppm FSR C linearity error ppmof ALL BITS ON a 000 000 1 2LSB 011 111 OFFSET ERROR 1 2LSB DITIGAL OUTPUT COB CODE 111 111 f 0 AR ANALOG INPUT FSR _iisp 2 2 00764 002 Figure 2 Transfer Characteristics for an Ideal Bipolar ADC Rev D Page 6 of 12 DESCRIPTION OF OPERATION On receipt of a CONVERT START command the AD1380 converts the voltage at its analog input into an equivalent 16 bit binary number This conversion is accomplished as follows the 16 bit successive approximation register SAR has its 16 bit outputs connected to both the device bit output pins and the corresponding bit inputs of the feedback DAC The analog input is successively compared to the feedback DAC output one bit at a time MSB first LSB last The
8. ANALOG DEVICES Low Cost 16 Bit Sampling ADC AD1380 FEATURES Complete sampling 16 bit ADC with reference and clock 50 kHz throughput 1 2 LSB nonlinearity Low noise SHA 300 pV p p 32 lead hermetic DIP Parallel output Low power 900 pW APPLICATIONS Medical and analytical instrumentation Signal processing Data acquisition systems Professional audio Automatic test equipment ATE Telecommunications GENERAL DESCRIPTION The AD1380 is a complete low cost 16 bit analog to digital converter including internal reference clock and sample hold amplifier Internal thin film on silicon scaling resistors allow analog input ranges of 2 5 V 5 V 10 V 0 V to 5 V and 0 V to 10 V Important performance characteristics of the AD1380 include maximum linearity error of 0 003 of FSR AD1380KD and maximum 16 bit conversion time of 14 us Transfer characteristics of the AD1380 gain offset and linearity are specified for the combined ADC sample and hold amplifier SHA so total performance is guaranteed as a system The AD 1380 provides data in parallel with corresponding clock and status outputs All digital inputs and outputs are TTL or 5 V CMOS compatible The serial output function is no longer available after date code 0120 Rev D Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of p
9. ORY 6 05 Rev C to Rev D Updated Format eue penes Universal Updated Outline Dimensions eerte 12 5 03 Rev B to Rev C Removed serial output function and updated te tete ee RH Universal Change to Product Description seen 1 Change to Functional Block Diagram sse 1 Change to Figure 5 uet eti tede dean 4 Deleted Text from Digital Output Data section 5 Deleted Figure 7 and Renumbered Remainder of Figures 5 Updated Outline Dimensions eene 8 Rev D Page 2 of 12 SPECIFICATIONS Typical at Ta 25 C Vs 15 V 5 V combined sample and hold ADC unless otherwise noted AD1380 Table 1 AD1380JD AD1380KD Model Min Typ Max Min Typ Max Unit RESOLUTION 16 16 Bits ANALOG INPUTS Bipolar 2 5 2 5 V 5 5 V 10 10 V Unipolar 0to5 0to5 V Oto 10 Oto 10 V DIGITAL INPUTS Convert Command TTL compatible trailing edge of positive 50 ns min pulse Logic Loading 1 1 LSTTL Loads TRANSFER CHARACTERISTICS COMBINED ADC SHA Gain Error 0 053 0 1 0 053 0 1 FSR Unipolar Offset Error 0 02 0 05 0 02 0 05 FSR Bipolar Zero Error 0 02 0 05 0 023 0 05 FSR Linearity Error 0 006 0 003 FSR Differential Linearity Error 0 003 0 003 FSR Noise 10 V Unipolar 85 85 uV rms 20 V Bipolar 115 115 uV rms THROUGHPUT Conversion T
10. atents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners FUNCTIONAL BLOCK DIAGRAM S H 10V 20V COMPARATOR GAIN OUT SPAN SPAN BIPOLAR IN ADJ 24 MSB SAMPLE BIT 2 S H IN 1 AND HOLD 5V 9 BIT 15 COMMON 9 LSB ANALOG TIMING CIRCUITRY COMMON 27 p START CLOCK 00764 001 CONVERT OUT NC NO CONNECT Figure 1 One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved AD1380 TABLE OF CONTENTS Specifications SR E 3 Digital Output Data ponen nR Ena T os 8 Absolute Maximum Ratings esee 5 Input Scaling eese eee eee 8 Ee 5 Calibration 14 Bit Resolution Examples 9 Theory Of OperatiOTina im on RIED 6 Grounding Decoupling and Layout Considerations 9 Description of Operation seen 7 Applications iniii eit e dene doe trt 11 Gain AGjUstime nt aimer ER DENISE ESSERE 7 Outline Dimensions eie RR ORO ER d 12 Zero Offset Adjustment 7 Ordering Guide tane teneris 12 Timing cnzeswivuM uc II 7 REVISION HIST
11. ime 14 14 us Acquisition Time 20 V Step 6 6 us SAMPLE AND HOLD Input Resistance 4 4 kQ Small Signal Bandwidth 900 900 kHz Aperture Time 50 50 ns Aperture Jitter 100 100 ps rms Droop Rate 50 50 uV ms Tmn to Tmax 1 1 mV ms Feedthrough 80 80 dB DRIFT ADC AND SHA Gain 20 20 Unipolar Offset 2 5 2 5 Bipolar Zero 2 5 2 5 ppm C No Missing Codes Guaranteed 0 to 70 13 Bits 0 to 70 14 Bits C DIGITAL OUTPUTS TTL COMPATIBLE All Codes Complementary 5 5 LSTTL Loads Clock Frequency 1 1 1 1 MHz POWER SUPPLY REQUIREMENTS Analog Supplies 14 5 15 15 5 14 5 15 15 5 V 14 5 15 15 5 14 5 15 15 5 V Digital Supply 4475 5 45 25 4475 5 45 25 V 15 V Supply Current 25 25 mA 15 V Supply Current 30 30 mA 5 V Supply Current 15 15 mA Power Dissipation 900 900 mW Rev D Page 3 of 12 AD1380 AD1380JD AD1380KD Model Min Typ Max Min Typ Max Unit TEMPERATURE RANGE Specified Oto 70 0 to 70 SG Operating 25 to 85 25 to 85 eG 1 Logic 0 0 8 V max Logic 1 2 0 V min for inputs Logic 0 0 4 V max Logic 1 2 4 V min for digital outputs Tested on 10 V and 0 V to 10 V ranges Adjustable to zero Full scale range 5Guaranteed but not 100 production tested Rev D Page 4 of 12 ABSOLUTE MAXIMUM RATINGS Table 2 Parameter Rating Supply Voltage 18V Logic Supply Voltage 47V Analog Ground to Digital Ground 0 3V Analog
12. of interest to more accurately determine the center or end points of each discrete quantization level A detailed description of this dynamic calibration technique is presented in Analog Digital Conversion Handbook edited by D H Sheingold Prentice Hall Inc 1986 GROUNDING DECOUPLING AND LAYOUT CONSIDERATIONS Many data acquisition components have two or more ground pins that are not connected together within the device These grounds are usually referred to as the DIGITAL COMMON logic power return ANALOG COMMON analog power return or analog signal ground These grounds Pin 8 and Pin 30 must be tied together at one point as close as possible to the converter Ideally a single solid analog ground plane under the converter would be desirable Current flows through the wires and etch stripes on the circuit cards and since these paths have resistance and inductance hundreds of millivolts can be generated between the system analog ground point and the ground pins of the AD1380 Separate wide conductor stripe ground returns should be provided for high resolution converters to minimize noise and IR losses from the current flow in the path from the converter to the system ground point In this way AD1380 supply currents and other digital logic gate return currents are not summed into the same return path as analog signals where they would cause measurement errors Each of the AD1380 supply terminals should be capacitively decoupled
13. quantization uncertainty of 1 2 LSB associated with the resolution in addition to the actual conversion errors The actual conversion errors associated with ADCs are combinations of analog errors due to the linear circuitry matching and tracking properties of the ladder and scaling networks reference error and power supply rejection The matching and tracking errors in the converter have been minimized by the use of monolithic DACs that include the scaling network The initial gain and offset errors are specified at 0 1 FSR for gain and 0 05 FSR for offset These errors may be trimmed to zero by the use of external trim circuits as shown in Figure 3 and Figure 4 Linearity error is defined for unipolar ranges as the deviation from a true straight line transfer characteristic from a zero voltage analog input which calls for a zero digital output to a point that is defined as full scale The linearity error is based on the DAC resistor ratios It is unadjustable and is the most meaningful indication of ADC accuracy Differential nonlinearity is a measure of the deviation in the staircase step width between codes from the ideal least significant bit step size Figure 2 Monotonic behavior requires that the differential linearity error be less than 1 LSB However a monotonic converter can have missing codes The AD1380 is specified as having no missing codes over temperature ranges noted in the Specifications section There are three
14. r LSB value for range and resolution used see Table 5 Voltages given are the nominal value for transition to the code specified Table 5 Input Voltage Range and LSB Values Analog Input Voltage Range 10V 5V 2 5V OVto 10V OVto 5V Code Designation COB or CTC COB or CTC COB or CTC CSB CSB FSR 20V 10V 5V 10 V 5V One Least Significant Bit LSB 2 2 2 2 2 2 n 8 78 13 mV 39 06 mV 19 53 mV 39 06 mV 19 53 mV n 10 19 53 mV 9 77 mV 4 88 mV 9 77 mV 4 88 mV n 12 4 88 mV 2 44 mV 1 22 mV 2 44 mV 1 22 mV n 13 2 44 mV 1 22 mV 0 61 mV 1 22 mV 0 61 mV n 14 1 22 mV 0 61 mV 0 31 mV 0 61 mV 0 31 mV n 15 0 61 mV 0 31 mV 0 15 mV 0 31 mV 0 15 mV 1 COB complementary offset binary CTC complementary twos complement achieved by using an inverter to complement the most significant bit to produce MSB 3 CSB complementary straight binary Rev D Page 8 of 12 AD1380 CALIBRATION 14 BIT RESOLUTION EXAMPLES External zero adjustment and gain adjustment potentiometers connected as shown in Figure 3 and Figure 4 are used for device calibration To prevent interaction of these two adjustments zero is always adjusted first and then gain Zero is adjusted with the analog input near the most negative end of the analog range 0 for unipolar and minus full scale for bipolar input ranges Gain is adjusted with the analog input near the most positive end of the analog range 0 V to 10 V Range Set analog input to 1 1
15. resolution of the ADC Connect the input signal as shown in Table 3 See Figure 8 for circuit details 10V SPAN permitting parallel data transfer to be clocked on the 1 to 0 transition of the STATUS flag see Figure 7 Parallel data output changes state on positive going clock edges BIT 16 VALID BUSY STATUS 20ns MIN TO 90ns a Table 3 Input Scaling Connections 00764 007 Figure 7 LSB Valid to Status Low COMPARATOR IN TO FROM DAC SAR BIPOLAR 7 5 N COMPARATOR OFFSET Vre ANALOG COMMON Figure 8 Input Scaling Circuit 00764 008 Connect Input Input Signal Line Output Code Connect Pin 4 to Connect Pin 7 to Signal to Connect Pin 32 to 10V COB Pin 5 Pin 32 Pin 31 Pin 7 5V COB Pin 5 Open Pin 31 Pin 6 2 5 V COB Pin 5 Pin 5 Pin 31 Pin 6 OVto 5V CSB Open Pin 5 Pin 31 Pin6 OVto 10V CSB Open Open Pin 31 Pin6 1 5 is extremely sensitive to noise and should be guarded by ANALOG COMMON Table 4 Transition Values vs Calibration Codes Output Code MSB LSB Range 10 V 5V 2 5V OVto 10V OVto 5V 000 0002 Full Scale 10V 45V 2 5 V 10 V 5V 3 2 LSB 3 2 LSB 3 2 LSB 3 2 LSB 3 2 LSB 011 111 Midscale OV OV OV 5V 2 5 V 1 2 LSB 1 2 LSB 1 2 LSB 1 2 LSB 1 2 LSB 111 110 Full Scale 10 V 5V 2 5 V OV OV 1 2 LSB 1 2 LSB 1 2 LSB 1 2 LSB 1 2 LSB Fo
16. rformance sampling analog to digital converters like the AD1380 require dynamic characterization to ensure that they meet or exceed their desired performance parameters for signal processing applications Key dynamic parameters include signal to noise ratio SNR and total harmonic distortion THD which are characterized using Fast Fourier Transform FFT analysis techniques The results of that characterization are shown in Figure 11 In the test a 13 2 kHz sine wave is applied as the analog input fo at a level of 10 dB below full scale the AD1380 is operated at a word rate of 50 kHz its maximum sampling frequency The results of a 1024 point FFT demonstrate the exceptional performance of the converter particularly in terms of low noise and harmonic distortion In Figure 11 the vertical scale is based on a full scale input referenced as 0 dB In this way all frequency energy cells can be calculated with respect to full scale rms inputs The resulting signal to noise ratio is 83 2 dB which corresponds to a noise floor of 93 2 dB Total harmonic distortion is calculated by adding the rms energy of the first four harmonics and equals 97 5 dB FUNDAMENTAL 13232 SAMPLE RATE 50000 SIGNAL dB 10 0 dB 93 2 dB 97 5 100 9 101 8 111 9 REL PWR DENSITY dB 00764 012 1 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY 48 8281 2 Figure 11 FFT of 13 2 kHz Inp
17. that the clock remains low until the next conversion Corresponding parallel data bits become valid on the same positive going clock edge tacauisiTion MAXIMUM THROUGHPUT TIME 1 CONVERT START koo CONVERSION TIME 2 Fi T wee CLOCK i 1 H H H 1 1 1 1 H F t 1 1 1 1 T STATUS fto iti ito its itits ite ty jts ito ths ta ths the ME HN 4 tty 0 BIT2 7 BIT3 I BIT4 7 BITS 77 BIT 6 BIT7 BIT8 BIT9 BIT 10 BIT 11 ___ BIT 12 BIT 13 ___ BIT14___ BIT 15 ___ LSB ZL NOTES 1 THE CONVERT START PULSEWIDTH IS 50ns MIN AND MUST REMAIN LOW DURING A CONVERSION THE CONVERSION IS INITIATED BY THE TRAILING EDGE OF THE CONVERT COMMAND 2 tconv 14us MAX taca 3 MSB DECISION 4 CLOCK REMAINS LOW AFTER LAST BIT DECISION 00764 006 Figure 6 Timing Diagram Binary Code 0110011101 111010 Rev D Page 7 of 12 AD1380 DIGITAL OUTPUT DATA Parallel data from TTL storage registers is in negative true form Logic 1 0 V and Logic 0 2 4 V Parallel data output coding is complementary binary for unipolar ranges and comple mentary offset binary for bipolar ranges Parallel data becomes valid at least 20 ns before the STATUS flag returns to Logic 0 INPUT SCALING The AD1380 inputs should be scaled as close to the maximum input signal range as possible to use the maximum signal
18. ut Signal at 10 dB with a 50 kHz Sample Rate FUNDAMENTAL 13232 SAMPLE RATE 50000 REL PWR DENSITY dB 2f dB 80 7 3f dB 99 9 4f dB 102 9 00764 011 1 44 129 171 214 257 299 342 384 427 469 512 FREQUENCY 48 8281 2 Figure 12 FFT of 13 2 kHz Input Signal at 0 4 dB with a 50 kHz Sample Rate AD1380 Increasing the input signal amplitude to 0 4 dB of full scale causes THD to increase to 80 6 dB as shown in Figure 12 At lower input frequencies however THD performance is improved Figure 13 shows a full scale 0 3 dB input signal at 1 41 kHz THD is now 96 0 dB FUNDAMENTAL 1416 SAMPLE RATE 50000 SIGNAL dB 0 3 NOISE dB 91 9 THD dB 96 0 REL PWR DENSITY dB 00764 013 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY x48 8281Hz 20V SPAN Figure 13 FFT of 1 4 kHz Input Signal at 0 3 dB with a 50 kHz Sample Rate The ultimate noise floor can be seen with low level input signals of any frequency In Figure 14 the noise floor is at 94 dB as demonstrated with an input signal of 24 kHz at 39 8 dB FUNDAMENTAL 23975 SAMPLE RATE 50000 REL PWR DENSITY dB 00764 014 1 44 86 129 171 214 257 299 342 384 427 469 512 FREQUENCY SPAN 8281Hz 20V Figure 14 FFT of 24 kHz Input Signal at 39 8 dB with 50 kHz Sample Rate Rev D

ANALOG DEVICES AD1380 handbook

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