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ANALOG DEVICES AD9873 handbook

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2. 0 20 40 60 80 100 0 20 40 60 80 100 FREQUENCY MHz FREQUENCY MHz TPC Single Sideband 65 MHz RBW 2 kHz TPC 5b Single Sideband 65 MHz RBW 2 kHz fc 66 MHz f 1 MHz Rser 10 kQ lour 4 fc 66 MHz f 1 MHz Rser 4kQ lout 10 mA 3 3 40 I ul ul S 5 S E E 60 lt lt 70 80 Lt d H 100 0 20 40 60 80 100 FREQUENCY MHz FREQUENCY MHz TPC 6a Single Sideband 42 MHz RBW 2 kHz TPC 6b Single Sideband 42 MHz RBW 2 kHz fc 43 MHz f 1 MHz Reser 10 lour 4 mA fo 43 MHz f 1 MHz Rser 4 lout 10 MAGNITUDE dB MAGNITUDE dB 0 20 40 60 80 100 0 20 40 60 80 100 FREQUENCY MHz FREQUENCY MHz TPC 7a Single Sideband 5 MHz
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4. 24 Notes Serial Port Operation 24 REV 0 SPECIFICATIONS 09873 Test Parameter Temp Level Min Typ Max Unit SYSTEM CLOCK DAC SAMPLING fsyscrk Frequency Range Full III 232 MHz OSC IN and XTAL CHARACTERISTICS Frequency Range Full III 3 33 MHz Duty Cycle 25 C 35 50 65 Input Capacitance 25 C IV 3 pF Input Resistance 25 C IV 100 MQ MCLK OUT JITTER Derived PLL 25 C IV 6 ps rms TxDAC CHARACTERISTICS Resolution N A N A 12 Bits Full Scale Output Current Full 2 4 20 mA Gain Error Using Internal Reference 25 C I 3 0 14 T3 FS Output Offset 25 I 1 1 FS Reference Voltage REFIO Level 25 I 1 18 1 23 1 28 Differential Nonlinearity DNL 25 C IV t2 5 LSB Integral Nonlinearity INL 25 LSB Output Capacitance 25 C IV 5 pF Phase Noise 1 kHz Offset 42 MHz 25 C IV 113 dBc Hz Output Voltage Compliance Range Full III 0 5 1 5 Wideband SFDR 5 MHz Analog Out 4 mA 25 C IV 59 dBc 65 MHz Analog Out 4 mA 25 C IV 54 dBc Narrowband SFDR 100 kHz Window 65 MHz Analog Out Iour 4 mA 25 C IV 79 dBc Tx MODULATOR CHARACTERISTICS Offset Full 50 55 Pass Band Amplitude Ripple f lt figcrx 8 Full III 0 1 dB Pass Band Amplitude Ripple f lt 4 Full III 0 5 dB Stop Band Response f gt x 3 4 Full III 63 dB 8 BIT
5. 8 AVDDIQ 2 0 25 REFB 8 AVDDIQ 2 0 25 V REFT 10 12 AVDD 2 0 5 REFB 10 12 AVDD 2 0 5 V A differential level of 0 5 V between the reference pins results in a 1 V ADC input level Ay A differential level of 1 V between the reference pins results in a 2 V ADC input level Internal reference sources can be powered down when exter nal references are used Register Address 02h Video Input For sampling video type waveforms such as NTSC and PAL signals the Video Input channel provides black level clamping Figure 23 shows the circuit configuration for using the video channel input Pin 100 An external blocking capacitor is used with the on chip video clamp circuit to level shift the input signal to a desired reference level The clamp circuit automati cally senses the most negative portion of the input signal and adjusts the voltage across the input capacitor This forces the black level of the input signal to be equal to the value programmed into the clamp level register register address 07h CLAMP LEVEL FS 2 AD9873 A A CLAMP LEVEL hues VIDEO INPUT Vi Figure 23 Video Clamp Circuit Input OFFSET 31 09873 AGND IQ SCH lt lt E E lt lt 88185818818 58 1 DRGND 2 DRVDD 3 MSB IF 11 4 IF 10 5 AD9873 IF 9 6 MQFP ew Pins Down 1 7 8 IF 6 9 IF 5 IF 4 IF 3 IF 2 IF 1 IF 0 MSB Rx IQ 3 Rx IQ 2 Rx
6. ai S 300 g 310 O 280 o E al 260 2 300 2 2 2 o 240 290 220 200 120 140 160 180 200 220 240 0 10 20 30 40 50 60 70 80 90 100 MHz DUTY CYCLE TPC 1 Power Consumption vs Clock Speed fsyscik TPC 2 Power Consumption vs Transmit Burst Duty Cycle DUAL SIDEBAND TRANSMIT SPECTRUM See Table IV for Dual Tone Generation MAGNITUDE dB MAGNITUDE dB 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY MHz FREQUENCY MHz TPC Dual Sideband Spectral Plot 5 MHz TPC Dual Sideband Spectral Plot 5 MHz f 1 MHz Hag 10 loyr 4 mA RBW 1 kHz f 1 MHz Hag 4 lour 10 MA RBW 1 kHz D D 1 40 ul 5 5 5 6 60 6 lt lt 80 4 J 90 100 55 57 59 61 63 65 67 69 71 73 75 FREQUENCY MHz FREQUENCY MHz TPC 4a Dual Sideband Spectral Plot fc 65 MHz TPC 4b Dual Sideband Spectral Plot fc 65 MHz f 1 MHz 10 lout 4 RBW 1 kHz f 1 MHz Reet 4 KO lour 10 MA RBW 1 kHz 14 REV 0 09873 SINGLE SIDEBAND TRANSMIT SPECTRUM MAGNITUDE dB MAGNITUDE dB
7. TOZSLON 1 81 7 anro 5 c 9001 91 io peog amog en LAN SIA CC ND 1 ef TidddAv A 91 a 4b od ho pes PE T t Ts Ws Sp S dOOrdL T 4 x X12 NS n 1 m ot KE IESEL D ar d ao GND ane Lb dOO T 12 peog amog T 0 D H ve 5 KIGAV Z t i I Qy 1 S TUO 1 i 5 4001 41 co 99 prog n NOOVAS 9 T if gt c s 9 L E 2 NOOVAEEF n Ic 1 AOT t 6l AE EF ao or ano o HA D aro mro T T T NOOdAEE LAN SJA WHO zn s dOOTAL 600 Kal ECH 9 pasi SUAE l SIA WHO CC l dad 4 4 M NNOO YAMOd JAE OT quo 6 S saa 1 oc L anro aero p i d E dOOT dL s fot peag n T t t ie 1 9 g sid laL in AOI 9901 E adaa E 7 s S DNV I3 Schon am Tat nro id SAISOATV LIDIG a 11 L 5 REN spna Oe wade 01 8 9 4 e 4 5 6 80 6 Ag edu any oU 8 P POZSLIN x Z nuren ME er bik WHO CC in SJA CC z ital Circuitry igi Figure 27 Evaluatio
8. tion byte into the AD9873 coincident with the first eight SCLK rising edges The instruction byte provides the AD9873 serial port controller with information regarding the data transfer cycle which is Phase 2 of the communication cycle The Phase 1 instruction byte defines whether the upcoming data transfer is read or write the number of bytes in the data transfer and the starting register address for the first byte of the data transfer The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9873 The remaining SCLK edges are for Phase 2 of the communication cycle Phase 2 is the actual data transfer between the AD9873 and the system controller Phase 2 of the communication cycle is a transfer of 1 2 3 or 4 data bytes as determined by the instruction byte Normally using one multibyte transfer is the preferred method However single byte data transfers are useful to reduce CPU overhead when register access requires one byte only Registers change immediately upon writing to the last bit of each transfer byte Instruction Byte The instruction byte contains the following information as shown in Table II Table II Instruction Byte Information MSB LSB 7 nn ja n a2 A1 R W 7 of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write Logic high in
9. Pk rms level of 10 dB Maximum Symbol Component Input Value 2047 LSBs 0 2 dB 2000 LSBs Maximum Complex Input rms Value 2000 LSBs 6 dB Pk rms dB 1265 LSBs rms Maximum Complex Input rms Value calculation uses both I and Q symbol components which adds a factor of 2 6 dB to the formula COMPLEX DATA INPUT 0 2dB 12 0 TWO S COMPLEMENT FORMAT If INV SINC filter is enabled an insertion loss of 1 4 dB for low frequencies occurs at the DAC output see Figure 12a 12b Programming the AD9873 to single tone transmit mode while disabling the INV SINC filter address OFh generates a maximum FS amplitude single tone with a frequency fc determined by the associated frequency tuning word Table IV shows typical input test signals with amplitude levels related to 12 bit full scale FS Tx Throughput and Latency Data inputs effect the output fairly quickly but remain effective due to AD9873 s filter characteristics Data transmit latency through the AD9873 is easiest to describe in terms of clock cycles 4 The numbers quoted are when an effect is first seen after an input value change Latency of I Q data entering the data assembler AD9873 input to the DAC output is 119 clock cycles 29 75 cycles DC values applied to the data assembler input will take up to 176 fsyscrx clock cycles 44 cycles to propagate and settle at the
10. 0 0 Version 3 0 r 0D 0 0 0 0 0 0 0 0 00 r OE 0 0 0 0 0 0 0 0 00 r OF 0 0 Profile Profile 0 Bypass Spectral Single Tone 00 rw Tx Select lt 1 gt Select lt 0 gt Inv Sinc Inversion Tx Tx Mode Tx Filter 10 Tx Frequency Turning Word Profile 0 lt 7 0 gt 00 rw Tx 11 Tx Frequency Turning Word Profile 0 lt 15 8 gt 00 rw Tx 12 Tx Frequency Turning Word Profile 0 lt 23 16 gt 00 rw Tx 13 Cable Driver Amplifier Gain Control Profile 0 lt 7 0 gt 00 rw Tx 14 Tx Frequency Turning Word Profile 1 lt 7 0 gt 00 rw Tx 15 Tx Frequency Turning Word Profile 1 lt 15 8 gt 00 rw Tx 16 Tx Frequency Turning Word Profile 1 lt 23 16 gt 00 rw Tx Ier Cable Driver Amplifier Gain Control Profile 1 lt 7 0 gt 00 rw Tx 18 Tx Frequency Turning Word Profile 2 7 07 00 rw Tx 19 Tx Frequency Turning Word Profile 2 15 8 00 rw Tx 1 Tx Frequency Turning Word Profile 2 lt 23 16 gt 00 rw Tx 1B Cable Driver Amplifier Gain Control Profile 2 lt 7 0 gt 00 rw Tx 1C Tx Frequency Turning Word Profile 3 7 07 00 rw Tx 1D Tx Frequency Turning Word Profile 3 lt 15 8 gt 00 rw Tx Tx Frequency Turning Word Profile 3 lt 23 16 gt 00 rw Tx 1F Cable Driver Amplifier Gain Control Profile 3 lt 7 0 gt 00 rw Tx 0 register bits should not be programmed with 1 REV 0 11 09873 REGISTER BIT DEFINITIONS 00h Bits 0 4 OSC IN Multiplier Register Address This register field is used to program the on chip multiplier PLL that gen
11. 10 1 EXTERNAL Rx IQ 0 POWER SUPPLY Rx SYNC DECOUPLING VDR O Vps O Tx SYNC MSB Tx 1Q 5 Tx IQ 4 Tx 10 3 Tx 10 2 Tx 1Q 1 31 Tx 1Q 0 32 DVDD 33 PROFILE 1 35 PROFILE 0 36 RESET 37 88 AGND 87 AVDD 86 REFT10 84 AVDD 83 AGND 82 Q IN AGND IQ LIN LIN AGND IQ REFT8 REFB8 AGND IQ AVDD IQ DRVDD REF CLK DRGND DGND SD SDELTAO SDELTA1 DVDD SD CA ENABLE CA DATA CA CLK DVDD OSC OSCIN OSCGND XTAL Y DGND OSC AGND PLL PLL FILTER AVDD PLL DVDD PLL DGND PLL AVDD Tx Tx DGND Tx AGND Tx Figure 24 Power Supply Decoupling POWER AND GROUNDING CONSIDERATIONS In systems seeking to simultaneously achieve high speed and high performance the implementation and construction of the printed circuit board design is often as important as the circuit design Proper RF techniques must be used in device selection placement routing supply bypassing and grounding Figure 24 illustrates proper power supply decoupling Split ground technique can be used to isolate digital and high speed clock generation noise from the analog front ends The analog front end may be further split to minimize crosstalk between the transmit and receive sections Noise sensitive video IF signals can also be separated from the more robust IQ ADC signal path One com mon ground underneath the chip connects all ground splits and assures short distances for ground pin connections Fi
12. 2 Figure 10b Input Signal Spectrum 3 a 0 25 Figure 11b Input Signal Spectrum 4 0 25 10 10 0 0 10 10 m 20 m 20 I I 30 30 2 2 E E 40 2 40 lt lt 50 50 60 60 70 70 80 80 0 01 02 04 05 06 07 08 0 9 1 0 0 01 02 04 05 06 07 08 0 9 1 0 FREQUENCY FS 2 FREQUENCY FS 2 Figure 10c Response to Input Signal Spectrum N 3 Figure 11c Response to Input Signal Spectrum N 4 26 REV 0 09873 1 MAGNITUDE dB 6 0 0 1 02 0 3 0 4 0 5 0 6 0 7 0 8 09 1 0 FREQUENCY RELATIVE NYQ BW Figure 10d Cascaded Filter Passband Detail N 3 1 1 2 MAGNITUDE dB 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 0 FREQUENCY RELATIVE BW Figure 11d Cascaded Filter Passband Detail 4 Inverse SINC Filter ISF The AD9873 transmit section is almost entirely digital The input signal is made up of a time series of digital data words These data words propagate through the device as numbers Ultimately this number stream must be converted to an analog signal To this end the AD9873 incorporates an integrated DAC The output waveform of the DAC is the familiar staircase pattern typical of a signal that is sampled and quantized The staircase pattern is a result of the finite time that the DAC holds a quantized level until the
13. 4 In addition to the ability to provide a change in sample rate between input and output a CIC filter also has an intrinsic low pass frequency response characteristic The frequency response of a CIC filter is dependent on three factors 1 The rate change ratio R 2 The order of the filter n 3 The number of unit delays per stage m It can be shown that the system function H z of a CIC filter is given by Hn B 1 27 DE The form on the far right has the advantage of providing a result for z 1 corresponding to zero frequency or dc The alternate form yields an indeterminate form 0 0 for z 1 but is other wise identical The only variable parameter for the AD9873 s CIC filter is R m and n are fixed at 1 and 3 respectively Thus the CIC system function for the AD9873 simplifies to REV 0 wE The transfer function is given by _ i n R j HC BI y dd aal R 1 R sin rf The frequency response in this form is such that f is scaled to the output sample rate of the CIC filter That is f 1 corresponds to the frequency of the output sample rate of the CIC filter H f R will yield the frequency response with respect to the input sample of the CIC filter Combined Filter Response The combined frequency response of HBF 1 HBF 2 and CIC is shown in Figure 10a to 10c and Figure 11a to 11 The usable bandwidth of the filter chain puts a limit on the ma
14. XTAL DGND OSC AGND PLL PLL FILTER AVDD PLL DVDD PLL DGND PLL AVDD Tx Tx REV 0 09873 Table L Register Address Default Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex Type 00 SDIO LSB MSB RESET OSC IN OSC IN OSC IN OSC IN OSC IN 10 rw Bidirectional First Multiplier Multiplier Multiplier Multiplier Multiplier M lt 4 gt M lt 3 gt M lt 2 gt lt 1 gt M lt 0 gt 01 PLL OSC IN MCLK MCLK MCLK MCLK MCLK MCLK 09 rw Lock Divider Divider Divider Divider Divider Divider Divider Detect N 3 4 lt 5 gt lt 4 gt 3 lt 2 gt lt 1 gt lt 0 gt 02 Power Down Power Down Power Down Power Down Power Down Power Down Power Down Power Down 00 IW PLL DAC Tx Digital Tx 12 Bit ADC Reference 10 Bit ADC Reference 8 Bit ADC 12 Bit ADC 10 Bit ADC 03 Sigma Delta Output 0 Control Word 3 0 LSB 0 0 0 0 00 rw XA 04 Sigma Delta Output 0 Control Word 11 4 MSB 00 rw XA 05 Sigma Delta Output 1 Control Word 3 0 LSB 0 0 0 0 00 rw XA 06 Sigma Delta Output 1 Control Word 11 4 MSB 00 rw XA 07 Video Input Clamp Level Control for Video Input 6 0 20 rw ADC Enable 08 ADC Clock 0 ADC Clock 0 0 0 Test Test 00 rw ADC Select Select 12 Bit ADC 10 Bit ADC 09 0 0 0 0 0 0 0 0 00 rw 0A 0 0 0 0 0 0 0 0 00 rw 0 0 0 0 0 0 0 0 00 rw 0C 0 0
15. accept a signal swinging below 0 V and shift it to an externally provided common mode voltage The AD8131 configuration is shown in Figure 21 REV 0 AD9873 Figure 22 Transformer Coupled Input Figure 22 shows the schematic of a suggested transformer circuit Transformers with turns ratios n n other than one may be selected to optimize the performance of a given application For example selecting a transformer with a higher impedance ratio e g Mini Circuits T16 6T with an impedance ratio of 22 71 16 nj n effectively steps up the signal amplitude thus further reducing the driving requirements of the signal source In Figure 22 a resistor R1 is added between the analog inputs to match the source impedance as in the formula 1 4 kV 22 71 ADC Voltage References The AD9873 has three independent internal references for its 8 bit 10 bit and 12 bit ADCs Both 8 bit ADCs have a 1 V p p input and share one internal reference source The 10 bit and 12 bit ADCs however are designed for 2 V p p input voltages with each of them having their own internal reference Figure 15 shows the proper connections of the reference pins REFT and REFB External references may be necessary for systems that require high accuracy gain matching between ADCs or improvements in tem perature drift and noise characteristics External references REFT and RFB need to be centered at AVDD 2 with offset voltages as specified
16. cos f FS 0 2 dB FS cos f 180 cos f or cos f FS 0 2 dB 28 REV 0 09873 this analog filter to have sufficiently flat gain and linear phase response across the bandwidth of interest to avoid modulation impairments A relatively inexpensive fifth order elliptical low pass filter is sufficient to suppress the aliased components for HFC network applications The AD9873 provides true and complement current outputs The full scale output current is set by the RSET resistor at Pin 49 The value of RSET for a particular IOUT is determined using the following equation RSET 32 Voacrset lour 39 4 lour For example if a full scale output current of 20 mA is desired then RSET 39 4 0 02 Q or approximately 2 kQ Every dou bling of the RSET value will halve the output current Maximum output current is specified as 20 mA The full scale output current range of the AD9873 is 2mA to 20 mA Full scale output currents outside of this range will degrade SFDR performance SFDR is also slightly affected by output matching that is the two outputs should be terminated equally for best SFDR performance The output load should be located as close as possible to the AD9873 package to minimize stray capacitance and inductance The load may be a simple resistor to ground an op amp current to voltage converter or a transformer coupled circuit It is best not to attempt to directly drive highly reactive loads suc
17. scale Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions APERTURE DELAY Aperture delay is a measure of the Sample and Hold Amplifier SHA performance and specifies the time delay between the rising edge of the sampling clock input to when the input signal is held for conversion APERTURE UNCERTAINTY JITTER Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC SIGNAL TO NOISE DISTORTION SINAD RATIO SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency including harmonics but excluding dc The value for SINAD is expressed in decibels EFFECTIVE NUMBER OF BITS ENOB For a sine wave SINAD can be expressed in terms of the number of bits Using the following formula SINAD 1 76 dB 6 02 it is possible to obtain a measure of performance expressed as N the effective number of bits SIGNAL TO NOISE RATIO SNR SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency excluding harmonics and dc The value for SNR is expressed in decibels TOTAL HARMONIC DISTORTION THD THD is the ratio of the rms sum of the first six harmonic com ponents to the rms value of the measured inp
18. with no degradation in performance The digital data outputs of the ADCs are represented in straight binary format They saturate to full scale or zero when the input signal exceeds the input voltage range Receive Timing The AD9873 sends multiplexed data to the Rx IQ and IF out puts on every rising edge of MCLK Rx SYNC frames the start of each Rx IQ data Symbol Both 8 bit ADCs transfer their data within four MCLK cycles using 4 bit data packages I MSB I LSB MSB and LSB 10 bit and 12 bit ADCs are com pletely read on every second MCLK cycle Rx SYNC is high for MCLK Rx SYNC every second 10 bit ADC data if 8 bit ADC is not in power down mode Driving the Analog Inputs Figure 19 illustrates the equivalent analog inputs of the AD9873 a switched capacitor input Bringing CLK to a logic high opens Switch 3 and closes Switches S1 and S2 The input source is connected to Ar and must charge capacitor Cy during this time Bringing CLK to a logic low opens S2 and then Switch 1 opens followed by closing S3 This puts the input in the hold mode AD9873 Figure 19 Differential Input Architecture The structure of the input SHA places certain requirements on the input drive source The combination of the pin capacitance and the hold capacitance is typically less than 5 pF The input source must be able to charge or discharge this capacitance to its n bit accuracy in one half of a clock cycle When the SHA goe
19. 0 ns Data Valid Time tpy Full III 30 ns REV 0 5 AD9873 SPECIFICATIONS Test Parameter Temp Level Min Typ Max Unit CMOS LOGIC INPUTS Logic 1 Voltage 25 C 2 0 V Logic 0 Voltage 25 III 0 8 V Logic 1 Current 25 12 pA Logic 0 Current 25 C III 12 pA Input Capacitance 25 IV 3 pF CMOS LOGIC OUTPUTS 1 mA Load Logic 1 Voltage 25 C 2 4 Logic 0 Voltage 25 C III 0 4 V POWER SUPPLY Analog Supply Current 145 25 II 91 115 mA Digital Supply Current Ips Full Operating Conditions Register 02h 00h 25 IV 250 mA Zero Input Tx Register 02h 00h 25 C II 175 205 mA 25 Tx Burst Duty Cycle Register 02h 00h 25 IV 210 mA Power Down Digital Tx Register 02h 20h 25 C II 42 55 mA Power Supply Rejection Differential Signal Tx DAC 25 IV lt 0 25 FS 8 Bit ADC 25 C IV lt 0 004 FS 10 Bit ADC 25 C IV lt 0 002 FS 12 Bit ADC 25 C IV lt 0 0004 FS NOTES Single tone generated by applying a 1 6875 MHz sine signal to the Channel and the 90 degree phase shifted cosine signal to the I Channel Sampling directly with fosccm 2 No degradation due to Clock Multiplier PLL ADC Clock Select Register 08h Bits 5 and 7 set to 1 5Sampling directly with fosccyy No degradation due to Clock Multiplier PLL ADC Clock Select Register 08h Bits 5 and 7 set to 1 4See performance graph TPC 2 for power saving in burst mode opera
20. 27 DGND PLL Tx 10 4 28 AVDD Tx Tx 1Q 3 29 Tx Tx 1Q 2 30 Tc OLD O o 9 2 Sr Sr St Sr Sr Sr Sr Sr Sn t 2 2 x Ze dd2guuo2sso 2o0coB5uzo 0 z ajar z Set Sag 8 d lt aa 0 C13 Beer O 1pF 10kQ L Figure 2 Basic Connections Diagram 22 REV 0 09873 PROGRAMMABLE CLOCK OUTPUT REF CLK The AD9873 provides a frequency programmable clock output REF CLK Pin 71 MCLK fyc y and the master clock divider ratio stored in register address 01h determine its frequency frer uc vi R SIGMA DELTA OUTPUTS The AD9873 contains two independent sigma delta outputs that when low pass filtered generate level programmable DC voltages of Vsp Sigma Delta Code 4096 Vrogici Vrocico Influenced by CMOS logic output levels 8 tucLkK 4096 x 8 gt lt 000h S 0018 0028 800h FFFh 8 4096 x 8 tucLK Figure 3 Sigma Delta Output Signals In cable modem set top box applications the outputs can be used to control external variable gain amplifiers and RF tuners A simple single pole R C low pass filter provides sufficient filtering see Figure 4 SIGMA DELTA 0 12 DC 0 4 TO DRVDD 0 6V CONT
21. 8 PLANE 0 10 0 25 MAX MIN CONTROLLING DIMENSIONS ARE IN MILLIMETERS REV 0 39 C01584 4 5 7 00 rev 0 PRINTED IN U S A
22. 8 Bit ADC Single Tone Spectral Plot Using PLL Input Frequency 5 MHz 2048 Point FFT BER REV 0 09873 MAGNITUDE dB o a 85 105 p Al DU APA WWW WWW Mi il 2 4 6 8 10 12 13 5 FREQUENCY MHz TPC 21 12 Bit ADC Single Tone Spectral Plot Using PLL Input Frequency 10 MHz 4096 Point FFT MAGNITUDE dB FREQUENCY MHz TPC 22 10 Bit ADC Single Tone Spectral Plot Using PLL Input Frequency 10 MHz 4096 Point FFT MAGNITUDE dB FREQUENCY MHz TPC 23 Video Input Single Tone Spectral Plot Using PLL Input Frequency 5 MHz 4096 Point FFT REV 0 MAGNITUDE dB REDE T IN io did adn d 0 2 4 6 8 10 12 13 5 FREQUENCY MHz TPC 24 12 Bit ADC Single Tone Spectral Plot Without PLL Input Frequency 10 MHz 4096 Point FFT MAGNITUDE dB 0 2 4 6 8 10 12 13 5 FREQUENCY MHz TPC 25 10 Bit ADC Single Tone Spectral Plot Without PLL Input Frequency 10 MHz 4096 Point FFT MAGNITUDE dB 0 2 4 6 8 10 12 13 5 FREQUENCY MHz TPC 26 Video Input Single Tone Spectral Plot Without PLL Input Frequency 5 MHz 4096 Point FFT WER 09873 THEORY OF OPERATION architecture The following is a general description of the device To gain a general understanding of the AD9873 it is helpful functionalit
23. ADC CHARACTERISTICS Resolution N A N A 8 Bits Conversion Rate Full III 16 5 MHz Pipeline Delay N A N A 3 5 ADC Cycles DC Accuracy Differential Nonlinearity 25 C IV 0 5 LSB Integral Nonlinearity 25 C IV 0 5 LSB Offset Error for Each 8 Bit ADC 25 C IV 0 75 FSR Gain Error for Each 8 Bit ADC 25 C IV 4 FSR Offset Matching Between 8 Bit ADCs Full IV 3 LSB Gain Matching Between 8 Bit ADCs Full IV 4 5 LSB Analog Input Input Voltage Range Full IV 1 V p p Input Capacitance 25 C IV 1 4 pF Differential Input Resistance 25 C IV 4 Aperture Delay 25 C IV 2 0 ns Aperture Uncertainty Jitter 25 C IV 1 2 ps rms Input Bandwidth 3 dB 25 C IV 90 MHz Input Referred Noise 25 C IV 600 UN Reference Voltage Error REFT8 REFBS 0 5 V 25 C I 4 92 mV Dynamic Performance Ary 0 5 dB FS f 5 MHz Signal to Noise and Distortion Ratio SINAD Full II 43 5 48 dB REV 0 3 AD9873 SPECIFICATIONS Test Parameter Temp Level Min Typ Max Unit 8 BIT ADC CHARACTERISTICS Continued Dynamic Performance 0 5 dB FS f 5 MHz Effective Number of Bits Full II 6 9 7 68 Bits Effective Number of Bits ENOB Full IV 7 68 Signal to Noise Ratio SNR Full II 43 5 48 dB Total Harmonic Distortion THD Full II 66 51 dB Spurious Free Dynamic Range SFDR Full II 58 64 dB Differential Phase 25 IV lt 0 1 Degree Differential Gain 25 C IV 1 LSB 10 BIT ADC CHARACTERISTICS Resolution N A N A 10 Bits Con
24. ANALOG DEVICES Analog Front End Converter for Set Top Box Cable Modem AD9873 FUNCTIONAL BLOCK DIAGRAM FEATURES Low Cost 3 3 V CMOS Analog Front End Converter for MCNS DOCSIS DVB DAVIC Compliant Set Top Box Cable Modem Applications 232 MHz Quadrature Digital Upconverter DC to 65 MHz Output Bandwidth 12 Bit Direct IF D A Converter TxDAC Programmable Reference Clock Multiplier PLL Direct Digital Synthesis Interpolator SIN x x Compensation Filter Four Programmable Pin Selectable Modulator Profiles Single Tone Mode for Frequency Synthesis Applications 12 Bit 33 MSPS Sampling Direct IF A D Converter with Auxiliary Automatic Clamp Video Input Multiplexer 10 Bit 33 MSPS Sampling Direct IF A D Converter Dual 8 Bit 16 5 MSPS Sampling IO A D Converter Two Independently Programmable Sigma Delta Converters Direct Interface to AD8321 AD8323 PGA Cable Driver Programmable Frequency Output Power Down Modes APPLICATIONS Cable and Satellite Systems PC Multimedia Digital Communications Data and Video Modems Cable Modem Set Top Boxes Powerline Modem Broadband Wireless Communication GENERAL DESCRIPTION The AD9873 integrates a complete 232 MHz quadrature digital transmitter and a multichannel receiver with four high performance analog to digital converters ADC for various video and digital data signals The AD9873 is designed for cable modem set top box applications where cost size power dissi pation and dyna
25. DAC output Enabling the Inverse SINC Filter adds only 2 fsyscrx clock cycles latency Frequency hopping is accomplished via changing the PROFILE input pins The time required to switch from one frequency to another is less than 234 fsysc x cycles with the Inverse SINC Filter engaged With the Inverse SINC Filter bypassed the latency drops to less than 232 fsyscrx cycles 58 5 cycles D A Converter 12 bit digital to analog converter DAC is used to convert the digitally processed waveform into an analog signal The worst case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases Please see the AD9851 data sheet for a detailed explanation of aliased images The wideband 12 bit DAC in the AD9873 maintains spurious free dynamic range SFDR performance of 59 dBc up to four 42 MHz and 54 dBc up to four 65 MHz The conversion process will produce aliased components of the fundamental signal at n X fsvscik fcannmn n 1 2 3 These are typically filtered with an external RLC filter at the DAC output It is important for MODULATOR 3dB MAX Figure 14 Signal Level Contribution Table IV I Q Input Test Signals Input Level Modulator Output Level Single Tone fc f cos f FS 0 2 dB FS 3 0 dB cos f 90 sin f FS 0 2 dB Single Tone fc f cos f FS 0 2 dB FS 3 0 dB cos f 270 sin f FS 0 2 dB Dual Tone fc f
26. In systems that must use dc coupling use an op amp to comply with the input requirements of the AD9873 Op Amp Selection Guide Op amp selection for the AD9873 is highly application dependent In general the performance requirements of any given application can be characterized by either time domain or frequency domain constraints In either case one should carefully select an op amp that preserves the performance of the ADC This task becomes challenging when one considers the AD9873 s high performance capabilities coupled with other system level requirements such as power consumption and cost The ability to select the optimal op amp may be further complicated either by limited power sup ply availability and or limited acceptable supplies for a desired op amp Newer high performance op amps typically have input and output range limitations in accordance with their lower supply voltages As a result some op amps will be more appropriate in systems where ac coupling is allowed When dc coupling is required op amps headroom constraints such as rail to rail op amps or ones where larger supplies can be used should be considered Analog Devices offers differential output operational amplifiers like the AD8131 or AD8132 They can be used for differential or single ended to differential signal conditioning with 8 bit performance to directly drive ADC inputs The AD8138 is a higher performance version of the AD8132 It provides 12 bit perform
27. M response which is the product of the SINC and ISF responses It should be mentioned at this point that the ISF exhibits an insertion loss of 1 4 dB Thus signal levels at the output of the AD9873 with the ISF bypassed are 1 4 dB higher than with the ISF engaged However for modulated output signals which have a relatively wide bandwidth the ben efits of the SINC compensation usually outweighed the 1 4 dB loss in output level The decision of whether or not to use the ISF is an application specific system design issue THEIS LZ MAGNITUDE dB 0 01 0 2 0 3 04 05 0 6 07 08 0 9 1 0 FREQUENCY FS 2 Figure 12b SINC Compensated Response 27 09873 Figure 13 16 Quadrature Modulation Tx Signal Level Considerations The quadrature modulator itself introduces a maximum gain of 3 dB in signal level To visualize this assume that both the I data and Q data are fixed at the maximum possible digital value x Then the output of the modulator z is z x cos t x 05 It can be shown that assumes a maximum value of ls x x2 a gain of 3 dB However if the same number of bits were used to represent the values as is used to represent the x values an overflow would occur To prevent this possibility an effective 3 dB attenuation is internally imple mented on the I and Q data path 1 2 1 2 The following example assumes
28. PERFORMANCE CHARACTERISTICS 14 CABLE DRIVER AMPLIFIER GAIN CONTROL 29 Typical Power Consumption Characteristics 14 RECEIVE PATH Rx 6 Ee Res 30 Dual Sideband Transmit Spectrum 14 ADC Theory of Operation 30 Single Sideband Transmit Spectrum 15 Receive Taming k s eC eb 30 Typical QAM Transmit Performance Characteristics 16 Driving the Analog Inputs 30 Typical ADC Performance Characteristics 18 Op Amp Selection Guide 31 THEORY OF OPERATION 20 ADC Differential Inputs 31 Transmit Section 21 ADC Voltage References 31 OSC IN Clock Multiplier 21 Video EE 31 Receive Section 21 POWER AND GROUNDING CONSIDERATIONS 32 CLOCK AND OSCILLATOR CIRCUITRY 22 EVALUATION BOARD 33 PROGRAMMABLE CLOCK OUTPUT REF 23 Hardware wei adhe uyu wer sha dw PUES 33 SIGMA DELTA OUTPUTS 23 P EDS 33 SERIAL INTERFACE FOR REGISTER CONTROL 23 OUTLINE DIMENSIONS 39 General Operation of the Serial Interface 23 Instruction Byte er dEr etam bei exa 23 Serial Interface Port Pin Description 24 MSB LSB Transfers
29. RBW 2 kHz TPC 7b Single Sideband 5 MHz RBW 2 kHz fc 6 MHz f 1 MHz 10 lout 4 mA fo 6 MHz f 1 MHz Rser 4kQ lour 10 mA REV 0 15 09873 MAGNITUDE dB 25 2 0 1 5 10 05 0 0 5 1 0 1 5 20 2 5 FREQUENCY OFFSET MHz TPC 8a Single Sideband 65 MHz RBW 500 Hz fc 66 MHz f 1 MHz Rser 10 lour 4 mA MAGNITUDE dB 100 50 40 30 20 10 0 10 20 30 40 50 FREQUENCY OFFSET kHz TPC 9 Single Sideband 65 MHz RBW 50 Hz 66 MHz f 1 MHz Rser 10 lour 4 mA MAGNITUDE dB 25 2 0 1 5 1 0 05 0 0 5 1 0 1 5 2 0 2 5 FREQUENCY OFFSET MHz TPC 8b Single Sideband 65 MHz RBW 500 Hz 66 MHz f 1 MHz Reser 4 lour 10 mA MAGNITUDE dB 2 5 2 0 1 5 1 0 0 5 0 0 5 1 0 1 5 2 0 2 5 FREQUENCY OFFSET kHz TPC 10 Single Sideband 65 MHz RBW 10 Hz fc 66 MHz f 1 MHz Rser 10 4 TYPICAL QAM TRANSMIT PERFORMANCE CHARACTERISTICS 16 QAM 2 56 Mbit s SINC Filter Enabled Square Root Raised Cosine Filter with Alpha 0 25 Rser 4 10 SYSCLK 163 84 MHz foscIN 20 48 MHz M 8 4 MAGNITUDE dB MAGNITUDE dB FREQUENCY MHz TPC 11 16 OAM 42 MHz Spectral Pl
30. ROL WORD 1 DC 0 4 TO DRVDD 0 6V TYPICAL 50k2 C 0 01pF f 1 2 318Hz Figure 4 Sigma Delta RC Filter In more demanding applications where additional gain level shift or drive capability is required a first or second order active filter might be considered for each sigma delta output see Figure 5 AD9873 R SIGMA DELTA ie OP250 Voc Vsp 2 1 R R1 GAIN 1 R R1 2 Vorrset 1 R R1 TYPICAL 50 0 01 12 RC 318 2 VoFFSETREF Figure 5 Sigma Delta Active Filter With Gain and Offset REV 0 SERIAL INTERFACE FOR REGISTER CONTROL The AD9873 serial port is a flexible synchronous serial communi cations port allowing easy interface to many industry standard microcontrollers and microprocessors The serial I O is com patible with most synchronous transfer formats including both the Motorola SPI and Intel SSR protocols The interface allows read write access to all registers that configure the AD9873 Single or multiple byte transfers are supported as well as MSB first or LSB first transfer formats The AD9873 s serial interface port can be configured as a single pin I O SDIO or two unidirectional pins for in out SDIO SDO General Operation of the Serial Interface There are two phases to a communication cycle with the AD9873 Phase 1 is the instruction cycle which is the writing of an instruc
31. a bandwidth limit on the maxi mum transmit spectrum This is the familiar Nyquist limit and is equal to one half fioc x which hereafter will be referred to as fyyg Half Band Filters HBFs HBF 1 is a 15 tap filter that provides a factor of two increase in sampling rate HBF 2 is an 11 tap filter offering an additional factor of two increase in sampling rate Together HBF 1 and 2 provide a factor of four increase in the sampling rate 4 X or8 X fuvo In relation to phase response both HBFs are linear phase filters As such virtually no phase distortion is introduced within the passband of the filters This is an important feature as phase distortion is generally intolerable in a data transmission system Cascaded Integrator COMB CIC Filter A CIC filter is unlike a typical FIR filter in that it offers the flexibility to handle differing input and output sample rates only in integer ratios however In the purest sense a CIC filter can provide either an increase or a decrease in sample rate at the output relative to the input depending on the architecture If the integration stage precedes the comb stage the CIC filter provides sample rate reduction decimation When the comb stage precedes the integrator stage the CIC filter provides an increase in sample rate interpolation In the AD9873 the CIC filter is configured as a programmable inter polator and provides a sample rate increase by a factor of 3 or
32. aller ADC subblocks refining the conversion with progressively higher accuracy as it passes the results from stage to stage As a consequence of the distributed conversion ADCs require a small fraction of the 2N comparators used in a traditional n bit flash type ADC A sample and hold function within each of the stages permits the first stage to operate on a new input sample while the remaining stages operate on preceding samples Each stage of the pipeline excluding the last consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier MDAC The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors The last stage simply consists of a flash ADC CORRECTION LOGIC Figure 17 ADC Architecture The analog inputs of the AD9873 incorporate a novel structure that merges the input sample and hold amplifiers SHA and the first pipeline residue amplifiers into single compact switched capacitor circuits This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline By matching the sampling network of the input SHA with the first stage flash ADC the ADCs can sample inputs well beyond the Nyquist frequency
33. ance and allows different gain settings Please contact the factory or local sales office for updates on Analog Devices latest amplifier product offerings ADC Differential Inputs The AD9873 uses 1 V p p input span for the 8 bit ADC inputs and 2 V p p for the 10 and 12 bit ADCs Since not all applica tions have a signal preconditioned for differential operation there is often a need to perform a single ended to differential conver sion In systems that do not need a dc input an RF transformer with a center tap is the best method to generate differential inputs beyond 20 MHz for the AD9873 This provides all the benefits of operating the ADC in the differential mode without con tributing additional noise or distortion An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC An improvement in THD and SFDR performance can be realized by operating the AD9873 in differential mode The performance enhancement between the differential and single ended mode is most considerable as the input frequency approaches and goes beyond the Nyquist frequency i e f gt FS 2 AD9873 IU AINN Y Figure 21 Single Ended to Differential Input Drive SINGLE ENDED ANALOG INPUT The AD8131 provides a convenient method of converting a single ended signal to a differential signal This is an ideal method for generating a direct coupled signal to the AD9873 The AD8131 will
34. der The OSC IN multiplier output clock can be divided by 4 or 3 to generate the chip s master clock Active high indicates a divide ratio of 3 Default low configures a divide ratio of N 4 01h Bit 7 PLL Lock Detect If this bit is set to 1 REF CLK pin is disabled from the nor mal usage In this mode REF CLK high signals that the internal phase lock loop PLL is in lock with CLK IN 02h Bits 0 7 Power Down Sections of the chip that are not used can be put in a power saving mode when the corresponding bits are set to 1 This register has a default value of 00h with all sections active Bit 0 Power Down 8 bit ADC powers down the 8 bit ADC and stops RxSYNC framing signal Bit 1 Power Down 10 bit ADC reference powers down the internal 10 bit ADC reference Bit 2 Power Down 10 bit ADC powers down the 10 bit ADC Bit 3 Power Down 12 bit ADC reference powers down the internal 12 bit ADC reference Bit 4 Power Down 12 bit ADC powers down the 12 bit ADC Bit 5 Power Down Tx powers down the transmit section of the chip Bit 6 Power Down DAC Tx powers down the DAC Bit 7 Power Down PLL powers down the CLK IN Multiplier a 2 03h to 06h Sigma Delta Output Control Words The Sigma Delta Output Control Words 0 and 1 are 12 bits wide and split in MSB bits 11 4 and LSB bits 3 0 Changes to the sigma delta outputs take effect immediately for every MSB or LSB register write Sigma delta output control
35. dicates read operation Logic zero indicates a write operation N1 NO Bits 6 and 5 of the instruction byte determine the number of bytes to be transferred during the data transfer cycle The bit decodes are shown in the Table III Table III Decode Bits NO Description 0 0 Transfer 1 Byte 0 1 Transfer 2 Bytes 1 0 Transfer 3 Bytes 1 1 Transfer 4 Bytes A4 A3 A2 Al AO Bits 4 3 2 1 0 of the instruction byte determine which register is accessed during the data transfer portion of the communications cycle For multibyte transfers this address is the starting byte address The remaining register addresses are generated by the AD9873 23 09873 Serial Interface Port Pin Description SCLK Serial Clock The serial clock pin is used to synchronize data to and from the AD9873 and to run the internal state machines SCLK maximum frequency is 15 MHz All data input to the AD9873 is registered on the rising edge of SCLK All data is driven out of the AD9873 on the falling edge of SCLK CS Chip Select Active low input starts and gates a communi cation cycle It allows more than one device to be used on the same serial communications lines The SDO and SDIO pins will go to a high impedance state when this input is high Chip select should stay low during the entire communication cycle SDIO Serial Data I O Data is always written into the AD9873 on this pin However this pin can be used as a bidirectio
36. dth due to the frequency response of the filters The maximum value of o that can be implemented is 0 45 This is because the data bandwidth becomes 1 2 1 Inyo 0 725 which puts the data bandwidth at the extreme edge of the flat portion of the filter response 25 09873 If a particular application requires an value between 0 45 and 1 The combined HB1 HB2 and CIC filter introduces over the the user must oversample the baseband data by at least a factor frequency range of the data to be transmitted a worst case droop of four of less than 0 2 dB 10 10 0 0 10 10 m 20 m 20 1 1 G G 2 2 E E 40 2 40 lt lt 50 50 60 60 70 70 80 80 0 02 03 04 05 06 07 08 09 1 0 0 02 03 04 05 06 07 08 09 1 0 FREQUENCY FS 2 FREQUENCY FS 2 Figure 10a Cascaded Filter 12x Interpolator 3 Figure 11a Cascaded Filter 16x Interpolator 4 10 10 0 0 10 10 m 20 m 20 1 1 30 30 2 2 E E 40 40 lt lt 50 50 60 60 70 70 80 80 0 02 04 05 06 07 08 09 1 0 0 02 03 04 05 06 07 08 09 1 0 FREQUENCY FS 2 FREQUENCY FS
37. erates the chip s high frequency system clock For example to multiply the external crystal clock foscm by 19 decimal program register address 00h Bits 5 1 as 13h Default value is M 16 10h Valid entries range from M 1 to 31 M 1 no PLL requires a very stable high frequency clock at OSC IN A changed frequency is stable PLL locked after a maximum of 200 fmc x cycles Wake Up Time 00h Bit 5 RESET Writing a one to this bit resets the registers to their default val ues and restarts the chip The RESET bit always reads back 0 Register address 00h bits are not cleared by this software reset However a low level at the RESET pin would force all registers including all bits in address 00h to their default state 00h Bit 6 LSB MSB First Active high indicates SPI serial port access of instruction byte and data registers is least significant bit LSB first Default low indicates most significant bit MSB first format 00h Bit 7 SDIO Bidirectional Default low indicates SPI serial port uses dedicated input output lines SDIO and SDO pin High configures serial port as single line SDIO pin is used bidirectional 01h Bits 0 5 MCLK Divider This register is used to divide the chip s master clock by where R is an integer between 2 and 63 The generated reference clock REF CLK can be used for external frequency controlled devices Default value is R 9 01h Bit 6 OSC IN Divi
38. es the die version of the chip It can only be read OFh Bit 0 Single Tone Tx Mode Active high configures the AD9873 for single tone applications The AD9873 will supply a single frequency output as determined by the frequency tuning word FTW selected by the active profile In this mode the Tx IQ input data pins are ignored but should be tied high or low Default value of single tone Tx mode is 0 inactive OFh Bit 1 Spectral Inversion Tx When set to 1 inverted modulation is performed 1 cos wt sin oi Default is logic zero noninverted modulation I cos wt sin Bit 2 Bypass Inv Sinc Tx Filter Active high configures the AD9873 to bypass the SIN X X compensation filter Default value is 0 inverse sinc filter enabled REV 0 09873 OFh Bit 4 5 Profile Select The AD9873 quadrature digital upconverter is capable of storing four preconfigured modulation modes called profiles that define a transmit frequency tuning word and cable driver amplifier con trol Profile Select bits lt 1 0 gt or PROFILE 1 0 pins program the current register profile to be used Profile Select bits should always be 0 if PROFILE pins are used to switch between pro files Using the Profile Select bits as a means of switching between different profiles requires the PROFILE pins to be tied low 10h 1Fh Burst Parameter Tx Frequency Tuning Words The frequency tuning word FTW determines the DDS genera
39. ffset 1 kHz from the carrier Phase noise can be measured directly in single tone transmit mode with a spectrum analyzer that supports noise marker measurements It detects the relative power between the carrier and the offset 1 KHz sideband noise and takes the reso lution bandwidth rbw into account by subtracting 10 log rbw It also adds a correction factor that compensates for the imple mentation of the resolution bandwidth log display and detector characteristic OUTPUT COMPLIANCE RANGE The range of allowable voltage at the output of a current output DAC Operation beyond the maximum compliance limits may cause either output stage saturation resulting in nonlinear per formance or breakdown SPURIOUS FREE DYNAMIC RANGE SFDR The difference in dB between the rms amplitude of the DACs output signal or ADC s input signal and the peak spurious signal over the specified bandwidth Nyquist bandwidth unless otherwise noted PIPELINE DELAY LATENCY The number of clock cycles between conversion initiation and the associated output data being made available OFFSET ERROR First transition should occur for an analog value 1 2 LSB above negative full scale Offset error is defined as the deviation of the actual transition from that point GAIN ERROR The first code transition should occur at an analog value 1 2 LSB above negative full scale The last transition should occur for an analog value 1 1 2 LSB below the nominal full
40. ged fsyscrx frequency is stable after a maximum of 200 fyc cycles Wake Up Time DATA TRANSFER CYCLE L soo pesce Ts 2 s 1 papa soo El Ceci Figure 6a Serial Register Interface Timing MSB First DATA TRANSFER CYCLE EE 1 1 soo Figure 6b Serial Register Interface Timing LSB First cs INSTRUCTION CYCLE SCLK cs INSTRUCTION CYCLE SCLK 5 SCLK ton Saa 5 SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 7 Timing Diagram for Register Write to AD9873 SCLK tov SDIO eegen DATA DATA BIT 1 SDO Figure 8 Timing Diagram for Register Read from AD9873 TRANSMIT PATH Tx Transmit Timing The AD9873 provides a master clock MCLK and expects 6 bit multiplexed Tx IQ data on each rising edge Transmit symbols are framed with the Tx SYNC input Tx SYNC high indicates the start of a transmit symbol Four consecutive 6 bit data packages form a symbol I MSB I LSB Q MSB and Q LSB Data Assembler The input data stream is representative complex data Two 6 bit words form a 12 bit symbol component two s complement format Four input samples are required to produce one I Q data pair The sample rate at the input to the first half band filter is a quarter of the input data rate fucr x REV 0 09873 MCLK Tx SYNC Figure 9 Transmit Timing Diagram The sample rate fioc k puts
41. gure 24 32 uses two separate power supplies VAs powers the analog and clock generation section of the chip while Vps is used for the digital signals of the chip An extra power supply Vpg is only needed in applications that require lower level digital outputs and Dypp pins should be connected together for normal mode Vps and Vpr should not be directly connected to the power supply of noisy digital signal processing chips It might even be considered as an analog supply Ferrite beads and 10 LF decoupling capacitors isolate power supplies between functional blocks Each supply pin is further decoupled with a 0 1 multi layer ceramic capacitor that is mounted as close as possible to the pin In the high speed PLL and DAC sections additional 0 01 uF capacitors may be required as shown in Figure 24 REV 0 09873 EVALUATION BOARD Hardware The AD9873 EB is an evaluation board for the AD9873 analog front end converter Careful attention to layout and circuit design allow the user to easily and effectively evaluate the AD9873 in any application where high resolution and high speed conversion is required This board allows the user flexibility to operate the AD9873 in various configurations Several jumper or solder bridge settings are available The ADC inputs can be differentially driven by transformers or by an AD8138 when using connector J8 as the only input Differential to single ended transmit output options incl
42. h as an LC filter Driving an LC filter without a transformer requires that the filter be doubly terminated for best performance that is the filter input and output should both be resistively terminated with the appropriate values The parallel combination of the two terminations will determine the load that the AD9873 will see for signals within the filter pass band For example a 50 Q terminated input output low pass filter will look like a 25 Q load to the AD9873 The output compliance voltage of the AD9873 is 0 5 V to 1 5 V Any signal developed at the DAC output should not exceed 1 5 V otherwise signal distortion will result Furthermore the signal may extend below ground as much as 0 5 V without damage or signal distortion The AD9873 true and complement outputs can be differentially combined for common mode rejection using a broadband 1 1 transformer Using a grounded center tap results in signals at the AD9873 DAC output pins that are symmetrical about ground As previously mentioned by differentially combining the two signals the user can provide some degree of common mode signal rejection A differential combiner might consist of a transformer or an operational amplifier The object is to combine or amplify only the difference between two signals and to reject any common usually undesirable characteristic such as 60 Hz hum or clock feedthrough that is equally present on both individual signals Connecting the AD9873
43. ilter fRootRaisedcos 73mV Unit View D Measurement I Marker 9 843 75us 0 331 1 5 Filter Raiseacosine Reference 27 Alpha 7 BT 0 25 Auto Carrier Carrier Hz Scale 390 625ns div acy Ref OdBm VECTOR REALTIME TPC 14 Tx Output 64 OAM Analysis 17 09873 TYPICAL ADC PERFORMANCE CHARACTERISTICS ADC Sample Rate derived directly from foscin 27 MHz 13 5 MSPS for 8 bit ADCs Single Tone 5 MHz Input Signal unless otherwise noted m 5 1 1 c 5 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 INPUT SIGNAL FREQUENCY MHz INPUT SIGNAL FREQUENCY MHz TPC 15 SNR vs Input Frequency TPC 18 SFDR vs Input Frequency 60 62 64 8 BIT ADC 66 g g 2 1 1 70 2 z F 7 o TT 10 BIT ADC 74 76 F 78 X 12 BIT ADC 80 0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100 INPUT SIGNAL FREQUENCY MHz INPUT SIGNAL FREQUENCY MHz TPC 16 SINAD vs Input Frequency TPC 19 THD vs Input Frequency a a 1 I 5 lt 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 INPUT SIGNAL FREQUENCY MHz FREQUENCY MHz TPC 17 Video Input Characteristics vs Input Frequency TPC 20
44. ine wave The AD9873 provides for a 24 bit frequency tuning word which results in a tuning resolution of 12 9 Hz at a rate of 216 MHz good rule of thumb when using the AD9873 as a frequency synthesizer is to limit the fundamental output frequency to 30 of fsyscrk This avoids generating aliases too close to the desired fundamental output frequency thus minimizing the cost of filtering the aliases All applicable programming features of the AD9873 apply when configured in single tone mode These features include 1 Frequency hopping via the PROFILE inputs and associated tuning word which allows Frequency Shift Keying FSK modulation 2 Ability to bypass the SIN x x compensation filter 3 Power down modes OSC IN Clock Multiplier As mentioned earlier the output data is sampled at the rate of fsyscrx Since the AD9873 is designed to operate at frequencies up to 232 MHz there is the potential difficulty of trying to provide a stable input clock foscyy Although stable high frequency oscillators are available commercially they tend to be cost prohibitive and create noise coupling issues on the printed circuit board To alleviate this problem the AD9873 has a built in programmable clock multiplier and an oscillator circuit This allows the use of a relatively low frequency thus less expensive crystal or oscillator to generate the OSC IN signal The low frequency OSC IN signal can then be multiplied i
45. ion 51 Tx Transmitter DAC Output 52 Txt Transmitter DAC 53 AVDD Tx Analog Supply Voltage Tx 54 DGND PLL PLL Digital Ground 55 DVDD PLL PLL Digital Supply Voltage 56 AVDD PLL PLL Analog Supply Voltage 57 PLL FILTER PLL Loop Filter Connection 58 AGND PLL PLL Analog Ground 59 DGND OSC Digital Ground Oscillator 60 XTAL Crystal Oscillator Inv Output 61 OSC IN Oscillator Clock Input 62 DVDD OSC Digital Supply Oscillator 63 CA CLK Cable Amplifier Control Clock Output REV 0 9 09873 AVDD DRGND DRVDD MSB IF 11 IF 10 IF 9 IF 8 IF 7 IF 6 IF 5 IF 4 IF 3 IF 2 IF 1 IF 0 MSB RxIQ 3 RxIQ 2 RxIQ 1 RxIQ 0 RxSYNC DRGND DRVDD MLCK DVDD DGND TxSYNC MSB TxIQ 5 TxIQ 4 TxIQ 3 TxIQ 2 N H x PIN 1 IDENTIFIER AD9873 TOP VIEW Pins Down PIN CONFIGURATION Ge oe ss 4 lt 4 lt lt lt ER lt lt lt lt 281538 2 5 sS 2 25 2 25 8 25 TxIQ 1 31 TxIQ 0 32 DVDD 33 DGND 34 PROFILE 1 35 PROFILE 0 36 RESET 37 DVDD 38 DGND 39 DGND 40 SCLK 41 C 10 00 43 00 44 DGND Tx 45 DVDD Tx 46 PWR DOWN 47 REFIO 48 FSADJ 49 AGND Tx 50 AGND IQ IIN AGND IQ REFT8 REFB8 AGND IQ AVDD IQ DRVDD REF CLK DRGND DGND SD SDELTA 0 SDELTA 1 DVDD SD CA ENABLE CA DATA CA CLK DVDD OSC OSC IN
46. ister access window allows AD9873 register write and read back in decimal binary or hexadecimal data format The register map window provides a very easy function orientated program ming of AD9873 bits and registers Programming hints appear when the cursor is moved over an input field Registers are updated on every WRITE button click The advanced register access window allows programming of register access sequences D x gt dvanced Register Access EZ Download Update 01 09h h 01 1 0011 0001 b 13 1F h 13 13 d 13216 CONTINUOUS READ HHH SSH S xl Figure 25 Evaluation Board Software REV 0 33 ops IECH 0005719 wa ECH vif 6141 So eu V a DEE LAG 186 lr beds UNE 2 2 NOLINE LISTA gt nu 51 rz EM SISINGY 6n m CIOXINOD 1 gt soo mowo KS ampia DAV aac 0 92 XLAS O 89 39 DNAS D 963 X01 XD ur ond PEI ER des dee Geen 152 E dzz 1012 0012 40 962 HIOEES LETT zHW0 of 8 22 3HWOL MS moo n Le iu 22 ad sso EK 982 sta 911 DN z x 2 XLAGAV 104 301 4
47. le The AD9873 serial port controller address will increment from 1Fh to 00h for multibyte I O operations if the MSB first mode is active The serial port controller address will decrement from 00h to 1Fh for multibyte I O operations if the LSB first mode is active Notes on Serial Port Operation The AD9873 serial port configuration bits reside in Bits 6 and 7 of register address 00h It is important to note that the configu ration changes immediately upon writing to the last bit of the register For multibyte transfers writing to this register may occur during the middle of a communication cycle Care must be taken to compensate for this new configuration for the remain ing bytes of the current communication cycle The same considerations apply to setting the reset bit in reg ister address 00h All other registers are set to their default values but the software reset does not affect the bits in register address 00h It is recommended to use only single byte transfers when chang ing serial port configurations or initiating a software reset 24 write to Bits 1 2 and 3 of address 00h with the same logic levels as for Bits 7 6 and 5 bit pattern XY1001YX binary allows the user to reprogram a lost serial port configuration and to reset the registers to their default values A second write to address 00h with RESET bit low and serial port configuration as specified above XY reprograms the OSC IN Multiplier setting A chan
48. mic performance are critical attributes A single external crystal is used to control all internal conversion and data processing cycles The transmit section of the AD9873 includes a high speed direct digital synthesizer DDS a high performance high speed 12 bit digital to analog converter DAC programmable clock multiplier circuitry digital filters and other digital signal processing functions to form a complete quadrature digital up converter device TxDAC is a registered trademark of Analog Devices Inc REV 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices AD9873 INTERPOLATOR T FILTER SERIAL TECH CONTROL FUNCTIONS PROFILE On the receiver side two 8 bit ADCs are optimized for IQ demodulated out of band signals An on chip 10 bit ADC is typically used as a direct IF input of 256 QAM modulated signals in cable modem applications second direct IF input and an auxiliary video input with automatic programmable clamp function are multiplexed to a high performance 12 bit video ADC The chip s programmable sigma delta modulated outputs and an output clock may be used to control external compo
49. n Board Schematic Second Page Power and D 35 REV 0 09873 DIGITAL RECEIVE JP6 1 TXS RXSYNC i ANALOG DEVICES ADS873 Eval Board Rev A d 1 5 d 00 D6323e I ei RSS H 118 7 1687 C22 n 3 408323 Ok ra T1 T LI 2 a HI hh Bh ui AX d SS WA LE gt d d r ill Figure 29 Evaluation Board PCB Top Layer 36 REV 0 09873 e 0000000000900 eoeoceceo e 0600005000008 o Figure 30 Evaluation Board PCB Ground Plane Figure 31 Evaluation Board PCB Power Plane REV 0 37 09873 Den sei Bye Figure 32 Evaluation Board PCB Bottom Layer E 5 gt t 5 Figure 33 Evaluation Board PCB Assembly Bottom Side REV 0 38 09873 OUTLINE DIMENSIONS Dimensions shown in inches and mm 100 Lead Metric Quad Flatpack MQFP S 100C 0 921 23 4 0 906 23 0 0 791 20 10 0 787 20 00 0 783 19 90 0 742 18 85 80 51 81 50 0 555 14 10 me 0 551 14 00 12 35 TOP VIEW 0 547 13 90 PINS DOWN 0 685 17 4 0 669 17 0 e PIN 1 100 31 1 30 gt F F lt 0 029 0 73 0 015 0 35 0 023 0 57 0 009 0 25 0 110 2 80 0 102 2 60 0 041 1 03 SEATING 0 004 0 010 0 037 0 7
50. n frequency by an integer factor of between 1 and 31 inclusive to become the clock For DDS applications the carrier is typically limited to about 30 of fsyscrk For a 65 MHz carrier the recommended system clock is above 216 MHz The OSC IN Multiplier function maintains clock integrity as evidenced by the AD9873 s system phase noise characteristics of 113 dBc Hz External loop filter components consisting of a series resistor 1 3 and capacitor 0 01 pF provide the compensation zero for the CLK IN Multiplier PLL loop The overall loop performance has been optimized for these compo nent values Receive Section The AD9873 includes four high speed high performance ADCs Two matched 8 bit ADCs are optimized for analog IQ demodu lated signals and can be sampled with up to 16 5 MSPS A direct IF 10 bit ADC and a 12 bit ADC can digitize signals at a maxi mum sampling frequency of 33 MSPS Input signal selection to the 12 bit ADC can be programmed to either direct IF or video NTSC PAL A programmable automatic clamp control pro vides black level offset correction for video signals The ADC sampling frequency can either be derived directly from the OSC IN crystal or from the on chip OSC IN Multiplier For highest dynamic performance it is recommended to choose a OSC IN frequency that can be used to directly sample the ADCs 21 09873 Digital 8 bit ADC outputs are multiplexed to one 4 bit bus clocked b
51. nal data line The configuration of this pin is controlled by Bit 7 of register address Oh The default is logic zero which configures the SDIO pin as unidirectional SDO Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data In the case where the AD9873 operates in a single bidirectional I O mode this pin does not output data and is set to a high imped ance state MSBILSB Transfers The AD9873 serial port can support both most significant bit MSB first or least significant bit LSB first data formats This functionality is controlled by register address Oh Bit 6 The default is MSB first When this bit is set active high the AD9873 serial port is in LSB first format That is if the AD9873 is in LSB first mode the instruction byte must be written from least significant bit to most significant bit Multibyte data transfers in MSB format can be completed by writing an instruction byte that includes the register address of the most significant byte In MSB first mode the serial port internal byte address generator decrements for each byte required of the multibyte communication cycle Multibyte data transfers in LSB first format can be completed by writing an instruction byte that includes the register address of the least significant byte In LSB first mode the serial port internal byte address generator increments for each byte required of the multibyte communication cyc
52. nents such as programmable gain amplifiers PGA and mixer stages Three pins provide a direct interface to the AD8321 AD8323 programmable gain amplifier PGA cable driver The AD9873 is available in a space saving 100 lead MQFP package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 World Wide Web Site http www analog com Fax 781 326 8703 Analog Devices Inc 2000 09873 TABLE OF CONTENTS Page Page FEATURES iie t xa sa 1 TRANSMIT PATH 24 GENERAL DESCRIPTION 1 Transmit Timing 24 SPECIFICATIONS BEDE a ERS 3 Data Assembler tain eve EA 24 ABSOLUTE MAXIMUM RATINGS 7 Half Band Filters HBFs 25 THERMAL CHARACTERISTICS 7 Cascaded Integrator COMB CIC Filter 25 EXPLANATION OF TEST LEVELS 7 Combined Filter Response 25 ORDERING GUIDE 7 Inverse SINC Filter ISF 27 DEFINITIONS OF TERMS 8 Tx Signal Level Considerations 28 PIN FUNCTION DESCRIPTIONS 9 Tx Throughput and Latency 28 PIN CONFIGURATION 10 D A qukuspa TERR Vete s 28 REGISTER BIT DEFINITIONS 12 PROGRAMMING WRITING THE AD8321 AD8323 TYPICAL
53. next sampling instant This is known as a zero order hold function The spectrum of the zero order hold function is the familiar SIN x x or SINC envelope The series of digital data words presented at the input of the DAC represent an impulse stream It is the spectrum of this impulse stream which is the characteristic of the desired output signal Due to the zero order hold effect of the DAC however the output spectrum is the product of the zero order hold spectrum the SINC envelope and the Fourier transform of the impulse stream Thus there is an intrinsic distortion in the output spectrum which follows the SINC response 1 0 P MAGNITUDE dB 0 01 02 03 04 05 06 07 08 09 10 FREQUENCY FS 2 Figure 12a SINC and ISF Filter Response REV 0 The SINC response is deterministic and totally predictable Thus it is possible to predistort the input data stream in a manner which compensates for the SINC envelope distortion This can be accomplished by means of an ISF The ISF incorporated on the AD9873 is a 5 tap linear phase FIR filter Its frequency response characteristic is the inverse of the SINC envelope and it equalizes the SINC droop up to 0 6 times the Nyquist fre quency Figure 12a and Figure 12b show the effectiveness of the ISF in correcting for the SINC distortion Figure 12a includes a graph of the SINC envelope and ISF response while Figure 12b shows the SYSTE
54. o con struct each individual I and Q data paths it should be apparent that the input 6 bit data rate is four times the sample rate 4 X Once through the Data Assembler the I Q data streams are fed through two half band filters half band filters 1 and 2 The combination of these two filters results in a factor of four 4 increase of the sample rate Thus at the output of half band filter 2 the sample rate is 4 X In addition to the sample rate increase the half band filters provide the low pass filtering characteristic necessary to suppress the spectral images produced by the upsampling process After passing through the half band filter stages the I Q data streams are fed to a Cascaded Integrator Comb CIC filter This filter is configured as an interpolating filter which allows further upsampling rates of 3 or 4 The CIC filter like the half bands has a built in low pass characteristic Again this provides for suppres sion of the spectral images produced by the upsampling process The digital quadrature modulator stage following the CIC filters is used to frequency shift the baseband spectrum of the incom ing data stream up to the desired carrier frequency this process is known as upconversion The carrier frequency is numerically controlled by a Direct Digital Synthesizer DDS The DDS uses its internal reference clock to generate the desired carrier frequency wi
55. og Ground 8 Bit ADCs 24 33 38 DVDD Digital Supply Voltage 75 REFB8 Bottom Reference Decoupling 25 34 DGND Digital Ground IQ 8 Bit ADC s Reference 39 40 76 REFTS8 Top Reference Decoupling 26 Tx SYNC Synchronization Input for IQ 8 Bit ADC s Reference Transmitter 78 IIN Inverting I Analog Input 21 32 Tx IQ 5 Multiplexed I and Q Input 79 IIN Noninverting I Analog Input IQ 0 Data for Transmitter Two s 81 QIN iuvene E Complement 35 36 PROFILE 1 0 Profile Selection Inputs 82 Q IN Noninverting Q Analog Input 37 RESET Master Reset Input Reset applies Se ee 91 AGND Analog Ground 10 12 Bit ADC for all Interfaces and Registers 41 SCLK Serial Interface Input Clock e REFB10 ee e 42 CS Serial Interface Chip Select 86 REFTIO Top Rakan as Deconpling 43 SDIO Serial Interface Data I O IF 10 Bit ADC s Reference SDO Serial Interface Data Output 89 IF10 Noninverting IF10 Analog Input 45 DGND Tx Digital Ground Tx Section 90 IF10 Inverting IF10 Analog Input 46 DVDD Tx Digital Supply Voltage Tx 93 REFB12 Bottom Reference Decoupling 47 PWR DOWN Transmit Power Down IF 12 Bit ADC s Reference Control Input 94 REFT12 Top Reference Decoupling 48 REFIO DAC Bandgap requires 0 1 IF 12 Bit ADC s Reference Capacitor to Ground 97 IF12 Inverting IF12 Analog Input 49 FSADJ Full Scale DAC Current Output 98 12 Noninverting IF12 Analog Input 100 VIDEO IN Single Ended Video Input 50 AGND Tx Analog Ground Tx Sect
56. on Board CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the AD9873 features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality WARNING emma ESD SENSITIVE DEVICE REV 0 09873 DEFINITIONS OF TERMS DIFFERENTIAL NONLINEARITY ERROR DNL NO MISSING CODES An ideal converter exhibits code transitions that are exactly 1 LSB apart DNL is the deviation from this ideal value Guaranteed no missing codes to 10 bit resolution indicates that all 1024 codes respectively must be present over all operating ranges INTEGRAL NONLINEARITY ERROR INL Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale The point used as negative full scale occurs 1 2 LSB before the first code transition Positive full scale is defined as a level 1 1 2 LSB beyond the last code transition The deviation is measured from the middle of each particular code to the true straight line PHASE NOISE Single sideband phase noise power density is specified relative to the carrier dBc Hz at a given frequency o
57. ontrol registers to 0 for the lowest gain and sets the profile select to 0 The AD9873 writes all 0 out of the 3 wire cable amplifier control interface if the gain was on a different setting different from 0 before 3 Change in Profile Selection The AD9873 samples the PROFILE 0 PROFILE 1 input pins together with the two profile select bits and writes to the AD832x gain control regis ters when a change in profile and gain is determined The data written to the cable driver amplifier comes from the AD9873 gain control register associated with the current profile 4 Write to AD9873 Cable Driver Amplifier Control Registers The AD9873 will write gain control data associated with the current profile to the AD832x whenever the selected AD9873 cable driver amplifier gain setting is changed Once a new stable gain value has been detected 48 to 64 MCLK cycles after initiation data write starts with CA ENABLE going low The AD9873 will always finish a write sequence to the cable driver amplifier once it is started The logic controlling data transfers to the cable driver amplifier uses up to 200 MCLK cycles and has been designed to prevent erroneous write cycles from occurring 29 09873 RECEIVE PATH Rx ADC Theory of Operation The AD9873 s analog to digital converters implement pipelined multistage architectures to achieve high sample rates while con suming low power Each ADC distributes the conversion over several sm
58. ot RBW 1 kHz FREQUENCY MHz TPC 12 16 OAM 5 MHz Spectral Plot RBW 1 kHz 16 REV 0 REV 0 09873 View Active Freq mpl 6 16 00 3 36 07 PM Marker 45MHz 27 011dBm D 10 div 100 Center 45MHz Span 5MHz View B EVM Marker z6sym 252 307m Length 405syni div UNCAL OVERLOAD TRIGGERED PAUSE View C Polar Manual Setup View C Active 16QAM Measurement 6 16 00 3 36 07 Marker 25 9825 0 755 71 468deg Freq Err OHz igin O Modulation Symbol Rate 56 Measurement Filter fRootRaisedcos View D Measurement I Marker 10 937 Sus 0 24 Reference 1 5 Filter Start 03 Scale 16us div 45 Freq 45MHz RF Dual Blackman 1024 320u 160u 200 Auto On 1 TPC 13 Tx Output 16 OAM Analysis UNCAL OVERLOAD TRIGGERED PAUSE View C View Active Freq mpl 6 16 00 3 39 49 PM View C Active 64QAM Measurement 6 16 00 3 39 49 P polar Marker 45MHz 25 249dBm D 10 div 100 Center 45MHz View B EVM Marker 23sym 569 582mt M 0 42 0 o 1 405syn Span 5MHz Length div D WL L s OO Start 05 Scale 16us div Freq 45MHz RF Dual AC Blackman 1024 320u 160uj 200 Auto On 1 Marker 22 8018ym 0 333 5 408deqg Freq Err Origin Of Manual Setup Modulation saan Symbol Rate 56 Measurement F
59. pled by a low jitter clock at OSC IN or by a clock that is derived from the PLL output Operating modes can be selected in register address 08 Sampling the ADCs directly with the OSC IN clock requires MCLK to be programmed to be twice the OSC IN frequency CP1 CP2 c2 C5 0 1pF O 1pF 0 1pF 0 1pF z NN oo a a a a 2 2 2 5 2 2 5 5 6 5 lt lt lt coc lt q lt lt lt E m lt lt OO 2 gt Od 2 CO CO OO AGND IQ DRGND 2 IIN IDENTIFIER DRVDD 3 LIN Ic MSB 4 AGND IQ E IF 10 5 REFT8 C8 1 9 6 REFB8 O F T 10K iF 8 7 AGND IQ m iF 7 8 AVDD IQ ff iF 6 9 DRVDD 1 IF 5 10 iF 4 11 DRGND IF 3 12 DGND SO iF 2 13 SDELTAO 1 1 14 SDELTA1 iF 0 15 AD9873 DVDD SD MSB Rx IQ 3 16 DE MEW CA ENABLE Rx o 17 Pins Down CA DATA C10 Rx 1Q 1 18 CA CLK 20pF Rx 1Q 0 19 DVDD OSC dii Rx SYNC 20 OS IN 20pF DRGND 21 XTAL oe DRVDD 22 DGND OSC GUARD TRACE MLCK 23 AGND PLL Ri C12 DVDD 24 PLL FILTER DGND 25 AVDD PLL___1 3k 0 01pF Tx SYNC 26 DVDD PLL MSB Tx 1Q 5
60. re 25 C IV 2 0 ns Aperture Uncertainty Jitter 25 C IV 1 2 ps rms Input Bandwidth 3 dB 25 C IV 85 MHz Input Referred Noise 25 C IV 75 UN Reference Voltage REFT12 REFBI2 1 V 25 I 6 200 mV REV 0 09873 Test Parameter Temp Level Min Typ Max Unit 12 BIT ADC CHARACTERISTICS Continued Dynamic Performance 0 5 dB FS f 5 MHz Signal to Noise and Distortion Ratio SINAD Full 62 3 65 Signal to Noise and Distortion Ratio SINAD Full IV 67 4 dB Effective Number of Bits ENOB Full III 10 0 10 5 Bits Effective Number of Bits ENOB Full IV 10 8 Bits Signal to Noise Ratio SNR Full 63 3 65 3 dB Signal to Noise Ratio SNR Full IV 67 4 dB Total Harmonic Distortion THD Full III 77 6 65 4 Total Harmonic Distortion THD Full IV 77 6 dB Spurious Free Dynamic Range SFDR Full 65 7 80 dB Spurious Free Dynamic Range SFDR Full IV 80 dB Differential Phase 25 C IV lt 0 1 Degree Differential Gain 25 C IV lt 1 LSB VIDEO CLAMP INPUT Input Voltage Range Full IV 2 Clamp Current Positive 25 C IV 1 3 mA Clamp Droop Current 25 C IV 2 pA Clamp Level Offset Programming Range 25 C 256 512 2032 LSB Clamp Level Resolution 25 C IV 16 LSB Carrier Rejection Filter Bandwidth 3 dB 25 C IV 0 6 MHz Dynamic Performance 0 5 dB FS f 5 MHz Signal to Noise and Distortion Ratio SINAD Full IV 52 dB Effective Number of Bi
61. s into track mode the input source must charge or discharge capacitor from the voltage already stored on Cy to the new voltage In the worst case a full scale voltage step on the input source must provide the charging current through the 100 0 of Switch 1 and quickly within 1 2 CLK period settle This situation corresponds to driving a low input impedance On the other hand when the source voltage equals the value previously stored on Cy the hold capacitor requires no input current and the equivalent input impedance is extremely high Adding series resistance between the output of the signal source and the pin reduces the drive requirements placed on the signal source Figure 20 shows this configuration Figure 20 Simple ADC Drive Configuration The bandwidth of the particular application limits the size of this resistor To maintain the performance outlined in the data sheet specifications the resistor should be limited to 50 Q or less For applications with signal bandwidths less than 10 MHz the user may proportionally increase the size of the series resistor Alter natively adding a shunt capacitance between the Am pins can lt tur IF 10 IF 12 IF 12 IF 10 IF 12 IF 12 SCENES CED 053093 ED AED OED OED 3 Figure 18 Receive Timing Diagram 30 REV 0 09873 lower the ac load impedance The value of this capacitance will depend on the source resistance and the required signal band width
62. ted carrier frequency fc and is formed via a concatenation of register addresses Bit 7 of register address 1Ah is the most significant bit of the profile 2 frequency tuning word Bit 0 of register address 18h is the least significant bit of the profile 2 frequency tuning word REV 0 The output frequency equation is given as fo FTW x fsyscix 2 Where fsyscrk Mx foscm and FTW lt 80 00 00h Changes to FTW bytes immediately take effect on active profiles Cable Driver Gain Control The AD9873 dedicates three output pins that directly interface to the AD832x family of gain programmable cable driver amplifier This allows direct control of the cable driver s gain via the AD9873 New data is automatically sent to the cable driver amplifier whenever a new burst profile with different gain setting becomes active or when the gain contents of an active AD8321 AD8323 gain control register changes Default value is 00h lowest gain 13 09873 Typical Performance Characteristics Vas 3 3 Vos 3 3 V foscin 27 MHz 216 MHz 54 MHz 8 N 4 ADC Sample Rate derived directly from foscu Rser 10 4 mA 75 DAC Load unless otherwise noted TYPICAL POWER CONSUMPTION CHARACTERISTICS 20 MHz Single Tone unless otherwise noted 380 340 SINGLE TONE 360 330 340 lt lt 5 16 QAM 320 1 320 E E
63. th a high degree of precision The carrier is applied to the I and Q multi pliers in quadrature fashion 90 phase offset and summed to yield a data stream that is at the modulated carrier It should be noted at this point that the incoming symbols have been converted from an input sample rate of fioc x to an output sample rate of see Figure 1 The modulated carrier is ultimately destined to serve as the input to the digital to analog converter DAC integrated on the AD9873 The DAC output spectrum is distorted due to the intrinsic zero order hold effect associated with DAC generated signals This distortion is deterministic and follows the familiar SIN X X or SINC envelope Since the SINC distortion is predictable it is also correctable Hence the presence of the optional Inverse SINC Filter preceding the DAC This is a FIR filter which has a transfer function conforming to the inverse of the SINC response Thus when selected it modifies the incoming data stream so that the SINC distortion which would otherwise appear in the DAC output spectrum is virtually eliminated REV 0 Single Tone Output Transmit Operation The AD9873 can be configured for frequency synthesis applica tions by writing the single tone bit true and applying a clock signal e g Rx SYNO to the Tx SYNC pin In single tone mode the AD9873 disengages the modulator and preceding data path logic to output a spectrally pure single frequency s
64. tion REV 0 09873 ABSOLUTE MAXIMUM RATINGS Power Supply VAS VDS 3 9V Digital Output Current 5mA Digital Inputs 0 3 V to DRVDD 0 3 V Analog Inputs 0 3 V to AVDD IQ 0 3 V Operating Temperature 0 C to 70 C Maximum Junction Temperature 150 C Storage Temperature 65 to 150 C 300 C Absolute maximum ratings are limiting values to be applied individually and beyond which the serviceability of the circuit may be impaired Functional operability under any of these conditions is not necessarily implied Exposure of absolute maximum rating conditions for extended periods of time may affect Lead Temperature Soldering 10 sec EXPLANATION OF TEST LEVELS 100 production tested Devices are 100 production tested at 25 C and guaran teed by design and characterization testing for commercial operating temperature range 0 C to 70 C III Parameter is guaranteed by design and or characteriz ation testing IV Parameter is a typical value only N A Test level definition is not applicable THERMAL CHARACTERISTICS Thermal Resistance 100 Lead MQFP device reliability Oja 40 5 C W ORDERING GUIDE Temperature Package Package Model Range Description Option AD9873JS 0 C to 70 C Metric Quad Flatpack MQFP S 100C AD9873 EB Evaluati
65. true and complement outputs to the differential inputs of the gain programmable cable drivers AD8321 or AD8323 provides an optimized solution for the standard com pliant cable modem upstream channel The cable driver s gain can be programmed through a direct 3 wire interface using the AD9873 s profile registers REV 0 C 7 O CA ENABLE CA DATA VARIABLE GAIN CA_CLK CABLE DRIVER AMPLIFIER Figure 15 Cable Amplifier Connection 8tycik 8tycik 8tycik CA ENABLE CA CLK CA DATA Figure 16 Cable Amplifier Interface Timing PROGRAMMING WRITING THE AD8321 AD8323 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the gain of the AD832x family cable driver amplifier can be accomplished via the AD9873 cable amplifier control interface Four 8 bit registers within the AD9873 one per profile store the gain value to be written to the serial 3 wire port Data transfers to the gain programmable cable driver amplifier are initiated by four conditions Each is described below 1 Power up and Hardware Reset Upon initial power up and every hardware reset the AD9873 clears the contents of the gain control registers to 0 which defines the lowest gain set ting of the AD832x Thus the AD9873 writes all 0s out of the 3 wire cable amplifier control interface 2 Software Reset Writing a one to Bit 5 of address 00h initiates software reset On a software reset the AD9873 clears the contents of the gain c
66. ts Full IV 8 34 Bits Signal to Noise Ratio SNR Full IV 61 0 dB Total Harmonic Distortion THD Full IV 53 0 dB Spurious Free Dynamic Range SFDR Full IV 55 0 dB Differential Phase 25 IV lt 0 1 Degree Differential Gain 2526 IV 8 LSB CHANNEL TO CHANNEL ISOLATION Tx DAC to ADC Isolation 5 MHz Analog Output Isolation Between Tx and 8 Bit ADCs 25 IV gt 80 dB Isolation Between Tx and 10 Bit ADC 25 C IV gt 85 dB Isolation Between Tx and 12 Bit ADC 25 C IV gt 90 dB ADC to ADC Isolation Am 0 5 dB FS f 5 MHz Isolation Between IF12 and Video 25 C III 70 gt 70 dB Isolation Between IF10 and IF12 25 C IV gt 80 dB Isolation Between Q in and IF10 25 C IV gt 80 dB Isolation Between Q in and I Inputs 25 C IV gt 70 dB TIMING CHARACTERISTICS 20 pF Load Wake Up Time N A N A 200 Cycles Minimum RESET Pulsewidth Low tgr N A N A 5 Cycles Digital Output Rise Fall Time 25 C 2 8 4 ns Tx Rx Interface Frequency 25 C III 66 MHz TxSYNC TxIQ Set Up Time tsy 25 C III 3 ns TxSYNC TxIQ Hold Time typ 25 III 3 ns RxSYNC RxIQ IF to Valid Time trv 25 C 5 2 ns RxSYNC RxIQ IF Hold Time 25 0 2 ns Serial Control Bus SCLK Frequency fscr x Full III 15 MHz Clock Pulsewidth High Full III 30 ns Clock Pulsewidth Low tpy Full III 30 ns Clock Rise Fall Time Full III 1 ms Data Chip Select Setup Time tps Full III 25 ns Data Hold Time tpp Full III
67. ude direct transformer coupled or filtered 75 MHz and variable gain amplified by the AD8323 Digital transmit Tx inputs are designed to be driven from various word generators and allow for proper load termination 09873 Register Access File Edit Character Interface Mode View Help Adress Data hexadecimal EE FF 16 255 OK 1111 1111 decimal binary pr LI 2123 5010 Foscin Multiplier Foscin Frequency Addr 00 10 Bidirectional LSB first Reset M be 13 50000000 MHz ps Laf ES Output Sampling Frequency KAN MHz Loci Detect Ps Ref Out Clock MHz MCLK ra r gio 54 00000000 MHz ee DAC TX ADC ga apc OO g bit ADC 3 Power Down 7 WRITE Addr 03 EO Sigma Delta 0 Output Level 702 Addr 04 2B Lad Addr 05 50 Sigma Delta 1 Output Level 1429 Addr 06 59 Si qud RECEIVE TRANSMIT Profile 0 Profile Profile 2 Profile 3 Profile Select Bypass Spectra Single Inv Sinc Inversion Tone Addr OF 02 Profile 0 Profile 1 Profile 2 Profile 3 Addr 10 1C 211 Carrier Frequency 11 C7 Dsi far 99999678 MHz 12 31 2 1 Add 13 1 Gob 08321 Gain 4 10 dB 509873 PWD WRITE Software The AD9873 EB software provides a graphical user interface that allows easy programming and read back of AD9873 register settings Three programming windows are available The Direct reg
68. ut signal and is expressed as a percentage or in decibels POWER SUPPLY REJECTION Power supply rejection specifies the converters maximum full scale change when the supplies are varied from nominal to minimum and maximum specified voltages CHANNEL TO CHANNEL ISOLATION CROSSTALK In an ideal multichannel system the signal in one channel will not influence the signal level of another channel The channel to channel isolation specification is a measure of the change that occurs to a grounded channel as a full scale signal is applied to another channel REV 0 09873 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Pin Function Pin No Mnemonic Pin Function 1 84 87 AVDD Analog Supply Voltage 64 CA DATA Cable Amplifier Control Data 92 95 10 12 Bit ADC Output 2 21 70 DRGND Pin Driver Digital Ground 65 CA ENABLE Cable Amplifier Control Enable 3 22 72 DRVDD Pin Driver Digital Supply Voltage Output 4 15 IF11 IFO Multiplexed Output of IF10 66 DVDD SD Supply Voltage Sigma Delta and IF12 Bit ADCs 67 SDELTAI Sigma Delta Output Stream 1 16 19 Rx IQ 3 Multiplexed Output of I and 68 SDELTAO Sigma Delta Output Stream 0 IQ 0 Q 8 Bit ADCs 69 DGND SD Ground Sigma Delta 20 Rx SYNC Demultiplexer Synchronization 71 REF CLK Programmable Reference Clock Output for IF and IQ ADCs Output Derived from MCLK 23 MCLK Master Clock Output 73 AVDD IQ Analog Supply 8 Bit ADCs Demultiplexer 74 77 80 AGND IQ Anal
69. version Rate Full III 33 MHz Pipeline Delay N A N A 5 5 ADC Cycles DC Accuracy Differential Nonlinearity 25 C IV 0 75 LSB Integral Nonlinearity 25 C IV 0 5 LSB Offset Error 25 C IV 0 5 FSR Gain Error 25 C IV 3 FSR Analog Input Input Voltage Range Full IV 2 V Input Capacitance 25 C IV 1 4 pF Differential Input Resistance 25 C IV 4 Aperture 25 IV 2 0 ns Aperture Uncertainty Jitter 25 C IV 1 2 ps rms Input Bandwidth 3 dB 25 C IV 95 MHz Input Referred Noise 25 C IV 350 UN Reference Voltage REFT10 REFB10 1 V 25 C I 6 200 mV Dynamic Performance 0 5 dB FS f 5 MHz Signal to Noise and Distortion Ratio SINAD Full II 57 9 60 1 dB Effective Number of Bits Full II 9 3 9 7 Bits Effective Number of Bits ENOB Full IV 9 8 Bits Signal to Noise Ratio SNR Full II 58 2 60 1 dB Total Harmonic Distortion THD Full II 75 8 63 9 dB Spurious Free Dynamic Range SFDR Full II 65 7 80 dB Differential Phase 25 lt 0 1 Degree Differential Gain 25 C IV lt 1 LSB 12 BIT ADC CHARACTERISTICS Resolution N A N A 12 Bits Conversion Rate Full 33 MHz Pipeline Delay N A N A 5 5 ADC Cycles DC Accuracy Differential Nonlinearity 25 C IV 0 75 LSB Integral Nonlinearity 25 C IV 15 LSB Offset Error 25 C IV 1 FSR Gain Error 25 C IV 2 FSR Analog Input Input Voltage Range Full IV 2 V p p Input Capacitance 25 C IV 1 4 pF Differential Input Resistance 25 C IV 4 Apertu
70. words have a default value of 0 The smaller the programmed values in these registers the lower are the integrated low pass filtered sigma delta output levels straight binary format 07h Bits 0 6 Clamp Level Control for Video Input 7 bit clamp level offset can be set for the internal automatic clamp level control loop of the Video Input Clamp level offset Clamp level control x 16 This register defaults to 32 20h which amounts to a clamp level offset of 512 LSB 200h Valid clamp level control values are 16 to 127 07h Bit 7 Video Input Enable This bit controls the multiplexer to the 12 bit ADC and deter mines if IF12 input or Video input is used The bit is default set to 0 for the IF12 input 08h Bit 0 Test 10 Bit ADC Active high allows nonmultiplexed 10 bit ADC data only to be read at IF outputs Output data changes at half MCLK clock rate This bit defaults to 0 08h Bit 1 Test 12 Bit ADC Active high allows nonmultiplexed 12 bit ADC data only to be read at IF outputs Output data changes at half MCLK clock rate This bit defaults to 0 08h Bit 5 and Bit 7 ADC Clock Select Active high indicates that the frequency at OSC IN is directly used to sample the on chip ADCs Default low indicates that the on chip ADCs generate their sampling frequencies from the internally generated master clock MCLK Both Bit 5 and Bit 7 need to be programmed with the same values 0Ch Bits 0 3 Version This register stor
71. xi mum data rate that can be propagated through the AD9873 A look at the passband detail of the combined filter response Figure 10d and Figure 11d indicates that in order to maintain an amplitude error of no more than 1 dB we are restricted to signals having a bandwidth of no more than about 60 of fuyo Thus in order to keep the bandwidth of the data in the flat portion of the filter passband the user must oversample the baseband data by at least a factor of two prior to presenting it to the AD9873 Note that without oversampling the Nyquist bandwidth of the baseband data corresponds to the fuyo As such the upper end of the data bandwidth will suffer 6 dB or more of attenuation due to the frequency response of the digital filters Furthermore if the baseband data applied to the AD9873 has been pulse shaped there is an additional concern Typically pulse shaping is applied to the baseband data via a filter having a raised cosine response In such cases an value is used to modify the bandwidth of the data where the value of a is such that lt o lt 1 A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwidth Thus with 2x oversampling of the baseband data and 1 the Nyquist bandwidth of the data will correspond with the I Q Nyquist bandwidth As stated earlier this results in problems near the upper edge of the data bandwi
72. y Later sections will detail each of the data path build to refer to Figure 1 which displays a block diagram of the device ing blocks QUADRATURE DATA MODULATOR AD9873 ASSEMBLER HALF BAND HALF BAND CIC r FSADJ FILTER 1 FILTER 2 FILTER INV SINC 12 12 I BYPASS Tx SYNC 12 OSC IN MULTIPLIER C XTAL MCLK s C OSC IN SDELTAO SDELTA1 I INPUT Q INPUT Rx SYNC O IF10 INPUT IF12 INPUT VIDEO INPUT Figure 1 Block Diagram 20 REV 0 09873 Transmit Section Modulation Mode Operation The AD9873 accepts 6 bit words which are strobed synchronous to the master clock MCLK into the Data Assembler Tx SYNC signals the start of a transmit symbol Two successive 6 bit words form a 12 bit symbol component The incoming data is assumed to be complex in that alternating 12 bit words are regarded as the inphase I and quadrature Q components of a symbol Symbol components are assumed to be in two s complement format The rate at which the 6 bit words are presented to the AD9873 will be referred to as the master clock rate The Data Assembler splits the incoming data words into separate I Q data streams The rate at which the I Q data word pairs appear at the output of the Data Assembler will be referred to as the Q Sample Rate Since two 6 bit input data words are used t
73. y a frequency of four times the sampling rate whereas the 10 and 12 bit ADCs are multiplexed together to one 12 bit bus clocked by Luc which is two times their sampling frequency CLOCK AND OSCILLATOR CIRCUITRY The AD9873 s internal oscillator generates all sampling clocks from a simple low cost series resonance fundamental frequency quartz crystal Figure 2 shows how the quartz crystal is connected between OSC IN Pin 61 and XTAL Pin 60 with parallel resonant load capacitors as specified by the crystal manufacturer The internal oscillator circuitry can also be overdriven by a TTL level clock applied to OSC IN with XTAL left unconnected fosc IN X An internal phase locked loop PLL generates the DAC sampling frequency fsyscrk by multiplying OSC IN frequency M times register address 00h The MCLK signal Pin 23 is derived by dividing this PLL output frequency with the interpo lation rate N of the CIC filter stages register address 01h SsysciK fosc X fosc in X MIN An external PLL loop filter Pin 57 consisting of a series resistor and ceramic capacitor Figure 15 R1 1 3 C12 0 01 is required for stability of the PLL Also a shield surrounding these components is recommended to minimize external noise coupling into the PLL s voltage controlled oscillator input guard trace connected to AVDD PLL Figure 1 shows that ADCs are either directly sam

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