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ANALOG DEVICES ADE7754 handbook

1. i o LPF2 QHA Vap 19 a O a AWG BVGAIN BVRMSOS me BIRMSOS 1 y BAPGAIN HPF 2 x gt E ue re D m QD cA 2 anc BPHCAL C9 BAPOS BWG CVGAIN 5 5 O x2 CVAG CIRMSOS lop CAPGAIN 2 lon 2 VN REV 0 Patents pending Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use norfor any infringements of patents or other rights ofthird parties that may result from its use No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective companies ADE7754 POWER SUPPLY MONITOR DIN DOUT SCLK CS Technology Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2003 Analog Devices Inc rights reserved ADE7794 Contents GENERAL DESCRIPTION 1 FEATURES A E Perla ere iren 1 SPECIFICATIONS iste a aa te DDR eS 3 TIMING CHARACTERISTICS 4 ABSOLUTE MAXIMUM RATINGS
2. 5 ORDERING GUIDE 5 PIN CONFIGURATION 0 5 PIN FUNCTION DESCRIPTIONS 5 TYPICAL PERFORMANCE CHARACTERISTICS 7 TERMINOLOGY o otera aae ovt rne etl e Ue P 9 Measurement Error 9 Phase Error Between Channels 9 Power Supply Rejection 9 ADC Offset Error eats Diese wane Be 9 Gai Error ea vee bee te PE Tt LRG ek ERA 9 Gain Error Match Ra REC SS 9 POWER SUPPLY MONITOR 9 ANALOG INPUTS eee IR e ente aee 9 ANALOG TO DIGITAL CONVERSION 10 Antialias Filter o Cre te ed 10 CURRENT CHANNEL ADG 11 Current Channel ADC Adjust 11 Current Channel Sampling 11 VOLTAGE CHANNEL 12 ZERO CROSSING DETECTION 12 Zero Crossing Timeout 13 PERIOD MEASUREMENT 13 LINE VOLTAGE SAG DETECTION p 13 PEAK DETECTION X 91 18 Peak Level Set W MW WW 14 TEMPERATURE MEASUREMENT 14 PHASE COMPENSATION 14 ROOT MEAN SQUARE MEASUREMENT 15 Current RMS Calculation 15 Current RMS Gain Adjust 16 Current RMS Offse
3. POWER PHASEA POWER PHASEB POWER PHASEC Figure 31 Active Energy Calibration 22 REV 0 ADE7754 Thus the IRQ line can also be used to signal the end of a cali bration Equation 14 is derived from Equations 8 and 12 nT x cos 2z f t dt f 2 0 14 nT E t VI dt 0 where 7 is an integer and T is the line cycle period Since the sinusoidal component is integrated over an integer number of line cycles its value is always zero Therefore nT E t J VI dt 0 15 0 E t VInT 16 The total active power calculated by the ADE7754 in the line accumulation mode depends on the configuration of the WATMOD bits in the WATMode register Each term of the formula can be disabled or enabled by the LWATSEL bits of the WATMode register The different configurations are described in Table III Table III Total Line Active Energy Calculation WATMOD LWATSELO LWATSEL1 LWATSEL2 0 1 Vax 2 Va X I5 0 Vc X Ic Note that Ig and Ic represent the current channels samples after APGAIN correction and high pass filtering The line active energy accumulation uses the same signal path as the active energy accumulation however the LSB size of the two registers is different If the line active energy register and active energy register are accumulated at the same
4. Address Default A5 A0 Name R W Length Value Description 13h LINCYC R W 16 FFFFh Line Cycle Register The content of this register sets the number of half line cycles while the active energy and the apparent energy are accumulated in the LAENERGY and LVAENERGY registers See the Energy Calculation section 14h SAGCYC R W 8 FFh SAG Line Cycle Register This register specifies the number of consecutive half line cycles where voltage channel input falls below a threshold level This regis ter is common to the three line voltage SAG detection The detection threshold is specified by SAGLVL register See the Line Voltage SAG Detection section 15h SAGLVL RW 8 0 SAG Voltage Level This register specifies the detection threshold for SAG event This register is common to the three line voltage SAG detection See the description of SAGCYC register for details 16h VPEAK R W 8 FFh Voltage Peak Level This register sets the level of the voltage peak detection If the selected voltage phase exceeds this level the PKV flag in the status register is set See Table XII 17h IPEAK R W 8 FFh Current Peak Level This register sets the level of the current peak detec tion If the selected current phase exceeds this level the PKI flag in the status register is set See Table XII 18h GAIN RW 8 0 PGA Gain Register This register is used to adjust the gain selection for the PGA in current and voltage channels See the Analog Inputs section and Table X Th
5. REV 0 7754 CFNUM 11 0 11 0 ACTIVE POWER 00 ACTIVE POWER _ d PHASE B 2 DFC o O cF 53 0 ACTIVE POWER TOTAL ACTIVE PHASE POWER 11 0 CFDEN 11 0 Figure 29 ADE7754 Energy to Frequency Conversion digital to frequency converter DFC is used to generate the CF pulsed output The DFC generates a pulse each time one LSB in the active energy register is accumulated An output pulse is generated when CFDEN CFNUM pulses are generated at the DFC output Under steady load conditions the output frequency is proportional to the active power The maximum output frequency CFNUM 00h and CFDEN 00h with full scale ac signals on the three phases i e current channel and voltage channel is approximately 96 kHz The ADE7754 incorporates two registers to set the frequency of CF CFNUM 11 0 and CFDEN 11 0 These are unsigned 12 bit registers that can be used to adjust the frequency of CF to a wide range of values These frequency scaling registers are 12 bit registers that can scale the output frequency by 1 2 to 1 with a step of 1 212 If the value 0 is written to any of these registers the value 1 would be applied to the register ratio CENUM GEDEN should be smaller than 1 t9 ensure proper operation the ratio of the registers CFNUM CFDEN is greater than 1 the CF frequency can no longer be guaranteed to be a consistent value For e
6. rms voltage and I rms current p t va x it 5 p t VI cos 2ox The average power over an integral number of line cycles n is given by the expression in Equation 6 P 6 nT REV 0 where T is the line cycle period P is referred to as the active or real power Note that the active power is equal to the dc compo nent of the instantaneous power signal p t in Equation 5 i e VI This is the relationship used to calculate active power in the ADE7754 for each phase The instantaneous power signal p 2 is generated by multiplying the current and voltage signals in each phase The dc component of the instantaneous power signal in each phase A B and C is then extracted by LPF2 low pass filter to obtain the active power information on each phase This process is illustrated in Figure 22 In a polyphase system the total electrical power is simply the sum of the real power in all active phases The solutions available to process the total active power are discussed in the following section INSTANTANEOUS POWER SIGNAL p t Vx I V x I cos 2wt QlA36E2Eh ACTIVE REAL POWER SIGNAL V I V I DIB717h i cnn 25 22 00000h N CURRENT t i t 21 sin ot N 7 AYZ Visi A a VOLTAGE Figure 22 Active Power Calculation Since LPF2 does not have an ideal brick wall frequency response see Figure 23
7. TOTAL APPARENT POWER x T F 2 APPARENT POWER i SIGNAL P T TOTAL APPARENT POWER IS gt ACCUMULATED INTEGRATED IN D1B71h THE APPARENT ENERGY REGISTER 00000h gt TIME nT Figure 37 Apparent Energy Calculation The upper 49 bit value of the internal register is divided by VADIV If the value in the VADIV register is 0 then the internal active energy register is divided by 1 VADIV is an 8 bit unsigned register The upper 24 bit values are then written in the 24 bit apparent energy register VAENERGY 23 0 RVAENERGY register 24 bits long is provided to read the apparent energy This register is reset to 0 after a read operation Figure 38 shows this apparent energy accumulation for full scale sinusoidal signals on the analog inputs The three curves illus trate the minimum time it takes the energy register to roll over when the individual VA gain registers contents all equal 3FFh 000h and 800h The VA gain registers are used to carry out an apparent power calibration in the ADE7754 The fastest integra tion time occurs when the VA gain registers are set to maximum full scale 1 3FFh 26 VAENERGY 23 0 7F FFFFh 1 4 AVAG BVAG CVAG 3FFh j AVAG BVAG CVAG 000h 2a AVAG BVAG CVAG 800h 3F FFFFh u I ff D 00 0000h gt 65 5 131 196 5 262 1327 5 393 i 4 k 40 0000h a M
8. 0 00 ERI 0 04 1 5V 0 08 7 TAY 1 0 12 5 25V 0 16 0 20 0 01 0 1 1 CURRENT INPUT fs 100 TPC 8 Real Power Error as a Percentage of Read ing over Power Supply with External Reference Gain 1 0 20 GAIN 1 1 0 15 INTERNAL REFERENCE 0 10 0 05 4 75V N AIT TSN 0 00 0 05 gt 0 10 0 15 1 0 20 0 01 0 1 1 10 100 CURRENT INPUT fs TPC 9 Real Power Error as a Percentage of Reading over Power Supply with Internal Reference Gain 1 PS2501 1 TO SPI BUS ONLY USED FOR CALIBRATION 1MO 220V wf 33nF 116 4 33955 SD 3 13475 LIMITS LOW 19 HIGH 19 MIN 2 21937 14 7485 16 9669 PERCENT ERROR PhA OFFSET mV TPC 11 Current Channel Offset Distribution Gain 1 REV 0 7754 TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7754 is defined by the formula Percentage Error Energy Registered by ADE T 154 True Energy True Energy Phase Error Between Channels The HPF high pass filter in the current channel has a phase lead re
9. 00 0 80 0 60 0 40 0 20 GAIN 1 INTERNAL REFERENCH 0 00 0 20 0 40 0 60 0 80 1 00 1 10 100 CURRENT INPUT fs TPC 4 Current RMS Error as a Percentage of Reading with Internal Reference Gain 1 0 50 GAIN 1 INTERNAL REFERENCE 0 40 VOLTAGE INPUT fs TPC 5 Voltage RMS Error as a Percentage of Reading with Internal Reference Gain 1 0 50 GAIN 1 0 5 EXTERNAL REFERENCE 0 40 0 30 0 20 0 10 0 00 0 10 0 20 0 30 0 40 0 50 0 01 0 1 1 10 VOLTAGE INPUT fs 100 TPC 6 Real Power Error as a Percentage of Reading over Power Factor with External Reference Gain 1 ADE PERCENT ERROR PERCENT ERROR PERCENT ERROR 1154 1 00 GAIN 1 0 80 INTERNAL REFERENCE 0 60 0 40 z1 E 0 20 0 00 0 20 0 40 0 60 0 80 1 00 45 50 60 65 55 FREQUENCY Hz TPC 7 Real Power Error as a Percentage of Read ing over Input Frequency with Internal Reference 0 20 GAIN 1 0 16 1 EXTERNAL REFERENCE 0 12 0 08 0 04
10. 17 80 0000h TIME sec Figure 38 Energy Register Roll Over Time for Full Scale Power Minimum and Maximum Power Gain Note that the apparent energy register contents roll over to full scale negative 80 0000h and continue increasing in value when the power or energy flow is positive as shown in Figure 38 By using the interrupt enable register the ADE7754 can be config ured to issue an interrupt IRQ when the apparent energy register is half full positive or negative Integration Times under Steady Load As described in the preceding section the discrete time sample period T for the accumulation register is 1 2 us 12 CLKIN With full scale sinusoidal signals on the analog inputs and the gain registers set to 000h the average word value from each apparent power stage is DIB71h See the Apparent Power Calculation section The maximum value that can be stored in th apparent energy register overflows is 223 1 or FF FFEFh As the average word 15 added to the internal register that store 248 1 FFFF FFFF FFFFh before it overflows the integration time under these conditions with VADIV 0 is calculated as follows FFFF FFFF FFFFh 3x D1B71h When VADIV is set to a value different from 0 the integration time varies as shown in Equation 23 Time Timeyjy XVADIV 23 Time x1 20s 131s 2minlls LINE APPARENT ENERGY ACCUMULATION The ADE7754 is designed with a special ap
11. 3 V to 0 3V Lead Temperature Soldering Analog Input Voltage to AGND Vapor Phase 60 215 C Ian Ipp Icn Ver Vcr 6 V to 6 V Infrared 15 s66 2 4 0 eR e c tet bs 220 C Reference Input Voltage to AGND 0 3 to AVpp 0 3 V RENE RN Em NN resses above those listed under Absolute Maximum Ratings may cause perma Digital Input Voltage to 0 3 V to DVpp 0 3 V nent damage to the device This is a stress rating only functional operation of the Digital Output Voltage to DGND 0 3 V to DVpp 0 3 V device at these or any other conditions above those listed in the operational Operating Temperature Range sections of this specification is not implied Exposure to absolute maximum rating Industrial 40 to 85 conditions for extended periods may affect device reliability ORDERING GUIDE Model Package Description Package Option ADE7754AR 24 Lead SOIC RW 24 ADE7754ARRL 24 Lead SOIC 24 in Reel EVAL ADE7754EB ADE7754 Evaluation Board RW Small Outline Wide Body Package in Tubes CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although the WARNING lt ADE7754 features proprietary ESD protection circuitry permanent damage may occur on devices Sept ete subjected
12. ADC one bit is passed directly to the multiplier and is not filtered This solution avoids a wide bits multiplier and does not affect the accuracy of the measurement HPF is not required to remove any dc offset since it is only required to remove the offset from one channel to eliminate errors in the power calculation In the voltage channel the samples may also be routed to the WFORM register WAVMODE to select VA VB or VC and sampling frequency However before being passed to the wave form register the ADC outputjisgpassed through single pole low pass filter with a cutoff frequehey 98260 Hz The plots in Figure 13 show the magnitude and phase response of this filter The filter output code of any inputs of the voltage channel swings between D70Bh 10 485d and 28F5h 10 485d for full scale sine wave inputs This has the effect of attenuating the signal For example if the line frequency is 60 Hz the signal at the output of LPF1 will be attenuated by 3 1 H f 0 974 0 2 dBs 2 1 60 Hz 260 Hz 0 0 60Hz 0 2dB 20 10 5 60Hz 13 amp 5 40 20 9 2 5 n 60 30 80 40 101 102 103 FREQUENCY Hz Figure 13 Magnitude and Phase Response of LPF1 12 Note that LPF1 does not affect the power calculation because it is used only in the waveform sample mode and rms calculation In waveform sample mode on
13. Peak Detection Bits 2 and 3 of the measurement mode register define the phase supporting the peak detection Current and voltage of this phase can be monitored at the same time Figure 17 shows a line voltage exceeding a threshold set in the voltage peak register VPEAK 7 0 The voltage peak event is recorded by setting the PKV flag in the interrupt status register If the PKV enable bit is set to Logic 1 in the interrupt enable register the IRQ logic output goes active low See the Interrupts section Peak Level Set The contents of the VPEAK and IPEAK registers compare to the absolute value of the most significant byte output of the selected voltage and current channels respectively Thus for example the nominal maximum code from the current channel ADC with full scale signal is 28662 2 the Current Channel Sampling section Th refor Wriung 28h to the IPEAK register will put the current channel peak detection level at full scale and set the current peak detection to its least sensi tive value Writing 00h puts the current channel detection level at zero The detection is done when the content of the IPEAK register is smaller than the incoming current channel sample TEMPERATURE MEASUREMENT The ADE7754 also includes an on chip temperature sensor A temperature measurement is made every 4 CLKIN seconds The output from the temperature sensing circuit is connected to an ADC for digitizing The resulting code is processe
14. Performance Characteristics ADE7754 0 50 WYE CONNECTION GAIN 1 1 INTERNAL REFERENCE 0 40 0 30 PHASEB 0 20 0 10 0 00 PHASE C 0 10 0 20 0 30 0 40 0 50 0 01 0 1 1 10 CURRENT fs 100 TPC 1 Real Power Error as a Percentage of Reading with Gain 1 and Internal Reference WYE Connection 0 50 DELTA CONNECTION GAIN 1 PF 0 5 INTERNAL REFERENCE 0 40 0 30 0 20 0 10 0 00 0 10 0 20 0 30 0 40 0 50 0 01 0 1 1 10 CURRENT fs 100 TPC 2 Real Power Error as a Percentage of Reading over Power Factor with Internal Reference DELTA Connection 1 00 GAIN 1 0 5 0 80 INTERNAL REFERENCE 0 60 85 C PF 0 5 0 40 25 C PF 0 5 0 20 0 00 j a 0 20 25 C PF 1 0 0 40 ry 0 60 0 80 1 00 0 01 0 1 1 10 CURRENT fs 100 TPC 3 Real Power Error as a Percentage of Reading over Power Factor with Internal Reference 1 0 PERCENT ERROR PERCENT ERROR PERCENT ERROR 1
15. Register This register defines the general configuration of the ADE7754 See Table IX OBh MMODE RW 8 70h Measurement Mode Register This register defines the channel used for period and peak detection measurements See Table XII OCh WAVMODE RAW 8 0 Waveform mode register This register defines the channel and sampling frequency used in waveform sampling mode See Table XIII 0Dh WATMODE R W 8 3Fh This register configures the formula applied for the active energy and line active energy measurements See Table XIV OEh VAMODE R W 8 3Fh This register configures the formula applied for the apparent energy and line apparent energy measurements See Table XV OFh IRQEN RAW 16 0 IRQ Enable Register It determines whether an interrupt event will generate an active low output at IRQ pin See Table XVI 10h STATUS R 16 0 IRQ Status Register This register contains information regarding the source of ADE7754 interrupts See Table XVII lih RSTATUS R 16 0 Same as the status register except that its contents are reset to O all flags cleared after a read operation 12h ZXTOUT RW 16 FFFFh Zero Cross Timeout Register If no zero crossing is detected within a time period specified by this register the interrupt request line IRQ will go active low for the corresponding line voltage The maximum timeout period is 2 3 seconds See the Zero Crossing Detection section 32 REV 0 7754 Table VIII Register List continued
16. apparent power infor mation the ADE7754 provides system calibration features for each phase i e channel offset correction phase calibration and gain calibration The CF logic output provides instanta neous active power information The ADE7754 has a waveform sample register that enables access to ADC outputs The part also incorporates a detection circuit for short duration low or high voltage variations The voltage threshold levels and the duration number of half line cycles of the variation are user programmable zero crossing detection is synchronized with the zero crossing point of the line voltage of each of the three phases The infor mation collected is used to measure each line s period It is also used internally to the chip in the line active energy and line apparent energy accumulation modes This permits faster and more accurate calibration of the power calculations This signal is also useful for synchronization of relay switching Data is read from the ADE7754 via the SPI serial interface The interrupt request output IRQ is an open drain active low logic output The IRQ output goes active low when one or more interrupt events h ye the ADE7754 A status regis ter ndicates the nature of ghe The ADE7754 is available in a 24 lead SOIC package FUNCTIONAL BLOCK DIAGRAM AAPGAIN
17. frequencies where it can be removed by the digital low pass filter This noise shaping is shown in Figure 8 ANTIALIAS FILTER RC DIGITAL FILTER SAMPLING SHAPED FREQUENCY SIGNAL NOISE x NOISE 4 0 2 417 833 FREQUENCY kHz SIGNAL HIGH RESOLUTION OUTPUT FROM DIGITAL 14 foise FREQUENCY kHz Figure 8 Noise Reduction Due to Oversampling and Noise Shaping in the Analog Modulator Antialias Filter Figure 7 shows an analog low pass filter RC on the input to the modulator This filter is used to prevent aliasing an artifact of all sampled systems Frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC appear in the sampled signal at a frequency below half the sampling rate Figure 9 illustrates the effect frequency com ponents arrows shown in black above half the sampling frequency also known as the Nyquist frequency i e 417 kHz get imaged or folded back down below 417 kHz arrows shown in gray This happens with all ADCs regardless of the archi tecture In the example shown only frequencies near the sampling frequency i e 833 kHz will move into the band of interest for metering i e 40 Hz to 2 kHz This allows use of a very simple LPF low pass filter to attenuate these high frequencies near 900 kHz and thus prevent distortion in the band of interest A simple RC filter single pole with a corner frequency of 10 kHz produces an attenuat
18. is set to Logic 1 The regular sum is done when this bit is set to Logic 0 default mode 3 NOLOAD The active energy of each phase is not accumulated in the total active energy registers if the instantaneous active power is lower than the no load threshold when this bit is set to Logic 0 this mode is selected by default 4 RESERVED This is intended for factory testing only and should be left at 0 5 6 PGA2 0 These bits are used to select the gain of the voltage channels inputs Bit 6 Bit 5 0 0 PGA2 1 0 1 PGA2 2 1 0 PGA2 4 0 M Reserved 7 RESERVED TAK is intended forfactory testing only and should belleft at 0 CFNUM Register 25h The CF scaling numerator and the sign of the active energy per phase are defined by writing reading to the CFNUM register Table XI summarizes the functionality of each bit in the CFNUM register Table XI CFNUM Register Bit Bit Default Location Mnemonic Value Description 0 Bh 0 CF Scaling Numerator Register The content of this register is used in the numerator of CF output scaling Ch NEGA 0 The sign of the Phase A instantaneous active power is available in this bit Logic 0 and Logic 1 correspond to positive and negative active power respectively The functionality of this bit is enabled by setting Bit 5 of the WATMode register to Logic 1 When disabled NEGA is equal to its default value Dh NEGB 0 The sign of the Phase B instantaneous active power is av
19. is used in R W R W R W R 29h Alrms 24 0 Phase A Current Channel RMS Register The register contains the rms component of one input of the current channel The source is selected by data bits in the mode register 2Ah R 24 0 Phase B Current Channel RMS Register 2Bh CIrms R 24 0 Phase C Current Channel RMS Register 2Ch AVrms R 24 0 Phase A Voltage Channel RMS Register 2Dh BVrms R 24 0 Phase B Voltage Channel RMS Register 2Eh CVrms R 24 0 Phase C Voltage Channel RMS Register 2Fh AIrmsOS RW 12 0 Phase A Current RMS Offset Correction Register 30h BIrmsOS R W 12 0 Phase B Current RMS Offset Correction Register REV 0 33 ADE7794 Table VIII Register List continued Address Default 45 40 Name R W Length Value Description 31h CIrmsOS RAW 12 0 Phase C Current RMS Offset Correction Register 32h AVrmsOS RW 12 0 Phase A Voltage RMS Offset Correction Register 33h BVrmsOS RW 12 0 Phase B Voltage RMS Offset Correction Register 34h CVrmsOS RW 12 0 Phase C Voltage RMS Offset Correction Register 35h AAPGAIN R W 12 0 Phase A Active Power Gain Adjust The active power accumulation of the Phase A can be calibrated by writing to this register The calibration range is 50 of the nominal full scale of the active power The resolution of the gain is 0 0244 LSB See the Current Channel ADC Gain Adjust section 36h BAPGAIN RW 12 0 Phase B Active Power Gain Adjust 37h CAPGAIN RW 12 0 Phase C Acti
20. of the HPF and Phase Compensation 40 Hz to 70 Hz 0 010 0 008 0 006 0 004 0 002 PHASE Degrees 48 50 52 54 56 FREQUENCY Hz 44 46 Figure 18c Gain Response of HPF and Phase Com pensation Deviation of Gain as of Gain at 54 Hz Despite being internally phase compensated the ADE7754 must work with transducers that may have inherent phase errors For example a phase error of 0 1 to 0 3 is not uncommon for a CT current transformer These phase errors can vary from part to part and they must be corrected in order to perform accurate power calculations The errors associated with phase mismatch REV 0 7754 are particularly noticeable at low power factors The ADE7754 provides a means of digitally calibrating these small phase errors The ADE7754 allows a small time delay or time advance to be introduced into the signal processing chain to compensate for small phase errors Because the compensation is in time this technique should be used only for small phase errors in the range of 0 1 to 0 5 Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics The phase calibration registers APHCAL BPHCAL and are twos complement 5 bit signed registers that can vary the time delay in the voltage channel signal path from 19 2 us to 19 2 us CLKIN 10 MHz One LSB is equiva lent to 1 2 us Wit
21. set Bit 3 Bit 2 Source 0 0 Phase A 0 1 Phase B 1 0 Phase 1 1 Reserved 4 6 ZXSEL 7 These bits select the phases used for counting the number of zero crossing in the line active and apparent accumulation modes as well as enabling these phases for the zero crossing timeout detection zero crossing period measurement and SAG detection Bits 4 5 and 6 select Phase As Phase and Phase C respectively a 7 Reserved Waveform Mode Register 0Ch The waveform sampling mode of the ADE7754 is defined by writing to the WAVMODE register Table XIII summarizes the func tionality of each bit in the WAVMODE register Table XIII WAVMODE Register Bit Bit Default Location Mnemonic Value Description 0 2 WAVSEL 0 These bits are used to select the source of the waveform sample Bit 2 Bit 1 Bit 0 Source 0 0 0 Voltage Phase A 0 0 1 Voltage Phase B 0 1 0 Voltage Phase C 0 1 1 Current Phase 1 0 0 Current Phase B 1 0 1 Current Phase C 1 1 1 Reserved 3 4 DTRT 0 These bits are used to select the waveform sampling update rate Bit 4 Bit 3 Update Rate 0 0 26 0 kSPS CLKIN 3 128 0 1 13 0 kSPS CLKIN 3 256 1 0 6 5 kSPS CLKIN 3 512 1 1 3 3 kSPS CLKIN 3 1024 5 LVARSEL 0 This bit is used to enable the accumulation of the line VAR energy into the LAENERGY register and of the line active energy into the LVAENERGY register REV 0 37 ADE7794 Watt Mode Register 0Dh The phases involved i
22. the serial bus in a high impedance state The CS logic input may be tied low if the ADE7754 is the only device on the serial bus However with CS tied low all initiated data transfer operations must be fully completed i e the LSB of each register must be transferred because there is no other way to bring the ADE7754 back into communications mode without resetting the entire device 1 setting the RESET pin logic low All the ADE7754 functionality is accessible via several on chip registers See Figure 41 The contents of these registers can be updated or read using the on chip serial interface After power on or toggling the RESET pin low or a falling edge on CS the ADE7754 is placed into communications mode In communica tions mode the ADE7754 expects the first commitnidation o be a write to the internal commiunidations register The data written to the communications register contains th addfess and specifies the next data transfer to be a read or a write command Therefore all data transfer operations with the ADE7754 whether read or write types must begin with a write to the communications register COMMUNICATIONS REGISTER REGISTER ADDRESS DECODE Figure 41 Addressing ADE7754 Registers via the Communications Register The communications register is an 8 bit write only register The MSB determines whether the next data transfer operation is read or a write The six LSBs contain the address of the reg
23. the voltage and current waveforms when one of this signals is phase shifted by 90 at each frequency It is defined mathematically in the IEEE Standards Dictionary 100 as o Reactive Power 2 V XI sin where V and I are the voltage and current rms values of the n harmonics of the line frequency respectively and is the phase difference between the voltage and current nth harmon ics The resulting waveform is called the instantaneous reactive power signal VAR Equation 19 gives an expression for the instantaneous reactive power signal in an ac system without harmonics when the phase of the current channel is shifted by 909 v t 2 sin ot 17 2 I sin or i 0 2 1 sin or 2 m 18 VAR t v t x i 2 V Is sin pK sin 20t 19 The av rag power oyer an n number of line cycles n is given in Equation 20 nT VAR J VAR t dt VI sin 20 nT where T is the line cycle period VAR is referred to as the reactive power Note that the reactive power is equal to the dc component of the instantaneous reactive power signal VAR t in Equation 19 This is the relationship used to calculate reactive power in the ADE7754 for each phase The instantaneous reactive power signal VAR t is generated by multiplying the current and voltage signals in each phase In this case the phase of the current channel is shifted by 89 The dc component of the i
24. 13 10 65 0 4193 1 12 10 00 0 3937 2 65 0 1043 Ke 0 75 0 0295 2 35 0 0925 0 25 0 0098 25 0 0098 gt 0 30 0 0118 0 10 0 0039 je gt 8 gt 1 27 0 0500 0 51 0 020 SEATING 2 1 27 0 0500 COPLANARITY BSC 0 33 0 013 PLANE Tm dua 0 33 0 013 0 23 0 0091 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN VW D AL REV 0 41 7754 ww conh ww conh ww conh
25. 4 us 4 CLKIN With full scale sinusoidal signals ongthe analog inputs and the watt gain registers set to 000 he eae word value from each LPE2is1B7 17h See Figur s 22 and 24 The maximum value that can be stored in the active energy register before it overflows is 223 1 or 7F FFFFh As the average word value is added to the internal register which can store 273 1 or 1F FFFF FFFF FFFFh before it overflows the integration time under these conditions with WDIV 0 is calculated as follows lF FFFF FFFF FFFFh 3 3x DIB717h When WDIV is set to a value different from 0 the integration time varies as shown in Equation 10 Time Time ypy XWDIV 10 Time x0 4 Us 88 s The WDIV register can be used to increase the time before the active energy register overflows thereby reducing the communi cation needs with the ADE7754 Energy to Frequency Conversion The ADE7754 also provides energy to frequency conversion for calibration purposes After initial calibration at manufac ture the manufacturer or the customer will often verify the energy meter calibration One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency proportional to the energy or active power under steady load conditions This output frequency can provide a simple single wire optically isolated interface to external cali bration equipment Figure 29 illustrates the energy to frequency conversion in the ADE7754
26. 7754 Figure 35 shows the maximum code hexadecimal output range of the apparent power signal for each phase Note that the output range changes depending on the contents of the apparent power gain registers and also on the contents of the active power gain REV 0 ADE7754 and voltage gain registers See the Current RMS Calculation and Voltage RMS Calculation sections Only the effect of the apparent power gain is shown on Figure 35 The minimum output range is given when the apparent power gain register content is equal to 800h and the maximum range is given by writing 7FFh to the apparent power gain register This can be used to calibrate the apparent power or energy calculation in the ADE7754 for each phase and the total apparent energy See the Total Apparent Power Calculation section APPARENT POWER VOLTAGE CHANNEL AND CURRENT CHANNEL 0 5V GAIN 150 FS 100 FS 50 FS 13A929h D1B71h 68DB9h 00000h AVAGAIN 11 0 F97247h 50 FS F2E48Fh 100 FS EC56D7h 150 FS Figure 35 Apparent Power Calculation Output Range Apparent Power Offset Calibration Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value See the Current RMS Calculation and Voltage RMS Calculation sections The voltage and current rms values are then multiplied in the apparent power signal processing Because no additional offsets are created in the multipli
27. 8Ch 1 CURRENT SIGNAL i t CURRENT CHANNEL rms 400000h 28F5C2h 2378EDh 122 5 FS 1CF68Ch 100 FS 00000h 147AE0h 70 7 FS 0000h AAPGAIN 11 0 D70A3Eh EB852Fh 70 7 FS C00000h 100 FS 122 5 FS E30974h DC8713h ADC OUTPUT WORD RANGE Figure 20 Current RMS Signal Processing Note that a crosstalk between phases can appear in the ADE7754 current rms measurements This crosstalk follows a specific 15 ADE7794 pattern Current rms measurements of Phase A are corrupted by the signal on the Phase C current input current rms measure ments of Phase B are corrupted by the signal on the Phase A current input and current rms measurements of Phase C are corrupted by the signal on the Phase B current input This crosstalk is present only on the current rms measurements and does not affect the regular active power measurements The level of the crosstalk is dependent on the level of the noise source and the phase angle between the noise source and the corrupted signal The level of the crosstalk can be reduced by writing 01F7h to the address 3Dh This 16 bit register is reserved for factory operation and should not be written to any other value When the current inputs are 120 out of phase and the register 3Dh is set to 7 the level of the current rms crosstalk is below 296 Current RMS Gain Adjust The active power gain registers AAPGAIN 11 0 BAPG
28. AIN and CAPGAIN affect the active power and current rms values Calibrating the current rms measurements with these registers is not recommended The conversion of the current rms registers values to amperes has to be done in an external microcontroller with a specific ampere LSB constant for each phase See the Cali bration of a 3 Phase Meter Based on the ADE7754 Application Note AN 624 Due to gain mismatches between phases the cali bration of the ampere LSB constant has to be done separately for each phase One point calibration is sufficient for this calibration The active power gain registers ease the calibration of the active energy calculation in MODE 1 and 2 of the WATMODE register If the APGAIN registers are p wet calibration WATMOD bits in WATMod registet amp 2 the current rms values are changed by the active power gain register value as described in the expression Current rms register Phase A 11 For example when 7FFh is written to the active power gain register the ADC output is scaled up by 22 5 Similarly 800h 2047d signed twos complement and ADC output is scaled by 29 3 These two examples are illustrated in Figure 20 Current RMS Offset Compensation The ADE7754 incorporates a current rms offset compensation for each phase AIRMSOS BIRMSOS and CIRMSOS These are 12 bit twos complement signed registers that can be used to remove offsets in the current rms calcula
29. ANALOG DEVICES Polyphase Multifunction Energy Metering IC with Serial Port ADE7754 FEATURES High Accuracy Supports IEC 687 61036 Compatible with 3 Phase 3 Wire 3 Phase 4 Wire and any Type of 3 Phase Services Less than 0 1 Error in Active Power Measurement over a Dynamic Range of 1000 to 1 Supplies Active Energy Apparent Energy Voltage RMS Current RMS and Sampled Waveform Data Digital Power Phase and Input Offset Calibration On Chip Temperature Sensor 4 C Typical after Calibration On Chip User Programmable Thresholds for Line Voltage SAG and Overdrive Detections SPI Compatible Serial Interface with Interrupt Request Line IRQ Pulse Output with Programmable Frequency Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time Single 5 V Supply GENERAL DESCRIPTION The ADE7754 is a high accuracy polyphase electrical energy measurement IC with a serial interface and a pulse output The ADE7754 incorporates second order ADCs reference circuitry temperature sensor and all the sigmalyprecessing required to perform active energy Measurements and rms calculation The ADE7754 provides different solutions for measuring active and apparent energy from the six analog inputs thus enabling the use of the ADE7754 in various power meter services such as 3 phase 4 wire 3 phase 3 wire and 4 wire delta In addition to rms calculation active and
30. MCU services the interrupt it must first carry out a read from the interrupt sta tus register to determine the source of the interrupt All the interrupts in the interrupt status register stay at their logic high state after an event occurs The state of the interrupt bit in the interrupt status register is reset to its default value once the reset interrupt status register is read Table XVII STATUS Register Bit Interrupt Default Event Location Flag Value Description 0 AEHF 0 Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the AENERGY register 1 the AENERGY register is half full 1 SAGA 0 Indicates that an interrupt was caused by a SAG on the line voltage of the Phase A 2 SAGB 0 Indicates that an interrupt was caused by a SAG on the line voltage of the Phase B 3 SAGC 0 Indicates that an interrupt was caused by a SAG on the line voltage of the Phase C 4 ZXTOA 0 Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase A 5 ZXTOB 0 Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase B 6 ZXTOC 0 Indicates that an interrupt was caused by a missing zero crossing on the line voltage of the Phase C 7 ZXA 0 Indicates a detection of rising zero crossing in the voltage channel of the Phase A 8 ZXB 0 Indicates a detection of rising zero crossing in the voltage channel of the Phase B 9 ZXC 0 Indicates a det
31. Q logic output goes active low if the enable bit for this event is Logic 1 in this register The IRQ logic output is reset to its default collector open state when the RSTATUS register is read Table XVI describes the function of each bit in the interrupt enable register Table XVI IRQEN Register Bit Interrupt Default Location Flag Value Description 0 AEHF 0 Enables an interrupt when there is a 0 to 1 transition of the MSB of the AENERGY register i e the AENERGY register is half full 1 SAGA 0 Enables an interrupt when there is a SAG on the line voltage of the Phase A 2 SAGB 0 Enables an interrupt when there is a SAG on the line voltage of the Phase B 3 SAGC 0 Enables an interrupt when there is a SAG on the line voltage of the Phase C 4 ZXTOA 0 Enables an interrupt when there is a zero crossing timeout detection on Phase A 5 ZXTOB 0 Enables an interrupt when there is a zero crossing timeout detection on Phase B 6 ZXTOC 0 Enables an interrupt when there is a zero crossing timeout detection on Phase C 7 ZXA 0 Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase A Zero crossing detection 8 ZXB 0 Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase B Zero crossing detection 9 ZXC 0 Enables an interrupt when there is a rising zero crossing in voltage channel of the Phase C Zero crossing detection Ah LENERGY 0 Enables an inte
32. TSEL bits are also used to select the terms of the LVAENERGY register The different configurations are described in Table III The accumulation of the reactive power in the LAENERGY register is different from the accumulation of the active power in the LAENERGY register Under the same signal conditions e g current and voltage channels at full scale and if the accu mulation of the active power with PF 1 over one second is Wh and the accumulation of the reactive power with PF 0 during that time is VARh then Why 9 546 VAR Note that I4 Ig and Ic represent V Surrent chann ls samples after APGAIN correction high pass filtering and 89 phase shift in the case of reactive energy accumulation Reactive Energy Accumulation Selection The ADE7754 accumulates the total reactive power signal in the LAENERGY register for an integer number of half cycles as shown in Figure 31 This mode is selected by setting Bit 5 of the WAVMode register Address 0Ch to Logic 1 When this bit is set the accumulation of the active energy over half line cycles in the LAENERGY register is disabled and done instead in the LVAENERGY register In this mode the accumulation of the apparent energy over half line cycles in the LVAENERGY is no longer available See Figure 33 ACTIVE POWER 0 REACTIVE POWER 1 REACTIVE POWER APPARENT POWER LAENERGY REGISTER LVAENERGY REGISTER BIT 5 WAVMODE REGISTER Figure 33 Selecti
33. V STA ofthe arefdefined by Wfiting to the V MODE register Table XV summarizes the functionality ofteach bit in the VAMODE register N Table XV VAMODE Register Bit Bit Default Location Mnemonic Value Description 0 2 LVASEL 7 These bits are used to select each part of the formula separately depending on the line appar ent energy measurement method The behavior of these bits is the same as VASEL bits Bit 2 selects the first term of the formula and so on 3 5 VASEL 7 These bits are used to select separately each part of the formula depending on the apparent energy measurement method Setting Bit 5 to Logic 1 selects the first term of the formula us X Setting Bit 4 to Logic 1 selects the second term of the formula VB X Bans VA ms VC ms 2 X or X depending on VAMOD configuration Setting Bit 3 to Logic 1 selects the first term of the formula VC ms X 1 Any combination of these bits can address calibration and operational needs 6 7 VAMOD 0 These bits are used to select the formula used for active energy calculation VAMODI VAMODO Apparent Energy Calculation 0 0 VArms X X IB ms X 1 0 1 VArms X WArms WCrms 2 X Bins X 1 1 0 VArms X WArms X Bins X IOS 1 1 Reserved 38 REV 0 7754 Interrupt Enable Register 0Fh When an interrupt event occurs in the ADE7754 the IR
34. ailable in this bit Logic 0 and Logic 1 correspond to positive and negative active power respectively The functionality of this bit is enabled by setting Bit 4 of the WATMode register to Logic 1 When disabled NEGB is equal to its default value Eh NEGC 0 sign of the Phase C instantaneous active power is available in this bit Logic 0 and Logic 1 correspond to positive and negative active power respectively The functionality of this bit is enabled by setting Bit 3 of the WATMode register to Logic 1 When disabled NEGC is equal its default value Fh RESERVED 36 REV 0 ADE7754 Measurement Mode Register 0Bh The configuration of the period and peak measurements made by the ADE7754 are defined by writing to the MMODE register Table XII summarizes the functionality of each bit in the MMODE register Table XII MMODE Register Bit Bit Default Location Mnemonic Value Description 0 1 PERDSEL 0 These bits are used to select the source of the measurement of the voltage line period Bit 1 Bit 0 Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved 2 3 PEAKSEL 0 These bits select the line voltage and current phase used for the PEAK detection If the selected line voltage is above the level defined in the PKVLVL register the flag in the interrupt status register is set If the selected current input is above the level defined in the PKILVL register the PKI flag in the interrupt status register is
35. brating the voltage rms measurements with these registers is not recommended The conversion of the voltage rms registers values to volts has to be done in an external microcontroller with a specific volt LSB constant for each phase See the Cali bration of a 3 Phase Meter Based on the ADE7754 Application Note AN 624 Due to gain mismatches between phases the cali bration of the volt LSB constant has to be done separately for each phase One point calibration is sufficient for this calibration voltage gain registers are aimed to ease the calibration of the apparent energy calculation in MODE 1 and MODE 2 of the VAMODE register REV 0 7754 If the VGAIN registers are used for apparent power calibration WATMOD bits in VAMODE register 1 2 the voltage rms values are changed by voltage gain register value as described in the expression Voltage rms register Phase A 212 For example when 7FFh is written to the voltage gain register the ADC output is scaled up by 50 7FFh 2047d 2047 212 0 5 Similarly 800h 2047d signed twos complement and ADC output is scaled by 50 These two examples illustrated in Figure 21 Voltage RMS Offset Compensation The ADE7754 incorporates a voltage rms offset compensation for each phase AVRMSOS BVRMSOS and CVRMSOS These are 12 bit twos complement signed registers that can be used to remove offsets in the voltage rms calculations An offset ma
36. cation of the rms values there is no specific offset compensation in the apparent power signal processing The offset compensation of the apparent pewer measurement in each phas Y AY by calibrating each indi vidual rms measurement TOTAL APPARENT POWER CALCULATION The sum of the apparent powers coming from each phase gives the total apparent power consumption Different combinations of the three phases can be selected in the sum by setting Bits 7 and 6 of the VAMode register mnemonic 1 0 Figure 36 demonstrates the calculation of the total apparent power PHASE VA PHASE B 29 TOTAL APPARENT POWER SIGNAL Vc Figure 36 Total Apparent Power Calculation REV 0 The total apparent power calculated by the ADE7754 depends on the configuration of the VAMOD bits in the VAMode register Each term of the formula used can be disabled or enabled by the setting VASEL bits respectively to Logic 0 or Logic 1 in the register The different configurations are described in Table IV Table IV Total Apparent Power Calculation VAMOD VASELO VASEL1 VASEL2 0d 5 X emus Vcnus X 5 X Varms Vcnus 2 X Vcnus X Icras 2d 5 X Vcnus X Icrms Note that Varms lanus and represent the voltag
37. complement 12 bit word to the active power gain register The following expression shows how the gain adjustment is related to the contents of that register Note that if the WSMP bit in the interrupt enable register is not set to Logic 1 no data is available in the waveform register Code x CURRENT RMS CALCULATION x1 x2 x4 WAVEFORM SAMPLE lap GAIN 1 0 MULTIPLIER DIGITAL LPF REGISTER 1 ACTIVE AND REACTIVE IN HPF POWER CALCULATION CHANNEL 1 800h 7FFh 100 FS AAPGAIN 11 0 3D70A3h 150 FS 0 5V GAIN1 28F5C2h 100 FS ov 400000h 147AE1h 50 FS 28F5C2h 100 FS 00000h AAPGAIN 11 0 EB851Fh 50 FS ANALOG 000000h D70A3Eh 100 FS INPUT RANGE C28F5Dh 150 FS D70A3Eh 100 FS CO0000h ADC OUTPUT WORD RANGE Figure 10 ADC and Signal Processing in Current Channel REV 0 11 ADE7794 VOLTAGE CHANNEL ADC Figure 12 shows the ADC and signal processing chain for the input V in voltage channel which is the same for VB and VC x1 x2 x4 _ GAIN 6 5 1 100 TO 100 FS TO ACTIVE AND val gt lt REACTIVE ENERGY O CALCULATION TO VOLTAGE RMS AND WAVEFORM SAMPLING VN VA 0 5V LPF OUTPUT WORD RANGE GAIN 60 2 27E9h D817h Y A ANALOG 2838h INPUT RANGE 50Hz D7C8h Y Figure 12 ADC and Signal Processing in Voltage Channel For energy measurements the output of the
38. d or startup current feature that eliminates any creep effects in the active energy measurement of the meter When enabled this function is independently applied on each phase s active power calculation This mode is selected by default and can be disabled 21 ADE7794 by setting to Logic 1 Bit 3 of the gain register Address 18h See Table X Any load generating an active power amplitude lower than the minimum amplitude specified will not be taken into account when accumulating the active power from this phase minimum instantaneous active power allowed in this mode is 0 005 of the full scale amplitude Because the maximum active power value is 13 743 895d with full scale analog input the no load threshold is 687d For example an energy meter with maximum inputs of 220 V and 40 A and Ib 10 A the maximum instantaneous active power is 3 435 974d assuming that both inputs represent half of the analog input full scale As the no load threshold represents 687d the start up current represents 8 mA or 0 08 of Ib Mode Selection of the Sum of the Three Active Energies The ADE7754 can be configured to execute the arithmetic sum of the three active energies Wh Why or the sum of the absolute value of these energies Wh Whac The selection between the two modes can be made by setting Bit 2 of the gain register Address 18h See Table X Logic high and logic low of this bit correspo
39. d and placed into the temperature register TEMP 7 0 which can be read by the user and has an address of 08h See the Serial Interface section The contents of the temperature register are signed twos complement with a resolution of 4 C LSB The temperature register produces a code of 00h when the ambient temperature is approximately 129 C The value of the register is temperature register temperature 129 4 The tempera ture in the ADE7754 has an offset tolerance of approximately 5 C The error can be easily calibrated out by an MCU PHASE COMPENSATION When the HPFs are disabled the phase difference between the current channel IA IB and IC and the voltage channel VA VB and VC is zero from dc to 3 3 kHz When the HPFs are enabled the current channels have a phase response as shown in Figure 18a and 18b The magnitude response of the filter is shown in Figure 18c As seen from in the plots the phase response is almost zero from 45 Hz to 1 kHz This is all that is required in typical energy measurement applications 14 0 05 0 04 PHASE Degrees 0 anh 100 200 300 400 500 600 700 800 900 1k FREQUENCY Hz Figure 18a Phase Response of the HPF and Phase Compensation 10 Hz to 1 kHz 0 010 0 008 0 006 0 004 0 002 PHASE Degrees 40 45 50 55 60 65 70 FREQUENCY Hz Figure 18b Phase Response
40. e DOUT logic output enters a high impedance state on the falling edge of the last SCLK pulse The read operation may be aborted by bringing the CS logic input high before the data transfer is com pleted The DOUT output enters a high impedance state on the rising edge of CS When an ADE7754 register is addressed for a read operation the entire contentg of that register are transferred to the serial pott This allows the DM modify its on chip registers without the risk Of corrupting ata during a multibyte transfer Note that when a read operation follows a write operation the read command i e write to communications register should not happen for at least 1 us after the end of the write operation If the read command is sent within 1 us of the write operation the last byte of the write operation may be lost 020208 MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE Figure 46 Serial Interface Read Timing Diagram REV 0 29 ADE7794 INTERRUPTS ADE7754 interrupts are managed through the interrupt status register STATUS 15 0 Address 10h and the interrupt enable register IRQEN 15 0 Address OFh When an interrupt event occurs in the ADE7754 the corresponding flag in the interrupt status register is set to Logic 1 See the Interrupt Status Register section If the enable bit for this interrupt in the interrupt enable register is Logic 1 then the IRQ logic output goes active low The flag bits in the interrupt status r
41. e and current channels RMS values ofthe corresponding registers For example for VAMOD 1 the formula used to process the apparent power is UM Total Apparent Power V X Larus X 2 osse BVAG ARMS CRMS x 1 X 1 55 2 5 X 5 Xu Pug a The polyphase meter coni ftd ion determines which formula should be used to calculate the apparent energy The American ANSI C12 10 standard defines the different configurations of the meter Table V describes which mode should be chosen for different configurations Table V Meter Form Configuration ANSI Meter Form VAMOD VASEL 58 138 3 wire Delta 0 3 or 5 or 6 6S 14S 4 wire Wye 1 7 8S 15S 4 wire Delta 2 7 9S 16S 4 wire Wye 0 7 Different gain calibration parameters are offered in the ADE7754 to cover the calibration of the meter in different configurations The APGAIN VGAIN and VAGAIN registers have different purposes in the signal processing of the ADE7754 APGAIN registers affect the apparent power calculation but should be used only for active power calibration VAGAIN registers are used to calibrate the apparent power calculation VGAIN regis ters have the same effect as VAGAIN registers when VAMOD 0 or 2 They should be left at their default value in these modes VGAIN registers should be used to compensate gain mismatches between channels in VAMOD 1 As mentioned previously the offset compensation
42. e of four output sample rates can be chosen by using Bits 3 and 4 of the WAVMODE regis ter The available output sample rates are 26 kSPS 13 5 kSPS 6 5 kSPS or 3 3 kSPS The interrupt request output IRQ signals a new sample availability by going active low The voltage waveform register is a twos complement 16 bit register Because the waveform register is a 24 bit signed register the waveform data from the voltage input is located in the 16 LSB of the waveform register The sign of the 16 bit voltage input value is not extended to the upper byte of the waveform register The upper byte is instead filled with zeros 24 bit waveform samples are transferred from the ADE7754 one byte eight bits at a time with the most significant byte shifted out first The timing is the same as that for the current channels and is shown in Figure 11 ZERO CROSSING DETECTION The ADE7754 has rising edge zero crossing detection circuits for each of voltage channels Vap and Vcp Figure 14 shows how the zero cross signal is generated from the output of the ADC of the voltage channel x1 x2 x4 GAIN 6 5 TO MULTIPLIER 1 100 TO 100 FS ZERO CROSSING DETECTION READ RSTATUS Figure 14 Zero Crossing Detection on Voltage Channel The zero crossing interrupt is generated from the output of LPFI which has a single pole at 260 Hz CLKIN 10 MHz As a result there is a phase lag between the analog inp
43. e would be ignored and the four LSBs of the first byte written to the ADE7754 would be the four MSBs of the 12 bit word Figure 45 illustrates this example REV 0 7754 SCLK DIN COMMAND BYTE ts DBO MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE Figure 44 Serial Interface Write Timing Diagram E322 CO CORCA CO C2 G2 C2 C2 CD MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE Figure 45 12 Bit Serial Write Operation Serial Read Operation During a data read operation from the ADE7754 data is shifted out at the DOUT logic output on the rising edge of SCLK As was the case with the data write operation a data read must be preceded by a write to the communications register With the ADE7754 in communications mode and CS logic low an 8 bit write to the communications register first takes place The MSB of this byte transfer must be 0 ifidiedting next data transfer operations 4 rea The six LSBs of this byte contain the address of the register to be fead The XDE7754 starts shifting out of the register data on the next rising edge of SCLK See Figure 46 At this point the DOUT logic output switches from high impedance state and starts driving the data bus remaining bits of register data are shifted out on subsequent SCLK rising edges The serial interface enters communications SCLK DIN DOUT COMMAND BYTE mode again as soon as the read has been completed Th
44. ection of rising zero crossing in the voltage channel of the Phase C Ah LENERGY 0 In line energy accumulation it indicates the end of an integration over an integer number of half line cycles LINCYC See the Energy Calculation section Bh RESET 0 Indicates that the ADE7754 has been Ch PKV 0 Indicates that an Interrupt was CAused when the selected voltage input is above the value in the PKVLV register Dh PKI 0 Indicates that an interrupt was caused when the selected current input is above the value in the PKILV register Eh WFSM 0 Indicates that new data is present in the waveform register Fh VAEHF 0 Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the VAENERGY register 1 the VAENERGY register is half full INTERRUPT STATUS REGISTER F E D C B A 9 8 7 6 5 4 3 2 4 0 ADDR 10h VAEHF APPARENT ENERGY REGISTER HALF FULL ACTIVE ENERGY REGISTER HALF FULL WFSM SAG NEW WAVEFORM SAMPLE READY SAG EVENT DETECT PKI ZX CURRENT CHANNEL PEAK DETECTION ZERO CROSSING TIMEOUT DETECTION PKV ZX VOLTAGE CHANNEL PEAK DETECTION ZERO CROSSING DETECTION LENERGY END OF THE LAENERGY AND LVAENERGY ACCUMULATION REGISTER CONTENTS SHOW POWER ON DEFAULTS 40 REV 0 OUTLINE DIMENSIONS 24 Lead Standard Small Outline Package SOIC Wide Body RW 24 Dimensions shown in millimeters and inches 15 60 0 6142 15 20 0 5984 24 13 7 60 0 2992 7 40 0 29
45. ed to the checksum register In the end of the serial read operation the content of the checksum register will equal the sum of all ones in the register previously read Using the checksum regis ter the user can determine whether an error has occurred during the last read operation Note that a read to the checksum register also generates a checksum of the checksum register itself CONTENT OF REGISTER n BYTES DOUT CHECKSUM REGISTER ADDR 3Eh Figure 40 Checksum Register for Serial Interface Read ADE7794 SERIAL INTERFACE ADE7754 has a built in SPI interface The serial interface of the ADE7754 is made of four signals SCLK DIN DOUT and CS The serial clock for a data transfer is applied at the SCLK logic input which has a Schmidt trigger input structure that allows slow rising and falling clock edges to be used data transfer operations are synchronized to the serial clock Data is shifted into the ADE7754 at the DIN logic input on the falling edge of SCLK Data is shifted out of the ADE7754 at the DOUT logic output on a rising edge of SCLK The CS logic input is the chip select input This input is used when multiple devices share the serial bus A falling edge on CS also resets the serial interface and places the ADE7754 into communications mode The CS input should be driven low for the entire data transfer operation Bringing CS high during a data transfer operation will abort the transfer and place
46. ed in the ADE7754 a simple mathemati cal formula can be used to extract the reactive energy The evaluation of the sign of the reactive energy makes up the calcu lation of the reactive energy Reactive Energy sign Reactive Power x il Apparent Energy Active Energy APPARENT POWER CALCULATION Apparent power is defined as the maximum active power that can be delivered to a load and are the effective voltage current delivered t6 Y apparent power AP is defined as X Ims Note that the apparent power equal to the multiplication of the rms values of the voltage and current inputs For a polyphase system the rms values of the current and voltage inputs of each phase A B and C are multiplied to obtain the apparent power information of each phase The total apparent power is the sum of the apparent powers of all the phases The different solutions available to process the total apparent power are discussed below Figure 34 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7754 24 APPARENT POWER rms SIGNAL P CURRENT RMS SIGNAL i t 0 5V GAIN1 D1B71h 1CF68Ch 00h MULTIPLIER Vrms VOLTAGE RMS SIGNAL v t 0 5V GAIN2 1CF68Ch 00h Figure 34 Apparent Power Signal Processing The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE
47. egister are set irrespective of the state of the enable bits In order to determine the source of the interrupt the system master MCU should perform a read from the reset interrupt status register with reset This is achieved by carrying out a read from Address 11h The IRQ output goes logic high on completion of the interrupt status register read command See the Interrupt Timing section When carrying out a read with reset the ADE7754 is designed to ensure that no interrupt events are missed If an interrupt event Occurs just as the interrupt status register is being read the event will not be lost and the IRQ logic output is guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt Using Interrupts with an MCU The timing diagram in Figure 47 illustrates a suggested imple mentation of ADE7754 interrupt management using an MCU At time the IRQ line goes active low indicating that one or more interrupt events have occurred The IRQ logic output should be tied to a negative edge triggered external interrupt on the MCU On detection of the negative edge the MOU should GLOBAL INTERRUPT INTERRUPT MASK FLAG CLEAR MCU READ PROGRAM SEQUENCE STATUS WITH RESET 11h be configured to start executing its interrupt service routine ISR On entering the ISR all interrupts should be disabled using the global interrupt enable bit At t
48. er This mode is selected by setting to Logic 1 Bit 5 of the WAVMode register Address When this bit is set the accumulation of the active energy over half line cycles in the LAENERGY register is disabled and done instead in the LVAENERGY register In this mode the accu REV 0 and apparent enefgles Fhese mulation of the apparent energy over half line cycles in the LVAENERGY is no longer available See Figure 33 Since the LVAENERGY register is an unsigned value the accumulation of the active energy in the LVAENERGY register is unsigned In this mode reactive energy the selection of the phases accumulated in the LAENERGY and LVAENERGY registers is done by the LWATSEL selection bits of the WATMode register ENERGIES SCALING The XADEY 54 pr vides Measutements of the active reactive asurements do not have the same scaling and thus cannot be compared directly to each other Energy Type 1 0 707 PF 0 Active Wh Wh x 0 707 0 Reactive 0 Wh x 0 707 9 546 Wh 9 546 Apparent Wh 3 657 Wh 3 657 Wh 3 657 CHECK SUM REGISTER The ADE7754 has a checksum register CHECKSUM 5 0 to ensure that the data bits received in the last serial read operation are not corrupted The 6 bit checksum register is reset before the first bit MSB of the register to be read is put on the DOUT pin During a serial read operation when each data bit becomes available on the rising edge of SCLK the bit is add
49. esonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7754 The clock frequency for specified operation is 10 MHz Ceramic load capacitors of 22 pF to 33 pF should be used with the gate oscillator circuit Refer to the crystal manufacturer s data sheet for load capacitance requirements A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7754 The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or a crystal is used Chip Select Part of the 4 wire serial interface This active low logic input allows the ADE7754 to share the serial bus with several other devices See the Serial Interface section Data Input for the Serial Interface Data is shifted in at this pin on the falling edge of SCLK See the Serial Interface section Serial Clock Input for the Synchronous Serial Interface All serial data transfers are synchronized to this clock See the Serial Interface section The SCLK has a Schmidt trigger input for use with a clock source that has a slow edge transition time e g opto isolator outputs Data Output for the Serial Interface Data is shifted out at this pin on the rising edge of SCLK This logic output is normally in a high impedance state unless it is driving data onto the serial data bus See the Serial Interface section 6 REV 0 PERCENT ERROR PERCENT ERROR PERCENT ERROR REV Typical
50. f 100 to 1 I Measurement Bandwidth 14 kHz ANALOG INPUTS Maximum Signal Levels 500 mV peak max Differential input VAp Vx Vgp Vx Vcp Vx Input Impedance DC 370 min Bandwidth 3 dB 14 kHz typ ADC Offset Error 25 mV max Uncalibrated error See Terminology for details Gain Error t typ External 2 5 V reference Gain Error Match t typ External 2 5 V reference REFERENCE INPUT Input Voltage Range 2 6 V max 2 4 V 896 2 2 V min 2 4 V 896 Input Impedance 3 7 max Input Capacitance 10 pF TEMPERATURE SENSOR AE Calibrated ON CHIP REFERENCE Reference Error 200 mV max Temperature Coefficient 30 ppm C typ CLKIN Input Clock Frequency 10 MHz typ LOGIC INPUTS RESET DIN SCLK CLKIN and CS Input High Voltage Ving 2 4 V min DVpp 5 V 5 Input Low Voltage Vint 0 8 V max DVpp 5 V 5 Input Current In t3 pA max Typical 10 nA Vy 0 V to DVpp Input Capacitance Cr 10 pF max LOGIC OUTPUTS CF IRQ DOUT and CLKOUT Output High Voltage 4 V min DVpp 5 V 5 Output Low Voltage Vor 1 V max DVpp 5 Vt 5 POWER SUPPLY For specified performance AVpp 4 15 V min 5 V 5 5 25 V max 5 V 596 DVpp 4 15 V min 5 V 5 5 25 V max 5 V 5 Alpp 7 mA max At 5 25 V DIpp 18 mA max At 5 25 V NOTES 1 Terminology section for explanation of specifications See plots in the Typical Performance Characteristics section Spec
51. ge selection see the TPCs However when HPFs are switched on the offset is removed from the current channels and the power calculation is unaffected by this offset Gain Error The gain error in the ADE7754 ADCs is defined as the differ ence between the measured ADC output code minus the offset and the ideal output code See the Current Channel and the Voltage Channel ADC sections The difference is expressed as a percentage of the ideal code Gain Error Match Gain error match is defined as the gain error minus the offset obtained when switching between a gain of 1 2 or 4 It is expressed as a percentage of the output ADC code obtained under gain of 1 POWER SUPPLY MONITOR The ADE7754 contains an on chip power supply monitor The analog supply AVpp is continuously monitored by the ADE7754 If the supply is less than 4 V 5 the ADE7754 goes into an inactive state 1 no energy is accumulated when the supply voltage is below 4 V This is useful to ensure correct device operation at power up and during power down The power sup ply monitor has built in hysteresis and filtering providing a high degree of immunity to false triggering due to noisy supplies REV 0 mum differential voltdge tok ov TIME POWER ON NACTIVE INACTIVE EXC SEL A ACTIVE RESET FLAG IN THE INTERRUPT STATUS REGISTER READ RSTATUS REGISTER Figure 4 On Chip Power Supply Monitoring The RESET bit in the in
52. gister decrements to zero before a zero crossing at the corresponding input is detected it indicates an absence of a zero crossing in the time determined by the ZXTOUT The ZXTO detection bit of the corresponding phase in the interrupt status register is then switched on Bits 4 to 6 An active low on the IRQ output also appears if the SAG enable bit for the corresponding phase in the interrupt enable register is set to Logic 1 In addition to the enable bits the zero crossing timeout detec tion interrupt of each phase is enabled disabled by setting the ZXSEL bits of the MMODE register Address OBh to Logic 1 or Logic 0 respectively When the zero crossing timeout detection is disabled by this method the ZXTO flag of the corresponding phase is switched on all the time Figure 15 shows the mechanism of the zero crossing timeout detection when the line voltage A stays at a fixed dc level for more than CLKIN 384 X ZXTOUT seconds 16 BIT INTERNAL REGISTER VALUE ZXTOUT VOLTAGE CHANNEL A ZXTOA DETECTION BIT Figure 15 Zero Crossing Timeout Detection PERIOD MEASUREMENT The ADE7754 also provides the period measurement of the line voltage The period is measured on the phase specified by Bits 0 to 1 of the MMODE register The period register is an unsigned 15 bit register and is updated every period of the selected phase Bits 0 and 1 and Bits 4 to 6 ofthe MMODE register select the phase for the period measureme
53. gure 31 The line active energy accumulation mode is always active Using this mode with only one phase selected is recommended If several phases are selected the amount accumulated may be smaller than it should be Each one of three phases zero crossing detection can contribute to the accumulation of the half line cycles Phase A B and C Zero crossings respectively are taken into account when count ing the number of half line cycles by setting Bits 4 to 6 of the MMODE register to Logic 1 Selecting phases for the zero crossing counting also has the effect of enabling the zero cross ing detection zero crossing timeout and period measurement for the corresponding phase as described in the zero crossing detection paragraph The number of half line cycles is specified in the LINCYC register LINCYC is an unsigned 16 bit register The ADE7754 can accumulate active power for up to 65535 combined half cycles Because the active power is integrated on an integer number of line cycles the sinusoidal component is reduced to zero This eliminates any ripple in the energy calculation Energy is calculated more accurately because of this precise timing control At the end of an energy calibration cycle the LINCYC flag in the interrupt status registerug set If the LINCYC enable bit in the interrupt enable register Ja to Logic 1 theIRQ output also goes active low AENERGY 23 0 23 H 51 man
54. h a line frequency of 50 Hz this gives a phase resolution of 0 022 at the fundamental i e 360 X 1 2 us X 50 Hz Figure 19 illustrates how the phase compensation is used to remove a 0 091 phase lead in IA of the current channel caused by an external transducer In order to cancel the lead 0 091 in IA of the current channel a phase lead must also be intro duced into VA of the voltage channel The resolution of the phase adjustment allows the introduction of a phase lead of 0 086 The phase lead is achieved by introducing a time advance into VA A time advance of 4 8 us is made by writing 4 1Ch to the time delay block APHCAL 4 0 thus reducing the amount of time delay by 4 8 us See the Calibration of a 3 Phase Meter Based on the ADE7754 Application Note AN 624 lap APHCAL 4 0 19 2us 19 2 5 0 1 v2 VA DELAYED BY 4 8ps 70 0868 AT 50Hz 1CH gt 50Hz 50Hz Figure 19 Phase Calibration ROOT MEAN SQUARE MEASUREMENT Root Mean Square rms is a fundamental measurement of the magnitude of an ac signal Its definition can be practical or mathematical Defined practically the rms value assigned to an ac signal is the amount of dc required to produce an equivalent amount of heat in the same load Mathematically the rms value of a continuous signal f t is defined as T F sca lf foa 1 T o REV 0 For time sampling signals rms calculation involves squaring the signal taking
55. he register data on the next falling edge of SCLK remaining bits of register data are shifted in on the falling edge of subsequent SCLK pulses See Figure 44 As explained previously the data write is initiated by a write to the communications register followed by the data During a data write operation to the ADE7754 data is transferred to all on chip registers one byte at a time After a byte is transferred into the serial port there is a finite amount of time before the content of the serial port buffer is transferred to one of the ADE7754 on chip registers Although another byte transfer to the serial port can start while the previous byte is being transferred to the destina tion register this second byte transfer should not finish until at least 1 us after the end of the previous byte transfer This func tionality is expressed in the timing specification ts See Figure 44 If a write operation is aborted during a byte transfer CS brought high then that byte will not be written to the destination register Destination registers may be up to 3 bytes wide See the Register Descriptions section Therefore the first byte shifted into the serial port at DIN is transferred to the MSB most significant byte of the destination register If the destination register is 12 bits wide for example a 2 byte data transfer must take place The data is always assumed to be right justified therefore in this case the four MSBs of the first byt
56. his point the MCU external interrupt flag can be cleared in order to capture inter rupt events that occur during the current ISR When the MCU interrupt flag is cleared a read from the reset interrupt status register with reset is carried out This causes the IRQ line to be reset logic high 1 See the Interrupt Timing section The reset interrupt status register contents are used to determine the source of the interrupt s and therefore the appropriate action to be taken If a subsequent interrupt event occurs during the ISR t3 that event will be recorded by the MCU external interrupt flag being set again On returning from the ISR the global interrupt enable bit will be cleared same instruction cycle and the external interrupt flag will cause the MCU to jump to its ISR once again This will ensure that the MCU does not miss any external interrupts Interrupt Timing The Serial Interface section should be reviewed first before reviewing interrupt timing As previously described when the TRQ output goes low the MCU ISR must read the interrupt status register in order to determine the source of the interrupt When reading the interrupt status register contents the IRQ output is set high on the last falling edge of SCLK of the first byte transfer read interrupt status register command The IRQ output is held high until the last bit of the next 8 bit transfer is shifted out interrupt status register contents See Figure 48 If an interr
57. ifications subject to change without notice REV 0 ADE7794 DVpp 5 V 5 AGND DGND 0 V On Chip Reference CLKIN 10 MHz XTAL TIMING CHARACTERISTICS 2 Tun to 40 C to 85 C unless otherwise noted Parameter Spec Unit Test Conditions Comments Write Timing ti 50 ns min CS Falling Edge to First SCLK Falling Edge ty 50 ns min SCLK Logic High Pulsewidth t3 50 ns min SCLK Logic Low Pulsewidth t4 10 ns min Valid Data Setup Time before Falling Edge of SCLK ts 5 ns min Data Hold Time after SCLK Falling Edge te 400 ns min Minimum Time between the End of Data Byte Transfers t7 50 ns min Minimum Time between Byte Transfers during a Serial Write tg 100 ns min CS Hold Time after SCLK Falling Edge Read Timing 193 4 us min Minimum Time between Read Command 1 a Write to Communication Register and Data Read tio 50 ns min Minimum Time between Data Byte Transfers during a Multibyte Read ti 30 ns min Data Access Time after SCLK Rising Edge following a Write to the Communications Register ti 100 ns max Bus Relinquish Time after Falling Edge of SCLK 10 ns min ti 100 ns max Bus Relinquish Time after Rising Edge of CS 10 ns min NOTES Sample tested during initial release and after any redesign or process change that may affect this parameter input signals are specified with tr tf 5 ns 1096 to 9096 and timed from a voltage level of 1 6 V See timing diagrams belo
58. ingless Only when a large number of samples are averaged will a meaningful result be obtained This averaging is carried out in the second part of the ADC the digital low pass filter Averaging a large number of bits from the modulator the low pass filter can produce 24 bit data words that are proportional to the input signal level The X A converter uses two techniques to achieve high resolu tion from what is essentially a 1 bit conversion technique The first is oversampling the signal is sampled at a rate frequency many times higher than the bandwidth of interest For example the sampling rate in the ADE7754 is CLKIN 12 833 kHz and the band of interest is 40 Hz to 2 kHz Oversampling 10 spreads the quantization noise noise due to sampling over a wider bandwidth With the noise spread more thinly over a wider bandwidth the quantization noise in the band of interest is lowered See Figure 8 Oversampling alone is not an efficient enough method to improve the signal to noise ratio SNR in the band of interest For example an oversampling ratio of 4 is required to increase the SNR by only 6 dB 1 bit To keep the oversampling ratio at a reasonable level the quantization noise can be shaped so that most of the noise lies at the higher frequencies In the X A modulator the noise is shaped by the integrator which has a high pass type of response for the quantization noise The result is that most of the noise is at the higher
59. ings in PGA 1 current channel and 2 voltage channel are selected by various bits in the gain register The no load threshold and sum of the absolute value can also be selected in the gain register See Table X GAIN REGISTER CURRENT AND VOLTAGE CHANNEL PGA CONTROL ADDR 18h PGA 2 GAIN SELECT PGA 1 GAIN SELECT 00 x1 NO LOAD 00 x1 01 x2 01 x2 10 x4 10 x4 REGISTER CONTENTS SHOW POWER ON DEFAULTS Figure 6 Analog Gain Register ANALOG TO DIGITAL CONVERSION The ADE7754 carries out analog to digital conversion using second order X A ADCs The block diagram in Figure 7 shows first order for simplicity X A ADC The converter is made up of two parts the X A modulator and the digital low pass filter MCLK 12 ANALOG LOW PASS FILTER LATCHED COMPARATOR DIGITAL LOW PASS FILTER V 1 BIT DAC Figure 7 First Order X A ADC modulator converts the input signal into a continuous serial stream of 1s and Os at a rate determined by the sampling clock In the ADE7754 the sampling clock is equal to CLKIN 12 The 1 bit DAC in the feedback loop is driven by the serial data stream The DAC output is subtracted from the input signal If the loop gain is high enough the average value of the DAC output and therefore the bit stream will approach that of the input signal level For any given input value in a single sampling interval the data from the 1 bit ADC is virtually mean
60. ion of approximately 40 dBs at 833 kHz See Figure 9 This is sufficient to eliminate the effects of aliasing REV 0 ADE7754 ALIASING EFFECTS For example when 7FFh is written to the active power gain register the ADC output is scaled up by 50 7FFh 20478 SAMPLING 2047 212 0 5 Similarly 800h 2047d signed twos comple FRENIS ment ADC output is scaled by 50 These two examples are illustrated in Figure 10 FREQUENCIES Current Channel Sampling The waveform samples of the current channel inputs may also 0 2 417 833 be routed to the waveform register wavmode register to select FREQUENCY kHz the speed and the phase to be read by the system master MCU The active energy and apparent energy calculation remains uninterrupted during waveform sampling i 1 IMAGE 1 1 1 Figure 9 ADC and Signal Processing in Current Channel or Voltage Channel When in waveform sample mode one of four output sample CURRENT CHANNEL ADC rates may be chosen using Bits 3 and 4 of the WAVMODE Figure 10 shows the ADC and signal processing chain for the register DTRT 1 0 mnemonic The output sample rate input IA of the current channels which are the same for IB and may be 26 0 kSPS 13 0 kSPS 6 5 kSPS or 3 3 kSPS See the IC In waveform sampling mode the ADC outputs are signed Waveform Mode Register section By setting the WSMP bit in twos complement 24 bit data word at a maximum of 26 kSPS the interrupt enab
61. is register is also used to configure the active energy accumulation no load threshold and sum of absolute values 19h AWG R W 12 0 Phase A Active Power Gain Register The active power caluation for Phase A can be calibrated by writing to this register The calibration range is 50 of the nominal full scale active power The resolution of the gain adjust is 0 0244 LSB BWG RW 12 0 Phase B Active Power Gain 1Bh CWG RN 12 0 Phase Active Power Gain 1Ch AVAG RW 12 0 VA Gain Register This register calculation can be calibrated by writing this register The calibration range is 50 of the nominal full scale real power The resolution of the gain adjust is 0 02444 LSB 1Dh BVAG RW 12 0 Phase B VA Gain 1Eh CVAG R W 12 0 Phase C VA Gain 1Fh APHCAL RW 5 0 Phase A Phase Calibration Register 20h BPHCAL RW 5 0 Phase B Phase Calibration Register 21h CPHCAL R W 5 0 Phase C Phase Calibration Register 22h AAPOS 12 0 Phase A Power Offset Calibration Register 23h BAPOS 12 0 Phase B Power Offset Calibration Register 24h CAPOS 12 0 Phase C Power Offset Calibration Register the numerator of CF output scaling 26h CFDEN 12 3Fh CF Scaling Denominator Register The content of this register is used in the denominator of CF output scaling 27h WDIV 8 0 Active Energy Register Divider 28h VADIV 8 0 Apparent Energy Register Divider R W R W R W 25h CFNUM RAW 12 Oh CF Scaling Numerator Register The content of this register
62. ister to be accessed See the Communications Register section for a more detailed description 28 Figure 42 and Figure 43 show the data transfer sequences for a read and write operation respectively On completion of a data transfer read or write the ADE7754 once again enters com munications mode i e the next instruction followed must be a write to the communications register cs sek __ __ COMMUNICATIONS REGISTER WRITE DIN JoJo 11 DOUT MULTIBYTE READ DATA Figure 42 Reading Data from the 7754 via the Serial Interface 5 __ ___ __ COMMUNICATIONS REGISTER WRITE Jilo __ MULTIBYTE WRITE DATA Figure 43 Writing Data to the 7754 via the Serial Interface A data transfer is completed when the LSB of the ADE7754 register being addressed for a write or a read is transferred to or from the ADE7754 Serial Write Operation The serial write sequence requires the following steps With the ADE7785rin Copirfrurifeatigns and the CS input logic low wgite to the communications register takes place The MSB of this byte transfer must be set to 1 indicating that the next data transfer operation is a write to the register The six LSBs of this byte contain the address of the register to be written to The ADE7754 starts shifting in t
63. l scale See the Calibration of a 3 Phase Meter Based on the ADE7754 Application Note AN 624 18 Reverse Power Information The ADE7754 detects when the current and voltage channels of any of the three phase inputs have a phase difference greater than 90 i e or or gt 909 This mechanism can detect wrong connection of the meter or generation of active energy The reverse power information is available for Phase A Phase B and Phase C respectively by reading Bits 12 to 14 of the CFNUM register See Table XI The state of these bits represents the sign of the active power of the corresponding phase Logic 1 corresponds to negative active power The ABNERGY phase selection sj WATSEL bits of the WAT Mode register enable th nefative power detection per phase If Phase A is enabled in the AENERGY accumulation Bit 5 of WATMode register sets to Logic 1 and the negative power detection for Phase A Bit 12 of CFNUM register indicates the direction of the active energy If Phase A is disabled in the AENERGY register the negative power bit for Phase A is set to Logic 0 TOTAL ACTIVE POWER CALCULATION sum of the active powers coming from each phase provides the total active power consumption Different combinations of the three phases can be selected in the sum by setting Bits 7 and 6 of the register mnemonic WATMOD 1 0 Figure 26 demonstrates the calculation of the total active p
64. le register to Logic 1 the interrupt request kilo samples per second The output of the ADC can be scaled by 50 by using the APGAINS register While the ADC outputs are 24 bit twos complement value the maximum full scale positive value from the ADC is limited to 400000h 4 194 304d The maximum full scale negative value is lim ited to C00000h 4 194 304d If the analog inputs are m overranged the ADC output code clamps at these values With Ueo the specified full scale analog input signal of 0 5 V the ADC SCEK I roduces an output code between D70A3Eh 2 684 354 and DSESC2h 42 684 354 as illustrated in Figure 10 which also Coon output IRQ will go active low when a sample is available The timing is shown in Figure 11 The 24 bit waveform samples are transferred from the ADE7754 one byte eight bits at a time with the most significant byte shifted out first shows a full scale voltage signal being applied to the differential DOUT 5 CURRENT CHANNEL DATA 24 BITS inputs and Ian Current Channel Fig ra T1 Waveform Current Channel The ADC gain in each phase ofthe eurr nt be The interr pt request output TRQ stays low until the interrupt adjusted using the multiplier and active power gain register routine reads the reset status register See the Interrupt section AAPGAIN 11 0 BAPGAIN and CAPGAIN The gain of the ADC is adjusted by writing a twos
65. m WATMOD WATSEL 58 138 3 wire Delta 0 3 or 5 or 6 68 148 4 wire 1 5 8S 15S 4 wire Delta 2 5 9S 16S 4 wire Wye 0 7 Different gain calibration parameters are offered in the ADE7754 to cover the calibration of the meter in different configurations Note that in Mode 0 the APGAIN and WGAIN registers have the same effect on the end result In this case APGAIN regis ters should be set at their default value and the gain adjustment should be made with the WGAIN registers REV 0 a ENERGY CALCULATION As stated earlier power is defined as the rate of energy flow This relationship can be expressed mathematically as dE B 7 where P power and E energy Conversely energy is given as the integral of power E Pat 8 The ADE7754 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal non readable 54 bit energy register The active energy register AENERGY 23 0 represents the upper 24 bits of this internal register This discrete time accumulation or summation is equivalent to integration in continuous time Equation 9 expresses the relationship Lim 2 p nT xT S where is the discrete time sample number and T is the sample period 19 ADE7794 The discrete time sample period T for the accumulation register in the ADE7754 is 0 4 us 4 10 MHz In addition to calculating the energy this integration removes any sin
66. n normal operation these bits should be left at Logic 0 DISMOD2 DISMOD1 DISMODO 0 0 0 Normal operation 1 0 0 Normal operation By setting this bit to Logic 1 the analog inputs to current channel are connected to the ADC for voltage channel and the analog inputs to voltage channel are connected to the ADC for current channel 0 0 1 Current channel A D converters off 1 0 1 Current channel A D converters off channels swapped 0 1 0 Voltage Channel A D converters off 1 1 0 Voltage Channel A D converters off channels swapped 0 1 1 ADE7754 in sleep mode 1 1 1 ADE7754 powered down 6 SWRST 0 Software Chip Reset data transfer to the ADE7754 should not take place for at least 18 us after a software reset 7 RESERVED This is intended forpfaetory gesting only and shouldybe left at 0 NN 5 REV 0 35 ADE7794 Gain Register 18h The gain of the analog inputs and the mode of accumulation of the active energies in the ADE7754 are defined by writing to the gain register Table X summarizes the functionality of each bit in the gain register Table X GAIN Register Bit Bit Default Location Mnemonic Value Description 0 1 PGAI 0 These bits are used to select the gain of the current channels inputs Bit 1 Bit 0 0 0 1 0 1 2 1 0 4 0 0 Reserved 2 ABS 0 The sum of the absolute active energies is done in the ANERGY and LAENERGY registers when this bit
67. n the active energy measurement of the ADE7754 are defined by writing to the WATMODE register Table XIV summarizes the functionality of each bit in the WATMODE register Table XIV WATMODE Register Bit Bit Default Location Mnemonic Value Description 0 2 LWATSEL 7 These bits are used to select each part of the formula separately depending on the line active energy measurement method The behavior of these bits is the same as WATSEL bits Bit 2 selects the first term of the formula and so on 3 5 WATSEL 7 These bits are used to select each part of the formula separately depending on the active energy measurement method These bits are also used to enable the negative power detection available in Bits 12 to 14 of CFNUM register See Table XI Setting Bit 5 to Logic 1 selects the first term of the formula VA X IA or VA X IA IB Setting Bit 4 to Logic 1 selects the second term of the formula VB X IB or 0 depending on WATMOD configuration Setting Bit 3 to Logic 1 selects the last term of the formula VC X IC or VC X IC IB Any combi nation of these bits can address calibration and operational needs 6 7 WATM 0 These bits are used to select the formula used for active energy calculation WATMI WAVMO Active Energy Calculation 0 0 VA XIA VB XIB VC X IC 0 1 VA X IA IB 0 VC X IC IB 1 0 X IA IB 0 VC X IC 1 1 Reserved VA Mode Register 0Eh x The phases involved in the apparentieney Ey
68. nd to the sum of absolute values and the arithmetic sum respectively This selection affects the active energy accumulation in the AENERGY RAENERGY and LAENERGY registers as well as the CF frequency output When the sum of the absolute values is selected the active energy from each phase is always counted positive in the total active energy It is particularly useful in a 3 phase 4 wire instal lation where the sign of the active power should always same If the meter is misconnected the power lines e g CT is connected in the wrong direction the tofal active recorded without this solution can be reduced by two thirds The sum of the absolute values ensures that the active energy recorded represents the actual active energy delivered In this mode the reverse power information available in the CFNUM register is still detecting when negative active power is present on any of the three phase inputs MMODE REGISTER BIT 4 FROM VA ADC FROM VB ADC ACCUMULATE ACTIVE POWER DURING LINCYC ZERO CROSSINGS CALIBRATION CONTROL ADC LINCYC 15 0 LINE ENERGY ACCUMULATION The ADE7754 is designed with a special energy accumulation mode that simplifies the calibration process By using the on chip zero crossing detection the ADE7754 accumulates the active power signal in the LAENERGY register for an integer number of half cycles as shown in Fi
69. nergy calculation ADE7754 for each phase and the active energy I the Total Active Power Calculation section POWER VOLTAGE CHANNEL 0 5V GAIN2 CURRENT CHANNEL 0 5V GAIN1 13A92A4h 150 FS D1B717h 100 F5 68DB8Ch 50 FS 0000000h AAPGAIN 11 0 OR AWGAIN 11 0 972474h L 50 FS 2E48E9h 100 FS EC56D5Ch 150 FS 000h 7FFh 800h Figure 25 Active Power Calculation Output Range Power Offset Calibration The ADE7754 also incorporates an active offset register on each phase AAPOS BAPOS and CAPOS These are signed twos complement 12 bit registers that can be used to remove offsets in the active power calculations offset may exist in the power calculation because of crosstalk between channels on the PCB or in the IC itself The offset calibration allows the con tents of the active power register to be maintained at zero when no power is being consumed One LSB in the active power offset register is equivalent to one LSB in the 28 bit energy bus displayed in Figure 24 Each time power is added to the internal active energy register the content of the active power offset register is added See the Total Active Power Calculation section Assuming the average value from LPF2 is 8637BCh 8 796 092d with full ac scale inputs on current channel and voltage channel then one LSB in the LPF2 output is equivalent to 0 01196 of measurement error at 60 dB down of ful
70. nstantaneous reactive power signal in each phase A B and C is then extracted by a low pass filter to obtain the reactive power information on each phase In a polyphase system the total reactive power is simply the sum of the reactive power in all active phases The different solutions available to process the total reactive power from the individual calculation are discussed in the following section Figure 32 shows the signal processing in each phase for the reactive power calculation in the ADE7754 Since the phase shift applied on the current channel is not 90 as it should be ideally the reactive power calculation done in the ADE7754 cannot be used directly for the reactive power calculation Consequently using the ADE7754 reactive power measurement only to get the sign of the reactive power is rec ommended The reactive power can be processed using the power triangle method 23 ADE7794 REACTIVE POWER SIGNAL P MULTIPLIER INSTANTANEOUS REACTIVE POWER SIGNAL p t Figure 32 Reactive Power Signal Processing TOTAL REACTIVE POWER CALCULATION The sum of the reactive powers coming from each phase gives the total reactive power consumption Different combinations of the three phases can be selected in the sum by setting Bits 7 to 6 of the WATMode register mnemonic WATMOD 1 0 Each term of the formula can be disabled or enabled by the LWATSEL bits of the WATMode register Note that in this mode the LWA
71. nt both selections should indicate the same phase The ZXSEL bits of the MMODE register Bits 4 to 6 enable the phases on which the period measurement can be done The PERDSEL bits select the phase for period measurement within the phases selected by the ZXSEL bits REV 0 The resolution of this register is 2 4 ts LSB when CLKIN 10 MHz which is 0 014 when the line frequency is 60 Hz When the line frequency is 60 Hz the value of the period regis is approximately 69444 The length of the register enables the measurement of line frequencies as low as 12 7 Hz LINE VOLTAGE SAG DETECTION ADE7754 can be programmed to detect when the absolute value of the line voltage of any phase drops below a certain peak value for a number of half cycles All phases of the voltage chan nel are controlled simultaneously This condition is illustrated in Figure 16 Vep du SAG EVENT RESET LOW WHEN VOLTAGE CHANNEL EXCEEDS SAGLVL 7 0 SAGCYC 7 0 06h 6 HALF CYCLES SAG INTERRUPT FLAG BIT 1 TO BIT 3 OF STATUS REGISTER Figure 16 SAG Detection Figure L6 shows dline NPE prine below a threshold set in the SAG leyel register SAGL 7 0 for nine half cycles Since the SAG Cycle register indicates a six half cycle thresh old SAGCYC 7 0 06h the SAG event is recorded at the end of the sixth half cycle by setting the SAG flag of the corre sponding phase in the interrupt status regi
72. nt Power Calculation section The VGAIN adjustment affects the rms calculation because it is done before the rms signal processing The voltage rms values are stored in unsigned 24 bit registers AVRMS BVRMS and CVRMS 256 LSB of the voltage rms register is approximately equivalent to one LSB of a voltage waveform sample The update rate of the voltage rms measurement is CLKIN 12 With the specified full scale ac analog input signal of 0 5 V the produces an output code that is approximately 10 217 decimal at 60 Hz See the Voltage Channel ADC section The equivalent rms value of a full scale ac signal is approximately 7 221d 1C35h which gives a voltage rms value of 1 848 772d 1C35C4h in the register With offset calibration the voltage rms measurement provided in the ADE7754 is accurate within 0 5 for signal input between full scale and full scale 20 VOLTAGE SIGNAL V t fo sicaina a VRMSOS 11 0 800h 7FFh AVGAIN 11 0 VOLTAGE VOLTAGE SIGNAL v t CHANNEL rms A 4000h 2A50A6h 150 FS 28FSh 1C35C4h 100 FS E1AE2h 50 FS 0000h AVGAIN 11 0 D70Ah 50 FS E3CA3Ch 100 FS AUD RANG 150 FS WORD RANGE 000h 7FFh 800h Y Figure 21 Voltage RMS Signal Processing Voltage RMS Gain Adjust The voltage gain registers AVGAIN 11 0 BVGAIN and CVGAIN affect the apparent power and voltage rms values Cali
73. number of line cycles as the line active energy register these two values can be compared easily See the Energies Scaling section The active and apparent energy are calculated more accurately because of this precise timing control and provide all the information needed for reactive power and power factor calculation At the end of an energy calibration cycle the LINCYC flag in the interrupt status register is set If the LINCYC enableibit insthe interrupt enable register is set to Logic 1 the IRQ output al 2065 activellow Thus the IRQ line can also be used to signal the end of a calibration The total apparent power calculated by the ADE7754 in the line accumulation mode depends on the configuration of the VAMOD bits in the VAMode register Each term of the formula used can be disabled or enabled by the LVASEL bits of the VAM ode register The different configurations are described in Table VI Table VI Total Line Apparent Energy Calculation VAMOD VASELO VASEL1 VASEL2 0d 5 X Vcnus X Icrms 5 X Varms Vcnus 2 X Vcnus X Icrms 2d 5 X X Vcnus X Icrms line apparent energy accumulation uses the same signal path as the apparent energy accumulation The LSB size of these two registers is equivalent The ADE7754 accumulates the total reactive power signal in the LAENERGY regist
74. o place the entire device on the analog ground plane This pin provides access to the on chip voltage reference which has a nominal value of 2 4 V 8 and a typical temperature coefficient of 30 ppm C An external reference source may also be connected at this pin In either case this pin should be decoupled to AGND with a 1 uF ceramic capacitor Analog Inputs for the Voltage Channel This channel is intended for use with the voltage transducer andpisweferenced as the voltage channel in this decuments These inputs are single ended voltage in maximum signal level of 0 5 with respect to Vx for To operation These inputs are voltage inputs with maximum differential input signal levels of 0 5 V 0 25 V and 0 125 V depending on the gain selections of the internal PGA See the Analog Inputs section All inputs have internal ESD protection circuitry An overvoltage of 6 V can be sustained on these inputs without risk of permanent damage Reset A logic low on this pin holds the ADCs and digital circuitry including the serial interface in a reset condition Interrupt Request Output This is an active low open drain logic output Maskable interrupts include active energy register at half level apparent energy register at half level and waveform sampling at up to 26 kSPS See the Interrupts section Master Clock for ADCs and Digital Signal Processing An external clock can be provided at this logic input Alternatively a parallel r
75. o 0 of the WATMODE register determine how the line accumu lation active energy is processed from the six analog inputs See Table XIV 04h VAENERGY 24 0 VA Energy Register Apparent power is accumulated over time in this read only register Bits 7 to 3 of the VAMODE register determine how the apparent energy is processed from the six analog inputs See Table XV 05h RVAENERGY R 24 0 Same as the VAENERGY register except that the register is reset to 0 following a read operation 06h LVAENERGY R 24 0 Apparent Energy Register The instantaneous apparent power is accu mulated in this read only register over the LINCYC number of half line cycles Bits 2 to 0 of the VAMODE register determine how the apparent energy is processed from the six analog inputs See Table XV 07h PERIOD R 15 0 6f the line imputestimated by zero cr ssing processing Data Bit 0 and 1 nd 4 to the MMODE register d termine the voltage channel used for period calculation See Table XII 08h TEMP R 8 0 Temperature Register This register contains the result of the latest temperature conversion Refer to the Temperature Measurement section for details on how to interpret the content of this register 09h WFORM R 24 0 Waveform Register This register contains the digitized waveform of one of the six analog inputs The source is selected by Data Bits 0 to 2 in the register See Table XIII R W 8 4 Operational Mode
76. of the phase apparent power calculation is done in each individual rms mea surement signal processing See the Apparent Power Offset Calibration section 25 ADE7794 APPARENT ENERGY CALCULATION The apparent energy is given as the integral of the apparent power Apparent Energy Apparent Power t dt 21 ADE7754 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal nonreadable 49 bit register The apparent energy register VAENERGY 223 0 represents the upper 24 bits of this internal register This discrete time accumulation or summa tion is equivalent to integration in continuous time Equation 22 expresses the relationship where n is the discrete time sample number and T is the sample period Apparent Energy Lim gt Apparent Power nT x T 22 T gt 0 n 0 The discrete time sample period T for the accumulation regis ter in the ADE7754 is 1 2 us 12 10 MHz Figure 37 shows a graphical representation of this discrete time integration or accumulation The apparent power signal is continuously added to the internal register This addition is a signed addition even if the apparent energy theoretically always remains positive VAENERGY 23 0 23 0 imt
77. on of Reactive Energy Accumulation The features of the reactive energy accumulation are the same as for the line active energy accumulation each one of three phases Zero crossing detection can contribute to the accumulation of the half line cycles Phase A B and C zero crossings respec tively are taken into account when counting the number of half line cycles by setting to Logic 1 Bits 4 to 6 ofthe MMODE register Selecting phases for the zero crossing counting also has 24 the effect of enabling the zero crossing detection zero crossing timeout and period measurement for the corresponding phase as described in the Zero Crossing Detection section The number of half line cycles is specified in the LINCYC register LINCYC is an unsigned 16 bit register The ADE7754 can accumulate active power for up to 65535 combined half cycles At the end of an energy calibration cycle the LINCYC flag in the interrupt status register is set If the LINCYC enable bit in the interrupt enable register is set to Logic 1 the IRQ output also goes active low Thus the IRQ line can also be used to signal the end of a calibration As explained in the Reactive Power Calculation section the purpose of the reactive energy calculation in the ADE7754 is not to give an accurate measurement of this value but to provide the sign of the reactive energy The ADE7754 provides an accu rate measurement of the apparent energy Because the active energy is also measur
78. ower which depends on the configuration of the WATMOD bits in the WA TMode register Each term of the formula can be disabled or enabled by setting WATSEL bits respectively to Logic 0 or Logic 1 in the WATMode register The different configurations are described in Table I Table I Total Active Power Calculation WATMOD WATSELO WATSEL1 WATSEL2 0d Va X X Ip Ve x Io 14 Va X 14 15 0 Ve X Ic Ig 2d Va X Ia g 0 Ve X Ic Note that Ig and Ic represent the current channel samples after APGAIN correction and high pass filtering REV 0 ADE7754 PHASE A Va BAPGAIN lc PHASE C Vc TOTAL INSTANTANEOUS POWER SIGNAL ACTIVE POWER SIGNAL P 2752545h Figure 26 Total Active Power Consumption Calculation 1 For example for WATMOD 1 the gains and offsets corrections are taken into consideration the formula that is used to process the active power is Total Active Power 4 mms xI f HA ZI aaros 1 NEM 212 212 212 x Ic ewe X Ig caros x ere 2 2 2 Depending on the polyphase meter service an appropriate for mula should be chosen to calculate the active power The American ANSI C12 10 standard defines the different configu rations of the meter Table II describes which mode should be chosen for each configuration Table II Meter Form Configuration ANSI Meter For
79. parent energy accu mulation mode that simplifies the calibration process By using the on chip zero crossing detection the ADE7754 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles as shown in Figure 39 The line apparent energy accumulation mode is always active Each of three zero crossing detection phases can contribute to the accumulation of the half line cycles Phase A B and C zero crossings are taken into account when counting the number of half line cycles by setting Bits 4 to 6 of the MMODE register to Logic 1 Selecting phases for the zero crossing counting also has the effect of enabling the zero crossing detection zero crossing timeout and period measurement for the corresponding phase as described in the zero crossing detection paragraph REV 0 MMODE REGISTER BIT 4 FROM VA ADC MMODE REGISTER BIT 5 FROM VB ADC LINCYC 15 0 FROM VC ADC ADE7754 LVAENERGY 23 0 ACCUMULATE APPARENT POWER i DURING LINCYC ZERO CROSSINGS APPARENT POWER PHASEA i APPARENT POWER PHASE i i 0 APPARENT POWER PHASEC Figure 39 Apparent Energy Calibration number of half line cycles is specified in the LINCYC unsigned 16 bit register The ADE7754 can accumulate apparent power for up to 65535 combined half cycles Because the apparent power is integrated on the same integral
80. ress of each ADE7754 on chip register RESERVED This bit is unused and should be set to 0 7 WR When this bit is a Logic 1 the data transfer operation immediately following the write to the com munications register will be interpreted as a write to the ADE7754 When this bit is a Logic 0 the data transfer operation immediately following the write to the communications register will be interpreted as a read operation DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO wm o as as D REV 0 31 ADE7794 Table VIII Register List Address Default A5 A0 Name R W Length Value Description 00h Reserved Reserved 01h AENERGY R 24 0 Active Energy Register Active power is accumulated over time in an inter nal register The AENERGY register is a read only register that reads this internal register and can hold a minimum of 88 seconds of active energy information with full scale analog inputs before it overflows See the Energy Calculation section Bits 7 to 3 of the WATMODE register determine how the active energy is processed from the six analog inputs See Table XIV 02h RAENERGY 24 0 Same as the AENERGY register except that the internal register is reset to 0 following a read operation 03h LAENERGY R 24 0 Line Accumulation Active Energy Register The instantaneous active power is accumulated in this read only register over the LINCYC number of half line cycles Bits 2 t
81. rrupt when the LAENERGY and LVAENERGY accumulations over LINCYC are finished Bh Reserved Ch PKV 0 Enabl the voltage input selegted ifthe ODE register is above the EL Salue register T Dh PKI 0 Enables n interrupt when the current input selected in the MMODE register is above the value in the PKILVL register Eh WFSM 0 Enables an interrupt when a data is present in the waveform register Fh VAEHF 0 Enables an interrupt when there is a 0 to 1 transition of the MSB of the VAENERGY register i e the VAENERGY register is half full INTERRUPT ENABLE REGISTER F E D C B A 9 8 7 6 5 4 3 2 4 0 ADDR OFh VAEHF APPARENT ENERGY REGISTER HALF FULL ACTIVE ENERGY REGISTER HALF FULL WFSM SAG NEW WAVEFORM SAMPLE READY SAG EVENT DETECT PKI ZX CURRENT CHANNEL PEAK DETECTION ZERO CROSSING TIMEOUT DETECTION PKV ZX VOLTAGE CHANNEL PEAK DETECTION ZERO CROSSING DETECTION RESERVED LENERGY END OF THE LAENERGY AND LVAENERGY ACCUMULATION REGISTER CONTENTS SHOW POWER ON DEFAULTS REV 0 39 ADE7794 Interrupt Status Register 10h Reset Interrupt Status Register 11h The interrupt status register is used to determine the source of an interrupt event When an interrupt event occurs in the ADE7754 the corresponding flag in the interrupt status register is set logic high The IRQ pin will go active low if the corresponding bit in the interrupt enable register is set logic high When the
82. rupt Timing 30 ACCESSING THE ADE7754 ON CHIP REGISTERS 31 Communications Register 31 Operational Mode Register OAh 35 Gain Register 18h 36 CFNUM Register 25 36 Measurement Mode Register OBh 37 Waveform Mode Register 37 Watt Mode Register ODh 38 VA Mode Register OEh 38 Interrupt Enable Register OFh 39 Interrupt Status Register 10h Reset Interrupt Status Register IIH PEE REA 40 OUTLINE DIMENSIONS 41 REV 0 ADE7754 SPECIFICATIONS mies Parameters Spec Unit Test Conditions Comments ACCURACY Active Power Measurement Error 0 1 typ Over a dynamic range 1000 to 1 Phase Error between Channels PF 0 8 Capacitive 0 05 max Phase lead 37 PF 0 5 Inductive 0 05 max Phase lag 60 AC Power Supply Rejection Output Frequency Variation 0 01 typ IBP N ICP N 100 mV rms DC Power Supply Rejection Output Frequency Variation 0 01 typ IBP N ICP N 100 mV rms Active Power Measurement Bandwidth 14 kHz typ Vi Measurement Error 0 5 typ Over dynamic range of 20 to 1 Vims Measurement Bandwidth 260 Hz typ Measurement Error 2 typ Over dynamic range o
83. s on the analog inputs The three displayed curves illustrate the minimum time it takes the energy register to roll over when the individual watt gain registers contents are all equal to 3FFh 000h and 800h The watt gain registers are used to carry out a power calibration in the ADE7754 As shown the fastest integration time occurs when the watt gain registers are set to maximum full scale i e 3FFh 20 AENERGY 23 0 7F FFFFh AWG CWG 3FFh p Mi AWG BWG CWG 000h AWG BWG CWG 800h 3F FFFFh 7 00 0000h 2 LAMB gt i 88 1132 176 220 2264 40 0000 je Z I T 80 0000h m IME sec Figure 28 Energy Register Roll Over Time for Full Scale Power Minimum and Maximum Power Gain Note that the active energy register contents roll over to full scale negative 80 0000h and continue increasing in value when the power or energy flow is positive See Figure 28 Conversely if the power is negative the energy register would underflow to full scale positive 7F FFFFh and continue decreasing in value By using the interrupt enable register the ADE7754 can be configured to issue an interrupt IRQ when the active energy register is half full positive or negative Integration Times Under Steady Load As mentioned in the last section the discrete time sample period T for the accumulation register is 0
84. specified operation This pin should be decoupled to DGND with a 10 uF capacitor in parallel with a ceramic 100 nF capacitor Analog Power Supply The supply should be maintained at 5 V 5 for specified operation Every effort should be made to minimize power supply ripple and noise at this pin through the use of proper decoupling The TPCs chart the power supply rejection performance This pin should be to decoupled AGND with a 10 uF capacitor in parallel with a ceramic 100 nF capacitor Analog Inputs for Current Channel This channel is intended for use with the current transducer is referenced in this document as the current channel These inputs are fully differential voltage inputs with maximum differential input signal levels of 0 5 V 0 25 V and 0 125 V depending on the gain selections of the internal PGA See the Analog Inputs section All inputs have internal ESD protection circuitry An overvoltage of 6 V can be sustained on these inputs without risk of permanent damage Analog Ground Reference Used for ADCs temperature sensor and reference This pin should be tied to the analog ground plane or the quietest ground reference in the system This quiet ground reference should be used for all analog circuitry such as anti aliasing filters and current and voltage transducers To keep ground noise around the ADE7754 to a minimum the quiet ground plane should be connected only to the digital ground plane at one point It is acceptable t
85. sponse To offset this phase response and equalize the phase response between channels a phase correction network is placed in the current channel The phase correction network ensures a phase match between the current channels and voltage channels to within 0 1 over a range of 45 Hz to 65 Hz and 0 2 over a range of 40 Hz to 1 kHz This phase mismatch between the voltage and the current channels can be reduced further with the phase calibration register in each phase x 100 Power Supply Rejection This quantifies the ADE7754 measurement error as a percentage of reading when power supplies are varied For the ac PSR mea surement a reading at nominal supplies 5 V is taken A second reading is obtained using the same input signal levels when an ac 175 mV rms 100 Hz signal is introduced onto the supplies Any error introduced by this ac signal is expressed as a percentage of reading See the Measurement Error definition above For the dc PSR measurement a reading at nominal supplies 5 V is taken A second r adirig i obfaided using the same input signal levels when th are 5 error introduced is again expressed as a percentage of reading ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs It means that with the analog inputs connected to AGND the ADCs still see a dc analog input signal The magni tude of the offset depends on the gain and input ran
86. ster Bits 1 to 3 in the interrupt status register If the SAG enable bit is set to Logic 1 for this phase Bits 1 to 3 in the interrupt enable register the TRQ logic output goes active low See the Interrupts section All the phases are compared to the same parameters defined in the SAGLVL and SAGCYC registers SAG Level Set The content of the SAG level register one byte is compared to the absolute value of the most significant byte output from the voltage channel ADC Thus for example the nominal maximum code from the voltage channel ADC with a full scale signal is 28F5h See the Voltage Channel ADC section Therefore writing 28h to the SAG level register puts the SAG detection level at full scale and sets the SAG detection to its most sensitive value READ RSTATUS REGISTER Writing 00h puts the SAG detection level at 0 The detection of a decrease of an input voltage is in this case hardly possible The detection is made when the content of the SAGLVL register is greater than the incoming sample PEAK DETECTION The ADE7754 also can be programmed to detect when the absolute value of the voltage or the current channel of one phase exceeds a certain peak value Figure 17 illustrates the behavior of the peak detection for the voltage channel 13 ADE7794 Var Vep Vcp PKV RESET LOW WHEN RSTATUS REGISTER IS READ PKV INTERRUPT FLAG BIT C OF STATUS REGISTER READ RSTATUS REGISTER Figure 17
87. t Compensation 16 Voltage RMS Calculation 16 Voltage RMS Gain Adjust 16 Voltage RMS Offset Compensation 17 ACTIVE POWER CALCULATION 17 Power Offset Calibration 18 Reverse Power Information 18 TOTAL ACTIVE POWER CALCULATION 18 ENERGY CALCULATION 19 Integration Times Under Steady Load 20 Energy to Frequency Conversion 20 No Load Threshold 21 Mode Selection of the Sum of the Three Active Energies 22 LINE ENERGY ACCUMULATION 22 REACTIVE POWER CALCULATION 23 TOTAL REACTIVE POWER CALCULATION 24 Reactive Energy Accumulation Selection 24 APPARENT POWER CALCULATION 24 Apparent Power Offset Calibration 25 TOTAL APPARENT POWER CALCULATION 25 APPARENT ENERGY CALCULATION 26 Integration Times under Steady Load 26 LINE APPARENT ENERGY ACCUMULATION 26 ENERGIES SCALING 2 a 27 CHECK SUM REGISTER 277 SERIALINTERFACE sees ene 28 Serial Write Operation 28 Serial Read Operation 29 INTERRUPTS Rc etr Rh 30 Using Interrupts with an MCU 30 Inter
88. terrupt status register is set to Logic 1 when AVpp drops below 4 V 596 The RESET flag is always masked by the interrupt enable register and cannot cause the pin to go low The power supply and decoupling for the part should ensure that the ripple at AVpp does not exceed 5 V t 5 as specified for normal operation ANALOG INPUTS The ADE7754 has six analog inputs divisible into two chan nels current and voltage The current channel consists of three pairs of fully differential voltage inputs Ip Ian Isr Igy and EFhe fullysdifferential Yoltage input pairs have maxi V voltage channel has three single end d voltage inputs Vap Vgp and These single ended voltage inputs have a maximum input voltage of 0 5 V with respect to Vy Both the current channel and the voltage channel have a PGA programmable gain amplifier with possible gain selections of 1 2 or 4 The same gain is applied to all the inputs of each channel The gain selections are made by writing to the gain register Bits 0 and 1 select the gain for the PGA in the fully differential current channel The gain selection for the PGA in the single ended volt age channel is made via Bits 5 and 6 Figure 5 shows how a gain selection for the current channel is made using the gain register GAIN 7 0 GAIN k SELECTION lap lan IBN Ion Figure 5 PGA in Current Channel ADE7794 Figure 6 shows how the gain sett
89. the active power signal has some ripple due to the instantaneous power signal This ripple is sinusoidal and has a frequency equal to twice the line frequency Since the ripple is sinusoidal in nature it is removed when the active power signal is integrated to calculate the energy See the Energy Calculation section 0 DECIBELS 1 1 eo e 1 3 10 30 100 FREQUENCY Hz Figure 23 Frequency Response of the LPF Used to Filter Instantaneous Power in Each Phase 17 ADE7794 CURRENT SIGNAL 100 TO 100 FS 28F5C2h i t 00h 1V GAIN1 D70A3Eh V VOLTAGE SIGNAL v t 100 TO 100 FS 28F5h 00h 1V GAIN2 D70Bh INSTANTANEOUS POWER SIGNAL p t APOS 11 0 ACTIVE POWER SIGNAL P D1B717h NoNo Figure 24 Active Power Signal Processing Figure 24 shows the signal processing in each phase for the active power in the ADE7754 Figure 25 shows the maximum code hexadecimal output range of the active power signal after AWG Note that the output range changes depending on the contents of the active power gain and watt gain registers See the Current Channel ADC section The minimum output range is given when the active power gain and watt gain registers contents are equal to 800h and the maximum range is given by writing 7FFh to the active power gain and watt gain registers These can be used to calibrate the active power or e
90. the average and obtaining the square root 2 The method used to calculate the rms value in the ADE7754 is to low pass filter the square of the input signal LPF3 and take the square root of the result With VE x N2 x sin wz then V t XV xcos 201 The rms calculation is simultaneously processed on the six analog input channels Each result is available on separate registers Current RMS Calculation Figure 20 shows the detail of the signal processing chain for the rms calculation on one of the phases of the current channel The current channel rms value is processed from the samples used in the current channel waveform sampling mode Note that the APGAIN adjustment affects the result of the rms calcu lation See the Current RMS Gain Adjust section The current rms values are stored in unsigned 24 bit registers AIRMS BIRMS and CIRMS One LSB of the current rms register is equivalent to 1 LSB of a current waveform sample The update rate of currengrms measurement is CLKIN 12 With the specified full scale analog input Signal of 0 5 V the ADC produces an Otitput Code which is approximately 2 684 354d See the Current Channel ADC section The equivalent rms values of a full scale ac signal is 1 898 124d With offset calibration the current rms measurement provided in the ADE7754 is accurate within 2 for signal input between full scale and full scale 100 Irms t 100 to 100 FS IRMSOS 11 0 1CF6
91. time the line active energy register will be four times bigger than the active energy register The LAENERGY register is also used to accumulate the reac tive energy by setting to Logic 1 Bit 5 of the WAVMode register Address See the Reactive Power Calculation section When this bit is set to 1 the accumulation of the active energy over half line cycles in the LAENERGY register is disabled and is done instead in the LVAENERGY register Because the LVAENERGY register is an unsigned value the accumulation of the active energy in the LVAENERGY register is unsigned in this mode The reactive energy is then accumulated in the LAENERGY register See Figure 33 In this mode reactive en ergy selecting the phases accumulated in the LAENERGY and LVAENERGY registers is done by the LWATSEL selec tion bits of the WATTMode register In normal mode Bit 5 of the WAVMODE register equals 0 and the type of active power summation in the LAENERGY register sum of absolute active power or arithmetic sum is selected by Bit 2 of the gain register In the mode where the active powers are accumulated in the LVAENERGY register and Bit 5 of the WAVMODE register equals 1 note that the sum of several active powers is always REV 0 done ignoring the sign of the active powers This is due to the unsigned nature of the LVAENERGY register which does not allow signed addition REACTIVE POWER CALCULATION Reactive power is defined as the product of
92. tions An offset may exist in the rms calculation due to input noises that are inte grated in the dc component of V t The offset calibration will allow the contents of the Igms registers to be maintained at zero when no current is being consumed n LSB of the current rms offset are equivalent to 32768 X n LSB of the square of the current rms register Assuming that the maximum value from the current rms calculation is 1 898 124 decimal with full scale ac inputs then 1 LSB of the current rms offset represents 0 005896 of measurement error at 40 dB below full scale Tone 28 IRMSOS 32768 where is the rms measurement without offset correction The current rms offset compensation should be done by testing the rms results at two non zero input levels One measurement can be 16 done close to full scale and the other at approximately full scale 100 The current offset compensation can then be derived using these measurements See the Calibration of a 3 Phase Meter Based on the ADE7754 Application Note AN 624 Voltage RMS Calculation Figure 21 shows the details of the signal processing chain for the rms calculation on one of the phases of the voltage channel The voltage channel rms value is processed from the samples used in the voltage channel waveform sampling mode The output of the voltage channel ADC can be scaled by 50 by changing VGAIN registers to perform an overall apparent power calibra tion See the Appare
93. to high energy electrostatic discharges Therefore proper ESD precautions are recommended ESD SENSITIVE DEVICE to avoid performance degradation or loss of fumetionality j NN D PIN CONFIGURATION 1 DGND 2 3 AVpp 4 REFiyour 12 PIN FUNCTION DESCRIPTIONS Pin No Mnemonic Description 1 Calibration Frequency Logic Output This pin provides active power information This output is intended to be used for operational and calibration purposes The full scale output frequency can be scaled by writing to the CFNUM and CFDEN registers See the Energy to Frequency Conversion section 2 DGND This pin provides the ground reference for the digital circuitry in the ADE7754 i e multiplier filters and a digital to frequency converter Because the digital return currents in the ADE7754 are small this pin can be connected to the analog ground plane of the whole system However high bus capacitance on the DOUT pin may result in noisy digital current which could affect performance REV 0 2b ADE7794 PIN FUNCTION DESCRIPTIONS continued Pin No Mnemonic Description 3 DVpp 4 AVpp 3 Taps Ian 3 Isr Igy 0 Icn 11 AGND 12 REF our 13 14 Vor 15 16 17 18 IRQ 19 CLKIN 20 CLKOUT 21 CS 22 DIN 23 SCLK 24 DOUT Digital Power Supply The supply voltage should be maintained at 5 V 5 for
94. upt is pending at this time the IRQ output will go low again If no interrupt ispoending the J output will remain high r INT FLAG SET ISR RETURN GLOBAL INTERRUPT MASK RESET ISR ACTION BASED ON STATUS CONTENTS Figure 47 Interrupt Management SCLK DIN DOUT READ STATUS REGISTER COMMAND XS E a tho ese eie m STATUS REGISTER CONTENTS Figure 48 Interrupt Timing 30 REV 0 7754 ACCESSING THE ADE7754 ON CHIP REGISTERS Communications Register All ADE7754 functionality is accessed via the on chip registers The communications register is an 8 bit write only register that Each register is accessed by first writing to the communications controls the serial data transfer between the ADE7754 and the register then transferring the register data For a full description host processor All data transfer operations must begin with a of the serial interface protocol see the Serial Interface section write to the communications register The data written to the communications register determines whether the next operation is a read or a write and which register is being accessed Table VII outlines the bit designations for the communications register Table VII Communications Register Bit Bit Location Mnemonic Description 0 to 5 AO to A5 six LSBs of the communications register specify the register for the data transfer operation Table VIII lists the add
95. usoidal component that may be in the active power signal Figure 27 shows a graphical representation of this discrete time integration or accumulation The active power signal is continuously added to the internal energy register Because this addition is a signed addition negative energy will be subtracted from the active energy contents AENERGY 23 0 23 0 am 531 1 0 MONA a TOTAL ACTIVE POWER IS ACCUMULATED INTEGRATED IN T THE ACTIVE ENERGY REGISTER xis 26667h 00000h Ld TIME nT UM Figure 27 Active Energy Calculation 54 bit value of the internal energy register is divided by WDIV If the value in the WDIV register is 0 then the internal active energy register is divided by 1 WDIV is an 8 bit unsigned register The upper 24 bits of the result of the division are then available in the 24 bit active energy register The AENERGY and RAENERGY registers read the same internal active energy register They differ by the state in which they are leaving the internal active energy register after a read Two operations are held when reading the RAENERGY register read and reset to 0 the internal active energy register Only one operation is held when reading the AENERGY register read the internal active energy register Figure 28 shows the energy accumulation for full scale sinusoidal signal
96. ut signal of the voltage channel and the output of LPF1 The phase response of this filter is shown in the Voltage Channel ADC section The phase lag response of LPF1 results in a time delay of approximately 0 6 ms 60 Hz between the zero crossing on the analog inputs of voltage channel and the falling of IRQ When one phase crosses zero from negative to positive values rising edge the corresponding flag in the interrupt status register Bits 7 to 9 is set Logic 1 An active low in the IRQ output also appears if the corresponding ZX bit in the interrupt enable register is set to Logic 1 The flag in the interrupt status register is reset to 0 when the inter rupt status register with reset RSTATUS is read Each phase has its own interrupt flag and enable bit in the interrupt register REV 0 ADE7754 In addition to the enable bits the zero crossing detection interrupt of each phase is enabled disabled by setting the ZXSEL bits of the MMODE register Address OBh to Logic 1 or 0 respectively Zero Crossing Timeout Each zero crossing detection has an associated internal timeout register not accessible to the user This unsigned 16 bit regis ter is decremented 1 LSB every 384 CLKIN seconds The registers are reset to a common user programmed value 1 e Zero cross timeout register ZX TOUT Address 12h every time a zero crossing is detected on its associated input The default value of ZXTOUT is FFFFh If the internal re
97. ve Power Gain Adjust 38h AVGAIN RAW 12 0 Phase A Voltage RMS Gain The apparent power accumulation of the Phase A can be calibrated by writing to this register The calibration range is 50 of the nominal full scale of the apparent power The resolution of the gain is 0 0244 LSB See the Voltage RMS Gain Adjust section 39h BVGAIN RAW 12 0 Phase B Voltage RMS Gain 3Ah CVGAIN RAW 12 0 Phase C Voltage RMS Gain 3Bh Reserved 3Dh 3Eh CHKSUM R 8 Check Sum Register The content of this register represents the sum of all 1s of the latest register read from the SPI port 3Fh VERSION R 8 1 Version of the Die R W Read Write capability of the regist t R Read only register R W Register that can be both read and written 1 ALI 34 REV 0 7754 Operational Mode Register 0Ah The general configuration of the ADE7754 is defined by writing to the OPMODE register Table IX summarizes the functionality of each bit in the OPMODE register Table IX OPMODE Register Bit Bit Default Location Mnemonic Value Description 0 DISHPF 0 The HPFs high pass filters in all current channel inputs are disabled when this bit is set 1 DISLPF 0 LPFs low pass filters in all current channel inputs are disabled when this bit is set 2 DISCF 1 frequency output is disabled when this bit is set 3 5 DISMOD 0 By setting these bits ADE7754 s A D converters can be turned off I
98. w and Serial Interface section of this data sheet 3Minimum time between read command and data read for all registers except wavmode register which is t 500 ns min Measured with the load circuit in Fig re l and Un as the time required for the output to cross 0 8 V or 2 4 V gt Derived from the measured time taken by the data outputs to change 0 5 V when loaded with the circuit in Figure 1 The measured number is then NS extrapolated back to remove the effects of charging or discharging the 50 pF Figure 1 Load Circuit for Timing Specifications capacitor The time quoted in the timing characteristics is the true bus relin quish time of the part and is independent of the bus loading 24V ts cs SCLK DIN DBO COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE Figure 2 Serial Write Timing SCLK DIN COLO eX OC Yoo COMMAND BYTE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE Figure 3 Serial Read Timing 4 REV 0 ADE7754 ABSOLUTE MAXIMUM RATINGS Storage Temperature Range 65 C to 150 25 C unless otherwise noted Junction Temperature 150 C AVppto AGND 0 3 V to 7 V 24 Lead SOIC Power Dissipation 88 mW DVpp to 0c eee eee ee 0 3 V to 7 V Thermal Impedance 53 C W DV pin to AV pais Gate eer e 0
99. xample if the output frequency is 18 744 kHz and the contents of CFDEN are zero 000h then the output frequency can be set to 6 103 Hz by writing BFFh to the CFDEN register The output frequency will have a slight ripple at a frequency equal to twice the line frequency because of imperfect filtering of the instantaneous power signal used to generate the active power signal See the Active Power Calculation section Equa tion 5 gives an expression for the instantaneous power signal This is filtered by LPF2 which has a magnitude response given by Equation 11 1 HCO i2 e 11 REV 0 The active power signal output of the LPF2 can be rewritten as p t VI Er x cos 4n t 2 12 INC 2 8 where f is the line frequency e g 60 Hz From Equation 8 VI E t VIt x sin 4n f t 2f 13 f Equation 13 shows that there is small ripple in the energy calculation due to a sin 2wt component This is graphically displayed in Figure 30 The ripple becomes larger as a percentage of the frequency at larger loads and higher output frequencies Choosing a lower output frequency at CF for calibration can significantly reduce the ripple Also averaging the output fre quency by using a longer gate time for the counter achieves the same results E t x sin 47 f t Figure 30 Output Frequency Ripple No Load Threshold ADE7754 includes selectable load threshol
100. y exist in the rms calculation due to input noises and offsets in the input samples The offset calibration allows the contents of the registers to be maintained at zero when no voltage 1s applied n LSB of the voltage rms offset are equivalent to 64 X n LSB of the voltage rms register Assuming that the maximum value from the voltage rms calculation is 1 898 124 decimal with full scale ac inputs then 1 LSB of the voltage rms offset represents 0 07 of measurement error at 26 dB below full scale rms rms VRMSOS x 64 Y where is the rms meat AMAA Ma offset correction The voltage rms offset compensation should be done by testing the rms results at two non zero input levels One measurement can be done close to full scale and the other at approximately full scale 10 The voltage offset compensation can then be derived from these measurements See the Calibration of a 3 Phase Meter Based on the ADE7754 Application Note AN 624 ACTIVE POWER CALCULATION Electrical power is defined as the rate of energy flow from source to load It is given by the product of the voltage and current waveforms The resulting waveform is called the instantaneous power signal and it is equal to the rate of energy flow at every instant of time The unit of power is the watt or joules sec Equa tion 5 gives an expression for the instantaneous power signal in an ac system v t A2V 3 i t 21 sin t 4 where V

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