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ANALOG DEVICES ADE7752 handbook

1. Rev C Page 7 of 24 ADE7752 ADE7752A TYPICAL PERFORMANCE CHARACTERISTICS WYE CONNECTION WYE CONNECTION 0 4 ON CHIP REFERENCE ON CHIP REFERENCE o3 PHASE C S P f 0 2 PHASE A PHASEA B C 2 0 1 8 cs O 0f PHASE B 5 x 0 1 a g 2 7 0 2 A 0 3 5 0 4 g S 0 5 8 0 1 1 10 100 CURRENT CHANNEL of Full Scale CURRENT CHANNEL of Full Scale Figure 4 Error as a Percent of Reading Figure 7 Error as a Percent of Reading over Temperature with Internal Reference Wye Connection with Internal Reference Wye Connection 1 0 0 5 WYE CONNECTION DELTA CONNECTION 0 8 ON CHIP REFERENCE 0 4 ON CHIP REFERENCE HI 0 6 85 C PF 0 5 0 3 PF 0 5 S 04 25 C PF 0 5 B 0 2 3 D 0 2 04 PF 1 5 o S o z x g 0 2 25 C PF 5 PF 0 5 a o k ira 40 C PF 0 5 0 4 amp 0 2 0 6 0 3 0 8 0 4 3 1 0 a 0 5 8 0 1 1 10 100 0 1 1 10 100 CURRENT CHANNEL of Full Scale CURRENT CHANNEL
2. Va Vc x Ia Vs Ve x Is where Va Vz and Vc represent the voltage on Phase A B and C respectively I and Is represent the current on Phase A and B respectively Rev C Page 20 of 24 ADE7752 ADE7752A As the voltage and current inputs respect Equations 5 and 6 the total real power P is P V V eta VeVi p iv x cos w t V2 x Ve x cow E xv2 xl xcos w t vzv xeo wr 2 y 2x Vo coo E x Zx 1 xeos ot 22 For simplification assume that a s c 0 and Va Vs Vc V The preceding equation becomes 2 2 P 2xVxI x sin 2 x sino x cos wt 9 T 27 2xV xI x sin x sin w t a n x cos a P then becomes P V xI x sin 22 sin 24 2 3 3 10 Vay XI X si 2 sin 20 where Van V x sin 27 3 and Vgn V x sin z 3 As the LPF on each channel eliminates the 2w1 component of the equation the real power measured by the ADE7752 is 5 5 P V xI x 4 V X Ip x AN A 5 BN B 2 If full scale ac voltage of 500 mV peak is applied to the voltage channels and current channels the expected output frequency is calculated as follows F 0 60 Hz SCF S0 S1 1 Van Ven li g le 300 mV pe k ac Sv rms 2 Vow I 0 Ver 2 4V nominal reference value Note that if the on chip reference is used actual output fre quencies may vary from device to device due to reference tolerance of 8 181x0 5x0 5x0 60 v3 ees 23 0 139
3. of Full Scale Figure 5 Error as a Percent of Reading over Power Factor Figure 8 Error as a Percent of Reading over Power Factor with Internal Reference Wye Connection with Internal Reference Delta Connection 0 5 0 5 TTT WYE CONNECTION WYE CONNECTION 0 4 EXTERNAL REFERENCE 0 4 EXTERNAL REFERENCE Hil 0 3 85 C PF 0 5 0 3 p 02 p 0 2 85 C PF 1 T o1 25 C PF 1 FEP oa o i ira 5 o0 5 o0 amp amp 25 C PF 1 o 0 1 ij 0 1 Q 40 C PF 0 5 9 A 0 2 425 C PF 0 5 paz 40 C PF 1 0 3 0 3 0 4 0 4 S 0 5 8 0 5 8 0 1 1 10 100 0 1 1 10 100 CURRENT CHANNEL of Full Scale CURRENT CHANNEL of Full Scale Figure 6 Error as a Percent of Reading over Power Factor Figure 9 Error as a Percent of Reading over Temperature with External Reference Wye Connection with External Reference Wye Connection Rev C Page 8 of 24 ADE7752 ADE7752A hed WYE CONNECTION N 88 0 4 ON CHIP REFERENCE 18 PEAN oe MIN 2 47468 MAX 12 9385 0 3 15 RANGE 15 4132 PF 1 0 2 S o1 12 28 d PF 0 5 0 1 2 6 fn 0 2 0 3 4 0 4 z Ta 3 to as 10 i 45 50 55 60 65 5 0 5 10 15 20 FRE
4. Table 1 ADE7752 ADE7752A Parameter Min Typ Max Min Typ Max Unit Conditions ACCURACY 2 Measurement Error on Current 0 1 0 1 Reading Voltage channel with full scale signal Channel 500 mV 25 C over a dynamic range of 500 to 1 Phase Error Between Channels PF 0 8 Capacitive 0 1 0 1 Degrees PF 0 5 Inductive 0 1 0 1 Degrees AC Power Supply Rejection SCF 0 S0 S1 1 Output Frequency Variation 0 01 0 01 Reading IA IB IC 100 mV rms CF VA VB VC 100 mV rms 50 Hz ripple on Vpp of 175 mV rms 100 Hz DC Power Supply Rejection S1 1 S0 SCF 0 Output Frequency Variation 0 1 0 1 Reading IA IB IC 100 mV rms CF VA VB VC 100 mV rms Voo 5 V 250 mV ANALOG INPUTS See the Analog Inputs section Maximum Signal Levels 0 5 0 5 Vpeak Var to Vn Ver to Vn Ve to Vn lap to lan differential lsp to len Icp to len Input Impedance DC 370 410 370 450 kQ CLKIN 10 MHz Bandwidth 3 dB 14 14 kHz CLKIN 256 CLKIN 10 MHz ADC Offset Error 25 25 mV Gain Error 9 9 Ideal External 2 5 V reference IA IB IC 500 mV dc REFERENCE INPUT REFin out Input Voltage Range 2 6 2 6 V 2 4 V 8 2 2 2 2 V 2 4 V 8 Input Impedance 3 3 3 3 kQ Input Capacitance 10 10 pF ON CHIP REFERENCE Nominal 2 4 V Reference Error 200 200 mV Temperature Coefficient 25 25 ppm C CLKIN All specifications for CLKIN of 10 MHz Input Clock Frequency 10 10 MHz LOGIC INPUTS ACF SO S1 and ABS Input High Voltage V
5. 2 02676 A 024 FREQUENCY RAD S Figure 25 Effect of Channel Offset on the Real Power Calculation 0 010 0 008 0 006 0 004 0 002 PHASE Degrees 02676 A 026 40 45 50 55 60 65 70 FREQUENCY Hz Figure 26 Phase Error Between Channels 40 Hz to 70 Hz Rev C Page 17 of 24 ADE7752 ADE7752A DIGITAL TO FREQUENCY CONVERSION After multiplication the digital output of the low pass filter contains the real power information of each phase Because this LPF is not an ideal brick wall filter implementation however the output signal also contains attenuated components at the line frequency and its harmonics cos hat where h 1 2 3 and so on The magnitude response of the filter is given by HO 8 f 8 where the 3 dB cutoff frequency of the low pass filter is 8 Hz For a line frequency of 50 Hz this would give an attenuation of the 2w 100 Hz component of approximately 22 dB The dominating harmonic is twice the line frequency cos 2wt due to the instantaneous power signal Figure 27 shows the instantaneous real power signal at the output of the CF which still contains a significant amount of instantaneous power information cos 2at This signal is then passed to the digital to frequency converter where it is integrated accumulated over time to produce an output frequency This accumulation of the signal suppresses or averages out any non dc component in the instantaneo
6. Frequency Outputs F1 and F2 ssss sssssssssssssssssessssssssssssereeessssssss 20 Frequency Output CF ss sssessssessssssssssessssssssressssssssseessssessseessseens 21 Selecting a Frequency for an Energy Meter Application 22 Frequency Outputs oi scscocccesssessicsdsseitesssstescsscnteseseestesssseaiecssasoies 22 No Load Threshold isis csis sccsscissctescossstecseanevadsssictescissstascasisteset 22 Negative Power Information cscessesseseseeseessesseeseessessees 23 Outline Dimensions iaieiiea senise seades 24 Ordering Guide h sisissscsstesesascvssnecdsessasnderatesasenshuecaastionsscsaseustaasbes 24 5 03 Rev 0 to Rev A Changed Fics to Fia aE aaiae Universal Change to Figure 6 siyi ana KKN 10 Changes to Frequency Outputs F1 and F2 section 13 Replaced Table Mingi ii eS Ee ashe 13 Changes to Examples 1 2 and 3 ecscesesesssessesseessessesstesseeseeaes 14 Replaced Table Miimii ieaiai aaiae 14 Replaced Tables IV V and VI ssssssssssessssssresesssserresssreressssreseeresseee 15 Changes to SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION section ssssssssssesssssssssssssssretessrteesessssss 15 Changes to NO LOAD THRESHOLD section ceesesseeseeseese 16 Replaced Table V ec ite htan tienda 16 Rev C Page 2 of 24 ADE7752 ADE7752A SPECIFICATIONS Voo 5 V 5 AGND DGND 0 V on chip reference CLKIN 10 MHz Tmn to Tmax 40 C to 85 C unless otherwise noted
7. frequency on F1 and F2 with a 100 imp kWhr meter constant is 0 15 Hz at 25 A and 220 V from Table 8 Looking at Table 9 the closest frequency to 0 15 Hz in column 5 is 0 12 Hz Therefore Fi 7 0 6 Hz is selected for this design SCF S1 so F1 F2 Min Hz CF Min Hz 0 0 0 2 56 x 10 4 09 x 10 1 0 0 2 40 x 10 1 92 x 10 0 0 1 1 02 x 10 1 64 x 10 1 0 1 9 59 x 10 1 54 x 107 0 1 0 3 84 x 10 6 14 x 10 1 1 0 3 84 x 10 3 07 x 10 0 1 1 1 54 x 10 1 23 x 10 1 1 1 1 20 x 107 1 92 x 10 Rev C Page 22 of 24 ADE7752 ADE7752A NEGATIVE POWER INFORMATION The ADE7752 detects when the current and voltage channels of The REVP pin output changes state at the same time a pulse is any of the three phase inputs have a phase difference greater issued on CE If several phases measure negative power the than 90 a or ds or pc gt 90 This mechanism can detect REVP pin output stays high until all the phases measure wrong connection of the meter or generation of active energy positive power If a phase has gone below the no load threshold The REVP pin output goes active high when negative power is REVP detection on this phase is disabled REVP detection on detected on any of the three phase inputs If positive active this phase resumes when the power returns out of no load energy is detected on all the three phases REVP pin output is low condition See the No Load Threshold section Rev C Page 23 of 24
8. that is proportional to the average real power The averaging of the real power signal is implicit to the digital to frequency conversion The output frequency or pulse rate is related to the input voltage signals by the following equation 6 181 x Vay xI Van x Ip Voy x Ic X Fi V 2 REF Freq where Freq the output frequency on F1 and F2 Hz Van Van and Ven the differential rms voltage signal on voltage channels V Ih In and Ic the differential rms voltage signal on current channels V Vrer the reference voltage 2 4 V 8 V F 7 one of seven possible frequencies selected by using the logic inputs SCF SO and S1 see Table 5 Table 5 Fi 7 Frequency Selection SCF S1 so F 7 Hz 0 0 0 1 27 1 0 0 1 19 0 0 1 5 09 1 0 1 4 77 0 1 0 19 07 1 1 0 19 07 0 1 1 76 29 1 1 1 0 60 F _7 is a fraction of the master clock and therefore varies if the specified CLKIN frequency is altered Example 1 Thus if full scale differential dc voltages of 500 mV are applied to VA VB VC IA IB and IC respectively 500 mV is the maximum differential voltage that can be connected to current and voltage channels the expected output frequency is calculated as follows F 0 60 Hz SCF S0 S1 1 Van Van Ven IA IB IC 500 mV dc 0 5 V rms of dc dc Veer 2 4 V nominal reference value Note that if the on chip reference is used actual outp
9. Frequency This logic input is used to select the frequency on the calibration output CF Table 7 shows how the calibration frequencies are selected Rev C Page 6 of 24 ADE7752 ADE7752A Pin No Mnemonic Description 19 CLKIN Master Clock for ADCs and Digital Signal Processing An external clock can be provided at this logic input Alternatively a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7752 The clock frequency for specified operation is 10 MHz Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit Refer to the crystal manufacturer s data sheet for load capacitance requirements 20 CLKOUT A crystal can be connected across this pin and CLKIN as described previously to provide a clock source for the ADE7752 The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used 21 22 SO S1 These logic inputs are used to select one of four possible frequencies for the digital to frequency conver sion This offers the designer greater flexibility when designing the energy meter See the Selecting a Frequency for an Energy Meter Application section 24 23 F1 F2 Low Frequency Logic Outputs F1 and F2 supply average real power information The logic outputs can be used to drive electromechanical counters and two phase stepper motors directly See the Transfer Function section
10. be used for all analog circuitry such as antialiasing filters current and voltage transducers and so on To keep ground noise around the ADE7752 to a minimum the quiet ground plane should connect to the digital ground plane at only one point It is acceptable to place the entire device on the analog ground plane 12 REFin our This pin provides access to the on chip voltage reference The on chip reference has a nominal value of 2 4V 8 and a typical temperature coefficient of 20 ppm C An external reference source may also be connected at this pin In either case this pin should be decoupled to AGND with a 1 uF ceramic capacitor 13 16 VN VCP VBP Analog Inputs for the Voltage Channel This channel is intended for use with the voltage transducer and VAP is referenced in this document as the voltage channel These inputs are single ended voltage inputs with a maximum signal level of 0 5 V with respect to VN for specified operation All inputs have internal ESD protection circuitry In addition an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage 17 ABS This logic input is used to select the way the three active energies from the three phases are summed This offers the designer the capability to do the arithmetical sum of the three energies ABS logic high or the sum of the absolute values ABS logic low See the Mode Selection of the Sum of the Three Active Energies section 18 SCF Select Calibration
11. for the current channel IA A current transformer CT is the current trans ducer selected for this example Notice the common mode voltage for the current channel is AGND and is derived by center tapping the burden resistor to AGND This provides the complementary analog input signals for IAP and IAN The CT turns ratio and burden resistor Rb are selected to give a peak differential voltage of 500 mV at maximum load cT Rf IAP O P PHASE NEUTRAL y 02676 A 019 Figure 19 Typical Connection for Current Channels VOLTAGE CHANNELS CONNECTION Figure 20 shows two typical connections for the voltage channel The first option uses a potential transformer PT to provide complete isolation from the main voltage In the second option the ADE7752 is biased around the neutral wire and a resistor divider is used to provide a voltage signal proportional to the line voltage Adjusting the ratio of Ra Rb and VR is also a convenient way of carrying out a gain calibration on the meter PT VAP O A s500mVv PHASE NEUTRAL 500mV 02676 A 018 PHASE NEUTRAL Ra gt gt Rf VR Rb VR Rf Figure 20 Typical Connections for Voltage Channels METER CONNECTIONS In 3 phase service two main power distribution services exist 3 phase 4 wire or 3 phase 3 wire The additional wire in the 3 phase 4 wire arrangement is the neutral wire The voltage lines have a phase difference of 120 21 3 radians between e
12. load This allows overcurrent signals and signals with high crest factors to be accommodated Table 9 shows the output frequency on F1 and F2 when all six analog inputs are half scale Table 9 F1 and F2 Frequency with Half Scale AC Inputs Frequency on F1 and F2 SCF S1 so Fi 7 Half Scale AC Inputs 0 0 0 1 27 0 26 1 0 0 1 19 0 24 0 0 1 5 09 1 02 1 0 1 4 77 0 96 0 1 0 19 07 3 84 1 1 0 19 07 3 84 0 1 1 76 29 15 35 1 1 1 0 60 0 12 FREQUENCY OUTPUTS Figure 2 shows a timing diagram for the various frequency outputs The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electro mechanical impulse counter The F1 and F2 outputs provide two alternating high going pulses The pulse width t is set at 275 ms and the time between the rising edges of F1 and F2 ts is approximately half the period of F1 t2 If however the period of F1 and F2 falls below 550 ms 1 81 Hz the pulse width of F1 and F2 is set to half of their period The maximum output frequencies for F1 and F2 are shown in Table 6 The high frequency CF output is intended to be used for communications and calibration purposes CF produces a 96 ms wide active high pulse ts at a frequency proportional to active power The CF output frequencies are given in Table 7 As in the case of F1 and F2 if the period of CF ts falls below 192 ms the CF pulse width is set to half the period For exam
13. only two current inputs and two voltage inputs of the ADE7752 are used in this case The real power calculated by the Rat Ct ADE7752 does not depend on the selected channels Ra cf D gt O IAN ANTIALIASING PHASE A Hira FILTERS source PHASE B PHASE A PHASE C SOURCE LOAD ANTIALIASING FILTERS PHASE B ANTIALIASING FILTERS IBP O IBN 3 g O VBP F Ra gt gt Rf VR Rb VR Rf g Ra gt gt Rf VR Rb VR Rf Figure 22 3 Phase 4 Wire Meter Connection with ADE7752 Figure 21 3 Phase 3 Wire Meter Connection with ADE7752 Rev C Page 16 of 24 ADE7752 ADE7752A POWER SUPPLY MONITOR The ADE7752 contains an on chip power supply monitor The power supply Vpn is continuously monitored by the ADE7752 If the supply is less than 4 V 5 the outputs of the ADE7752 are inactive This is useful to ensure correct device startup at power up and power down The power supply monitor has built in hysteresis and filtering This gives a high degree of immunity to false triggering due to noisy supplies As can be seen from Figure 23 the trigger level is nominally set at 4 V The tolerance on this trigger level is about 5 The power supply and decoupling for the part should be such that the ripple at Vpn does not exceed 5 V 5 as specified for normal operation HPF AND OFFSET EFFECTS Figure 25 shows the effect of offsets on the real power calcula tion As can be seen an
14. 1 87 1 0 0 1 19 8 x F1 F2 3 83 0 0 1 5 09 160 x F1 F2 327 46 1 0 1 4 77 16 x F1 F2 30 70 0 1 0 19 07 16 x F1 F2 122 81 1 1 0 19 07 8 x F1 F2 61 40 0 1 1 76 29 8 x F1 F2 245 61 1 1 1 0 60 16 x F1 F2 3 84 Rev C Page 21 of 24 ADE7752 ADE7752A SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION As shown in Table 5 the user can select one of seven frequen cies This frequency selection determines the maximum frequency on F1 and F2 These outputs are intended to be used to drive the energy register electromechanical or other Since only seven different output frequencies can be selected the available frequency selection has been optimized for a 3 phase 4 wire service with a meter constant of 100 imp kWhr and a maximum current between 10 A and 100 A Table 8 shows the output frequency for several maximum currents Imax with a line voltage of 220 V phase neutral In all cases the meter constant is 100 imp kWhr Table 8 V F1 and F2 Frequency at 100 imp kWhr Imax A F1 and F2 Hz 10 0 18 25 0 46 40 0 73 60 1 10 80 1 47 100 1 83 The Fi 7 frequencies allow complete coverage of this range of output frequencies on F1 and F2 When designing an energy meter the nominal design voltage on the voltage channels should be set to half scale to allow for calibration of the meter constant The current channel should also be no more than half scale when the meter sees maximum
15. ADE7752 ADE7752A OUTLINE DIMENSIONS 15 60 0 6142 f 15 20 0 5984 i 24 13 7 60 0 2992 7 40 0 2913 10 65 0 4193 1 12 10 00 0 3937 2 65 0 1043 0 75 0 0295 3 2 35 0 0925 IF 0 25 0 0098 anaa 4 0 30 0 0118 0 10 0 0039 VV TTT TA KA gt e le A 8 gt je COPLANARITY 1 27 0 0500 0 51 0 020 SEATING 9 33 0 0130 1 27 0 0500 0 BSC 0 31 0 012 0 20 0 0079 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 013 AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 28 24 Lead Standard Small Outline Package SOIC Wide Body RW 24 Dimensions shown in millimeters and inches ORDERING GUIDE Model Temperature Range Package Description Package Option ADE7752AR 40 C to 85 C 24 Lead SOIC Package RW 24 in Tubes ADE7752ARRL 40 C to 85 C 24 Lead SOIC Package RW 24 on 13 Reels ADE7752ARZ 40 C to 85 C 24 Lead SOIC Package RW 24 in Tubes ADE7752ARZ RL 40 C to 85 C 24 Lead SOIC Package RW 24 on 13 Reels ADE7752AAR 40 C to 85 C 24 Lead SOIC Package RW 24 in Tubes ADE7752AAR RL 40 C to 85 C 24 Lead SOIC Package RW 24 on 13 Reels ADE7752AARZ 40 C to 85 C 24 Lead SOIC Package RW 24 in Tubes ADE7752AARZ RL 40 C to 85 C 24 Lead SOIC Package RW 24 on 13 Reels EVAL ADE7752EB Evaluation Board EVAL ADE7752
16. AEB Evaluation Board Z Pb free part 2005 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective companies 02676 0 7 05 C ANALOG DEVICES Rev C Page 24 of 24 www analog com
17. ANALOG DEVICES Polyphase Energy Metering IC with Pulse Output ADE7752 ADE7752A FEATURES High accuracy supports 50 Hz 60 Hz IEC62053 2x Less than 0 1 error over a dynamic range of 500 to 1 Compatible with 3 phase 3 wire delta and 3 phase 4 wire Wye configurations The ADE7752 supplies average real power on frequency outputs F1 and F2 High frequency output CF is intended for calibration and supplies instantaneous real power Logic output REVP indicates a potential miswiring or negative power for each phase Direct drive for electromechanical counters and 2 phase stepper motors F1 and F2 Proprietary ADCs and DSP provide high accuracy over large variations in environmental conditions and time On chip power supply monitoring On chip creep protection no load threshold On chip reference 2 4 V 8 20 ppm C typical with external overdrive capability Single 5 V supply low power 60 mW typical ADE7752 30 mW typical ADE7752A Low cost CMOS process GENERAL DESCRIPTION The ADE7752 is a high accuracy polyphase electrical energy measurement IC The ADE7752A is a pin to pin compatible low power version of ADE7752 The functions of ADE7752 and ADE7752A are the same Both products are referred to in the text of this data sheet as ADE7752 The part specifications surpass the accuracy requirements as quoted in the IEC62053 2x standard The only analog circuitry used in the ADE7752 is in the analog to digital converters AD
18. Cs and reference circuit All other signal processing such as multi plication filtering and summation is carried out in the digital domain This approach provides superior stability and accuracy over extremes in environmental conditions and over time The ADE7752 supplies average real power information on the low frequency outputs F1 and F2 These logic outputs may be used to directly drive an electromechanical counter or to interface with an MCU The CF logic output gives instanta neous real power information This output is intended to be used for calibration purposes The ADE7752 includes a power supply monitoring circuit on the Vo pin The ADE7752 remains inactive until the supply voltage on Vpn reaches 4 V If the supply falls below 4 V no pulses are issued on F1 F2 and CF Internal phase matching circuitry ensures that the voltage and current channels are phase matched An internal no load threshold ensures the part does not exhibit any creep when there is no load The ADE7752 is available in a 24 lead SOIC package FUNCTIONAL BLOCK DIAGRAM IAP H N eet IAN HPF s K E PHASE CORRECTION IBP Q N a Oo wet gt lt ia 4kQ ABS Vop D Q DH m POWER SUPPLY MONITOR ADE7752 ADE7752A 2 DGND 9 CLKIN 0 CLKOUT DIGITAL TO FREQUENCY CONVERTER CORRECTION ji ia O 2 2 e AGND REFijjout REVP SCF SO Si F2 M CF 02676 A 001 Figure 1 24 Lead Standard Small Outline P
19. DE7752 are small it is acceptable to connect this pin to the analog ground plane of the whole system 3 Voo Power Supply This pin provides the supply voltage for the digital circuitry in the ADE7752 The supply voltage should be maintained at 5 V 5 for specified operation This pin should be decoupled to DGND with a 10 uF capacitor in parallel with a 100 nF ceramic capacitor 4 REVP This logic output goes logic high when negative power is detected on any of the three phase inputs that is when the phase angle between the voltage and the current signals is greater than 90 This output is not latched and is reset when positive power is once again detected See the Negative Power Information section 5 6 IAP IAN Analog Inputs for Current Channel This channel is intended for use with the current transducer and is 7 8 IBP IBN referenced in this document as the current channel These inputs are fully differential voltage inputs 9 10 ICP ICN with maximum differential input signal levels of 0 5 V See the Analog Inputs section Both inputs have internal ESD protection circuitry In addition an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage 11 AGND This pin provides the ground reference for the analog circuitry in the ADE7752 the ADCs temperature sensor and reference This pin should be tied to the analog ground plane or the quietest ground reference in the system This quiet ground reference should
20. He V2 xJ2x2 4 2 Freq 2x Table 6 shows a complete listing of all maximum output frequencies when using all three channel inputs Table 6 Maximum Output Frequency on F1 and F2 Max Frequency for Max Frequency for SCF S1 SO AC Inputs Hz DC Inputs Hz 0 0 0 0 51 1 02 1 0 0 0 48 0 96 0 0 1 2 04 4 09 1 0 1 1 91 3 84 0 1 0 7 67 15 35 1 1 0 7 67 15 35 0 1 1 30 70 61 4 1 1 1 0 24 0 48 FREQUENCY OUTPUT CF The pulse output calibration frequency CF is intended for use during calibration The output pulse rate on CF can be up to 160 times the pulse rate on F1 and F2 The lower the Fi 7 frequency selected the higher the CF scaling Table 7 shows how the two frequencies are related depending on the states of the logic inputs S0 S1 and SCE Because of its relatively high pulse rate the frequency at this logic output is proportional to the instantaneous real power As with F1 and F2 the frequency is derived from the output of the low pass filter after multiplica tion However because the output frequency is high this real power information is accumulated over a much shorter time Thus less averaging is carried out in the digital to frequency conversion With much less averaging of the real power signal the CF output is much more responsive to power fluctuations See Figure 15 Table 7 Maximum Output Frequency on CF SCF S1 SO F 7 Hz CF Max for AC Signals Hz 0 0 0 1 27 160 x F1 F2 8
21. QUENCY Hz CH_I PhA OFFSET mV Figure 10 Error as a Percent of Reading over Frequency Figure 12 Channel 1 Offset Distribution with an Internal Reference Wye Connection 0 5 SPOEG OEG PAL R DE OA T S 0 5 1 r rrr WYE CONNECTION WYE CONNECTION 0 4 EXTERNAL REFERENCE 0 4 H ON CHIP s 0 3 0 3 4 75V D 0 2 2e 5V 8 8 0 1 g 01 o g S o 5 0 x 0 1 S 0 1 j 2 EoD 5 25V 0 2 T 0 0 3 0 3 i 0 4 3 0 4 z g 0 5 8 BiT 1 10 100 0 1 1 10 100 CURRENT CHANNEL of Full Scale CURRENT CHANNEL of Full Scale Figure 13 Error as a Percent of Reading over Power Supply Figure 11 Error as a Percent of Reading over Power Supply with Internal Reference Wye Connection with External Reference Wye Connection Rev C Page 9 of 24 ADE7752 ADE7752A TEST CIRCUIT TO FREQ COUNTER ADE7752A IAN CF Q V 33nF v SAME AS IAP IAN 02676 A 014 Figure 14 Test Circuit for Performance Curves Rev C Page 10 of 24 ADE7752 ADE7752A TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7752 is defined by the following formula Energy Registered by ADE7752 True Energy Percentage Error x 100 True Energy Error Between Channels The high pass filter HPF in the current channel has a phase lead response To offset this phase response and equalize the phase response between channels a phase correction network is also p
22. ach other See Equation 5 V t ya x V X cos wt 2 V t v2 x V x cos or 5 4n Vo t v2 x Vo x cos ox where Va Vz and Vc represent the voltage rms values of the different phases The current inputs are represented by Equation 6 1 t 2 I xcos lot 9 1y t V2 1 xcos of os 6 Tel V Ie xcos of oc where Ia Iz and Ic represent the rms value of the current of each phase and u s and c represent the phase difference of the current and voltage channel of each phase The instantaneous powers can then be calculated as follows Pa t Va t x I t P3 t Va t x In t P t Vc t x Ict Then P t V x I xcoslp V x I xcos 2wt 9 4 P t V XI x cos 9 V x1 xcos zwr 0 7 P t V x I x cos g Ve x Ie xcos 20 ae vc As shown in Equation 7 in the ADE7752 the real power calcu lation per phase is made when current and voltage inputs of one phase are connected to the same channel A B or C Then the summation of each individual real power calculation gives the total real power information P t Pa t Ps t Pc t Rev C Page 15 of 24 ADE7752 ADE7752A Figure 21 shows the connections of the analog inputs of the Figure 22 shows the connections of the analog inputs of the ADE7752 with the power lines in a 3 phase 3 wire delta service ADE7752 with the power lines in a 3 phase 4 wire Wye service Note that
23. ackage SOIC Rev C Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved ADE7752 ADE7752A TABLE OF CONTENTS Specifications cheshire esis E E EE E EE 3 Timing Characteristics cceessesssessesseessessesssessessesssessessesssessesseens 4 Absolute Maximum Ratings ccccsessesssesesssesessesseessessessesesseess 5 ESD C t Mzn RRE R R R 5 Pin Configuration and Function Descriptions 6 Typical Performance Characteristics csssessesseesseseeseeseeseens 8 TeSt CUCU Pe Aah ON AE OGRE es OS ROE RAR OSA eee 10 TOTMUNOLO SY asdss avsasscasewsssussvesssstanesscousvectseshuesassasensseassnssssseiossacoes 11 Theory Of Operation iesaisti irii E aeeai iia 12 Power Factor Considerations ssssssssssssssesssssssssrssressssssssssseeee 12 Nonsinusoidal Voltage and Current sssssssssssssssssssssssersssssssssss 13 Analog Inputs ssccecss s
24. en obtained by adding the individual phase real power This scheme correctly calculates real power for nonsinusoidal current and voltage waveforms at all power factors All signal processing is carried out in the digital domain for superior stability over temperature and time p t i t x v t Vxl WHERE Vxl The low frequency output of the ADE7752 is generated by accumulating the total real power information This low frequency inherently means a long accumulation time between output pulses The output frequency is therefore proportional to the average real power This average real power information can in turn be accumulated by a counter for example to generate real energy information Because of its high output frequency and therefore shorter integration time the CF output is proportional to the instantaneous real power This pulse is useful for system calibration purposes that would take place under steady load conditions POWER FACTOR CONSIDERATIONS Low pass filtering the method used to extract the real power information from the individual instantaneous power signal is still valid when the voltage and current signals of each phase are not in phase Figure 16 displays the unity power factor condition and a DPF displacement power factor 0 5 or current signal lagging the voltage by 60 for one phase of the polyphase Assuming that the voltage and current waveforms are sinusoidal the real power component of the instantan
25. eous power signal or the dc term is given by P x cos 60 v t V x cos ot i t Ix cos ot Nxt PO EV XI 44 cos 20t 2 2 TIME INSTANTANEOUS POWER SIGNAL p t OS INSTANTANEOUS REAL POWER SIGNAL 4 A VB xIB INSTANTANEOUS TOTAL VCxIC POWER SIGNAL DIGITAL TO FREQUENCY DIGITAL TO FREQUENCY 02676 A 015 Figure 15 Signal Processing Block Diagram Rev C Page 12 of 24 ADE7752 ADE7752A This is the correct real power calculation INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL CURRENT VOLTAGE INSTANTANEOUS INSTANTANEOUS REAL POWER SIGNAL POWER SIGNAL 02676 A 016 Figure 16 DC Component of Instantaneous Power Signal Conveys Real Power Information PF lt 1 NONSINUSOIDAL VOLTAGE AND CURRENT The real power calculation method also holds true for nonsin usoidal current and voltage waveforms All voltage and current waveforms in practical applications have some harmonic content Using the Fourier Transform instantaneous voltage and current waveforms can be expressed in terms of their harmonic content v t V V2 x SV xsin nwt a 1 n 0 where v t is the instantaneous voltage Vo is the average value Vn is the rms value of voltage harmonic n a is the phase angle of the voltage harmonic i t Io x VI xsin not B 2 n 0 where i t is the instantaneous current Io is the dc component In i
26. hat the active energy recorded represents the actual active energy delivered In this mode the reverse power pin still detects when negative power is present on any of the three phase inputs POWER MEASUREMENT CONSIDERATIONS Calculating and displaying power information always has some associated ripple that depends on the integration period used in the MCU to determine average power as well as the load For example at light loads the output frequency may be 10 Hz With an integration period of 2 seconds only about 20 pulses are counted The possibility of missing one pulse always exists since the ADE7752 output frequency is running asynchro nously to the MCU timer This would result in a 1 in 20 or 5 error in the power measurement Rev C Page 19 of 24 ADE7752 ADE7752A TRANSFER FUNCTION FREQUENCY OUTPUTS F1 AND F2 The ADE7752 calculates the product of six voltage signals on current channel and voltage channel and then low pass filters this product to extract real power information This real power information is then converted to a frequency The frequency information is output on F1 and F2 in the form of active high pulses The pulse rate at these outputs is relatively low such as 29 32 Hz maximum for ac signals with SCF 1 S0 S1 1 see Table 6 This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time The result is an output frequency
27. ied out The result is a greatly attenuated sinusoidal content and a virtually ripple free frequency output F1 gt A S DIGITAL TO FREQUENCY 2 fe Fi w Fo fe 2 TIME DIGITAL TO CF FREQUENCY 3 A c m Oe a W oc uw LPF TO EXTRACT REAL POWER DC TERM cos 2ot ATTENUATED BY LPF 0 o 20 FREQUENCY RAD S INSTANTANEOUS REAL POWER SIGNAL FREQUENCY DOMAIN 02676 A 027 Figure 27 Real Power to Frequency Conversion Rev C Page 18 of 24 ADE7752 ADE7752A MODE SELECTION OF THE SUM OF THE THREE ACTIVE ENERGIES The ADE7752 can be configured to execute the arithmetic sum of the three active energies Wh Whga Whgs Whgc or the sum of the absolute value of these energies Wh Whygal Whgs Whgc The selection between the two modes can be made by setting the ABS pin Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values respectively When the sum of the absolute values is selected the active energy from each phase is always counted positive in the total active energy It is particularly useful in 3 phase 4 wire installa tion where the sign of the active power should always be the same If the meter is misconnected to the power lines for instance if CT is connected in the wrong direction the total active energy recorded without this solution can be reduced by two thirds The sum of the absolute values assures t
28. inn 2 4 2 4 V Voo 5 V 5 Input Low Voltage Vint 0 8 0 8 V Voo 5 V 5 Input Current lin 3 3 yA Typically 10 nA Vin 0 V to Voo Input Capacitance Cin 10 10 pF LOGIC OUTPUTS F1 and F2 Output High Voltage Vou 4 5 4 5 V Isource 10 MA Voo 5 V Output Low Voltage VoL 0 5 0 5 V Isink 10 MA Voo 5 V CF and REVP Output High Voltage Vou 4 4 V Voo 5 V lsource 5 MA Output Low Voltage VoL 0 5 0 5 V Voo 5 V Isink 5 MA POWER SUPPLY For specified performance Voo 4 75 5 25 4 75 5 25 V 5 V 5 lbo 12 16 6 9 mA 1 See the Terminology section for explanation of specifications 2 See the plots in the Typical Performance Characteristics section 3 Sample tested during initial release and after any redesign or process change that may affect this parameter Rev C Page 3 of 24 ADE7752 ADE7752A TIMING CHARACTERISTICS Voo 5 V 5 AGND DGND 0 V on chip reference CLKIN 10 MHz Tun to Tmax 40 C to 85 C unless otherwise noted Table 2 Parameter Conditions Spec Unit t3 F1 and F2 Pulse Width Logic High 275 ms t2 Output Pulse Period See the Transfer Function section See Table 6 sec ts Time between F1 Falling Edge and F2 Falling Edge 1 2 t2 sec t4 4 CF Pulse Width Logic High 96 ms ts CF Pulse Period See the Transfer Function and the Frequency Outputs sections See Table 7 sec te Minimum Time Between the F1 and F2 Pulse CLKIN 4 sec 1 Sample tested during i
29. is expressed as a percentage of the ideal frequency The ideal frequency is obtained from the ADE7752 transfer function See the Transfer Function section Rev C Page 11 of 24 ADE7752 ADE7752A THEORY OF OPERATION The six voltage signals from the current and voltage transducers are digitized with ADCs These ADCs are 16 bit second order A with an oversampling rate of 833 kHz This analog input structure greatly simplifies transducer interface by providing a wide dynamic range for direct connection to the transducer and also by simplifying the antialiasing filter design A high pass filter in the current channel removes the dc component from the current signal This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals See the HPF and Offset Effects section The real power calculation is derived from the instantaneous power signal The instantaneous power signal is generated by a direct multiplication of the current and voltage signals of each phase In order to extract the real power component the dc component the instantaneous power signal is low pass filtered on each phase Figure 15 illustrates the instantaneous real power signal and shows how the real power information can be extracted by low pass filtering the instantaneous power signal This method is used to extract the real power information on each phase of the polyphase system The total real power information is th
30. laced in the current channel The phase correction net work ensures a phase match between the current channels and voltage channels to within 0 1 over a range of 45 Hz to 65 Hz and 0 2 over a range of 40 Hz to 1 kHz See Figure 24 and Figure 26 Power Supply Rejection PSR This quantifies the ADE7752 measurement error as a percentage of reading when the power supplies are varied For the ac PSR measurement a reading at a nominal supply 5 V is taken A 200 mV rms 100 Hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels Any error introduced is expressed as a percentage of reading See definition for Measurement Error For the dc PSR measurement a reading at nominal supplies 5 V is taken The supply is then varied 5 and a second reading is obtained with the same input signal levels Any error introduced is again expressed as a percentage of reading ADC Offset Error This refers to the dc offset associated with the analog inputs to the ADCs It means that with the analog inputs connected to AGND the ADCs still see an analog input signal offset However because the HPF is always present the offset is removed from the current channel and the power calculation is not affected by this offset Gain Error The gain error of the ADE7752 is defined as the difference between the measured output frequency minus the offset and the ideal output frequency The difference
31. ly functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability the human body and test equipment and can discharge without detection Although this product features AAT SI proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy SAT 4 electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ESD SENSITIVE DEVICE Rev C Page 5 of 24 ADE7752 ADE7752A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS cF ije 24 F1 DGND 2 23 F2 Voo 3 22 S1 REVP 4 21 SO iap s ADE7752 20 cLkouT ADE7752A IAN 6 Top view IBN 8 ABS ICP 9 16 VAP ICN 10 15 VBP AGND 11 14 VCP 02676 A 003 REFiniout 12 13 VN Figure 3 Pin Configuration Table 4 Pin Function Descriptions Pin No Mnemonic Description 1 CF Calibration Frequency Logic Output The CF logic output gives instantaneous real power information This output is intended to be used for calibration purposes See the SCF pin description 2 DGND This provides the ground reference for the digital circuitry in the ADE7752 the multiplier filters and digital to frequency converter Because the digital return currents in the A
32. nitial release and after any redesign or process change that may affect this parameter See Figure 2 3 The pulse widths of F1 F2 and CF are not fixed for higher output frequencies See the Frequency Outputs section 4 CF is not synchronous to F1 or F2 frequency outputs gt The CF pulse is always 1 us in the high frequency mode F1 e nT 02676 A 002 Figure 2 Timing Diagram for Frequency Outputs Rev C Page 4 of 24 ADE7752 ADE7752A ABSOLUTE MAXIMUM RATINGS Ta 25 C unless otherwise noted Table 3 Parameter Rating Voo to AGND 0 3 V to 7 V Voo to DGND 0 3 V to 7 V Analog Input Voltage to AGND VAP VBP VCP VN IAP IAN IBP IBN ICP and ICN 6 V to 6 V Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 24 Lead SOIC Power Dissipation Oja Thermal Impedance Lead Temperature Soldering Vapor Phase 60 sec Infrared 15 sec 0 3 V to Voo 0 3 V 0 3 V to Voo 0 3 V 0 3 V to Voo 0 3 V 40 C to 4 65 C to 4 150 C 88 mW 250 C W 215 C 220 C 85 C 150 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating on
33. offset on the current channel and voltage channel contribute a dc component after multiplication Since this dc component is extracted by the LPF and is used to generate the real power information for each phase the offsets contribute a constant error to the total real power calculation ov INTERNAL RESET INACTIVE ACTIVE INACTIVE 02676 A 023 Figure 23 On Chip Power Supply Monitor PHASE Degrees o o wo 02676 A 025 0 100 200 300 400 500 600 700 800 900 100 FREQUENCY Hz Figure 24 Phase Error Between Channels 0 Hz to 1 kHz This problem is easily avoided by the HPF in the current channels By removing the offset from at least one channel no error component can be generated at dc by the multiplication Error terms at cos wt are removed by the LPF and the digital to frequency conversion See the Digital to Frequency Conversion section f cos wt Vos x fr cos wt Ios VxI Vos X Ios Vos X I cos wt Ips x V cos wt x cos 2wt The HPFs in the current channels have an associated phase response that is compensated for on chip Figure 24 and Figure 26 show the phase error between channels with the compensation network The ADE7752 is phase compensated up to 1 kHz as shown This ensures correct active harmonic power calculation even at low power factors DC COMPONENT INCLUDING ERROR TERM IS EXTRACTED BY THE LPF FOR REAL Vos x los POWER CALCULATION Vxl
34. ple if the CF frequency is 20 Hz the CF pulse width is 25 ms One exception to this is when the mode is S0 1 SCF S1 0 In this case the CF pulse width is 66 of the period NO LOAD THRESHOLD The ADE7752 also includes no load threshold and start up cur rent features that eliminate any creep effects in the meter The ADE7752 is designed to issue a minimum output frequency Any load generating a frequency lower than this minimum fre quency does not cause a pulse to be issued on F1 F2 or CE The minimum output frequency is given as 0 005 of the full scale output frequency for each of the F 7 frequency selections or approximately 0 00204 of the Fi 7 frequency see Table 10 For example for an energy meter with a 100 imp kWhr meter constant using Fi 7 4 77 Hz the minimum output frequency at F1 or F2 would be 9 59 x 10 Hz This would be 1 54x 10 Hz at CF 16 x F1 Hz In this example the no load threshold would be equivalent to 3 45 W of load or a start up current of 15 70 mA at 240 V Table 10 CF F1 and F2 Minimum Frequency at No Load Threshold When selecting a suitable F 7 frequency for a meter design the frequency output at Imax maximum load with a 100 imp kWhr meter constant should be compared with column 5 of Table 9 The frequency closest to that listed in Table 9 is the best choice of frequency Fi 7 For example if a 3 phase 4 wire Wye meter with a 25 A maximum current is being designed the output
35. s the rms value of current harmonic n Bn is the phase angle of the current harmonic Using Equations 1 and 2 the real power P can be expressed in terms of its fundamental real power P and harmonic real power Pu P P Pu where P V xI cos 3 9 a B P V_xI cos H 2 n n Pn 4 gn a B As can be seen from Equation 4 a harmonic real power compo nent is generated for every harmonic provided that harmonic is present in both the voltage and current waveforms The power factor calculation has been shown to be accurate in the case of a pure sinusoid Therefore the harmonic real power must also correctly account for power factor since it is made up of a series of pure sinusoids Note that the input bandwidth of the analog inputs is 14 kHz with a master clock frequency of 10 MHz Rev C Page 13 of 24 ADE7752 ADE7752A ANALOG INPUTS CURRENT CHANNELS The voltage outputs from the current transducers are connected to the ADE7752 current channels which are fully differential voltage inputs IAP IBP and ICP are the positive inputs for IAN IBN and ICN respectively The maximum peak differential signal on the current channel should be less than 500 mV 353 mV rms for a pure sinusoidal signal for the specified operation Figure 17 illustrates the maximum signal levels on IAP and IAN The maximum differential voltage between IAP and IAN is 500 mV The differential voltage signal on the inpu
36. ts must be referenced to a common mode such as AGND The maxi mum common mode signal shown in Figure 17 is 25 mV IAP IAN 500mV Vom COMMON MODE Vow 25mV MAX 500mV 02676 A 017 Figure 17 Maximum Signal Levels Current Channel VOLTAGE CHANNELS The output of the line voltage transducer is connected to the ADE7752 at this analog input Voltage channels are a pseudo differential voltage input VAP VBP and VCP are the positive inputs with respect to VN The maximum peak differential signal on the voltage channel is 500 mV 353 mV rms for a pure sinusoidal signal for specified operation Figure 18 illustrates the maximum signal levels that can be connected to the voltage channels of the ADE7752 Voltage channels must be driven from a common mode voltage In other words the differential voltage signal on the input must be referenced to a common mode usually AGND The analog inputs of the ADE7752 can be driven with common mode voltages of up to 25 mV with respect to AGND However best results are achieved using a common mode equal to AGND VAP VN 500mV VAP O DIFFERENTIAL INPUT T500mV MAX PEAK 2 VA yy i O COMMON MODE vem 25mV MAX V AGND Vom 500mV 02676 A 018 Figure 18 Maximum Signal Levels Voltage Channel Rev C Page 14 of 24 ADE7752 ADE7752A TYPICAL CONNECTION DIAGRAMS CURRENT CHANNEL CONNECTION Figure 19 shows a typical connection diagram
37. us real VA ABS LPF gt MULTIPLIER X IA VB LPF MULTIPLIER Q IB vc LPF MULTIPLIER X Ic power signal The average value of a sinusoidal signal is zero Thus the frequency generated by the ADE7752 is proportional to the average real power Figure 27 shows the digital to frequency conversion for steady load conditions constant voltage and current As can be seen in Figure 27 the frequency output CF varies over time even under steady load conditions This frequency variation is primarily due to the cos 2wt components in the instantaneous real power signal The output frequency on CF can be up to 160 times higher than the frequency on F1 and F2 The higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time while converting it to a frequency This shorter accumulation period means less averaging of the cos 2wt component As a conse quence some of this instantaneous power signal passes through the digital to frequency conversion This is not a problem in the application Where CF is used for calibration purposes the frequency should be averaged by the frequency counter This removes any ripple If CF is being used to measure energy such as in a microprocessor based application the CF output should also be averaged to calculate power Because the outputs F1 and F2 operate at a much lower frequency much more averaging of the instantaneous real power signal is carr
38. ut fre quencies may vary from device to device due to reference tolerance of 8 6 181 x 0 5 x 0 5 x 0 60 Freq 3 x 0 483 Hz 1 2 47 Example 2 In this example with ac voltages of 500 mV peak applied to the voltage channels and current channels the expected output frequency is calculated as follows F 0 60 Hz SCF S0 S1 1 Van Ven Voy IA IB IC 0 5 500 mV peak AC Vrms V2 Vpgr 2 4 V nominal reference value Note that if the on chip reference is used actual output fre quencies may vary from device to device due to reference tolerance of 8 6 181 x 0 5 x 0 5 x 0 6 Freq 3 x 0 24 Hz V2 x y2 x 2 4 As can be seen from these two example calculations the maximum output frequency for ac inputs is always half of that for dc input signals The maximum frequency also depends on the number of phases connected to the ADE7752 In a 3 phase 3 wire delta service the maximum output frequency is different from the maximum output frequency in a 3 phase 4 wire Wye service The reason is that there are only two phases connected to the analog inputs but also that in a delta service the current channel input and voltage channel input of the same phase are not in phase in normal operation Example 3 In this example the ADE7752 is connected to a 3 phase 3 wire delta service as shown in Figure 21 The total real energy calculation processed in the ADE7752 can be expressed as Total Real Power
39. vasasesssevsssossuccadstiensscossvscssusiannsdestennddassusssesriosaecees 14 Current Channels enaren 14 Voltage Chanels sunnin eriein 14 Typical Connection Diagrams ssessssssssssssssssssssssrssrteesssssssssseee 15 Current Channel Connection cccecesesseseseessessesseeseseenees 15 REVISION HISTORY 7 05 Rev B to Rev C Added ADE7752A as Universal Changed NEGP Pin Name to REVP sssssssssssssssssessssssssss Universal Changes to Table Tara a E EE EEE 3 Changes to Table 6 Table 7 sssssssssssssssssssssssssssseesssssssssresreesssssssss 21 Changes to Table 8 Table 9 Table 10 n22 Updated Outline Dimensions 124 Changes to Ordering Guide ceeeeseessesesssesessessessesseesessessees 24 9 03 Rev A to Rev B Updated Formats c ccccianaeaceaaade Universal Change to Figure 9 ccsscssstesssevasssssssevasecestoacausbasesssaasvasevstabecesssstaoes 15 Voltage Channels Connection cscccessessessesesssessesseesseseeses 15 Meter Conn cHons ceecccs cesssessversces E E R RRE oes 15 Power Supply Monitor ceeeeesessesseeseesesseesessesseseeneeaeeaeeneeneenesses 17 FIPFianid Offset Effects evssszes sesscessvesnzessponeseservecsegnustaveseprastecenves 17 Digital to Frequency Conversion cccessesssessessesssesessesseeseeses 18 Mode Selection of the Sum of the Three Active Energies 19 Power Measurement Considerations ccesssseeseeseeseesees 19 Transfer F nctio N seai karainan Ea aa a aae 20

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