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ANALOG DEVICES ADV7189B handbook

1. No connection SETADC sw man en 1 Rev B Page 85 of 104 ADV7189B Bits Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes OxC4 ADC ADC2 SW 3 0 Manual muxing 0 0 0 0 Noconnection SETADC_sw_man_ SWITCH 2 control for ADC2 0lolo 1 Noconnection en 1 0 0 AIN2 0 0 1 1 Noconnection 0 140 0 Noconnection 0 1 0 1 AIN5 0 1 1 0 AING 0 141 1 Noconnection 1 0 0 0 Noconnection 110 0 1 Noconnection 1 0 140 AIN8 1 0 1 1 Noconnection 1 1 0 0 Noconnection 1 1 0 1 AIN11 1 1 14 04 AIN12 1 1 1 1 Noconnection Reserved x x ADC SW MAN EN Enable 0 Disable manual setting of the input 1 Enable signal muxing OxDC Letterbox LB TH 4 0 Sets the threshold 0 1 1 0 0 Default threshold for the Control 1 value that determines if a line is detection of black lines black Reserved 1 0 1 Set as default OxDE Reserved OxDD Letterbox LB EL 3 0 Programs the end line 0 0 LBdetection ends with Control 2 of the activity window for LB the last line of active detection end of field video on a field 1100b 262 525 LB SL 3 0 Program the start line 0 1 0 0 Letterbox detection of the activity window for LB aligned with the start of detection start of field active video 01
2. Rev B Page 49 of 104 ADV7189B CGMS Data Registers CGMS1 7 0 Address 0x96 7 0 CGMS2 7 0 Address 0x97 7 0 CGMS3 7 0 Address 0x98 7 0 Figure 33 shows the bit correspondence between the analog video waveform and the CGMS1 CGMS2 CGMSS registers CGMS3 7 4 are undetermined and should be masked out by software 100 IRE REF CGMS1 7 0 70 IRE Closed Caption Data Registers CCAP1 7 0 Address 0x99 7 0 CCAP2 7 0 Address 0x9A 7 0 Figure 34 shows the bit correspondence between the analog video waveform and the CCAP1 CCAP2 registers CCAP1 7 contains the parity bit from the first word CCAP2 7 contains the parity bit from the second word Refer to the GDECAD Gemstar Decode Ancillary Data Format Address Ox4C 0 section CGMS2 7 0 CGMS3 3 0 49 1us 0 515 2 23515 20ns Figure 33 CGMS Data Extraction Table 60 CGMS Access Information CRC SEQUENCE 04983 0 033 Signal Name Register Location Address Register Default Value CGMS1 7 0 CGMS 1 7 0 150d 0x96 Readback Only CGMS2 7 0 CGMS 2 7 0 151d 0x97 Readback Only CGMS3 3 0 CGMS 3 3 0 152d 0x98 Readback Only 10 5 0 25us 12 9118 7 CYCLES OOCK RUN AR CCAP1 7 0 CCAP2 7 0 TRAN of 2 5 2 1 2 4 5 6 7 A 50 IRE T Y Y BUS BYTE 1 40 IRE REFERENCE COLOR BURST 9 CYCLES FREQUENCY 3 579545MHz AMPLITUDE 40 IRE 10 003us E 27 382us
3. sse 8 Changes to Table 5 i besseren ERR tH I 9 Changes to Figure Girsin 13 Changes to Table 8 ette tee tinte 14 Update Table Formatting seen 19 Update Page Layout E 29 Change to Table 31 Update Table Formatting sentent 39 Change to Table 55 mittit bibet tnn 40 Changes to Figure 21 entere anteire rte 42 Update Page Formatting 49 Change Footnote Numbering in Table 84 67 Change to Table 85 eterne ideis ete a redes Change to Table 87 ttt ets Change to Table 88 Change to Table Numbering 9 04 Revision 0 Initial Version Outline eene deeem ea 101 Ordering Guide eite e et de 101 7 05 Rev 0 to Rev A Updated Format ette epe Universal Changes to Features i i e Ete e CHR ERU 1 Changes to Analog Specifications sse 6 Changes to Table 7 eene hv rers err erre ERN 11 Changes to Clamp Operation Section sess 26 Changes to Table 305 iie eet iri te pedem 29 Changes to Figure 12 Figure 13 Figure 14 and Figure 15 30 Added CSFM 2 0 C Shaping Filter Mode Address 0x17 7 Section and Changes to Figure 16 sse 31 Changes to Luma Gain Section see 32 Changes to Table 54 ertet epe Prep 41 Changes to VSEHO VS End Horizontal Position Odd Address 0 33 7 Section sese 42 Changes to
4. E o Y on AINT Pb on AIN4 Pr on AIN5 o Y on AIN2 Pb on AIN3 Pr on AIN6 YPbPr CVBS in on AIN7 CVBS in on AIN8 CVBS in on AIN9 CVBS in on AIN10 4 4 2 2 23 23 o 2 2 oilo o 2lo 2 o CVBS in on AIN11 Composite VID SEL 3 0 The VID SEL bits allow the user to select the input video standard Auto detect PAL BGHID NTSC J without pedestal SECAM Auto detect PAL BGHID NTSC M with pedestal SECAM Auto detect PAL N NTSC J SECAM PAL with pedestal Auto detect PAL N NTSC M SECAM PAL and NTSC with pedestal NTSC NTSC M PAL 60 NTSC 4 43 PAL BGHID gt gt PAL BGHID without pedestal PAL M without pedestal PALM PAL combination N PAL combination N SECAM with pedestal za m 2 2 2 olo 2 2 o o 23 o 3i o 3io SECAM with pedestal Rev B Page 72 of 104 ADV7189B Bits Subaddress Register Bit Description 7 6 5 4 3 2 Comments Notes 0x01 Video Reserved 0 Set to default Selection ENVSPROC 0 Disable Vsync processor 1 Enable Vsync processor Reserved 0 Set to
5. 2linesof video system must remain in lock before o 1 oF 5linesofvideo showing a locked status 0 1 1 10 lines of video 1 0 0 100 lines of video 1 O 1 500 lines of video 1 1 0 1000 lines of video 1 1 1 100000 lines of video COL 2 0 Count out of lock 1 line of video determines the number of lines the 0 01 2 lines of video system must remain out of lock before showing a lost locked SE status 0111 10 lines of video 1 0 0 100 lines of video 1 0 1 500 lines of video 1 110 1000 lines of video 1 141 100000 lines of video SRLS Select raw lock signal Selects 0 Over field with vertical the determination of the lock info Status 1 Line to line evaluation FSCLE Fsc lock enable 0 Lock status set only by horizontal lock 1 Lock status set by horizontal lock and subcarrier lock Ox8F Free Run Reserved 0 0 0 0 Set to default Line LLC_PAD_SEL 2 0 Enables manual LLC1 nominal 27 MHz Length 1 selection of clock for LLC1 pin selected out on LLC1 pin 1 0 1 LLC2 nominally 13 5 MHz For 16 bit 4 2 2 out selected out on LLC1 pin OF SEL 3 0 0010 Reserved 0 Set to default 0x90 VBI Info WSSD Screen signaling detected 0 No WSS detected Read only status bits Read Only 1 WSS detected CCAPD Closed caption data 0 No CCAP signals detected 1 CCAP sequence detected EDTVD EDTV sequence 0 No EDTV sequence detected 1 EDTV sequence detected CGMSD CGMS sequence 0 No CGMS transi
6. 1 1 POWER SUPPLY 1 DECOUPLING FOR 1 1 EACH POWER PIN P19 P10 10 ITU R BT 656 PIXEL DATA 27MHz 1 9 Cb AND Cr 20 BIT ITU R BT 656 PIXEL DATA 9 13 5MHz 1 P19 P10 Y 20 BIT ITU R BT 656 PIXEL DATA 2 13 5MHz r gt 27MHz OUTPUT CLOCK h 13 5MHz OUTPUT CLOCK OE lt OUTPUT ENABLE I P I INTERRUPT O P SFL O P HS O P i gt VSOP i_ FIELD O P 1 69kQ 10nF 2ko 0 MPU INTERFACE 82nF CONTROL LINES 1000 PVDD DVDDIO RESET 100nF G 3 DGND AGND DGND Figure 46 Typical Connection Diagram Rev B Page 100 of 104 ADV7189B OUTLINE DIMENSIONS TOP VIEW PINS DOWN 10 MAX COPLANARITY BSC VIEW A LEADPITCH ROTATED 90 CCW 0 22 COMPLIANT TO JEDEC STANDARDS MS 026 BEC Figure 47 80 Lead Low Profile Quad Flat Package LQFP ST 80 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7189BKSTZ 0 to 70 80 lead Low Profile Quad Flat Package LQFP ST 80 2 ADV7189BBSTZ 40 C to 85 C 80 lead Low Profile Quad Flat Package LQFP ST 80 2 EVAL ADV7189BEB Evaluation Board The ADV7189B is a Pb free environmentally friendly product It is manufactured using the most up to date materials and processes Th
7. 1 enables the color kill function and must be enabled for CKILLTHR 2 0 to take effect Reserved Set to default Rev B Page 82 of 104 ADV7189B Bits Subaddress Register Bit Description 7 6 5 4 3 2 Comments Notes 0x41 Resample Reserved 1 Set to default Control SFL_INV Controls the behavior of 0 SFL compatible with the PAL switch bit ADV7190 ADV7191 ADV7194 encoders 1 SFL compatible with ADV717x ADV7173x encoders Reserved 0 Set to default 0x48 Gemstar GDECEL 15 8 See the Comments 0 GDECEL 15 0 16 LSB Line 10 Control 1 column individual enable bits that MSB Line 25 0x49 Gemstar GDECEL 7 0 See the Comments select the lines of video Default Do not Control 2 column even field lines 10 to 25 check for Gemstar that the decoder checks compatible data on for Gemstar compatible any lines 10 to 25 in data even fields Ox4A Gemstar GDECOL 15 8 See the Comments GDECOL 15 0 16 LSB Line 10 Control 3 column individual enable bits that MSB Line 25 select the lines of video Default Do not 0x4B Gemstar GDECOL 7 0 See above 0 odd field lines 10 to 25 check for Gemstar that the decoder checks compatible data on Control 4 p for Gemstar compatible any lines 10 to 25 in data odd fields Ox4C Gemstar GDECAD Control
8. Chroma Gain Control 2 CMG 7 CMG 6 CMG 5 CMG 4 CMG 3 CMG 2 CMG 1 CMG 0 Luma Gain Control 1 LAGT 1 LGAT O LMG 11 LMG 10 LMG 9 LMG 8 Luma Gain Control 2 LMG 7 LMG 6 LMG 5 LMG 4 LMG 3 LMG 2 LMG 1 LMG O Vsync Field Control 1 NEWAVMODE HVSTIM Rev Page 65 of 104 ADV7189B Register Name Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit O Vsync Field VSBHO VSBHE Control 2 Vsync Field VSEHO VSEHE Control 3 Hsync Position HSB 10 HSB 9 HSB 8 HSE 10 HSE 9 HSE 8 Control 1 Hsync Position HSB 7 HSB 6 HSB 5 HSB 4 HSB 3 HSB 2 HSB 1 5 0 Control 2 Hsync Position HSE 7 HSE 6 HSE 5 HSE 4 HSE 3 HSE 2 HSE 1 HSE 0 Control 3 Polarity PHS PVS PF PCLK NTSC Comb CTAPSN 1 CTAPSN O CCMN 2 CCMN 1 CCMN O YCMN 2 YCMN 1 YCMN O Contro PAL Comb CTAPSP 1 CTAPSP O CCMP 2 CCMP 1 CCMP O YCMP 2 YCMP 1 0 ADC Control PWRDN ADC 0 PWRDN ADC 1 PWRDN ADC 2 Reserved Manua CKILLTHR 2 CKILLTHR 1 CKILLTHR O Window Contro Reserved Resample SFL INV Contro Reserved Gemstar Ctrl 1 GDECEL 15 GDECEL 14 GDECEL 13 GDECEL 12 GDECEL 11 GDECEL 10 GDECEL 9 GDECEL 8 Gemstar Ctrl 2 GDECEL 7 GDECEL 6 GDECEL 5 GDECEL 4 GDECEL 3 GDECEL 2 GDECEL 1 GDECEL O Gemstar Ctrl 3 GDECOL 1
9. Rev B Page 36 of 104 ADV7189B CTAPSP 1 0 Chroma Comb Taps PAL Address 0x39 7 6 Table 49 CTAPSP Function CTAPSP 1 0 Description 00 Do not use 01 PAL chroma comb adapts 5 lines 3 taps to 3 lines 2 taps cancels cross luma only 10 PAL chroma comb adapts 5 lines 5 taps to 3 lines 3 taps cancels cross luma and hue error less well 11 default PAL chroma comb adapts 5 lines 5 taps to 4 lines 4 taps cancels cross luma and hue error well CCMP 2 0 Chroma Comb Mode PAL Address 0x39 5 3 Table 50 CCMP Function CCMP 2 0 Description Configuration Oxx default Adaptive comb mode Adaptive 3 line chroma comb for CTAPSP 01 Adaptive 4 line chroma comb for CTAPSP 10 Adaptive 5 line chroma comb for CTAPSP 11 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 110 Fixed chroma comb all lines of line memory Fixed 3 line chroma comb for CTAPSP 01 Fixed 4 line chroma comb for CTAPSP 10 Fixed 5 line chroma comb for CTAPSP 11 111 Fixed chroma comb bottom lines of line memory Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 YCMP 2 0 Luma Comb Mode PAL Address 0x39 2 0 Table 51 YCMP Function YCMP 2 0 Description Configuration Oxx d
10. 0x1D 0x40 Enable 28 MHz crystal OxOF 0x40 TRAQ 0x3A 0x16 Power down ADC 1 and ADC 2 0x3D OxC3 MWE enable manual window Ox3F OxE4 BGB to 36 0x50 0x04 Set DNR threshold to 4 for flat response OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x50 0x20 Recommended setting 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 0xC5 Recommended setting 0 7 0 93 Recommended setting 0x7D 0x00 Recommended setting 0x90 0xC9 Recommended setting 0x91 0x40 Recommended setting 0x92 0x3C Recommended setting 0x93 OxCA Recommended setting 0x94 OxD5 Recommended setting OxCF 0x50 Recommended setting OxDO Ox4E Recommended setting OxD5 Recommended setting OxD6 OxDD Recommended setting 0 07 Recommended setting OxE4 Ox3E Recommended setting OxE5 0x51 Recommended setting OxE9 Ox3E Recommended setting OxEA OxOF Recommended setting OxOE 0x00 Recommended setting Rev B Page 90 of 104 Mode 2 S Video Input Y AIN1 AIN4 All standards are supported through autodetect 10 bit ITU R BT 656 output on P19 to P10 Table 88 Mode 2 S Video Input ADV7189B Register Address Register Value Notes 0x00 0x03 0x15 0x1D 0x3A Ox3D Ox3F 0x50 OxOE OxB3 0x50 0x52 0x58 0x77 0 7 Ox7D 0x90 0x91 0x92 0x93 0x94 OxCF OxDO OxD6 OxE5 OxD5 0 07
11. DEF_Y 3 DEF_Y 2 DEF_Y 1 DEF Y O DEF VAL AUTO _EN DEF_VAL_EN Default Value C DEF_C 7 DEF_C 6 DEF_C 5 DEF_C 4 DEF_C 3 DEF_C 2 DEF_C 1 DEF C0 ADI Control SUB USR EN O Power Management RES PWRDN PDBP Status 1 COL KILL AD RESULT 2 AD RESULT 1 AD RESULT O FOLLOW PW FSC LOCK LOST LOCK IN LOCK Ident IDENT 7 IDENT 6 IDENT 5 IDENT 4 IDENT 3 IDENT 2 IDENT 1 IDENT O Status 2 FSC NSTD LL NSTD MV AGC DET MV PS DET MVCS T3 MVCS DET Status 3 PAL SW LOCK INTERLACE STD FLD LEN FREE RUN ACT SD OP 50HZ GEMD INST HLOCK Analog Clamp Contro CCLEN Digital Clamp Control 1 DCT 1 DCT 0 Reserved Shaping Filter Contro CSFM 2 CSFM 1 CSFM O YSFM 4 YSFM 3 YSFM 2 YSFM 1 YSFM O Shaping Filter Control 2 WYSFMOVR WYSFM 4 WYSFM 3 WYSFM 2 WYSFM 1 WYSFM O Comb Filter Contro NSFSEL 1 NSFSEL O PSFSEL 1 PSFSEL O Reserved ADI Control 2 TRI LLC EN28XTAL VS JIT COMP EN Reserved Pixel Delay Contro SWPC AUTO PDC EN CTA 2 CTA 1 0 LTA 1 LTA O Reserved Misc Gain Contro CKE PW UPD AGC Mode Contro LAGC 2 LAGC 1 LAGC O CAGC 1 0 Control 1 1 CAGT O CMG 11 CMG 10 CMG 9 CMG 8
12. For more information on three state control refer to the Three State Output Drivers and the Three State LLC Drivers sections Individual drive strength controls are provided via the DR STR XX bits When TIM OE is 0 default HS VS and FIELD are three stated according to the TOD bit When TIM OE is 1 HS VS and FIELD are forced active all the time Drive Strength Selection Data DR STR 1 0 Address 0xF4 5 4 For EMC and crosstalk reasons it can be desirable to strengthen or weaken the drive strength of the output drivers The DR STR 1 0 bits affect the P 19 0 output drivers For more information on three state control refer to the Drive Strength Selection Clock and the Drive Strength Selection Sync sections Table 11 DR STR C Function DR STR C 1 0 Description 00 01 default 10 11 Low drive strength 1x Medium low drive strength 2x Medium high drive strength 3x High drive strength 4x Drive Strength Selection Clock DR STR C 1 0 Address 0xF4 3 2 The DR STR C 1 0 bits can be used to select the strength of the clock signal output driver LLC pin For more information refer to the Drive Strength Selection Sync and the Drive Strength Selection Data sections Table 12 STR C Function DR STR C 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4
13. STATUS 1 1 MEMORY 04983 0 009 Figure 9 Lock Related Signal Path Rev B Page 22 of 104 SRLS Select Raw Lock Signal Address 0 51 6 Using the SRLS bit the user can choose between two sources for determining the lock status per Bits 1 0 in the Status 1 register e The time_win signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video It reacts quickly e The free_run signal evaluates the properties of the incoming video over several fields and takes vertical synchronization information into account Setting SRLS to 0 default selects the free_run signal Setting SRLS to 1 selects the time_win signal FSCLE Fsc Lock Enable Address 0 51 7 The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits 1 0 in Status Register 1 This bit must be set to 0 when operating the ADV7189B in YPrPb component mode in order to generate a reliable HLOCK status bit Setting FSCLE to 0 default makes the overall lock status dependent on only the horizontal sync lock Setting FSCLE to 1 makes the overall lock status dependent on the horizontal sync lock and Fsc lock VS Coast 1 0 Address 0xF9 3 2 These bits are used to set VS free run coast frequency Table 19 VS_COAST 1 0 Function ADV7189B Table 20 CIL Function CIL 2 0 Descrip
14. 0x80 default Gain on luma channel 1 0x00 Gain on luma channel 0 OxFF Gain on luma channel 2 SD SAT Cb 7 0 SD Saturation Cb Channel Address OxE3 7 0 This register allows the user to control the gain of the Cb channel only The user can adjust the saturation of the picture Table 23 SD SAT Cb Function SD SAT Cb 7 0 Description 0x80 default Chroma gain 0 dB 0x00 Gain on Cb channel 42 dB OxFF Gain on Cb channel 6 dB Rev B Page 23 of 104 ADV7189B SD_SAT_Cr 7 0 SD Saturation Cr Channel Address 0 4 7 0 This register allows the user to control the gain of the Cr channel only Table 24 SD_SAT_Cr Function SD_SAT_Cr 7 0 Description The hue adjustment value is fed into the AM color demodulation block Therefore it only applies to video signals that contain chroma information in the form of an AM modulated carrier CVBS or Y C in PAL or NTSC It does not affect SECAM and does not work on component video inputs YPrPb Table 28 HUE Function 0x80 default 0x00 OxFF Chroma gain 0 dB Gain on Cb channel 42 dB Gain on Cb channel 6 dB SD OFF Cb 7 0 SD Offset Cb Channel Address OxE1 7 0 This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture There is a functional overlap with the Hue 7 0 register Table 25 SD OFF Cb Function HUE 7 0 Description 0x00 def
15. 1 Figure 21 NTSC Default BT 656 The polarity of H V and F is embedded in the data FIELD 1 04983 0 021 OUTPUT VIDEO HS OUTPUT vs OUTPUT FIELD NVBEG 4 0 0 0 NVEND A4 0 0x3 OUTPUT NFTOG 4 0 0x5 FIELD 2 264 2651 266 267 268 269 270 271 72 273 274 275 276 277eeel 1 1 output 3 VIDEO SE TIR de OUTPUT i A OUTPUT i NVBEG 4 0 0 0 NVEND A4 0 0x3 FIELD gt OUTPUT 9 NFTOG 4 0 0x5 04983 0 022 Figure 22 NTSC Typical Vsync Field Positions Using Register Writes Shown in Table 56 Rev B Page 42 of 104 ADV7189B Table 56 Recommended User Settings for NTSC See Figure 22 Register Register Name Write 0x31 Vsync Field Control 1 Ox1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Position Control 1 0x00 0x35 Hsync Position Control 2 0x00 0x36 Hsync Position Control 3 0x7D 0x37 Polarity OxA1 OxE5 NTSV V Bit Beg 0x41 OxE6 NTSC_V_Bit_End 0x84 OxE7 NTSC_F_Bit_Tog 0x06 NVBEGDELO NTSC Vsync Begin Delay on Odd Field Address 0xE5 7 When NVBEGDELO is 0 default there is no delay DELAY BEGIN OF VSYNC BY NVBEG 4 0 ADVANCE BEGIN OF BeUNC ENVEECIIO Setting NVBEGDELO to 1 delays Vsync going high on an odd field by a line relative to NVBEG NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 1 NVBEGSIGN NTSC Vsync Begin
16. Convert the readback value to decimal 0x47A 1146d 2 Apply Equation 2 to convert the readback value 1146 1024 1 12 CKE Color Kill Enable Address 0x2B 6 The color kill enable bit allows the optional color kill function to be switched on or off For QAM based video standards PAL and NTSC as well as FM based systems SECAM the threshold for the color kill decision is selectable via the CKILLTHR 2 0 bits If color kill is enabled and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines color processing is switched off black and white output To switch the color processing back on another 128 consecutive lines with a color burst greater than the threshold are required The color kill option only works for input signals with a modu lated chroma part For component input YPrPb there is no color kill Setting CKE to 0 disables color kill Setting CKE to 1 default enables color kill CKILLTHR 2 0 Color Kill Threshold Address 0x3D 6 4 The CKILLTHR 2 0 bits allow the user to select a threshold for the color kill function The threshold applies to only QAM based NTSC and PAL or FM modulated SECAM video standards To enable the color kill function the CKE bit must be set For settings 000 001 010 and 011 chroma demodulation inside the ADV7189B may not work satisfactorily for poor input video signals Table 42 CKILLTHR Function Descr
17. PRE WITH DIGITAL 04983 0 010 Figure 10 Clamping Overview Rev B Page 25 of 104 ADV7189B The following sections describe the I C signals that can be used to influence the behavior of the clamping block on the ADV7189B CCLEN Current Clamp Enable Address 0x14 4 The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether This can be useful if the incoming analog video signal is clamped externally When CCLEN is 0 the current sources are switched off When CCLEN is 1 default the current sources are enabled DCT 1 0 Digital Clamp Timing Address 0x15 6 5 The clamp timing register determines the time constant of the digital fine clamp circuitry It is important to realize that the digital fine clamp reacts very quickly because it is supposed to immediately correct any residual dc level error for the active line The time constant of the digital fine clamp must be much quicker than the one from the analog blocks By default the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal Table 29 DCT Function DCT 1 0 Description 00 Slow TC 1 sec 01 Medium TC 0 5 sec 10 default Fast TC 0 1 sec 11 Determined by the ADV7189B depending on the I P video parameters DCFE Digital Clamp Freeze Enable Address 0x15 4 This register bit allows the user to freeze the digital clamp loo
18. Table 55 ede nere tette tient 44 Changes to Table 845 69 Changesito Table 85 ette ree is 73 Changes to Table 86 ud ud P 91 Changes to Table 87 us s 92 Changes to Table 88 s s M 93 Changes to Table 89 esie ers eere iie rebas 94 Added XTAL Load Capacitor Value 99 Inserted Figure 44 Renumbered Sequentially 99 Changes to Figure 46 101 Updated Outline Dimensions BUT RUNI II UP 102 Changes to Ordering Guide sse 102 Rev B Page 3 of 104 ADV7189B INTRODUCTION The ADV7189B is a high quality single chip multiformat video decoder that automatically detects and converts PAL NTSC and SECAM standards in the form of composite S Video and component video into a digital ITU R BT 656 format The advanced and highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video charac teristics including tape based sources broadcast sources security surveillance cameras and professional systems ANALOG FRONT END The ADV7189B analog front end comprises three 12 bit noise shaped video ADCs that digitize the analog video signal before applying it to the standard definition processor
19. The analog front end employs differential channels to each ADC to ensure high performance in mixed signal applications The front end also includes a 12 channel input mux that enables multiple video signals to be applied to the ADV7189B Current and voltage clamps are positioned in front of each ADC to ensure the video signal remains within the range of the converter Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7189B The ADCs are configured to run in 4x oversampling mode STANDARD DEFINITION PROCESSOR The ADV7189B is capable of decoding a large selection of base band video signals in composite S Video and component formats The video standards supported by the ADV7189B include PAL B D I G H PAL60 PAL M PAL N PAL Nc NTSC NTSC 4 43 and SECAM B D G K L The ADV7189B can automatically detect the video standard and process it accordingly The ADV7189B has a 5 line super adaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required Video user controls such as brightness contrast saturation and hue are also available within the ADV7189B The ADV7189B implements a patented adaptive digital line length tracking ADLLT algorithm to track varying video line lengths
20. depending on what data was detected the appropriate data registers should be read The data registers are filled with decoded VBI data even if their corresponding detection bits are low it is likely that bits within the decoded data stream are wrong The closed captioning data CCAP is available in the IC registers and is also inserted into the output video data stream during horizontal blanking The Gemstar compatible data is not available in the PC registers and is inserted into the data stream only during horizontal blanking WSSD Wide Screen Signaling Detected Address 0x90 0 Logic 1 for this bit indicates the data in the WSS1 and WSS2 registers is valid The WSSD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the transmitted data When WSSD is 0 no WSS is detected and confidence in the decoded data is low When WSSD is 1 WSS is detected and confidence in the decoded data is high CCAPD Closed Caption Detected Address 0x90 1 Logic 1 for this bit indicates the data in the CCAP1 and CCAP2 registers is valid The CCAPD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the transmitted data When CCAPD is 0 no CCAP signals are detected and confidence in the decoded data is low When CCAPD is 1 the CCAP sequence is detected and confidence in the decod
21. e Chroma Resample The chroma data is digitally resampled to keep it perfectly aligned with the luma data The resampling is done to correct for static and dynamic line length errors of the incoming video signal e Chroma 2D Comb The two dimensional 5 line superadaptive comb filter provides high quality YC separation in case the input signal is CVBS e AV Code Insertion At this point the demodulated chroma Cr and Cb signal is merged with the retrieved luma values AV codes as per ITU R BT 656 can be inserted Rev B Page 20 of 104 ADV7189B SYNC PROCESSING The ADV7189B extracts syncs embedded in the video data stream There is currently no support for external HS VS inputs The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm The raw sync information is sent to a line length measurement and prediction block The output of this is then used to drive the digital resampling section to ensure that the ADV7189B outputs 720 active pixels per line The sync processing on the ADV7189B also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video e Vsync Processor This block provides extra filtering of the detected Vsyn
22. 0x2B 0 The peak white and average video algorithms determine the gain based on measurements taken from the active video The PW_UPD bit determines the rate of gain change LAGC 2 0 must be set to the appropriate mode to enable the peak white or average video mode in the first place For more information refer to the LAGC 2 0 Luma Automatic Gain Control Address 0x2C 7 0 section Setting PW_UPD to 0 updates the gain once per video line Setting PW_UPD to 1 default updates the gain once per field Chroma Gain CAGC 1 0 Chroma Automatic Gain Control Address 0x2C 1 0 The two bits of color automatic gain control mode select the basic mode of operation for automatic gain control in the chroma path Table 39 CAGC Function BETACAM Description 0 default Assuming YPrPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE CAGC 1 0 Description 00 Manual fixed gain use CMG 11 0 01 Use luma gain for chroma 10 default Automatic gain based on color burst 11 Freeze chroma gain 1 Assuming YPrPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant
23. 0x50 0x04 Set DNR threshold to 4 for flat response OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 5 Recommended setting 0 7 0 93 Recommended setting 0x7D 0x00 Recommended setting 0x90 0xC9 Recommended setting 0x91 0x40 Recommended setting 0x92 0x3C Recommended setting 0x93 OxCA Recommended setting 0x94 OxD5 Recommended setting OxCF 0x50 Recommended setting OxDO Ox4E Recommended setting OxD5 Recommended setting OxD6 OxDD Recommended setting 4 Recommended setting OxE5 0x51 Recommended setting OxE9 Ox3E Recommended setting OxOE 0x00 Recommended setting Rev B Page 92 of 104 Mode 4 CVBS Tuner Input PAL Only on AIN4 10 bit ITU R BT 656 output on P19 to P10 Table 90 Mode 4 CVBS Tuner Input PAL Only ADV7189B Register Address Register Value Notes 0x00 0x03 0x07 0x15 0x17 0x19 0x1D 0x3A 0x3D Ox3F 0x50 OxOE 0x50 0x52 0x58 0x77 0 7 Ox7D 0x90 0x91 0x92 0x93 0x94 OxCF OxDO OxD5 OxD6 0 07 OxE4 OxE5 OxE9 OxEA OxOE 0x83 0x00 0x01 0x00 0x41 OxFA 0x40 0x40 0x16 OxC3 OxE4 Ox0A 0x80 0x20 0x18 OxED 0xC5 0x93 0x00 0xC9 0x40 Ox3C OxCA OxD5 0x50 Ox4E OxAO OxDD OxEA Ox3E 0x51 Ox3E OxOF 0x00 CVBS AIN4 Force PAL only mode Enable 10 bit ou
24. 1 Detected FSC NSTD x Fsc frequency 1 Detected nonstandard Reserved x x 0x13 Status INST_HLOCK 1 horizontal lock Unfiltered Register 3 achieved Read Only GEMD 1 Gemstar data detected SD_OP_50HZ SD 60 Hz detected SD Field rate detect Reserved x SD 50 Hz detected FREE_RUN_ACT x 1 Free run mode active Blue screen output STD FLD_LEN x 1 Field length standard Correct Field length found INTERLACED x 1 Interlaced video Field sequence found detected PAL SW LOCK x 1 Swinging burst Reliable swinging detected burst sequence 0x14 Analog Reserved 0 Set to default Clamp CCLEN Current clamp enable 0 Current sources switched Control allows the user to switch off the off current sources in the analog front 1 Current sources enabled Reserved Set default Rev B Page 75 of 104 ADV7189B Subaddress Register Bit Description Comments Notes 0x15 Digital Clamp Control 1 Reserved Set to default DCT 1 0 Digital clamp timing determines the time constant of the digital fine clamp circuitry Slow TC 1 sec Medium TC 0 5 sec Fast TC 0 1 sec W olo o o TC dependent on video Reserved Set to default 0x17 Shaping Filter Control YSFM 4 0 Selects Y Shaping Filter mode when in CVBS only mode Allows the user to select a wide range of low pass and notch filters If either auto mode is se
25. 1 0 Chroma Automatic Gain Timing Address 0x2D 7 6 The chroma automatic gain timing register allows the user to influence the tracking speed of the chroma automatic gain control This register has an effect only if the CAGC 1 0 register is set to 10 automatic gain Table 40 CAGT Function CAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive Rev B Page 32 of 104 ADV7189B CG 11 0 Chroma Gain Address 0x2D 3 0 Address 0x2E 7 0 CMG 11 0 Chroma Manual Gain Address 0x2D 3 0 Address 0x2E 7 0 Chroma Gain 11 0 is a dual function register If written to a desired manual chroma gain can be programmed This gain becomes active if the CAGC 1 0 mode is switched to manual fixed gain Refer to Equation 2 for calculating a desired gain If read back this register returns the current gain value Depending on the setting in the CAGC 1 0 bits this is either e Chroma manual gain value CAGC 1 0 set to chroma manual gain mode e Chroma automatic gain value CAGC 1 0 set to any of the automatic modes Table 41 CG CMG Function CG 11 0 CMG 11 0 Read Write Description CMG 11 0 Write Manual gain for chroma path CG 11 0 Read Currently active gain 0 CG lt 4095 Chroma _ Gain 0 4 2 1024 For example freezing the automatic gain loop and reading back the CG 11 0 register results in a value of 0x47A 1
26. 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 Fixed 3 line chroma comb for CTAPSN 01 Fixed 4 line chroma comb for CTAPSN 10 Fixed 5 line chroma comb for CTAPSN 11 Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 YCMN 2 0 Luma Comb Mode NTSC Address 0x38 2 0 Table 47 Y CMN Function YCMN 2 0 Description Configuration Oxx default Adaptive comb mode Adaptive 3 line 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory 110 Fixed luma comb all lines of line memory 111 Fixed luma comb bottom lines of line memory Fixed 2 line 2 taps luma comb Fixed 3 line 3 taps luma comb Fixed 2 line 2 taps luma comb PAL Comb Filter Settings Used for PAL B G H I D PAL M PAL Combinational PAL 60 and NTSC443 CVBS inputs PSFSEL 1 0 Split Filter Selection PAL Address 0x19 1 0 The PSFSEL 1 0 control selects how much of the overall signal bandwidth is fed to the combs A wide split filter selection eliminates dot crawl but shows imperfections on diagonal lines The opposite is true for selecting a narrow bandwidth split filter Table 48 PSFSEL Function PSFSEL 1 0 Description 00 Narrow 01 default Medium 10 Wide 11 Widest
27. 34 Digital Noise Reduction DNR sse 34 Comb Filters yeyere arer Pg e er re 35 AV Code Insertion and Controls ses 38 Synchronization Output Signals sss 40 Sync Processing ceca rte te 48 VBI Data Decoder Re ees 48 Pixel Port Configuration sse 60 MPU Port Description 61 Register ACCESSES ce eR EIE es 62 Register Programming essent 62 DG Sequencerz cocotte tos CEA 62 PO Bes ister Maps sedeo esed esed eoe eed eed eed eS 63 Register Map Details eerte 67 PC Interrupt Register 68 Programming Examples eerte 90 Examples Using 28 MHz Clock ses 90 Examples Using 27 MHz Clock see 94 PCB Layout Recommendations sene 97 Analog Interface Inp ts eter tete ends 97 Power Supply Decoupling sse 97 M 97 Digital Outputs Both Data and Clocks 97 DigitalInp ts 2 epu Te PR 98 Aritialiasing Filters tieniti 98 Rev B Page 2 of 104 ADV7189B Crystal Load Capacitor Value Selection 98 Typical Circuit Connection seen 99 REVISION HISTORY 9 05 Rev A to Rev B Changes to Tables aerei rentrer i e tries 6 Changes to Table 2 5 eee RE E 7 Changes to Table 3 and Table 4
28. 6 5 4 3 2 1 0 Comments Notes 0x44 Interrupt SD_LOCK_MSKB 0 Masks SD_LOCK_Q bit Mask 1 1 Unmasks SD_LOCK_Q bit SD_UNLOCK_MSKB 0 Masks SD_UNLOCK_Q bit Read Write 1 Unmasks SD_UNLOCK_Q bit Register Reserved 0 Not used Reserved 0 Not used Register Access Reserved 0 Not used Page 2 SD_FR_CHNG_MSKB 0 Masks SD_FR_CHNG_Q bit 1 Unmasks SD_FR_CHNG_Q bit MV PS CS MSKB 0 Masks MV PS CS Qbit 1 Unmasks MV PS CS bit Reserved x Not used 0x45 Reserved X X X X X X x 0x46 Interrupt CCAPD Q 0 Closed captioning not detected These bits Status 2 in the input video signal can be 1 Closed captioning data cleared or Read Only detected in the video input masked by Register signal _ 0 Gemstar data not detected he input video signal Register Register the inp g 0x48 Access 1 Gemstar data detected in the respectively Page 2 input video signal CGMS_CHNGD_Q 0 No change detected in CGMS data in the input video signal 1 A change is detected in the CGMS data in the input video signal WSS CHNGD Q 0 No change detected in WSS data in the input video signal 1 A change is detected in the WSS data in the input video signal Reserved x Not used Reserved x Not used Reserved x Not used MPU_STIM_INTRQ_Q 0 Manual interrupt not set 1 Manual interrupt set 0x47 Interrupt CCAPD_CLR 0 Do not clear Clear 2 1 Clears CCAPD_Q bit GEMD_CLR 0 Do not clear Write Only 1 Clears GEMD_Q bit CGMS_CHNGD_CLR 0 Do not clear Register 1 Clears CGMS CHNGD Q
29. APPLICATIONS High end DVD recorders Video projectors HDD based PVRs DVDRs LCD TVs Set top boxes Professional video products AVR receivers The 12 analog input channels accept standard composite S Video YPrPb video signals in an extensive number of combinations AGC and clamp restore circuitry allow an input video signal peak to peak range of 0 5 V to 1 6 V Alternatively these can be bypassed for manual settings The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise accurate sampling and digital filtering The line locked clock output allows the output data rate timing signals and output clock signals to be synchronous asynchronous or line locked even with 5 line length variation The output control signals allow glueless interface connections in almost any application The ADV7189B modes are set up over a 2 wire serial bidirectional port PC compatible The ADV7189B is fabricated in a 3 3 V CMOS process Its monolithic CMOS construction ensures greater functionality with lower power dissipation The ADV7189B is packaged in a small 80 lead LQFP Pb free package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2005 Analog Devices Inc All rights reserved ADV7189B TABLE OF CONTENTS Introductio 4 Analog Front End a DERREEEREERA 4 Standard Definition Processor sse 4 F
30. Bit Description 716 5 43 Comments Notes Power Reserved Set to default Management PDBP Power down bit priority Chip power down selects between PWRDN bit or PIN controlled by pin Bit has priority pin disregarded Reserved 0 0 Set to default PWRDN Power down places the 0 System functional decoder in a full power down 1 Powered down See PDBP OxOF Bit 2 mode Reserved 0 Set to default RES Chip reset loads all 2 bits 0 Normal operation with default values 1 Start reset sequence Executing reset takes approx 2 ms This bit is self clearing 0x10 Status IN_LOCK In lock right now 1 Provides information Register 1 LOST_LOCK Lost lock since last read 1 about Read Only 7 status of the FSC_LOCK Fsc lock right now 1 decoder FOLLOW PW x Peak white AGC mode active 1 AD_RESULT 2 0 Autodetection 0 0 0 NTSM MJ Detected standard result reports the standard of the olol1 NTSC 443 Input video o lilo PALM 0 1 1 PAL 60 1 0 0 PAL BGHID 1 0 1 SECAM 1 1 0 PAL combination N 1 1 1 SECAM 525 COL_KILL Color kill is active 1 Color kill 0x11 IDENT IDENT 7 0 Provides identification X x x ADV7189B 0x13 Read Only on the revision of the part 0x12 Status MVCS DET MV color striping detected 1 Detected Register 2 MVCS MV color striping type 0 Type 2 Read Only 12 Type3 MV PS DET MV pseudo sync detected 1 Detected MV AGC DET x MV AGC pulses detected 1 Detected LL NSTD x Nonstandard line length
31. D 5 D 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 0 1 0 1 1 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev B Page 55 of 104 ADV7189B NTSC CCAP Data PAL CCAP Data Half byte output mode is selected by setting CDECAD 0 the Half byte output mode is selected by setting CDECAD 0 full byte mode is enabled by CDECAD 1 See the GDECAD full byte output mode is selected by setting CDECAD 1 Gemstar Decode Ancillary Data Format See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section The data packet formats are shown in Address 0x4C 0 section Table 72 and Table 73 list the bytes Table 70 and Table 71 of the data packet NTSC closed caption data is sliced on line 21d on even and odd PAL closed caption data is sliced from Lines 22 and 335 The fields The corresponding enable bit has to be set high See the corresponding enable bits have to be set section and the GDECOL 15 0 Gemstar Decoding Odd Lines See the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x4A 7 0 Address 0x4B 7 0 secti
32. Input Video Type Luma Gain Chroma Gain Any Manual gain luma Manual gain chroma CVBS Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak White Dependent on color burst amplitude Taken from luma path Y C Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak White Dependent on color burst amplitude Taken from luma path YPrPb Dependent on horizontal sync depth Taken from luma path Luma Gain LAGC 2 0 Luma Automatic Gain Control Address 0x2C 7 0 The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path There are ADI internal parameters to customize the peak white gain control Contact ADI sakes for more information Table 34 LAGC Function LAGC 2 0 Description 000 Manual fixed gain use LMG 11 0 001 AGC blank level to sync tip peak white algorithm off 010 default AGC blank level to sync tip peak white algorithm on 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Freeze gain LAGT 1 0 Luma Automatic Gain Timing Address Ox2F 7 6 The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control Note this register only has an effect if the LAGC 2 0 register is set to 001 010 011 or 100 automatic gain control modes If peak white AGC is enabled and active see the STATUS 1
33. Not used 001 Chroma 2 chroma pixel early 010 Chroma 4 1 chroma pixel early 011 default No delay 100 Chroma 1 chroma pixel late 101 Chroma 2 chroma pixel late 110 Chroma 3 chroma pixel late 111 Not used Rev B Page 39 of 104 ADV7189B SYNCHRONIZATION OUTPUT SIGNALS HS Configuration The following controls allow the user to configure the behavior of the HS output pin only e Beginning of HS signal via HSB 10 0 e 5 signal via HSE 10 0 e Polarity of HS using PHS The HS Begin and HS End registers allow the user to freely position the HS output pin within the video line The values in HSB 10 0 and HSE 10 0 are measured in pixel units from the falling edge of HS Using both values the user can program both the position and length of the HS output signal HSB 10 0 HS Begin Address 0x34 6 4 Address 0x35 7 0 The position of this edge is controlled by placing a binary number into HSB 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV code 00 00 XY see Figure 20 HSB is set to 00000000010b which is 2 LLC1 clock cycles from count 0 The default value of HSB is 0x002 indicating that the HS pulse starts two pixels after the falling edge of HS Table 55 HS Timing Parameters See Figure 20 HSE 10 0 HS End Address 0x34 2 0 Address 0x36 7 0 The position of this edge is controlled by placing a
34. OxE4 OxE9 OxEA OxOE 0x06 0x00 0x00 0x40 0x40 0x12 OxC3 OxE4 0x04 0x80 OxFE 0x20 0x18 OxED 0xC5 0x93 0x00 0xC9 0x40 Ox3C OxCA OxD5 0x50 Ox4E OxDD 0x51 OxAO OxEA Ox3E Ox3E OxOF 0x00 Y1 AINT C1 AINA Enable 10 bit output on P19 to P10 Slow down digital clamps Enable 28 MHz crystal TRAQ Power down ADC 2 MWE enable manual window BGB to 36 Set DNR threshold to 4 for flat response ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev B Page 91 of 104 ADV7189B Mode 3 YPrPb Input 5251 6251 Y on AIN2 Pr on AIN3 and Pb on AIN6 All standards are supported through autodetect 10 bit ITU R BT 656 output on P19 to P10 Table 89 Mode 3 YPrPb Input 5251 6251 Register Address Register Value Notes 0x00 Ox0A Y2 AIN2 Pr2 AIN3 Pb2 AIN6 0x03 0x00 Enable 10 bit output on P19 toP10 0x1D 0x40 Enable 28 MHz crystal 0x40 TRAQ
35. PAL V Bit End 0001 0100 rw 233 OxE9 PAL F Bit Toggle 01100011 rw 234 Reserved XXXX XXXX rw 235 to 243 OxEB to OxF3 Rev B Page 64 of 104 ADV7189B Register Name Reset Value rw Subaddress Dec Hex Drive Strength xx01 0101 rw 244 OxF4 Reserved XXXX XXXX rw 245 to 247 OxF5 to OxF7 IF Comp Control 0000 0000 rw 248 OxF8 VS Mode Control 0000 0000 rw 249 OxF9 Table 83 Common and Normal Page 1 Register Map Bit Names Register Name Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Control VID_SEL 3 VID_SEL 2 VID_SEL 1 VID_SEL O INSEL 3 INSEL 2 INSEL 1 INSEL O Video Selection ENHSPLL BETACAM ENVSPROC Reserved Output Control VBI_EN TOD OF_SEL 3 OF_SEL 2 OF_SEL 1 OF_SEL O SD_DUP_AV Extended Output Control BT656 4 TIM_OE BL C VBI EN SFL PI RANGE Reserved Reserved Autodetect Enable AD SEC525 EN AD SECAM EN AD N443 EN AD P60 EN AD PALN EN AD PALM EN AD NTSC EN AD PAL EN Contrast CON 7 CON 6 CON 5 CON 4 CON 3 CON 2 CON 1 CON O Reserved Brightness BRI 7 BRI 6 BRI 5 BRI 4 BRI 3 BRI 2 BRI 1 BRI O Hue HUE 7 HUE 6 HUE 5 HUE 4 HUE 3 HUE 2 HUE 1 HUE O Default Value Y DEF_Y 5 DEF_Y 4
36. Rev B Page 99 of 104 ADV7189B DVDDIO FERRITE BEAD 3V 33uF 10pF V DGND oann FERRITE BEAD PVDD 08V 33uF 10uF VN AGND FERRITE BEAD AVDD o 3V 33uF 10pF Tacno FERRITE BEAD DVDDG 1 8V AGND DGND CD asur Tour V DGND SVIDEO ANTIALIAS F L FILTER CIRCUIT 100nF Y ANTIALIAS r FILTER CIRCUIT 100nF Pr ANTIALIAS FILTER CIRCUIT Pb ANTIALIAS FILTER CIRCUIT e ANTIALIAS cEvS FILTER CIRCUIT i RECOMMENDED ANTIALIAS FILTER to 1 CIRCUIT IS SHOWN IN FIGURE 45 ON THE i Bs PREVIOUS PAGE THIS CIRCUIT INCLUDES 1 1 100nF 100nF 100nF V 750 TERMINATION RESISTOR INPUT i AGND BUFFER AND ANTIALIASING FILTER Sessa cease oe SS ae eae J AGND CAPY1 0 1uF 0 1uF 1 Eo CAPY2 0 1uF AGND lH 1 10uF 5 0 1nF 1 AGND CAPC2 CML 10 0 1pF REFOUT Y Y 10uF 0 1uF i 4 1CAPACITOR VALUES ARE DEPENDANT AGND 1MO 1 XTAL ATTRIBUTES i DVDDIO SELECT PC 2 Y ADDRESS i DGND DVSS DVDDIO DVDDIO O O 28 63636MHz CI 4 47pF Y DGND ADV7189B 1 o o1uF POWER SUPPLY Yoann V paNp 1 1 POWER SUPPLY Vacnp PACHPOWERPN i S E o 01uF POWER SUPPLY 1 DECOUPLING FOR EACH POWER
37. Sign Address 0 5 5 Setting NVBEGSIGN to 0 delays the start of Vsync Set for user manual programming NVBEGDELE NTSC Vsync Begin Delay on Even Field Address 0 5 6 When NVBEGDELE is 0 default there is no delay Setting NVBEGDELE to 1 delays Vsync going high on an even field by a line relative to NVBEG Setting NVBEGSIGN to 1 default advances the start of Vsync Not recommended for user programming NVBEG 4 0 NTSC Vsync Begin Address OxE5 4 0 1 0 0 ADVANCE BY 0 5 LINE lt lt ADVANCE BY 0 5 LINE 04983 0 023 Figure 23 NTSC Vsync Begin The default value of NVBEG is 00101 indicating the NTSC Vsync begin position For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified Rev B Page 43 of 104 ADV7189B ADVANCE END OF VSYNC BY NVEND 4 0 DELAY END OF VSYNC BY 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO ADDITIONAL DELAY BY 1LINE 1 0 ADVANCE BY 0 5 LINE 0 ADVANCE BY 0 5 LINE 04983 0 024 VSYNC END Figure 24 NTSC Vsync End NVENDDELO NTSC Vsync End Delay on Odd Field Address 0xE6 7 When NVENDDELO is 0 default there is no delay Setting NVENDDELO to 1 delays Vsync from going low on an odd field by a line relative to NVEND NVENDDELE NTSC Vsync End Delay on Even Field Address OxE6 6 When NVENDDELE is set to 0 default there is no delay Set
38. The Gemstar compatible data recovery block GSCD supports 1x and 2x data transmissions In addition it can serve asa closed caption decoder Gemstar compatible data transmissions can occur only in NTSC Closed caption data can be decoded in both PAL and NTSC Rev B Page 51 of 104 ADV7189B The block is configured via in the following ways e GDECEL 15 0 allow data recovery on selected video lines on even fields to be enabled and disabled e GDECOL 15 0 enable the data recovery on selected lines for odd fields e GDECAD configures the way in which data is embedded in the video data stream The recovered data is not available through but is being inserted into the horizontal blanking period of an ITU R BT656 compatible data stream The data format is intended to comply with the recommendation by the International Telecommunications Union ITU R BT 1364 See Figure 35 For more information see the ITU website at www itu ch The format of the data packet depends on the following criteria e Transmission is 1x or 2x e is output in 8 bit or 4 bit format see the description of the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 bit e Data is closed caption CCAP or Gemstar compatible Data packets are output if the corresponding enable bit is set see the GDECEL and GDECOL descriptions and if the decoder detects the presence of data This means for video lines where no data has
39. This section describes the configuration of each register The communications register is an 8 bit write only register After the part has been accessed over the bus and a read write opera tion is selected the subaddress is set up The subaddress register determines to from which register the operation takes place Table 82 lists the various operations under the control of the Subaddress register for the control port Register Select SR7 SRO These bits are set up to point to the required starting address 2 SEQUENCER An sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more I C registers for example HSB 11 0 When such a parameter is changed using two or more write operations the parameter can hold an invalid value for the time between the first being completed and the last being completed In other words the top bits of the parameter can already hold the new value while the remaining bits of the parameter still hold the previous value To avoid this problem the sequencer holds the already updated bits of the parameter in local memory all bits of the parameter are updated together once the last register write operation has completed The correct operation of the IC sequencer relies on the following e AIIT C registers for the parameter in question must be written to in order of ascending addresses For example for HSB 10 0 write to Address 0
40. a fixed response and some shaping filters YSH that have selectable responses e Luma Gain Control The automatic gain control AGC can operate on a variety of different modes including gain based on the depth of the horizontal sync pulse peak white mode and fixed manual gain e Luma Resample To correct for line length errors and dynamic line length changes the data is digitally resampled e Luma 2D Comb The two dimensional comb filter provides YC separation e AV Code Insertion At this point the decoded luma Y signal is merged with the retrieved chroma values AV codes as per ITU R BT 656 can be inserted SD CHROMA PATH The input signal is processed by the following blocks e Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Chroma Demodulation This block employs a color sub carrier Fsc recovery unit to regenerate the color subcarrier for any modulated chroma scheme The demodulation block then performs an AM demodulation for PAL and NTSC and an FM demodulation for SECAM e Chroma Filter Block This block contains a chroma decimation filter CAA with a fixed response and some shaping filters CSH that have selectable responses e Gain Control Automatic gain control AGC can operate on several different modes including gain based on the color subcarrier s amplitude gain based on the depth of the horizontal sync pulse on the luma channel or fixed manual gain
41. binary num ber into HSE 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FE 00 00 XY see Figure 20 HSE is set to 00000000000b which is 0 LLC1 clock cycles from count 0 The default value of HSE 10 0 is 000 indicating that the HS pulse ends zero pixels after falling edge of HS For example 1 To shift the HS toward active video by 20 LLC1s add 20 LLCIs to both HSB and HSE that is HSB 10 0 00000010110 HSE 10 0 00000010100 2 To shift the HS away from active video by 20 LLCIs add 1696 LLC1s to both HSB and HSE for NTSC that is HSB 10 0 1101010010 HSE 10 0 11010100000 1696 is derived from the NTSC total number of pixels 1716 To move 20 LLC1s away from active video is equal to subtracting 20 from 1716 and adding the result in binary to both HSB 10 0 and HSE 10 0 PHS Polarity HS Address 0x37 7 The polarity of the HS pin can be inverted using the PHS bit When PHS is 0 default HS is active high When PHS is 1 HS is active low Characteristic HS to Active Video LLC1 Active Video Total LLC1 HS Begin Adjust HS End Adjust Clock Cycles Samples Line Clock Cycles Standard HSB 10 0 Default HSE 10 0 Default Cin Figure 20 Default D in Figure 20 E in Figure 20 NTSC 00000000010b 00000000000b 272 720Y 720C 1440 1716 NTSC Square 00000000010b 00000000000b 276 640Y 640C 12
42. bit Access Page 2 WSS CHNGD CLR 0 Do not clear Clears WSS_CHNGD_Q bit Reserved x Not used Reserved x Not used Reserved x Not used MPU_STIM_INTRQ_CLR 0 Do not clear 1 Clears MPU_STIM_INTRQ_Q bit Rev B Page 69 of 104 ADV7189B Bit Subaddress Register Bit Description 6 5 4 3 Comments Notes 0x48 Interrupt CCAPD_MSKB Masks CCAPD_Q bit Mask 2 Unmasks CCAPD_Q bit GEMD_MSKB Masks GEMD_Q bit Unmasks GEMD_Q bit rite CGMS CHNGD MSKB Masks CGMS CHNGD Q bit Unmasks CGMS_CHNGD_Q bit Register Access WSS_CHNGD_MSKB 0 Masks WSS_CHNGD_Q bit Page 2 1 Unmasks WSS_CHNGD_Q bit Reserved 0 Not used Reserved 0 Not used Reserved 0 Not used MPU_STIM_INTRQ_MSKB Masks MPU_STIM_INTRQ_Q bit Unmasks MPU_STIM_INTRQ_Q bit 0x49 Raw Status SD OP 50Hz SD 60 Hz signal output These bits 3 SD 60 50Hz frame rate at SD 50 Hz signal output cannot be output cleared or ReadOnly SD V LOCK SD vertical sync lock not ien Regist i egister established Ox4A is used SD vertical sync lock for this Register established purpose Access SD_H_LOCK SD horizontal sync lock not Page 2 established SD horizontal sync lock established Reserved x Not used SCM_LOCK 0 SECAM lock not established SECAM Lock 1 SECAM lock established Reserved x Not used Reserved x Not used Reserved Not used Ox4A Interrupt SD OP CHNG Q
43. bit determines the direction of the data Logic 0 on the LSB of the first byte means the master writes information to the peripheral Logic 1 on the LSB ofthe first byte means the master reads information from the peripheral The ADV7189B acts as a standard slave device on the bus The data on the SDA pin is eight bits long supporting the 7 bit addresses plus the R W bit The ADV7189B has 249 subaddresses to enable access to the internal registers It therefore interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses auto increment allowing data to be written to or read from the starting subaddress A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without having to update all the registers Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCLK high period the user should only issue one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADV7189B does not issue an acknowledge and returns to the idle condition If in auto increment mode the user exceeds the highest subaddress the following action is taken 1 Inread
44. bit goes high for a valid checksum ADI recommended setting Wide Screen Signaling Data WSS1 7 0 Address 0x91 7 0 WSS2 7 0 Address 0 92 7 0 1 7 RUN IN START SEQUENCE CODE 38 4us 42 5us WSS1 7 0 Figure 31 shows the bit correspondence between the analog video waveform and the WSS1 WSS2 registers WSS2 7 6 are undetermined and should be masked out by software EDTV Data Registers EDTV1 7 0 Address 0x93 7 0 EDTV2 7 0 Address 0x94 7 0 EDTV3 7 0 Address 0x95 7 0 Figure 32 shows the bit correspondence between the analog video waveform and the EDTV1 EDTV2 EDTV3 registers EDTV3 7 6 are undetermined and should be masked out by software EDTV3 5 is reserved for future use and for now contains a 0 The three LSBs of the EDTV waveform are currently not supported wssors o ACTIVE VIDEO 04983 0 031 Figure 31 WSS Data Extraction Table 58 WSS Access Information Signal Name Register Location Address Register Default Value WSS1 7 0 WSS 1 7 0 145d 0x91 Readback Only WSS2 5 0 WSS 2 5 0 146d 0x92 Readback Only EDTV1 7 0 EDTV2 7 0 EDTV3 5 0 NOT SUPPORTED 04983 0 032 Figure 32 EDTV Data Extraction Table 59 EDTV Access Information Signal Name Register Location Address Register Default Value EDTV1 7 0 EDTV 1 7 0 147d 0x93 Readback Only EDTV2 7 0 EDTV 2 7 0 148d 0x94 Readback Only EDTV3 7 0 EDTV 3 7 0 149d 0x95 Readback Only
45. continues to drive low until the SD LOCK bit is either masked or cleared Interrupt Drive Level The ADV7189B resets with open drain enabled and all interrupts masked off Therefore INTRQ is in a high impedance state after reset 01 or 10 has to be written to INTRQ OP SEL 1 0 for a logic level to be driven out from the INTRQ pin It is also possible to write to a register in the ADV7189B that manually asserts the INTRQ pin This bitis MPU STIM INTRQ detection as follows MV INTRQ SEL 1 0 Macrovision Interrupt Selection Bits Address 0x40 Interrupt Space 5 4 Table 78 MV INTRQ SEL MV INTRQ SEL 1 0 Description 00 01 default 10 11 Reserved Pseudo sync only Color stripe only Either pseudo sync or color stripe Additional information relating to the interrupt system is detailed in Table 84 Rev B Page 59 of 104 ADV7189B PIXEL PORT CONFIGURATION The ADV7189B has a very flexible pixel port that can be config ured in a variety of formats to accommodate downstream ICs Table 79 and Table 80 summarize the various functions that the ADV7189B pins can have in different modes of operation The ordering of components for example Cr vs Cb CHA B C can be changed Refer to the SWPC Swap Pixel Cr Cb Address 0x27 7 section Table 79 indicates the default positions for the Cr Cb components OF SEL 3 0 Output Format Selection Address 0x03 5 2 The modes in which the A
46. default BETACAM 0 Standard video input 1 Betacam input enable ENHSPLL 0 Disable Hsync processor 1 Enable Hsync processor Reserved 1 Set to default 0x03 Output SD_DUP_AV Duplicates the AV AV codes to suit 8 bit Control codes from the luma into the interleaved data output chroma path AV codes duplicated for 16 bit interfaces Reserved Set as default OF_SEL 3 0 Allows the user to 0 10 bit LLC1 4 2 2 choose from a set of output ITU R BT 656 formats 1 20 bit LLC1 4 2 2 0 0 1 0 16 bit LLC1 4 2 2 0 0 1 1 8 bit LLC1 4 2 2 ITU R BT 656 1 0 0 Not used 0 1 0 1 Not used o 1 1 0 Not used Oo 1 1 1 Not used 1 0 0 Not used 1 0 0 1 Not used 1 0 1 0 Not used 1 0 1 1 Not used 111 0 Not used 1 1 0 1 Not used 1 1 11 0 Not used 1 1 1 1 Not used TOD Three State Output Drivers 0 Output pins enabled See also TIM_OE and This bit allows the user to three TRI LLC state the output drivers P 19 0 HS 1 Drivers three stated VS FIELD and SFL VBI EN Allows VBI data Lines 1 to 0 All lines filtered and scaled 21 to be passed through with only Only active video region a minimum amount of filtering filtered performed 0x04 Extended RANGE Allows the user to select 16 lt Y lt 235 16 lt C lt 240 ITU R BT 656 Output the range of output values Can be 1 Y 254 1 C 254 Extended range Control BT656 compliant or can fill the whole accessible number range EN SFL PIN SFL output is disabl
47. field identifier EF 1 indicates that the data was recovered from a video line on an even field 2x This bit indicates whether the data sliced was in Gemstar 1x or 2x format A high indicates 2x format Line 3 0 This entry provides a unique code for each of the possible 16 source lines of video from which Gemstar data may have been retrieved See Table 74 and Table 75 DC 1 0 Data count value The number of user data words in the packet divided by 4 The number of user data words UDW in any packet must be an integral number of 4 Padding is required at the end if necessary requirement as set in ITU R BT 1364 See Table 65 The 2x bit determines whether the raw information retrieved from the video line was 2 or 4 bytes The state of the GDECAD bit affects whether the bytes are trans mitted straight that is two bytes transmitted as two bytes or whether they are split into nibbles that is two bytes transmitted as four half bytes Padding bytes are then added where necessary CS 82 The checksum is provided to determine the integrity of the ancillary data packet It is calculated by summing up D 8 2 of DID SDID the Data Count byte and all UDWs and ignoring any overflow during the summation Since all data bytes that are used to calculate the checksum have their 2 LSBs set to 0 the CS 1 0 bits are also always 0 CS 8 describes the logic inversion of CS 8 The value ICS 8 is included in the checksum entry of
48. internal controls contact ADI sales for more information NTSC Comb Filter Settings Used for NTSC M J CVBS inputs NSFSEL 1 0 Split Filter Selection NTSC Address 0x19 3 2 The NSFSEL 1 0 control selects how much of the overall signal bandwidth is fed to the combs A narrow split filter selection gives better performance on diagonal lines but leaves more dot crawl in the final output image The opposite is true for selecting a wide bandwidth split filter Table 44 NSFSEL Function NSFSEL 1 0 Description 00 default Narrow 01 Medium 10 Medium 11 Wide CTAPSN 1 0 Chroma Comb Taps NTSC Address 0x38 7 6 Table 45 CTAPSN Function CTAPSN 1 0 Description 00 Do not use 01 NTSC chroma comb adapts 3 lines 3 taps to 2 lines 2 taps NTSC chroma comb adapts 5 lines 5 taps to 3 lines 3 taps 11 NTSC chroma comb adapts 5 lines 5 taps to 4 lines 4 taps 10 default Rev B Page 35 of 104 ADV7189B CCMN 2 0 Chroma Comb Mode NTSC Address 0x38 5 3 Table 46 CCMN Function CCMN 2 0 Description Configuration Oxx default Adaptive comb mode 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory 110 Fixed chroma comb all lines of line memory 111 Fixed chroma comb bottom lines of line memory Adaptive 3 line chroma comb for CTAPSN 01 Adaptive 4 line chroma comb for CTAPSN 10 Adaptive 5 line chroma comb for CTAPSN 11 Fixed
49. line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video characteristics including tape based sources broadcast sources security surveillance cameras and professional systems The 12 bit accurate A D conversion provides professional quality video performance and is unmatched This allows true 10 bit resolution in the 10 bit output mode Rev B Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 0 5 V to 1 6 V analog signal input range Differential gain 0 496 typ Differential phase 0 4 typ Programmable video controls Peak white hue brightness saturation contrast Integrated on chip video timing generator Free run mode generates stable video output with no I P VBI decode support for close captioning WSS CGMS EDTV Gemstar 1x 2x Power down mode 2 wire serial MPU interface IC compatible 3 3 V analog 1 8 V digital core 3 3 V IO supply 2 temperature grades 0 C to 70 C and 40 C to 85 C 80 lead LQFP Pb free package
50. mode the highest subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read A no acknowledge condition is when the SDA line is not pulled low on the ninth pulse M In write mode the data for the invalid byte is not loaded into any subaddress register a no acknowledge is issued by the ADV7189B and the part returns to the idle condition l 0 DATA ACK STOP 04983 0 036 Figure 39 Bus Data Transfer WRIT SEQUENCE S SLAVE as sue ADDR Jas fao LSB 0 LSB 1 i 80 5 Stave oon AGI sue aoon no S SAVE ADR AST oaa fao oa Ron S START BIT P STOP BIT A S ACKNOWLEDGE BY SLAVE A M ACKNOWLEDGE BY MASTER A S NO ACKNOWLEDGE BY SLAVE A M NO ACKNOWLEDGE BY MASTER 04983 0 037 Figure 40 Read and Write Sequence Rev B Page 61 of 104 ADV7189B REGISTER ACCESSES The MPU can write to or read from most of the ADV7189B s registers excepting the registers that are read only or write only The subaddress register determines which register the next read or write operation accesses All communications with the part through the bus start with an access to the subaddress register Then a read write operation is performed from to the target address which then increments to the next address until a stop command on the bus is performed REGISTER PROGRAMMING
51. normal as per the Timing Diagrams Rev B Page 18 of 104 GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder The IDENT register allows the user to identify the revision code of the ADV7189B The other three registers contain status bits from the ADV7189B IDENTIFICATION IDENT 7 0 Address 0x11 7 0 This register provides identification of the revision of the ADV7189B An identification value of 0x11 indicates the ADV7189 released silicon An identification value of 0x13 indicates the ADV7189B silicon STATUS 1 STATUS 1 7 0 Address 0x10 7 0 This read only register provides information about the internal status of the ADV7189B These bits are used to set VS free run coast frequency See the VS Coast 1 0 Address OxF9 3 2 section and COL 2 0 Count Out of Lock Address 0x51 5 3 for information on the timing Depending on the setting of the FSCLE bit the Status 0 and Status 1 are based solely on horizontal timing information or on the horizontal timing and lock status of the color subcarrier See the FSCLE FSC Lock Enable Address 0x51 7 section SD AUTODETECTION RESULT AD RESULT 2 0 Address 0x10 6 4 The AD RESULTT 2 0 bits report back on the findings from the autodetection block For more information on enabling the autodetection block see the General Setup section For information on configuring it see the Autodetection of SD Modes section Table 14 AD RE
52. subcarrier Fsc For good quality CVBS signals this relationship is known the comb filter algorithms can be used to separate out luma and chroma with high accuracy With nonstandard video signals the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block Rev B Page 26 of 104 An automatic mode for Y shaped filtering is provided In this mode the ADV7189B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard YFSM WYSFMOVR and WYSFM allow the user to manually override these automatic decisions in part or in full The luma shaping filter has three control registers e YSFM 4 0 allows the user to manually select a shaping filter mode applied to all video signals or to enable an automatic selection dependent on video quality and video standard e WYSFMOVR allows the user to manually override the WYSFM decision WYSFM 4 0 allows the user to select a different shaping filter mode for good quality CVBS component YPrPb and S VHS YC input signals In automatic mode the system preserves the maximum possible bandwidth for good CVBS sources since they can successfully be combed as well as for luma components of YPrPb and YC sources since they need not be combed For poor quality signals the system se
53. the data packet to ensure that the reserved values of 0x00 and OxFF do not occur Table 66 to Table 69 outline the possible data packages Gemstar 2x Format Half Byte Output Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Gemstar 1x Format Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Rev B Page 53 of 104 ADV7189B Table 66 Gemstar 2x Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 1 Line 3 0 0 0 SDID 5 0 0 0 0 1 0 0 0 Data count 6 IEP EP 0 0 Gemstar word1 7 4 0 0 User data words 7 IEP EP 0 0 Gemstar word1 3 0 0 0 User data words 8 IEP EP 0 0 Gemstar word2 7 4 0 0 User data words 9 IEP EP 0 0 Gemstar word2 3 0 0 0 User data words 10 IEP EP 0 0 Gemstar word3 7 4 0 0 User data words 11 IEP EP 0 0 G
54. to Ox1C ADI Control 2 0000 0xxx rw 29 0x1D Reserved XXXX XXXX rw 30 to 38 Ox1E to 0x26 Pixel Delay Control 0101 1000 rw 39 0x27 Reserved XXXX XXXX rw 40 to 42 0x28 to 0x2A Misc Gain Control 1110 0001 rw 43 0x2B AGC Mode Control 1010 1110 rw 44 0 2 Chroma Gain Control 1 11110100 rw 45 Ox2D Chroma Gain Control 2 0000 0000 rw 46 Ox2E Luma Gain Control 1 1111 xxxx rw 47 Ox2F Luma Gain Control 2 XXXX XXXX rw 48 0x30 Vsync Field Control 1 0001 0010 rw 49 0x31 Vsync Field Control 2 0100 0001 rw 50 0x32 Vsync Field Control 3 1000 0100 rw 51 0x33 Hsync Position Control 1 0000 0000 rw 52 0x34 Hsync Position Control 2 0000 0010 rw 53 0x35 Hsync Position Control 3 0000 0000 rw 54 0x36 Polarity 0000 0001 rw 55 0x37 NTSC Comb Control 1000 0000 rw 56 0x38 PAL Comb Control 1100 0000 rw 57 0x39 ADC Control 0001 0000 rw 58 0x3A Reserved XXXX XXXX rw 59 to 60 Ox3B to Ox3C Manual Window Control 0100 0011 rw 61 0x3D Rev B Page 63 of 104 ADV7189B Subaddress Register Name Reset Value rw Dec Hex Reserved XXXX XXXX rw 62 to 64 Ox3E to 0x40 Resample Control 0100 0001 rw 65 0x41 Reserved XXXX XXXX rw 66 to 71 0x42 to 0x47 Gemstar Ctrl 1 00000000 rw 72 0x48 Gemstar Ctrl 2 0000 0000 rw 73 0x49 Gemstar Ctrl 3 0000 0000 rw 74 Ox4A Gemstar Ctrl 4 0000 0000 rw 75 4 GemStar Ctrl 5 XX
55. 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 2X Line 3 0 0 0 SDID 5 0 0 0 0 DC 1 DC 0 0 0 Data count DC 6 IEP EP 0 0 Word1 7 4 0 0 User data words 7 0 0 Word1 3 0 0 0 User data words 8 IEP EP 0 0 Word2 7 4 0 0 User data words 9 IEP EP 0 0 Word2 3 0 0 0 User data words 10 IEP EP 0 0 Word3 7 4 0 0 User data words 11 IEP EP 0 0 Word3 3 0 0 0 User data words 12 IEP EP 0 0 Word4 7 4 0 0 User data words 13 IEP EP 0 0 Word4 3 0 0 0 User data words 14 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 0 0 Checksum Rev B Page 52 of 104 Table 65 Data Byte Allocation ADV7189B Raw Information Bytes User Data Words 2x Retrieved from the Video Line GDECAD Including Padding Padding Bytes DC 1 0 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 Gemstar Bit Names DID The data identification value is 0x140 10 bit value Care has been taken that in 8 bit systems the 2 LSBs do not carry vital information EP and EP The EP bit is set to ensure even parity on the data word D 8 0 Even parity means there is always an even number of 1s within the D 8 0 bit arrangement This includes the EP bit describes the logic inverse of EP and is output on D 9 The EP is output to ensure that the reserved codes of 00 and FF cannot happen EF Even
56. 00b 23 286 NTSC OxDF Reserved Reserved 1 1 1 SD Offset SD_OFF_CB 7 0 Adjusts the hue 1 0 0 0 0 Cb by selecting the offset for the Cb channel OxE2 SD Offset SD_OFF_CR 7 0 Adjusts the hue 1 0 0 Cr by selecting the offset for the Cr channel OxE3 SD SD_SAT_CB 7 0 Adjusts the 1 0 0 O 0 0 0J 0 Chroma gain 0 dB Saturation saturation of the picture by Cb affecting gain on the Cb channel OxE4 SD SD SAT CR 7 0 Adjusts the 1 0 0 0 0 0 O O Chroma gain 0 dB Saturation saturation of the picture by Cr affecting gain on the Cr channel Rev B Page 86 of 104 ADV7189B Bits Subaddress Register Bit Description 4 3 Comments Notes OxE5 NTSC Bit NVBEG 4 0 How many lines after 0 0 NTSC default BT 656 Begin Icount rollover to set V high NVBEGSIGN Set to low when manual programming Not suitable for user programming NVBEGDELE Delay V bit going No delay high by one line relative to Additional delay by NVBEG even field 1line NVBEGDELO Delay V bit going No delay high by one line relative to Additional delay by NVBEG odd field 1line OxE6 NTSC V Bit NVEND 4 0 How many lines 0 0 NTSC default BT 656 End after Icounr rollover to set V low NVENDSIGN Set to low when manual programming Not suitable
57. 01 AIN5 0110 AIN6 0110 AIN6 0110 AIN6 0111 No Connection 0111 No Connection 0111 No Connection 1000 No Connection 1000 No Connection 1000 No Connection 1001 AIN7 1001 No Connection 1001 No Connection 1010 AIN8 1010 No Connection 1010 AIN8 1011 AIN9 1011 AIN9 1011 No Connection 1100 AIN10 1100 AIN10 1100 No Connection 1101 AIN11 1101 AIN11 1101 AIN11 1110 AIN12 1110 AIN12 1110 AIN12 1111 No Connection 1111 No Connection 1111 No Connection Rev B Page 15 of 104 ADV7189B GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip POWER SAVE MODES Power Down PDBP Address 0x0F 2 The digital core of the ADV7189B can be shut down by using a pin PWRDN and a bit PWRDN see below The PDBP con trols which of the two has the higher priority The default is to give the pin PWRDN priority This allows the user to have the ADV7189B powered down by default When PDBD is 0 default the digital core power is controlled by the PWRDN pin the bit is disregarded When PDBD is 1 the bit has priority the pin is disregarded PWRDN Address 0x0F 5 Setting the PWRDN bit switches the ADV7189B into a chip wide power down mode The power down stops the clock from entering the digital section of the chip thereby freezing its operation No bits are lost during power down The PWRDN bit also affects the analog blocks and switches them into low current modes The inter
58. 0x20 Recommended setting 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 0xC5 Recommended setting 0x7C 0x93 Recommended setting 0x7D 0x00 Recommended setting OxDO 0x48 Recommended setting OxD5 OxAO Recommended setting 0 07 Recommended setting OxE4 Ox3E Recommended setting OxE9 Ox3E Recommended setting OxEA OxOF Recommended setting OxOE 0x00 Recommended setting Rev B Page 96 of 104 PCB LAYOUT RECOMMENDATIONS The ADV7189B is a high precision high speed mixed signal device To achieve the maximum performance from the part it is important to have a well laid out PCB board The following is a guide for designing a board using the ADV7189B ANALOG INTERFACE INPUTS Take care when routing the inputs on the PCB Track lengths should be kept to a minimum and 75 trace impedances should be used when possible Trace impedances other than 75 increase the chance of reflections POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0 1 and 10 nF capacitors The fundamental idea is to have a decoupling capacitor within about 0 5 cm of each power pin Also avoid placing the capacitor on the opposite side of the PC board from the ADV7189B as doing so interposes resistive vias in the path The bypass capacitors should be located between the power plane and the power pin Current should flow from the power plane to the capacitor to the power pi
59. 101 the output is nominally 13 5 MHz LLC on the LLCI pin Data Port Pins P 19 0 Processor Format and Mode 19 18 17 16 15 14 13 12 11 10 9 8 17 6 5 1413 12 1 0 Video Out 8 Bit 4 2 2 YCrCb 7 0 OUT Video Out 10 Bit 4 2 2 YCrCb 9 0 OUT Video Out 16 Bit 4 2 2 Y 7 0 OUT CrCb 7 0 OUT Video Out 20 Bit 4 2 2 Y 9 0 OUT CrCb 9 0 OUT Table 80 Standard Definition Pixel Port Modes Pixel Port Pins P 19 0 Function P 19 10 P9 9 0 OF SEL 3 0 Format P 19 12 P 11 10 P 9 2 P 1 0 0000 10 Bit at LLC1 4 2 2 YCrCb 9 2 YCrCb 1 0 Three State Three State 0001 20 Bit at LLC2 4 2 2 Y 9 2 Y 1 0 CrCb 9 2 CrCb 1 0 0010 16 Bit at LLC2 4 2 2 Y 7 0 Three state CrCb 7 0 Three state 0011 default 8 Bit at LLC1 4 2 2 YCrCb 7 0 Three state Three state Three state 0110 1111 Reserved Reserved Do not use Rev B Page 60 of 104 MPU PORT DESCRIPTION The ADV7189B supports a 2 wire PC compatible serial inter face Two inputs serial data SDA and serial clock SCLK carry information between the ADV7189B and the system master controller Each slave device is recognized by a unique address The ADV7189B5 port allows the user to set up and configure the decoder and to read back captured VBI data The ADV7189B has four possible slave addresses for both read and write operations depending o
60. 111 SVHS 14 0 1000 SVHS 7 1 0000 SVHS 15 0 1001 SVHS 8 1 0001 SVHS 16 0 1010 SVHS 9 1 0010 SVHS 17 0 1011 SVHS 10 1 0011 SVHS 18 CCIR 601 0 1100 SVHS 11 1 0100 PALNN 1 0 1101 SVHS 12 1 0101 PAL NN 2 0 1110 SVHS 13 10110 PAL NN 3 01111 SVHS 14 10111 PAL WN 1 1 0000 SVHS 15 11000 PAL WN 2 1 0001 SVHS 16 1 1001 NTSC NN 1 1 0010 SVHS 17 11010 NTSC 2 10011 default SVHS 18 CCIR 601 1011 NISC NN A 1 0100 1 1111 Do not use 1 1100 NTSC WN 1 1 1101 NTSC WN 2 11110 NTSC WN 3 11111 Reserved Rev B Page 28 of 104 COMBINED Y ANTIALIAS S VHS LOW PASS FILTERS Y RESAMPLE N AMPLITUDE dB amp 0 2 4 6 8 10 12 FREQUENCY MHz Figure 12 S VHS Combined Responses The filter plots in Figure 12 show the S VHS 1 narrowest to S VHS 18 widest shaping filter settings Figure 14 shows the PAL notch filter responses The NTSC compatible notches are shown in Figure 15 COMBINED Y ANTIALIAS CCIR MODE SHAPING FILTER Y RESAMPLE AMPLITUDE dB 5 eo g 100 120 A Ah f 0 2 4 6 8 10 12 FREQUENCY MHz Figure 13 Y S VHS 18 Extra Wideband Filter CCIR 601 Compliant COMBINED Y ANTIALIAS NTSC NOTCH FILTERS Y RESAMPLE AMPLITUDE dB FREQUENCY MHz Figure 14 PAL Notch Filter Response 04983 0 012 04983 0 013 04983 0 0
61. 1310 1 311 312 313 314 315 316 317 318 319 320 321 322 323 337 I 1 i H 1 rang 1 output 11 VIDEO it s OUTPUT vs OUTPUT Iena PVBEG 4 0 0x1 PVEND 4 0 0x4 FIELD OUTPUT 04983 0 027 PFTOG 4 0 0x6 Figure 27 PAL Typical Vsync Field Positions Using Register Writes in Table 57 PVBEGDELO PAL Vsync Begin Delay on Odd Field 1 0 Address OxES 7 When PVBEGDELO is 0 default there is no delay ADVANCE BEGIN OF DELAY BEGIN OF VSYNC BY PVBEG 4 0 VSYNC BY PVBEG 4 0 Setting PVBEGDELO to 1 delays Vsync going high on an odd field by a line relative to PVBEG NOT VALID FOR USER PROGRAMMING PVBEGDELE PAL Vsync Begin Delay on Even Field dE ODD FIELD T Address 0xE8 6 When PVBEGDELE is 0 there is no delay PVBEGDELO PVBEGDELE Setting PVBEGDELE to 1 default delays Vsync going high on an even field by a line relative to PVBEG n PVBEGSIGN PAL Vsync Begin Sign Address 0xE8 5 ADDITIONAL ADDITIONAL Setting PVBEGSIGN to 0 delays the beginning of Vsync Set for DELAY BY DELAY BY 1 LINE 1 LINE user manual programming Setting PVBEGSIGN to 1 default advances the beginning of Vsync Not recommended for user programming PVBEG 4 0 PAL Vsync Begin Address 0xE8 4 0 The default value of PVBEG is 00101 indicating the PAL Vsync begin position ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE For all NTSC PAL V
62. 15 ADV7189B COMBINED Y ANTIALIAS NTSC NOTCH FILTERS Y RESAMPLE AMPLITUDE dB 04983 0 015 FREQUENCY MHz Figure 15 NTSC Notch Filter Response CHROMA FILTER Data from the digital fine clamp block is processed by three sets of filters Note the data format at this point is CVBS for CVBS inputs or chroma only for Y C or Cr Cb interleaved for YCrCb input formats Chroma Antialias Filter CAA The ADV7189B over samples the CVBS by a factor of 2 and the Chroma UV by a factor of 4 A decimating filter CAA is used to preserve the active video band and to remove any out of band components The CAA filter has a fixed response Chroma Shaping Filters CSH The shaping filter block can be programmed to perform a variety of low pass responses It can be used to selectively reduce the band width of the chroma signal for scaling or compression Digital Resampling Filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system without user intervention The plots in Figure 16 show the overall response of all filters together Rev B Page 29 of 104 ADV7189B CSFM 2 0 C Shaping Filter Mode Address 0x17 7 The C shaping filter mode bits allow the user to select from a range of low pass filters
63. 273 When BT656 4 is 1 the BT656 4 specification is used The V bit goes low at EAV of Lines 20 and 283 SD DUP AV Duplicate AV Codes Address 0x03 0 Depending on the output interface width it can be necessary to duplicate the AV codes from the luma path into the chroma path SD DUP AV 1 16 20 BIT INTERFACE 16 20 BIT INTERFACE In an 8 10 bit wide output interface Cb Y Cr Y interleaved data the AV codes are defined as FF 00 00 AV with AV being the transmitted word that contains information about H V F In this output interface mode the following assignment takes place Cb FE Y 00 Cr 00 and Y AV Ina 16 20 bit output interface where Y and Cr Cb are delivered via separate data buses the AV code is over the whole 16 20 bits The SD AV bit allows the user to replicate the AV codes on both busses so the full AV sequence can be found on the Y bus as well as on the Cr Cb bus See Figure 19 When SD DUP AV is 0 default the AV codes are in single fashion to suit 8 10 bit interleaved data output When SD DUP AV is 1 the AV codes are duplicated for 16 20 bit interfaces VBI EN Vertical Blanking Interval Data Enable Address 0x03 7 The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering All data for Line 1 to Line 21 is passed through and available at the output port The ADV7189
64. 3 276 13 GDECEL 3 Gemstar 4 277 14 GDECEL 4 Gemstar 5 278 15 GDECEL 5 Gemstar 6 279 16 GDECEL 6 Gemstar 7 280 17 GDECEL 7 Gemstar 8 281 18 GDECEL 8 Gemstar 9 282 19 GDECEL 9 Gemstar 10 283 20 GDECEL 10 Gemstar 11 284 21 GDECEL 11 Gemstar or closed caption 12 285 22 GDECEL 12 Gemstar 13 286 23 GDECEL 13 Gemstar 14 287 24 GDECEL 14 Gemstar 15 288 25 GDECEL 15 Gemstar Rev Page 57 of 104 ADV7189B Table 75 PAL Line Enable Bits and Corresponding Line Numbering 4 Line Number 5 Line 3 0 ITU R BT 470 Enable Bit Comment 12 8 GDECOL 0 Not valid a 0 13 9 GDECOLI1 Not valid 2 14 10 GDECOL 2 Not valid g P 15 11 3 Not valid amp 0 12 GDECOLI4 Not valid uix 1 13 GDECOL 5 Not valid 8 2 14 GDECOL 6 Not valid 3 3 15 GDECOL 7 Not valid 8 4 16 GDECOL 8 Not valid 71220 25 3 0 3 5 4 0 4 5 50 5 17 GDECOL 9 Not valid FREQUENCY MHz 6 18 GDECOL 10 Not valid Figure 36 NTSC IF Compensation Filter Responses 7 19 GDECOL 11 Not valid 8 20 GDECOL 12 Not valid 4 9 21 GDECOL 13 Not valid 10 22 GDECOL 14 Closed caption os Bes 11 23 GDECOL 15 Not valid 0 12 321 8 GDECELI O Not valid A 13 322 9 GDECEL 1 Not valid d 14 323 10 GDECEL 2 Not valid ad 15 324 11 GDECEL 3 Not valid 3 0 325 12 GDECEL 4 Not valid 1 326 13 GDECEL 5 Not valid E 2 327 14 GDECEL 6 Not valid 8 E 3 328 15 GDECEL 7 Not valid EE T DEAD 4
65. 3 4 ns valid data taccess tio t13 Data Output Transitional Time t14 End of valid data to negative 2 4 ns clock edge tuoip to tra Propagation Delay to Hi Z tis 6 ns Max Output Enable Access Time tie 7 ns Min Output Enable Access Time 117 4 ns 1 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7189BKSTZ The min max specifications are guaranteed over this range ANALOG SPECIFICATIONS Guaranteed by characterization 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvpnio 3 0 V to 3 6 V Pvpp 1 65 V to 2 0 V operating temperature range unless otherwise specified Recommended Analog input video signal range 0 5 V to 1 5 V typically 1 Table 4 Parameter Symbol Test Condition Min Typ Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0 1 uF Input Impedance Clamps switched off 10 Large Clamp Source Current 0 75 mA Large Clamp Sink Current 0 75 mA Fine Clamp Source Current 60 uA Fine Clamp Sink Current 60 uA 1 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7189BKSTZ 2 The min max specifications are guaranteed over this range Rev B Page 8 of 104 ADV7189B THERMAL SPECIFICATIONS Table 5 Parameter Symbol Test Conditions Min Typ Max Unit THERMAL CHARACTERISTICS Junction to Case Thermal Resistance 4 layer PCB with solid ground plane 7 6 C W Junction to Ambient Thermal Resistance Still Ai
66. 329 16 GDECEL 8 Not valid Figure 37 PAL IF Compensation Filter Responses 5 330 17 GDECEL 9 Not valid 6 331 18 GDECEL 10 Not valid See Table 86 for programming details 7 332 19 GDECELT 1 1 Not valid PC Interrupt System 8 333 20 GDECEL 12 Not valid 9 334 21 GDECEL 13 Notvalid The ADV7189B has a comprehensive interrupt register set This 10 335 22 GDECEL 14 Closed caption map is located in the Register Access See Table 85 for details of 11 336 23 GDECEL 15 Not valid the interrupt register map How to access this map is described in Figure 38 IF Compensation Filter IFFILTSEL 2 0 IF Filter Select Address OxF8 2 0 The IFFILTSEL 2 0 register allows the user to compensate for SAW filter characteristics on a composite input as would be observed on tuner outputs Figure 36 and Figure 37 show IF filter compensation for NTSC and PAL COMMON 12 SPACE ADDRESS 0x00 gt Ox3F ADDRESS 0x0E BIT 6 5 00b ADDRESS 0x0E BIT 6 5 016 12C SPACE REGISTER ACCESS PAGE 1 12C SPACE REGISTER ACCESS PAGE 2 ADDRESS 0x40 gt 0x4C INTERRUPT REGISTER SPACE Figure 38 Register Access Page 1 and Page 2 ADDRESS 0x40 gt OxFF NORMAL REGISTER SPACE The options for this feature are as follows 04983 0 044 e Bypass Mode default e NTSC consists of three filter characteristics e PAL consists of three filter characteristics
67. 33 764us E Figure 34 Closed Caption Data Extraction Table 61 CCAP Access Information Signal Name Register Location Address Register Default Value CCAP1 7 0 CCAP 1 7 0 153d 0x99 Readback Only CCAP2 7 0 CCAP 2 7 0 154d 9 Readback Only Rev B Page 50 of 104 ADV7189B Letterbox Detection Incoming video signals may conform to different aspect ratios 16 9 wide screen of 4 3 standard For certain transmissions in the wide screen format a digital sequence WSS is transmitted with the video signal If a WSS sequence is provided the aspect ratio of the video can be derived from the digitally decoded bits WSS contains In the absence of a WSS sequence letterbox detection can be used to find wide screen signals The detection algorithm examines the active video content of lines at the start and end of a field If black lines are detected this may indicate the currently shown picture is in wide screen format The active video content luminance magnitude over a line of video is summed together At the end of a line this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black The threshold value needed may depend on the type of input signal some control is provided via LB_TH 4 0 Detection at the Start of a Field The ADV7189B expects a section of at least six consecutive black lines of video at the top of a field Once tho
68. 5 GDECOL 14 GDECOL 13 GDECOL 12 GDECOL 11 GDECOL 10 GDECOL 9 GDECOL 8 Gemstar Ctrl 4 GDECOL 7 GDECOL 6 GDECOL 5 GDECOL 4 GDECOL 3 GDECOL 2 GDECOL 1 GDECOL O Gemstar Ctrl 5 GDECAD CTI DNR Ctrl 1 DNR_EN CTI AB 1 CTI AB O CTI AB EN CTI EN CTI DNR Ctrl 2 CTI C TH 7 CTI C TH 6 CTI C TH 5 CTI C THA CTI C TH 3 CTI C TH2 CTI C TH 1 CTI C TH O Reserved CTI DNR Ctrl 4 DNR TH 7 DNR TH 6 DNR TH 5 DNR TH 4 DNR TH 3 DNR TH 2 DNR TH 1 DNR_TH O Lock Count FSCLE SRLS COL 2 COL 1 COL O CIL 2 CIL 1 CIL O Reserved Free Run Line LLC PAD SEL 2 LLC PAD SEL 1 LLC PAD SEL O Length 1 Reserved VBI Info CGMSD EDTVD CCAPD WSSD WSS 1 WSS1 7 WSS1 6 WSS1 5 WSS1 4 WSS1 3 WSS1 2 WSS1 1 WSS1 0 WSS 2 WSS2 7 WSS2 6 WSS2 5 WSS2 4 WSS2 3 WSS2 2 WSS2 1 WSS2 0 EDTV 1 EDTV1 7 EDTV1 6 EDTV1 5 EDTV1 4 EDTV1 3 EDTV1 2 EDTV1 1 EDTV1 0 EDTV 2 EDTV2 7 EDTV2 6 EDTV2 5 EDTV2 4 EDTV2 3 EDTV2 2 EDTV2 1 EDTV2 0 EDTV 3 EDTV3 7 EDTV3 6 EDTV3 5 EDTV3 4 EDTV3 3 EDTV3 2 EDTV3 1 EDTV3 0 CGMS 1 CGMS1 7 CGMS1 6 CGMS1 5 CGMS1 4 CGMS1 3 CGMS1 2 CGMS1 1 CGMS1 0 CGMS 2 CGMS2 7 CGMS2 6 CGMS2 5 CGMS2 4 CGMS2 3 CGMS2 2 CGMS2 1 CGMS2 0 CGMS 3 CGMS3 7 CGMS3 6 CGMS3 5 CGMS3 4 CGMS3 3 CGMS3 2 CGMS3 1 CGMS3 0 CCAP 1 CCAP1 7 CCAP1 6 CCAP 1 5 CCAP1 4 CCAP1 3 CCAP1 2 CCAP1 1 CCAP1 0 CCAP 2 CCAP2 7 CCAP2 6 CCAP2 5 CCAP2 4 CCAP2 3 CCAP2 2 CCAP2 1 CCAP2 0 Letterbox 1 LB_LCT 7 LB_LCT 6 LB_LCT 5 LB_LCT 4 LB_LCT 3 LB_LCT 2 LB_LCT 1 LB_LCT O Letterbox 2 LB_LCM 7 LB_LCM 6 LB_LCM 5 LB_LCM 4 LB_LCM 3 LB_LCM 2 LB_LCM 1 LB_LCM O L
69. 50 0x20 Recommended setting 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 OxC5 Recommended setting 0x7C 0x93 Recommended setting 0 7 0x00 Recommended setting OxDO 0x48 Recommended setting OxD5 OxAO Recommended setting 0 07 OxEA Recommended setting OxE4 Ox3E Recommended setting OxE9 Ox3E Recommended setting OxEA OxOF Recommended setting OxOE 0x00 Recommended setting Rev B Page 94 of 104 ADV7189B Mode 2 S Video Input Y on AIN1 and C on AIN4 All standards are supported through autodetect 10 bit ITU R BT 656 output on P19 to P10 Table 92 Mode 2 S Video Input Register Address Register Value Notes 0x00 0x06 Y1 AIN1 C1 AINA 0x03 0x00 Enable 10 bit output on P19 to P10 0x15 0x00 Slow down digital clamps 0x3A 0x12 Power down ADC 2 0x50 0x04 Set DNR threshold to 4 for flat response OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x50 0x20 Recommended setting 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 5 Recommended setting 0 7 0x93 Recommended setting 0x7D 0x00 Recommended setting OxDO 0x48 Recommended setting OxD5 OxAO Recommended setting 0 07 Recommended setting OxE4 Ox3E Recommended setting OxE9 Ox3E Recommended setting OxEA OxOF Recommended setting OxOE 0x00 Recommended setting Mode 3 YPrPb Input 525i 625i
70. 7 0 Address 0x10 7 0 section the actual gain update speed is dictated by the peak white AGC loop and as a result the LAGT settings have no effect As soon as the part leaves peak white AGC LAGT becomes relevant again The update speed for the peak white algorithm can be customized by the use of internal parameters Contact ADI for more information Table 35 LAGT Function LAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive LG 11 0 Luma Gain Address 0x2F 3 0 Address 0x30 7 0 LMG 11 0 Luma Manual Gain Address Ox2F 3 0 Address 0x30 7 0 Luma Gain 11 0 is a dual function register If written to a desired manual luma gain can be programmed This gain becomes active if the LAGC 2 0 mode is switched to manual fixed gain Equation 1 shows how to calculate a desired gain If read back this register returns the current gain value Depending on the setting in the LAGC 2 0 bits this is one of the following values e Luma manual gain value LAGC 2 0 set to luma manual gain mode e Luma automatic gain value LAGC 2 0 set to any of the automatic modes Table 36 LG LMG Function LG 11 0 LMG 11 0 Read Write Description LMG 11 0 2 X Write Manual gain for luma path LG 11 0 Read Actually used gain 0 LG x 4095 0 2 1 2048 0 Luma _Gain Rev B Page 31 of 104 ADV7189B For example program the ADV71
71. 80 1560 Pixel PAL 00000000010b 00000000000b 284 720Y 720C 1440 1728 ACTIVE VIDEO gt 2 1 BLANK 4 SAV 4 ACTIVE VIDEO _ 04983 0 020 Figure 20 HS Timing Rev B Page 40 of 104 ADV7189B VS and FIELD Configuration The following controls allow the user to configure the behav ior of the VS and FIELD output pins as well as to generate embedded AV codes e ADV encoder compatible signals via NEWAVMODE e PVS PF e HVSTIM e VSBHO VSBHE VSEHO VSEHE e NTSC control NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG 4 0 e NVENDDELO NVENDDELE NVENDSIGN NVEND 4 0 NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 0 e For PAL control PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 0 PVENDDELO PVENDDELE PVENDSIGN PVEND 4 0 PFTOGDELO PFTOGDELE PFTOGSIGN 4 0 NEWAVMODE New AV Mode Address 0 31 4 When NEWAVMODE is 0 EAV SAV codes are generated to suit ADI encoders No adjustments are possible Setting NEWAVMODE to 1 default enables the manual position of the VSYNC Field and AV codes using Registers 0x34 to 0x37 and Register OxE5 to OxEA Default register settings are CCIR656 compliant see Figure 21 for NTSC and Figure 26 for PAL For recommended manual user settings see Table 56 and Figure 22 for NTSC see Table 57 and Figure 27 for PAL HVSTIM Hor
72. 89B into manual fixed gain mode with a desired gain of 0 89 1 Use Equation 1 to convert the gain 0 89 x 2048 1822 72 2 Truncate to integer value 1822 72 1822 3 Convert to hexadecimal 1822d Ox71E 4 Split into two registers and program Luma Gain Control 1 3 0 0x7 Luma Gain Control 2 7 0 0 1 5 Enable Manual Fixed Gain Mode Set LAGC 2 0 to 000 BETACAM Enable Betacam Levels Address 0 01 5 If YPrPb data is routed through the ADV7189B the automatic gain control modes can target different video input levels as outlined in Note the BETACAM bit is valid only if the input mode is YPrPb component The BETACAM bit sets the target value for AGC operation A review of the following sections is useful INSEL 3 0 Input Selection Address 0x00 3 0 to find out how component video YPrPb can be routed through the ADV7189B e Video Standard Selection to select the various standards for example with and without pedestal The automatic gain control AGC algorithms adjust the levels based on the setting of the BETACAM bit See Table 37 Table 37 BETACAM Function Table 38 Betacam Levels Betacam Betacam Variant SMPTE Name mV mV mV MII mV Y Oto 714 0to714 Oto 0 to 700 incl Range incl 7 5 700 7 596 pedestal pedestal Uand 467to 467 505 to 350 324 to 324 V 505 350 Sync 286 286 300 300 Depth PW_UPD Peak White Update Address
73. ANALOG DEVICES Multiformat SDTV Video Decoder ADV7189B FEATURES Multiformat video decoder supports NTSC J M 4 43 PAL B D G H I M N SECAM Integrates three 54 MHz Noise Shaped Video 12 bit ADCs Clocked from a single 28 MHz crystal Line locked clock compatible LLC Adaptive Digital Line Length Tracking ADLLT signal processing and enhanced FIFO management gives mini TBC functionality 5 line adaptive comb filters Proprietary architecture for locking to weak noisy and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision copy protection detection CTI chroma transient improvement DNR digital noise reduction Multiple programmable analog input formats CVBS composite video S Video Y C YPrPb component VESA MII SMPTE and BetaCam 12 analog video input channels Automatic NTSC PAL SECAM identification Digital output formats 8 bit 10 bit 16 bit 20 bit ITU R BT 656 YCrCb 4 2 2 output HS VS and FIELD GENERAL DESCRIPTION The ADV7189B integrated video decoder automatically detects and converts a standard analog baseband television signal com patible with worldwide standards NTSC PAL and SECAM into 4 2 2 component video data compatible with 20 16 10 and 8 bit CCIR601 CCIR656 The advanced and highly flexible digital output interface enables performance video decoding and conversion in
74. B does not blank the luma data and automatically switches all filters along the luma data path into their widest bandwidth For active video the filter settings for YSH and are restored Refer to the BL C VBI Blank Chroma during VBI section for information on the chroma path When EN is 0 default all video lines are filtered scaled When VBI EN is 1 only the active video region is filtered scaled SD DUP AV 0 8 10 BIT INTERFACE omms Bm Y o X e X X238 Be X X Eo Cb Y Cr Y semen o n E98 BOXE E P e AV CODE SECTION 27 AV CODE SECTION WERE FE dn ong 04983 0 019 AV CODE SECTION Figure 19 AV Code Duplication Control Rev B Page 38 of 104 ADV7189B BL_C_VBI Blank Chroma During VBI Address 0x04 2 Setting BL_C_VBI high the Cr and Cb values of all VBI lines are blanked This is done so any data that may arrive during VBI is not decoded as color and output through Cr and Cb As a result it is possible to send VBI lines into the decoder then output them through an encoder again undistorted Without this blanking any wrongly decoded color is encoded by the video encoder therefore the VBI lines are distorted Setting BL_C_VBI to 0 decodes and outputs color during VBI Setting BL_C_VBI to 1 default blanks Cr and Cb values during VBI RANGE Range Selection Address 0 04 0 AV codes as per ITU R BT 656 formerly known as CCIR 656 consist of a fixed header made up of O
75. CHNGD_ MSKB MSKB Q_MSKB MSKB MSKB Raw Status 3 r 73 0x49 SCM_LOCK SD_H_LOCK SD V LOCK SD OP 50HZ Interrupt Status 3 r 74 Ox4A PAL SW LK SCM LOCK SD AD SD H LOCK SD V LOCK SD OP CHNGO CHNG Q CHNG CHNGO CHNG Interrupt Clear 3 xx00 w 75 0x4B PAL_SW_L SCM_LOCK SD_AD_CH SD_H_ SD_V_LOCK SD_OP_ 0000 K_CHNG_ _CHNG_ NG_CLR LOCK_ _CHNG_ CHNG_CLR CLR CLR CHNG_CLR CLR Interrupt Mask b3 xx00 rw 76 Ox4C PAL SW SCM LOCK SD AD SD_H_ SD_V_ SD_OP_ 0000 LK_CHNG_ _CHNG_ CHNG_ LOCK_ LOCK_ CHNG_MSKB MSKB MSKB MSKB CHNG_MSKB CHNG_MSKB 1 To access the interrupt register map the register access page 1 0 bits in register address OxOE must be programmed to 01b Rev B Page 67 of 104 ADV7189B PC INTERRUPT REGISTER MAP The following registers are located in Register Access Page 2 Table 85 Interrupt Page 2 Register Map Details Bit Subaddress Register Bit Description 7161543 1 0 Comments Notes 0x40 Interrupt INTRO OP SEL 1 0 Open drain Config 1 Interrupt Drive Level Select olaq Drive low when active 1 0 Drive high when active Register 1 4 Reserved Access 2 MPU_STIM_INTRQ 1 0 Manual interrupt mode disabled Manual Interrupt Set Mode Manual interrupt mode enabled Reserved x Not used MV_INTRQ_SEL 1 0 0 0 Reserved Macrovi
76. Chroma Transient Improvement Alpha Blend Address 0x4D 3 2 The CTI AB 1 0 controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one It thereby controls the visual impact of CTI on the output data For CTI AB 1 0 to become active the CTI block must be enabled via the EN bit and the alpha blender must be switched on via CTI AB EN Sharp blending maximizes the effect of CTI on the picture but can also increase the visual impact of small amplitude high frequency chroma noise Table 43 CTI AB Function CTI AB 1 0 Description 00 Sharpest mixing between sharpened and original chroma signal 01 Sharp mixing 10 Smooth mixing 11 default Smoothest alpha blend function CTI C TH 7 0 CTI Chroma Threshold Address Ox4E 7 0 The CTI C TH 7 0 value is an unsigned 8 bit number speci fying how big the amplitude step in a chroma transition is to be steepened by the CTI block Programming a small value into this register causes even smaller edges to be steepened by the CTI block Making CTI C TH 7 0 a large value causes the block to only improve large transitions The default value for C TH 7 0 is 0x08 indicating the threshold for the chroma edges prior to CTI DIGITAL NOISE REDUCTION DNR Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and their removal therefore improv
77. DSIGN 0 Set to low when manual programming 1 Not suitable for user programming PVENDDELE Delay V bit going 0 No delay low by one line relative to PVEND 1 Additional delay by even field 1line PVENDDELO Delay V bit going 0 No delay low by one line relative to PVEND 1 Additional delay by odd field 1line OxEA PALF Bit PFTOG 4 0 How many lines after 1 PAL default BT 656 Toggle Icount rollover to toggle F signal PFTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PFTOGDELE Delay F transition by 0 No delay one line relative to PFTOG even 1 Additional delay by field 1line PFTOGDELO Delay F transition 0 No delay by one line relative to PFTOG 1 Additional delay by odd field 1 line 4 Drive DR_STR_S 1 0 Select the drive 0 Low drive strength 1x Strength strength for the sync output 1 Medium low drive signals strength 2x 0 Medium high drive strength 3x 1 High drive strength 4x DR STR C 1 0 Select the drive Low drive strength 1 strength for the clock output ONSE Medium low drive signal strength 2x 1 0 Medium high drive strength 3x 1 1 High drive strength 4x DR STR 1 0 Select the drive 0 0 Low drive strength 1x strength for the data output 0 1 Medium low drive signals Can be increased or strength 2x decreased for EMC or crosstalk Medium high drive reasons strength 3x 1 1 High drive strength 4x Reserved x x No delay OxF8 IF Com
78. DV7189B pixel port can be configured are under the control of OF SEL 3 0 See Table 80 for details The default LLC frequency output on the LLCI pin is approxi mately 27 MHz For modes that operate with a nominal data rate of 13 5 MHz 0001 0010 the clock frequency on the LLCI pin stays at the higher rate of 27 MHz For information on outputting the nominal 13 5 MHz clock on the pin see the LLC1 Output Selection LLC PAD SEL 2 0 Address 0x8F 6 4 section Table 79 P19 to PO Output Input Pin Mapping SWPC Swap Pixel Cr Cb Address 0x27 7 This bit allows Cr and Cb samples to be swapped When SWPC is 0 default no swapping is allowed When SWPC is 1 the Cr and Cb values can be swapped LLCI Output Selection LLC PAD SEL 2 0 Address 0x8F 6 4 The following write allows the user to select between the LLC1 nominally at 27 MHz and LLC2 nominally at 13 5 MHz The LLC2 signal is useful for LLC2 compatible wide bus 16 20 bit output modes See OF SEL 3 0 for additional information The LLC2 signal and data on the data bus are synchronized By default the rising edge of LLC1 LLC2 is aligned with the Y data the falling edge occurs when the data bus holds C data The polarity of the clock and therefore the Y C assignments to the clock edges can be altered by using the Polarity LLC pin When LLC PAD SEL 2 0 is 000 default the output is nominally 27 MHz LLC on the LLCI pin When LLC_PAD_SEL 2 0 is
79. GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 The 16 bits of the GDECEL 15 0 are interpreted as a collection of 16 individual line decode enable signals Each bit refers to a line of video in an even field Setting a bit to 1 enables the decoder block to retrieve Gemstar or closed caption compatible data on that particular line Setting a bit to 0 prevents the decoder from trying to retrieve data See Table 74 and Table 75 To retrieve closed caption data services on NTSC Line 284 GDECEL 11 must be set To retrieve closed caption data services on PAL Line 335 GDECEL 14 must be set The default value of GDECEL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address Ox4B 7 0 The 16 bits of the GDECOL 15 0 form a collection of 16 individual line decode enable signals See Table 74 and Table 75 To retrieve closed caption data services on NTSC Line 21 GDECOL 11 must be set To retrieve closed caption data services on PAL Line 22 GDECOL 14 must be set The default value of GDECOL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field GDECAD Gemstar Decode Ancillary Data Format Address 0 4 0 The decoded data from Gemstar compatible transmissions or closed captio
80. GN PVBEG 4 PVBEG 3 PVBEG 2 PVBEG 1 PVBEG O PAL V Bit End PVENDDEL O PVENDDEL E PVENDSIGN PVEND 4 PVEND 3 PVEND 2 PVEND 1 PVEND O PAL F Bit Toggle PFTOGDEL PFTOGDEL E PFTOGSIGN PFTOG 4 PFTOG 3 PFTOG 2 PFTOG 1 PFTOG O Reserved Drive Strength DR_STR 1 DR_STR O DR_STR_C 1 DR STR COO DR STR S 1 DR STR S 0 Reserved IF Comp Control IFFILTSEL 2 IFFILTSEL 1 IFFILTSEL O VS Mode VS COAST VS COAST EXTEND VS EXTEND VS Control MODE 1 MODE O MIN_FREQ MAX_FREQ 2 REGISTER MAP DETAILS The following registers are located in the Common I2C Register Maps and Register Access sections Page 2 Table 84 Interrupt Page 2 Register Map Details Reset Subaddress Register Name Value rw Dec Hex 7 6 5 4 3 2 1 0 Interrupt Config 0 0001 rw 64 0x40 INTRQ_DU INTRQ_ MV_INTRQ MV_INTRQ MPU_STIM INTRQ_OP INTRQ_OP x000 R_SEL 1 DUR_SEL O _SEL 1 _SEL O _INTRQ _SEL 1 _SEL O Reserved 65 0x41 Interrupt Status 1 r 66 0x42 MV_PS_ SD_FR_ SD_ SD_LOCK_ Cs Q CHNG Q UNLOCK Q Interrupt Clear 1 x000 w 67 0x43 MV_PS_ SD_FR_CH SD_UNLOCK SD_LOCK_ 0000 CS_CLR NG_CLR _CLR CLR Interrupt Mask b1 x000 rw 68 0x44 MV PS SD FR CH SD UNLOCK SD LOCK 0000 CS MSKB NG MSKB _MSKB MSKB Reserved 69 0x45 Interrupt Status 2 r 70 0x46 MPU_STIM WSS_CHN CGMS_ GEMD_Q CCAPD_Q _INTRQ_Q GD_Q CHNGD_Q Interrupt Clear 2 Oxxx w 71 0x47 MPU_STIM WSS_ CGMS_ GEMD_CLR CCAPD_ 0000 _INTRQ_ CHNGD_ CHNGD_ CLR CLR CLR CLR Interrupt Mask b2 rw 72 0x48 MPU_ WSS_ CGMS_ GEMD_ CCAPD_ 0000 STIM_INTR CHNGD_
81. NPUT MUXING ADV7189B INTERNAL MAPPING FUNCTIONS e E E ES E E Figure 6 Internal Pin Connections The ADV7189B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder Figure 6 outlines the overall structure of the input muxing provided in the ADV7189B As can be seen in Figure 6 there are two different ways in which the analog input muxes can be controlled e Control via functional registers INSEL Using INSEL 3 0 simplifies the setup of the muxes and minimizes crosstalk between channels by pre assigning the input channels This is referred to as ADI recommended input muxing e Control via an C manual override sw man en ADCO sw ADCI sw ADC2 sw This is provided for applications with special requirements for example number combinations of signals that would not be served by the pre assigned input connections This is referred to as manual input muxing Refer to Figure 7 for an overview of the two methods of controlling the ADV7189B s input muxing ADI Recommended Input Muxing maximum of 12 CVBS inputs can be connected and decoded by the ADV7189B As seen in Figure 5 this means the sources have to be connected to adjacent pins on the IC This calls for a careful design of the PCB layout for example ground shielding between all signals routed through tracks that are physically close together INSEL 3 0 Input Selecti
82. No change in SD signal standard These bits Status 3 SD 60 50 Hz frame rate at detected at the input can be input A change in SD signal standard cleared and Read Only is detected at the input masked by Register SD V No change SD vertical sync Ed lock status Reai egister Register SD vertical sync lock status has Ox4C Access changed respectively Page 2 SD_H_LOCK_CHNG_Q No change in SD horizontal sync lock status SD horizontal sync lock status has changed SD AD CHNG Q x No change in AD_RESULT 2 0 SD autodetect changed bits in Status Register 1 AD RESULT 2 0 bits in Status Register 1 have changed SCM LOCK CHNG Q 0 No change in SECAM lock status SECAM Lock 1 SECAM lock status has changed PAL SW LK CHNG x No change in PAL swinging burst lock status PAL swinging burst lock status has changed Reserved x Not used Reserved Not used Rev B Page 70 of 104 ADV7189B Bit Subaddress Register Bit Description 6 5 4 3 Comments Notes Ox4B Interrupt SD OP CHNG CLR Do not clear Clear 3 Clears SD OP CHNG SD_V_LOCK_CHNG_CLR Do not clear Write Only Clears SD V LOCK CHNG Qbit Register SD H LOCK CHNG CLR Do not clear Clears SD_H_LOCK_CHNG_Q bit Register Access SD_AD_CHNG_CLR 0 Do not clear Page 2 1 Clears SD_AD_CHNG_Q bit SCM_LOCK_CHNG_CLR 0 Do not clear 1 Clears SCM_LOCK_CHNG_Q
83. Rev B Page 58 of 104 Interrupt Request Output Operation When an interrupt event occurs the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL 1 0 ADV7189B INTRQ_OP_SEL 1 0 Interrupt Duration Select Address 0x40 Interrupt Space 1 0 Table 77 INTRQ_OP_SEL INTRQ_DURSEL 1 0 Interrupt Duration Select Address 0x40 Interrupt Space 7 6 INTRQ OP SEL 1 0 Description 00 default Open drain 01 Drive low when active 10 Drive high when active 11 Reserved Table 76 INTRQ DUR SEL INTRQ DURSEL 1 0 Description 00 default 01 10 11 3 Xtal periods 15 Xtal periods 63 Xtal periods Active until cleared When the active until Cleared interrupt duration is selected and the event that caused the interrupt is no longer in force the interrupt persists until it is masked or cleared Multiple Interrupt Events If Interrupt Event 1 occurs and then Interrupt Event 2 occurs before the system controller has cleared or masked Interrupt Event 1 the ADV7189B does not generate a second interrupt signal The system controller should check all unmasked interrupt status bits since more than one can be active Macrovision Interrupt Selection Bits The user can select between pseudo sync pulse and color stripe For example if the ADV7189B loses lock an interrupt is generated and the INTRQ pin goes low If the ADV7189B returns to the locked state INTRQ
84. SH1 to SH5 and wideband mode for the chrominance signal The auto selection options automatically select from the filter options to give the specified response See settings 000 and 001 in Table 32 Table 32 CSFM Function CSFM 2 0 Description 000 default Autoselect 1 5 MHz bandwidth 001 Autoselect 2 17 MHz bandwidth 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband mode COMBINED C ANTIALIAS C SHAPING FILTER C RESAMPLER ATTENUATION dB amp 40 04983 0 016 0 1 2 3 4 5 6 FREQUENCY MHz Figure 16 Chroma Shaping Filter Responses Figure 16 shows the responses of SH1 narrowest to SH5 widest in addition to the wideband mode GAIN OPERATION The gain control within the ADV7189B is done on a purely digital basis The input ADCs support a 12 bit range mapped into a 1 6 V analog voltage range Gain correction takes place after the digitization in the form of a digital multiplier Advantages of this architecture over the commonly used programmable gain amplifier PGA before the ADCs include the fact that the gain is now completely independent of supply temperature and process variations As shown in Figure 17 the ADV7189B can decode a video signal as long as it fits into the ADC window The two components to this are the amplitude of the input signal and the dc level it resides on The dc level is set by the clamping circuitry see the Clamp Operatio
85. SULT Function Table 15 STATUS 1 Function ADV7189B STATUS 1 7 0 Bit Name Description 0 LOCK In lock right now 1 LOST LOCK Lost lock since last read of this register 2 FSC LOCK Fsc locked right now 3 FOLLOW PW AGC follows peak white algorithm 4 AD RESULT Result of autodetection 5 AD RESULT 1 Result of autodetection 6 AD RESULT 2 Result of autodetection 7 COL KILL Color kill active STATUS 2 STATUS 2 7 0 Address 0x12 7 0 Table 16 STATUS 2 Function STATUS 2 7 0 Bit Name Description 0 MVCS DET Detected Macrovision color striping 1 MVCS T3 Macrovision color striping protection Conforms to Type 3 if high to Type 2 if low 2 MV PS DET Detected Macrovision pseudo sync pulses 3 MV AGC DET Detected Macrovision AGC pulses 4 LL NSTD Line length is nonstandard 5 FSC NSTD Fsc frequency is nonstandard 6 Reserved 7 Reserved STATUS 3 STATUS 3 7 0 Address 0x13 7 0 Table 17 STATUS 3 Function AD RESULT 2 0 Description 000 NTSM MJ 001 NTSC 443 010 PAL M 011 PAL 60 100 PAL BGHID 101 SECAM 110 PAL Combination N 111 SECAM 525 STATUS 3 7 0 Bit Name Description 0 INST HLOCK Horizontal lock indicator instantaneous 1 GEMD Gemstar Detect 2 SD OP 50HZ Flags whether 50 Hz or 60 Hz is present at output 3 Reserved for future use 4 FREE RUN ACT ADV7189B outputs a blue screen see the DEF VAL EN Default Va
86. TOYULNOD 59317113 TOYULNOD NAS Vivd IgA ANV 39VJH31NI 1VIH3S 868LZAQV NOLLVH3N39 52019 SNISS32O8d DNAS NOILVWIO3 uossadoo0udadud viva 100 0 86r0 AdidA OACIA S S8A9 a ZLNIV LNIV e Figure 1 Rev B Page 5 of 104 ADV7189B SPECIFICATIONS ELECTRICAL CHARACTERISTICS At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V Pvpp 1 65 V to 2 0 V operating temperature range unless otherwise specified Table 1 Parameter Symbol Test Conditions Min Typ Max Unit STATIC PERFORMANCE Resolution Each ADC N 12 Bits Integral Nonlinearity INL BSL at 54 MHz 1 5 42 5 8 LSB Differential Nonlinearity DNL BSL at 54 MHz 0 7 0 7 0 95 2 LSB DIGITAL INPUTS Input High Voltage Vin 2 V Input Low Voltage Vit 0 8 V Input Current lin 50 50 uA All other pins 10 10 uA Input Capacitance Cin 10 pF DIGITAL OUTPUTS Output High Voltage Vou Isource 0 4 MA 2 4 V Output Low Voltage VoL Isink 3 2 MA 0 4 V High Impedance Leakage Current Leak 50 uA All other pins 10 uA Output Capacitance Cour 20 pF POWER REQUIREMENTS Digital Core Power Supply Dvoo 1 65 1 8 2 V Digital I O Power Supply Dvopio 3 0 3 3 3 6 V PLL Power Supply Pvop 1 65 1 8 2 0 V Analog Power Supply Avoo 3 15 3 3 3 45 V Digital Core Supply Current Ipvop 82 mA Digital I O Supply Current Ipvopio 2 mA PLL Supply Curre
87. VSEHO 0 VS goes low in the middle of the line odd field VS changes state at the start of the line odd field Rev B Page 79 of 104 ADV7189B Bits Subaddress Register Bit Description 716 5 43 Comments Notes 0x34 HS Position HSE 10 8 HS end allows the HS output ends HSE 10 0 Using HSB and HSE Control 1 positioning of the HS output within pixels after the falling the user can program the video line edge of Hsync the position and Reserved 0 Set to 0 length of the output HSB 10 8 HS begin allows the QU Sou OF HS output starts HSB 10 0 Hsyne positioning of the HS output within pixels after the falling the video line edge of Hsync Reserved 0 Set to 0 0x35 HS Position HSB 7 0 See above using Control 2 HSB 10 0 and HSE 10 0 the user can program the position and length of HS output signal 0x36 HS Position HSE 7 0 See above Control 3 0x37 Polarity PCLK Sets the polarity of LLC1 Invert polarity Normal polarity as per timing diagrams Reserved Set to 0 PF Sets the FIELD polarity 0 Active high 1 Active low Reserved 0 Set to 0 PVS Sets the VS polarity 0 Active high 1 Active low Reserved 0 Set to 0 PHS Sets HS polarity 0 Active high 1 Active low Rev B Page 80 of 104 ADV7189B Subaddress Register Bit Description Bits C
88. Value Y Address 0x0C 7 2 When the ADV7189B loses lock on the incoming video signal or when there is no input signal the DEF_Y 5 0 register allows the user to specify a default luma value to be output This value is used under the following conditions lt lt IfDEF VAL AUTO EN bit is set to high and the ADV7189B lost lock to the input video signal This is the intended mode of operation automatic mode e TheDEF VAL EN bit is set regardless of the lock status of the video decoder This is a forced mode that can be useful during configuration The DEF Y 5 0 values define the 6 MSBs of the output video The remaining LSBs are padded with 0s For example in 10 bit mode the output is Y 9 0 DEF Y 5 0 0 0 0 0 DEF Y 5 0 is 0 0 Blue is the default value for Y Register OxOC has a default value of 0x36 DEF C 7 0 Default Value C Address 0x0D 7 0 The DEF C 7 0 register complements the DEF Y 5 0 value It defines the 4 MSBs of Cr and Cb values to be output if e TheDEF VAL AUTO EN bit is set to high and the ADV7189B can t lock to the input video automatic mode e DEF VAL EN bit is set to high forced output The data that is finally output from the ADV7189B for the chroma side is Cr 7 0 DEF C 7 4 0 0 0 0 Cb 7 0 DEF C 3 0 0 0 0 0 In full 10 bit output mode two extra LSBs of value 00 are appended DEF C 7 0 is 0x7C blue is the default value for Cr and Cb Rev B P
89. XX rw 76 4 CTI DNR Ctrl 1 11101111 rw 77 0x4D CTI DNR Ctrl 2 0000 1000 rw 78 0x4E Reserved XXXX XXXX rw 79 0x4F CTI DNR Ctrl 4 0000 1000 rw 80 0x50 Lock Count 0010 0100 rw 81 0x51 Reserved XXXX XXXX rw 82 to 142 0x52 to 0x8E Free Run Line Length 1 0000 0000 w 143 Ox8F Reserved 0000 0000 w 144 0x90 VBI Info XXXX XXXX r 144 0x90 WSS 1 XXXX XXXX r 145 0x91 WSS 2 XXXX XXXX r 146 0x92 EDTV 1 XXXX XXXX r 147 0x93 EDTV 2 XXXX XXXX r 148 0x94 EDTV 3 XXXX XXXX r 149 0x95 CGMS 1 XXXX XXXX r 150 0x96 CGMS 2 XXXX XXXX r 151 0x97 CGMS 3 XXXX XXXX r 152 0x98 CCAP 1 XXXX XXXX r 153 0x99 CCAP 2 XXXX XXXX r 154 Ox9A Letterbox 1 XXXX XXXX r 155 Ox9B Letterbox 2 XXXX XXXX r 156 0x9C Letterbox 3 XXXX XXXX r 157 Ox9D Reserved XXXX XXXX rw 158 to 177 Ox9E to OxB1 CRC Enable 0001 1100 w 178 OxB2 Reserved XXXX XXXX rw 179 to 194 OxB2 to OxC2 ADC Switch 1 XXXX XXXX rw 195 0xC3 ADC Switch 2 rw 196 4 Reserved XXXX XXXX rw 197 to 219 5 to 0 Letterbox Control 1 1010 1100 rw 220 OxDC Letterbox Control 2 0100 1100 rw 221 OxDD Reserved 0000 0000 rw 222 OxDE Reserved 0000 0000 rw 223 OxDF Reserved 0001 0100 rw 224 SD Offset Cb 1000 0000 rw 225 OxE1 SD Offset Cr 1000 0000 rw 226 OxE2 SD Saturation Cb 1000 0000 rw 227 OxE3 SD Saturation Cr 1000 0000 rw 228 OxE4 NTSC V Bit Begin 0010 0101 rw 229 OxE5 NTSC V Bit End 0000 0100 rw 230 OxE6 NTSC F Bit Toggle 01100011 rw 231 OxE7 PAL V Bit Begin 01100101 rw 232 OxE8
90. Y on AIN2 Pr on AIN3 and Pb on AIN6 All standards are supported through autodetect 10 bit ITU R BT 656 output on P19 to P10 Table 93 Mode 3 YPrPb Input 5251 6251 Register Address Register Value Notes 0x00 Ox0A Y2 AIN2 Pr2 AIN3 Pb2 AIN6 0x03 0x00 Enable 10 bit output on P19 to P10 0x50 0x04 Set DNR threshold to 4 for flat response OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 5 Recommended setting 0 7 0 93 Recommended setting 0x7D 0x00 Recommended setting OxDO 0x48 Recommended setting OxD5 OxAO Recommended setting OxE4 Ox3E Recommended setting OxE9 Ox3E Recommended setting OxOE 0x00 Recommended setting Rev B Page 95 of 104 ADV7189B Mode 4 CVBS Tuner Input PAL Only on AIN4 10 bit ITU R BT 656 output on P19 to P10 Table 94 Mode 4 CVBS Tuner Input PAL Only Register Address Register Value Notes 0x00 0x83 CVBS AIN4 Force PAL only mode 0x03 0x00 Enable 10 bit output on P19 to P10 0x07 0x01 Enable PAL autodetection only 0x15 0x00 Slow down digital clamps 0x17 0x41 Set CSFM to SH1 0x19 OxFA Stronger dot crawl reduction 0x3A 0x16 Power down ADC 1 and ADC 2 0x50 Set higher DNR threshold OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x50
91. age 24 of 104 DEF_VAL_EN Default Value Enable Address 0x0C 0 This bit forces the use of the default values for Y Cr and Cb Refer to the descriptions for DEF_Y and DEF_C for additional information In this mode the decoder also outputs a stable 27 MHz clock HS and VS Setting DEF_VAL_EN to 0 default outputs a colored screen determined by user programmable Y Cr and Cb values when the decoder free runs Free run mode is turned on and off by the DEF_VAL_AUTO_EN bit Setting DEF_VAL_EN to 1 forces a colored screen output determined by user programmable Y Cr and Cb values This overrides picture data even if the decoder is locked DEF_VAL_AUTO_EN Default Value Automatic Enable Address 0x0C 1 This bit enables the automatic use of the default values for Y Cr and Cb when the ADV7189B cannot lock to the video signal Setting DEF_VAL_AUTO_EN to 0 disables free run mode If the decoder is unlocked it outputs noise Setting DEF_VAL_EN to 1 default enables free run mode A colored screen set by the user programmable Y Cr and Cb values is displayed when the decoder loses lock CLAMP OPERATION The input video is ac coupled into the ADV7189B through a 0 1 capacitor The recommended range of the input video signal range be 0 5 V to 1 6 V typically 1 V p p If the signal exceeds the range it cannot be processed correctly in the decoder Because the input is ac coupled into the decoder its dc value needs to be resto
92. ating the NTSC Vsync end position NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 The default value of NFTOG is 00011 indicating the NTSC Field toggle position For all NTSC PAL FIELD timing controls both the F bit in the AV code and the FIELD signal on the FIELD pin are modified Rev B Page 44 of 104 ADV7189B Table 57 Recommended User Settings for PAL See Figure 27 Register Register Name Write 0x31 Vsync Field Control 1 Ox1A 0x32 Vsync Field Control 2 0x81 0x33 Vsync Field Control 3 0x84 0x34 Hsync Position Control 1 0x00 0x35 Hsync Position Control 2 0x00 0x36 Hsync Position Control 3 0x7D 0x37 Polarity 0x29 OxE8 PAL_V_Bit_Beg 0x41 OxE9 PAL_V_Bit_End 0x84 OxEA PAL_F_Bit_Tog 0x06 FIELD 1 i 624 65 1 2 3 4 5 6 7 9 10 22 m 4 PVEND 4 0 0x4 PFTOG 4 0 0x3 iex FIELD 2 311 312 313 314 315 316 317 318 319 320 321 3220 0 335 336 1 337 OUTPUT VIDEO PVBEG 4 0 5 PVENDJ 4 0 0x4 Moo 4 amp PFTOG 4 0 0x3 Figure 26 PAL Default BT 656 The polarity of H V and F is embedded in the data 04983 0 026 Rev B Page 45 of 104 ADV7189B pore PU j 1622 1 1623 624 65 1 2 3 4 5 e 7 8 9 10 111 bs a i ourpur if VIDEO HS OUTPUT l vs amp OUTPUT PVBEG 4 0 0 1 PVEND A 0 0x4 7 OUTPUT PFTOG 4 0 0x6
93. ault there is no delay Setting PFTOGDELO to 1 delays the F toggle transition on an odd field by a line relative to PFTOG PFTOGDELE PAL Field Toggle Delay on Even Field Address OxEA 6 When PFTOGDELE is 0 there is no delay Setting PFTOGDELE to 1 default delays the F toggle transition on an even field by a line relative to PFTOG PFTOGSIGN PAL Field Toggle Sign Address OxEA 5 Setting PFTOGSIGN to 0 delays the field transition Set for user manual programming Setting PFTOGSIGN to 1 default advances the field transition Not recommended for user programming PFTOG PAL Field Toggle Address 0 4 0 The default value of PFTOG is 00011 indicating the PAL field toggle position For all NTSC PAL field timing controls the F bit in the AV code and the Field signal on the FIELD DE pin are modified ADVANCE TOGGLE OF FIELD BY PTOG 4 0 DELAY TOGGLE OF FIELD BY PFTOG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 1 ADDITIONAL ADDITIONAL DELAY BY 1 LINE FIELD TOGGLE Figure 30 PAL F Toggle 04983 0 030 Rev B Page 47 of 104 ADV7189B SYNC PROCESSING The ADV7189B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video If desired the blocks can be disabled via the following two bits ENHSPLL Enable Hsync Processor Address 0x01 6 The Hsync processor is desi
94. ault Phase of the chroma signal 0 Ox7F Phase of the chroma signal 90 0x80 Phase of the chroma signal 4 90 SD OFF Cb 7 0 Description 0x80 default 0x00 OxFF 0 offset applied to the Cb channel 312 mV offset applied to the Cb channel 312 mV offset applied to the Cb channel SD OFF Cr 7 0 SD Offset Cr Channel Address 0xE2 7 0 This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture There is a functional overlap with the Hue 7 0 register Table 26 SD OFF Cr Function SD OFF Cr 7 0 Description 0x80 default 0x00 OxFF 0 offset applied to the Cr channel 312 mV offset applied to the Cr channel 312 mV offset applied to the Cr channel BRI 7 0 Brightness Adjust Address 0x0A 7 0 This register controls the brightness of the video signal through the ADV7189B It allows the user to adjust the brightness of the picture Table 27 BRI Function BRI 7 0 Description 0x00 default Offset of the luma channel OIRE Ox7F Offset of the luma channel 100IRE OxFF Offset of the luma channel 100IRE HUE 7 0 Hue Adjust Address 0x0B 7 0 This register contains the value for the color hue adjustment It allows the user to adjust the hue of the picture HUE 7 0 has a range of 90 with 0x00 equivalent to an adjustment of 0 The resolution of HUE 7 0 is 1 bit 0 7 DEF Y 5 0 Default
95. been decoded no data packet is output even if the corresponding line enable bit is set DATA IDENTIFICATION a DATA OPTIONAL PADDING CHECK FS PREAMBLE FOR ANCILLARY DATA Each data packet starts immediately after the EAV code of the preceding line Figure 35 and Table 64 show the overall structure of the data packet Entries within the packet are as follows Fixed preamble sequence of 0x00 OxFF OxFF Data identification word DID The value for the DID marking a Gemstar or CCAP data packet is 0x140 10 bit value Secondary data identification word SDID which contains information about the video line from which data was retrieved whether the Gemstar transmission was of 1x or 2x format and whether it was retrieved from an even or odd field Data count byte giving the number of user data words that follow User data section Optional padding to ensure that the length of the user data word section of a packet is a multiple of four bytes requirement as set in ITU R BT 1364 Checksum byte Table 64 lists the values within a generic data packet that is output by the ADV7189B in 10 bit format SECONDARY DATA IDENTIFICATION 04983 0 035 USER DATA 4 OR 8 WORDS Figure 35 Gemstar and CCAP Embedded Data Packet Generic Table 64 Generic Data Output Packet Byte DI9 DI8 DI7 DI6 D 5 D 4 DI3 D 2 D 1 0 0 Description 0 0 0
96. bit PAL_SW_LK_CHNG_CLR 0 Do not clear 1 Clears PAL_SW_LK_CHNG_Q bit Reserved x Not used Reserved Not used Ox4C Interrupt SD OP CHNG MSKB Masks SD OP CHNG QObit Mask 2 Unmasks SD OP CHNG Qbit SD V LOCK CHNG MSKB Masks SD V LOCK CHNG bit Read Unmasks SD V LOCK CHNG Q Write bit Register SD H LOCK CHNG MSKB Masks SD_H_LOCK_CHNG_Q bit Unmasks SD_H_LOCK_CHNG_Q Register bi it Access Page 2 SD AD CHNG 0 Masks SD AD CHNG bit 1 Unmasks SD AD CHNG Qbit SCM LOCK CHNG MSKB 0 Masks SCM LOCK CHNG bit 1 Unmasks SCM LOCK CHNG bit PAL SW LK CHNG MSKB 0 Masks PAL SW LK CHNG bit 1 Unmasks PAL SW LK CHNG Q bit Reserved x Not used Reserved Not used Rev B Page 71 of 104 ADV7189B The following registers are located in the Common Map and Register Access Page 1 Table 86 Common and Normal Page 1 Register Map Details Subaddress Register Bit Description Bits 7161514 Comments Notes 0x00 Input Control INSEL 3 0 The INSEL bits allow the user to select an input channel as well as the input format CVBS in on AIN1 CVBS in on AIN2 CVBS in on AIN3 CVBS in on AIN4 CVBS in on AIN5 CVBS in on AIN6 Composite Y on AIN1 Con AIN4 Y on AIN2 C on AIN5 Y on AIN3 C on AIN6 S Video o o ojo ojoj o o uw ojoj ojoj o
97. cs to give improved vertical lock e Hsync Processor The Hsync processor is designed to filter incoming Hsyncs that are corrupted by noise providing much improved performance for video signals with stable time base but poor SNR VBI DATA RECOVERY The ADV7189B can retrieve the following information from the input video e Wide screen signaling WSS e generation management system CGMS e Closed captioning CC e Macrovision protection presence e EDTV data e Gemstar compatible data slicing The ADV7189B is also capable of automatically detecting the incoming video standard with respect to Color subcarrier frequency e Field rate Line rate The ADV7189B can configure itself to support PAL BGHID PAL M N PAL combination N NTSC M NTSC J SECAM 50 Hz 60 Hz NTSC4 43 and PAL60 GENERAL SETUP Video Standard Selection The VID SEL 3 0 register allows the user to force the digital core into a specific video standard Under normal circumstances this should not be necessary The VID SEL 3 0 bits default to an autodetection mode that supports PAL NTSC SECAM and variants thereof The following section provides more informa tion on the autodetection system Autodetection of SD Modes To guide the autodetect system of the ADV7189B individ ual enable bits are provided for each of the supported video standards Setting the relevant bit to 0 inhibits the standard from being detected automatically Instead
98. curacy HUE 1 Degrees Color Saturation Accuracy CL_AC 1 Color AGC Range 5 400 Chroma Amplitude Error 0 4 Chroma Phase Error 0 3 Degrees Chroma Luma Intermodulation 0 1 LUMA SPECIFICATIONS Luma Brightness Accuracy CVBS 1 V I P 1 Luma Contrast Accuracy CVBS 1 V I P 1 96 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7189BKSTZ The min max specifications are guaranteed over this range Rev B Page 7 of 104 ADV7189B TIMING SPECIFICATIONS Guaranteed by characterization 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6 V 1 65 V to 2 0 V operating temperature range unless otherwise specified Table 3 Parameter Symbol Test Conditions Min Max Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 28 6363 MHz Frequency Stability 50 ppm PC PORT SCLK Frequency 400 kHz SCLK Min Pulse Width High ti 0 6 Hs SCLK Min Pulse Width Low t 1 3 us Hold Time Start Condition ts 0 6 us Setup Time Start Condition t4 0 6 us SDA Setup Time ts 100 ns SCLK and SDA Rise Time te 300 ns SCLK and SDA Fall Time t7 300 ns Setup Time for Stop Condition ts 0 6 us RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio to tio 45 55 55 45 96 duty cycle LLC1 Rising to LLC2 Rising th 0 5 ns LLC1 Rising to LLC2 Falling te 0 5 ns DATA AND CONTROL OUTPUTS Data Output Transitional Time tis Negative clock edge to start of
99. de Sel Tee No delay CTA 2 0 101b 1 0 0 Chroma 1 pixel late 110 1 Chroma 2 pixels late YPrPb mode 1 1 0 Chroma 3 pixels late CTA 2 0 110b 1 1 1 Not valid setting AUTO_PDC_EN Automatically 0 Use values in LTA 1 0 and programs the LTA CTA values so CTA 2 0 for delaying that luma and chroma are aligned luma chroma at the output for all modes of 1 LTA and CTA values operation determined automatically SWPC Allows the Cr and Cb 0 No swapping samples to be swapped 1 Swap the Cr and Cb O P samples 0x2B Misc Gain PW_UPD Peak white update 0 Update once per video Peak white must Control determines the rate of gain line be enabled 1 Update once per field See LAGC 2 0 Reserved 1 0 0 0 Set to default CKE Color kill enable allows the 0 Color kill disabled For SECAM color kill color kill function to be switched 7 Color kill enabled threshold is set at on and off 8 See CKILLTHR 2 0 Reserved 1 Set to default Ox2C AGC Mode CAGC 1 0 Chroma automatic gain 0 0 Manual fixed gain Use CMG 1 1 0 Control control selects the basic mode of 0 1 Use luma gain for chroma operation for the AGC in the Au tic dai Based lor burst chroma path utomatic gain ased on color burs 1 1 Freeze chroma gain Reserved 1 Set to 1 LAGC 2 0 Luma automatic gain Manual fixed gain Use LMG 11 0 control selects the mode of 0 0 1 AGC Peak white algorithm Blank level to sync tip operation for the gain control in off the lue
100. e limit the capacitance that each of the digital outputs drives to less than 15 pF This can easily be accomplished by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV7189B creating more digital noise on its power supplies Rev B Page 97 of 104 ADV7189B DIGITAL INPUTS The digital inputs on the ADV7189B are designed to work with 3 3 V signals and are not tolerant of 5 V signals Extra compo nents are needed if 5 V logic signals are required to be applied to the decoder ANTIALIASING FILTERS For inputs from some video sources that are not bandwidth limited signals outside the video band can alias back into the video band during A D conversion and appear as noise on the output video The ADV7189B oversamples the analog inputs by a factor of 4 This 54 MHz sampling frequency reduces the requirement for an input filter for optimal performance it is recommended that an antialiasing filter be employed The recommended low cost circuit for implementing this buffer and filter circuit for all analog input signals is shown in Figure 45 The buffer is a simple emitter follower using a single npn transistor The antialiasing filter is implemented using passive components The passive filter is a third order Butterworth filter with a 3 dB point of 9 MHz The frequency response of the passive filter is shown in Figure 43 T
101. e ADC range After digitization the digital fine clamp block corrects for any remaining variations in dc level Since the dc level of an input video signal refers directly to the brightness of the picture transmitted it is important to perform a fine clamp with high accuracy otherwise brightness variations can occur Dynamic changes in the dc level lead to visually objectionable artifacts so it is recommended not to use dynamic changes The damping scheme has to complete two tasks It must be able to acquire a newly connected video signal with a com pletely unknown dc level and it must maintain the dc level during normal operation For quickly acquiring an unknown video signal the large current clamps can be activated It is assumed the amplitude of the video signal is of a nominal value at this point Control of the coarse and fine current clamp parameters is performed auto matically by the decoder Standard definition video signals may have excessive noise on them In particular CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise 2100 mV A voltage clamp is unsuitable for this type of video signal Instead the ADV7189B employs a set of four current sources that cause coarse 50 5 mA and fine 0 1 mA currents to flow into and away from the high imped ance node that carries the video signal see Figure 10 PROCESSOR TS FINE CLAMP SDP
102. e a reset value specified They keep their last written value These bits are marked as having a reset value of x in the register table After the reset sequence the part immediately starts to acquire the incoming video signal After setting the RES bit or initiating a reset via the pin the part returns to the default mode of operation with respect to its primary mode of operation All bits are loaded with their default values making this bit self clearing Executing a software reset takes approximately 2 ms However it is recommended to wait 5 ms before any further writes are performed The master controller receives a no acknowledge condi tion on the ninth clock cycle when chip reset is implemented See the MPU Port Description section for a full description When RES is 0 default operation is normal When RES is 1 the reset sequence starts Rev B Page 16 of 104 ADV7189B GLOBAL PIN CONTROL Three State Output Drivers TOD Address 0 03 6 This bit allows the user to three state the output drivers of the ADV7189B Upon setting the TOD bit the P 19 0 HS VS FIELD and SFL pins are three stated The timing pins HS VS FIELD can be forced active via the TIM OE bit For more information on three state control refer to the Three State LLC Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits The ADV7189B supports thr
103. e autodetection of NTSC style systems with a 4 43 MHz color subcarrier Setting AD_N443_EN to 1 default enables the detection AD_P60_EN Enable Autodetection of PAL60 Address 0 07 4 Setting AD_P60_EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate Setting AD_P60_EN to 1 default enables the detection AD PALN EN Enable Autodetection of PAL N Address 0x07 3 Setting AD PALN EN to 0 disables the detection of the PAL N standard Setting AD PALN EN to 1 default enables the detection AD PALM EN Enable Autodetection of PAL M Address 0x07 2 Setting AD PALM EN to 0 disables the autodetection of PAL M Setting AD PALM EN to 1 default enables the detection AD NTSC EN Enable Autodetection of NTSC Address 0x07 1 Setting AD NTSC EN to 0 disables the detection of standard NTSC Setting AD NTSC EN to 1 default enables the detection AD PAL EN Enable Autodetection of PAL Address 0x07 0 Setting AD PAL EN to 0 disables the detection of standard PAL Setting AD PAL EN to 1 default enables the detection SELECT THE RAW LOCK SIGNAL SRLS TIME WIN FREE RUN Fgc LOCK TAKE Fgc LOCK INTO ACCOUNT FSCLE COUNTER INTO LOCK COUNTER OUT OF LOCK SFL INV Subcarrier Frequency Lock Inversion This bit controls the behavior of the PAL switch bit in the SFL GenLock Telegram data stream It was implemented to solve some compatibility issues with video encoders It solves two pr
104. e coating on the leads of each device is 100 pure Sn electroplate The device is suitable for Pb free applications and can withstand surface mount soldering at up to 255 C 5 C In addition it is backward compatible with conventional SnPb soldering processes This means the electroplated Sn coating can be soldered with Sn Pb solder pastes at conventional reflow temperatures of 220 C to 235 C 27 Pb free part Rev B Page 101 of 104 ADV7189B NOTES Rev B Page 102 of 104 ADV7189B NOTES Rev B Page 103 of 104 ADV7189B NOTES Purchase of licensed C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips PC Patent Rights to use these components in an system provided that the system conforms to the I C Standard Specification as defined by Philips 2005 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D04983 0 9 05 B DEVICES Rev B Page 104 of 104 www analog com
105. ed SFL output enables SFL information output on encoder and decoder the SFL pin to be connected directly BL C VBI Blank Chroma during 0 Decode and output color During VBI VBI If set enables data in the VBI 1 Blank Crand Cb region to be passed through the decoder undistorted TIM_OE Timing signals output 0 HS VS F three stated Controlled by TOD enable 1 HS VS F forced active Reserved x x Reserved 1 BT656 4 Allows the user to select 0 BT656 3 compatible an output mode compatible with 1 BT656 4 compatible ITU R BT656 3 4 Rev B Page 73 of 104 ADV7189B Bits Subaddress Register Bit Description 716 5 43 Comments Notes 0x07 Autodetect AD PAL EN PAL B G I H Disable Enable autodetect enable Enable AD NTSC EN NTSC autodetect Disable enable Enable AD PALM EN PAL M autodetect Disable enable Enable AD PALN EN PAL N autodetect 0 Disable enable 1 Enable P60 EN PAL 60 autodetect 0 Disable enable 1 Enable AD N443 EN NTSC443 autodetect 0 Disable enable 1 Enable AD SECAM EN SECAM autodetect 0 Disable enable 1 Enable AD SEC525 EN SECAM 525 0 Disable autodetect enable 1 Enable 0x08 Contrast CON 7 0 Contrast adjust This is 1 0 Luma gain 1 0x00 Gain 0 Register the user control for contrast 0x80 Gain 1 adjustment OxFF Gain 2 0x09 Reserved Reserved Ox0A Brightness BRI 7 0 T
106. ed data is high EDTVD EDTV Sequence Detected Address 0x90 2 Logic 1 for this bit indicates the data in the EDTV1 2 3 registers is valid The EDTVD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the transmitted data When EDTVD is 0 no EDTV sequence is detected Confidence in decoded data is low When EDTVD is 1 an EDTV sequence is detected Confidence in decoded data is high CGMSD CGMS A Sequence Detected Address 0x90 3 Logic 1 for this bit indicates the data in the CGMSI 2 3 registers is valid The CGMSD bit goes high if a valid CRC checksum has been calculated from a received CGMS packet When CGMSD is 0 no CGMS transmission is detected and confidence in the decoded data is low When CGMSD is 1 the CGMS sequence is decoded and confidence in the decoded data is high Rev B Page 48 of 104 ADV7189B ENABLE CRC CGMS A Sequence Address 0xB2 2 For certain video sources the CRC data bits can have an invalid format In such circumstances the CRC checksum validation procedure can be disabled The CGMSD bit goes high if the rising edge of the start bit is detected within a time window When CRC ENABLE is 0 no CRC check is performed The CGMSD bit goes high if the rising edge of the start bit is detected within a time window When CRC ENABLE is 1 default CRC checksum is used to validate the CGMS sequence The CGMSD
107. ee stating via a dedicated pin When set high the OE pin three states the output drivers for P 19 0 HS VS FIELD and SFL The output drivers are three stated if the TOD bit or the OE pin is set high When TOD is 0 default the output drivers are enabled When TOD is 1 the output drivers are three stated Three State LLC Drivers TRI LLC Address 0x1D 7 This bit allows the output drivers for the LLC1 pin and LLC2 pin ofthe ADV7189B to be three stated For more information on three state control refer to the Three State Output Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits When TRI LLC is 0 default the LLC pin drivers work according to the DR STR C 1 0 setting pin enabled When TRI LLC is 1 the LLC pin drivers are three stated Timing Signals Output Enable TIM OE Address 0x04 3 The OE bit should be regarded as an addition to the TOD bit Setting it high forces the output drivers for HS VS and FIELD into the active that is driving state even if the TOD bit is set If set to low the HS VS and FIELD pins are three stated dependent on the TOD bit This functionality is useful if the decoder is to be used as a timing generator only This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free run mode where a separate chip can output for instance a company logo
108. efault Adaptive comb mode Adaptive 5 lines 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 3 lines 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 5 lines 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 3 lines 2 taps luma comb Rev B Page 37 of 104 ADV7189B AV CODE INSERTION AND CONTROLS This section describes the C based controls that affect e Insertion of AV codes into the data stream e Data blanking during the vertical blank interval VBI e The range of data values permitted in the output data stream e The relative delay of luma vs chroma signals Note Some of the decoded VBI data is being inserted dur ing the horizontal blanking interval See the Gemstar Data Recovery section for more information BT656 4 ITU Standard BT R 656 4 Enable Address 0x04 7 The ITU has changed the position for toggling of the V bit within the SAV EAV codes for NTSC between Revisions 3 and Revision 4 The BT656 4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard For further information review the standard at www itu int Note the standard change affects NTSC only and has no bearing on PAL When BT656 4 is 0 default the BT656 3 specification is used The V bit goes low at EAV of Lines 10 and
109. emstar word3 3 0 0 0 User data words 12 IEP EP 0 0 Gemstar word4 7 4 0 0 User data words 13 IEP EP 0 0 Gemstar word4 3 0 0 0 User data words 14 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Table 67 Gemstar 2x Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 1 Line 3 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 Gemstar Word 1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 Gemstar Word3 7 0 0 0 User data words 9 Gemstar Word4 7 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Table 68 Gemstar 1x Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 0 Line 3 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 IEP EP 0 0 Gemstar Word1 7 4 0 0 User data words 7 IEP EP 0 0 Gemstar Word 1 3 0 0 0 User data words 8 IEP EP 0 0 Gemstar Word2 7 4 0 0 User data words 9 IEP EP 0 0 Gemstar Word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Rev B Page 54 of 104 Tab
110. es are detected Ox9D Letterbox 3 Read Only LB LCB 7 0 Letterbox data register Reports the number of black lines detected at the bottom of active video This feature examines the active video at the start and at the end of each field It enables format detection even if the video is not accompanied by a CGMS or WSS sequence OxB2 CRC Enable Write Register Reserved Set as default CRC ENABLE Enable CRC checksum decoded from CGMS packet to validate CGMSD Turn off CRC check CGMSD goes high with valid checksum Reserved Set as default 0xC3 ADC SWITCH 1 ADCO SW 3 0 Manual muxing control for ADCO No connection AIN1 AIN2 AIN3 AIN4 AIN5 a ojo AIN6 No connection ojojojojojo oj o No connection AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 ioil o 2 o 23 oj o 23 o 2 oj 3 o No connection SETADC sw man en 1 ADC1_SWJ 3 0 Manual muxing control for ADC1 No connection No connection No connection AIN3 AIN4 AIN5 AIN6 No connection No connection No connection No connection AIN9 AIN10 AIN11 ojo AIN12 i 2 2 2 2 2 1 o o oi jo ojo o jo
111. es picture quality DNR EN Digital Noise Reduction Enable Address Ox4D 5 The DNR EN bit enables the DNR block or bypasses it Setting DNR EN to 0 bypasses DNR disables it Setting DNR EN to 1 default enables digital noise reduction on the luma data Rev B Page 34 of 104 ADV7189B DNR_TH 7 0 DNR Noise Threshold Address 0x50 7 0 The DNR TH 7 0 value is an unsigned 8 bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data Programming a large value into _ 7 0 causes the DNR block to interpret even large transients as noise and remove them The effect on the video data is therefore more visible Programming a small value causes only small transients to be seen as noise and to be removed The recommended DNR TH 7 0 setting for A V inputs is 0x04 and the recommended DNR TH 7 0 setting for tuner inputs is OxOA The default value for DNR TH 7 0 is 0x08 indicating the threshold for maximum luma edges to be interpreted as noise COMB FILTERS The comb filters of the ADV7189B have been greatly improved to automatically handle video of all types standards and levels of quality The NTSC and PAL configuration registers allow the user to customize comb filter operation depending on which video standard is detected by autodetection or selected by manual programming In addition to the bits listed in this section there are some further ADI
112. etterbox 3 LB_LCB 7 LB_LCB 6 LB_LCB 5 LB_LCB 4 LB_LCB 3 LB_LCB 2 LB_LCB 1 LB_LCB O Reserved CRC Enable CRC_ENABLE Reserved ADC Switch 1 ADC1_SW 3 ADC1_SW 2 ADC1_SW 1 ADC1_SW 0 ADCO_SW 3 ADCO_SW 2 ADCO_SW 1 ADCO SW 0 ADC Switch 2 ADC SW M AN ADC2 SW 3 ADC2 SW 2 ADC2 SW 1 ADC2 SW 0 Reserved Letterbox LB TH 4 LB TH 3 LB TH 2 LB TH 1 LB TH O Control 1 Letterbox LB SL 3 LB SL 2 LB SL 1 LB SL O LB LB EL 2 LB EL 1 LB ELO Control 2 Reserved Reserved Reserved Rev B Page 66 of 104 ADV7189B Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SD Offset Cb SD OFF CB 7 SD OFF CB 6 SD OFF CB 5 SD OFF CB 4 SD OFF CB 3 SD OFF CB 2 SD OFF CB 1 SD OFF CB O SD Offset Cr SD OFF CRZ7 SD OFF CR 6 SD OFF CR 5 SD OFF CRA4A SD OFF CR3 SD OFF CR2 SD OFF CR 1 SD OFF CR O SD Saturation SD SAT CB 7 SD SAT CB 6 SD SAT CB 5 SD SAT CBA SD SAT CB 3 SD SAT CB2 SD SAT CB 1 SD SAT CB O Cb SD Saturation SD SAT CRZ7 SD SAT 6 SD SAT CR 5 SD SAT CRA SD SAT CR3 SD SAT CR2 SD SAT CR 1 SD SAT CRO Cr NTSC V Bit NVBEGDEL O NVBEGDEL E NVBEGSIGN NVBEG 4 NVBEG 3 NVBEG 2 NVBEG 1 NVBEG O Begin NTSC V Bit End NVENDDEL O NVENDDEL E NVENDSIGN NVEND 4 NVEND 3 NVEND 2 NVEND 1 NVEND O NTSC F Bit NFTOGDEL O NFTOGDEL E NFTOGSIGN NFTOG A NFTOG 3 NFTOG 2 NFTOG 1 NFTOG 0 Toggle PAL V Bit Begin PVBEGDEL O PVBEGDEL E PVBEGSI
113. face itself is unaffected and remains operational in power down mode The ADV7189B leaves the power down state if the PWRDN bit is set to 0 via or if the overall part is reset using the RESET pin Note PDBP must be set to 1 for the PWRDN bit to power down the ADV7189B When PWRDN is 0 default the chip is operational When PWRDN is 1 the ADV7189B is in chip wide power down ADC Power Down Control The ADV7189B contains three 12 bit ADCs ADC 0 ADC 1 and ADC 2 If required it is possible to power down each ADC individually The ADCs should be powered down when in e CVBS mode ADC 1 and ADC 2 should be powered down to save on power consumption e S Video mode ADC 2 should be powered down to save on power consumption PWRDN ADC 0 Address 0x3A 3 When 0 is 0 default the ADC is in normal operation When PWRDN 0 is 1 ADC 0 is powered down PWRDN ADCOC 1 Address 0x3A 2 When PWRDN ADC 1 is 0 default the ADC is in normal operation When PWRDN_ADC_1 is 1 ADC 1 is powered down PWRDN ADC 2 Address 0x3A 1 When PWRDN ADC 2 is 0 default the ADC is in normal operation When 2 is 1 ADC 2 is powered down RESET CONTROL Chip Reset RES Address 0x0F 7 Setting this bit equivalent to controlling the RESET pin on the ADV7189B issues a full chip reset All registers get reset to their default values Note Some register bits do not hav
114. facturer For detailed crystal circuit design and optimiza tion an application note on crystal design considerations is available for further reference XTAL XTAL 1 Rz1MO 0 C1 47pF XTAL C2 47pF lt i 28 63636MHz 04983 Figure 44 Crystal Circuit Use the following guidelines to ensure correct operation e Use the correct frequency crystal which is 28 63636 MHz Tolerance should be 50 ppm or better e Usea parallel resonant crystal e Place a 1 shunt resistor across pins XTAL1 and XTAL2 as is shown in Figure 45 e Know the Croa for the crystal part number selected The value of Capacitors C1 and C2 must match Croan for the specific crystal part number in the user s system e find Croan use the following guideline 1 2 C 2 Cs Cpg Where Cy is the pin to ground capacitance Approximately 4 pF to 10 pF Cs is the PCB stray capacitance Approximately 2 pF to 3pF For example Croan 30 pF C 2 30 3 4 50 pF Therefore two 47 pF capacitors can be chosen for 1 and C2 Rev B Page 98 of 104 ADV7189B TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7189B video decoder are shown in Figure 45 and Figure 46 For a detailed schematic diagram for the ADV7189B refer to the ADV7189B evaluation note AVDD_5V FILTER L10 12uH m 4983 0 041 AGND Figure 45 ADI Recommended Anti Aliasing Circuit for All Input Channels
115. for user programming NVENDDELE Delay V bit going No delay low by one line relative to NVEND Additional delay by even field 1line NVENDDELO Delay V bit going No delay low by one line relative to NVEND Additional delay by odd field 1line OxE7 NTSCFBit NFTOG 4 0 How many lines after 0 0 NTSC default Toggle Icount rollover to toggle F signal NFTOGSIGN Set to low when manual programming Not suitable for user programming NFTOGDELE Delay F transition No delay by one line relative to NFTOG Additional delay by even field 1line NFTOGDELO Delay F transition No delay by one line relative to NFTOG Additional delay by odd field 1line OxE8 PAL V Bit PVBEG 4 0 How many lines after 0 0 PAL default BT 656 Begin Icount rollover to set V high PVBEGSIGN Set to low when manual programming Not suitable for user programming PVBEGDELE Delay V bit going No delay high by one line relative to Additional delay by PVBEG even field 1line PVBEGDELO Delay V bit going No delay high by one line relative to Additional delay by PVBEG odd field 1line Rev B Page 87 of 104 ADV7189B Bits Subaddress Register Bit Description 7 6 5 4 3 2 0 Comments Notes OxE9 PAL V Bit PVEND 4 0 How many lines after 1 0 1 0 PAL default BT 656 End lcouwr rollover to set V low PVEN
116. from sources such as a VCR ADLLT enables the ADV7189B to track and decode poor quality video sources such as VCRs noisy sources from tuner outputs VCD players and camcorders The ADV7189B contains a chroma transient improvement CTI processor that sharpens the edge rate of chroma transitions resulting in sharper vertical transitions The ADV7189B can process a variety of VBI data services such as closed captioning CC wide screen signaling WSS copy generation management system CGMS EDTV Gemstar 1x 2x and extended data service XDS The ADV7189B is fully Macrovision certified detection circuitry enables Type L Type IL and Type III protection levels to be identified and reported to the user The decoder is also fully robust to all Macrovision signal inputs Rev B Page 4 of 104 ADV7189B FUNCTIONAL BLOCK DIAGRAM OULNI 14S 5 SH viva 19 OUTPUT FORMATTER TOYULNOSD LAdLNO 3384 JOYULNOD 971 aaZISJHLNAS 8WO2 31dWvs3u VINOHHO VWOHUHO NOILH3SNI 3002 7TOHLINOO AV awos 31dWvsau NOILOSLAGOLNV 15 TOULNOD 1V8019 TOYHLNOD NIVO 7TOH1NOO NIVO NOILO313Gd NOISIAOHD VIN AU3AOO3H VLVC IGA Yala AH3AOO3H 9S4 1oVHlX3 dari VW 55390 NOILINISAG QHVONVIS div 1o 3NIJ VINOHH vivd
117. gned to filter incoming Hsyncs that have been corrupted by noise providing improved performance for video signals with stable time bases but poor SNR Setting ENHSPLL to 0 disables the Hsync processor Setting ENHSPLL to 1 default enables the Hsync processor ENVSPROC Enable Vsync Processor Address 0x01 3 This block provides extra filtering of the detected Vsyncs to give improved vertical lock Setting ENVSPROC to 0 disables the Vsync processor Setting ENVSPROC to 1 default enables the Vsync processor VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7189B e Wide screen signaling WSS e generation management systems CGMS e Closed captioning CC e EDTV e Gemstar 1x and 2x compatible data recovery The presence of any of the above signals is detected and if applicable a parity check is performed The result of this testing is contained in a confidence bit in the VBI Info 7 0 register Users are encouraged to first examine the VBI Info register before reading the corresponding data registers All VBI data decode bits are read only All VBI data registers are double buffered with the field sig nals This means that data is extracted from the video lines and appears in the appropriate registers with the next field transition They are then static until the next field The user should start I C read sequence with VS by first examining the VBI Info register Then
118. he flat pass band up to 6 MHz is essential The attenuation of the signal at the output of the filter due to the voltage divider of R24 and R63 is compen sated for in the ADV7189B part using the automatic gain control The ac coupling capacitor at the input to the buffer creates a high pass filter with the biasing resistors for the transistor This filter has a cut off of 2 x mx R39 R89 x C93 0 62 Hz It is essential the cutoff of this filter is less than 1 Hz to ensure correct operation of the internal clamps within the part These clamps ensure that the video stays within the 5 V range of the op amp used 40 80 100 04983 0 040 120 100k 300k 1M 3M 10M 30M 100M 300M 1G FREQUENCY Hz Figure 43 Third Order Butterworth Filter Response CRYSTAL LOAD CAPACITOR VALUE SELECTION Figure 44 shows an example reference clock circuit for the ADV7189B Special care must be taken when using a crystal cir cuit to generate the reference clock for the ADV7189B Small variations in reference clock frequency can cause autodetection issues and impair the ADV7189B performance Note Load capacitor values are dependent on crystal attributes The load capacitance given in a crystal data sheet specifies the parallel resonance frequency within the tolerance at 25 C It is therefore important to design a circuit that matches the load capacitance in order to achieve the frequency stipulated by the manu
119. hen HS is high low When VSEHO is 0 the VS pin goes low inactive at the middle ofa line of video odd field When VSEHO is 1 default the VS pin changes state at the start of a line odd field VSEHE VS End Horizontal Position Even Address 0x33 6 The VSEHO and VSEHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSEHE is 0 default the VS pin goes low inactive at the middle of a line of video even field When VSEHE is 1 the VS pin changes state at the start of a line even field PVS Polarity VS Address 0x37 5 The polarity of the VS pin can be inverted using the PVS bit When PVS is 0 default VS is active high When PVS is 1 VS is active low PF Polarity FIELD Address 0x37 3 The polarity of the FIELD pin can be inverted using the PF bit When PF is 0 default FIELD is active high When PF is 1 FIELD is active low Rev B Page 41 of 104 ADV7189B FIELD 1 OUTPUT 770 VIDEO it E TEUELLILILLULBSET ET UT LI LI NVEND A4 0 0x4 1BT 656 4 i REG 0x04 BIT 7 1 NFTOG 4 0 0x3 FIELD 2 264 265 266 267 268 269 270 271 272 273 274 275 276 OUTPUT e UT VIDEO 11 NVEND 4 0 0x4 1BT 656 4 REG 0x04 7 1 NFTOG 4 0 0 3 TAPPLIES IF NEMAVMODE 0 MUST BE MANUALLY SHIFTED IF NEWAVMODE
120. his register controls the 0x00 OIRE Register brightness of the video signal Ox7F 100IRE 0x80 100IRE OxOB Hue HUE 7 0 This register contains the 0 0 0 0 Hue range Register value for the color hue adjustment 90 to 90 Ox0C Default DEF_VAL_EN Default value enable Free run mode dependent Value Y on DEF_VAL_AUTO_EN Force Free run mode on and output blue screen DEF_VAL_AUTO_EN Default value Disable Free run mode When lock is lost Enable Automatic Free Free run mode can run mode blue screen be enabled to output stable timing clock and a set color DEF Y 5 0 Default value Y This 010 Y 7 0 DEF Y 5 0 0 0 Default Y value register holds the Y default value output in Free run mode OxOD Default DEF C 7 0 Default value C The Cr 0 1 qu eds Cr 7 0 DEF C 7 410 0 0 Default Cb Cr value Value C and Cb default values are defined 0 output Free run in this register Cb 7 0 DEF_C 3 0 0 0 mode Default values 0 0 give blue screen output OxOE ADI Control Reserved 0 0 Set as default SUB USR EN Enables the user to access the Interrupt map Access User Reg Map Access Interrupt Reg Map See Figure 38 Reserved Set as default Rev B Page 74 of 104 ADV7189B Bits Subaddress Register
121. iption CKILLTHR 2 0 SECAM NTSC PAL 000 No color kill Kill at 0 596 001 Kill at 5 Kill at 1 596 010 Kill at 7 Kill at 2 596 011 Kill at 8 Kill at 4 096 100 default Kill at 9 596 Kill at 8 5 default 101 Kill at 1596 Kill at lt 16 0 110 Kill at 3296 Kill at 32 096 111 Reserved for ADI internal use only Do not select Rev B Page 33 of 104 ADV7189B CHROMA TRANSIENT IMPROVEMENT CTI The signal bandwidth allocated for chroma is typically much smaller than that of luminance In the past this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance The uneven bandwidth however can lead to visual artifacts in sharp color transitions At the border of two bars of color both components luma and chroma change at the same time see Figure 18 Due to the higher bandwidth the signal transition of the luma component is usually a lot sharper than that of the chroma component The color edge is not sharp but is blurred in the worst case over several pixels LUMA SIGNAL WITH A LUMA TRANSITION ACCOMPANIED SIGNAL BY A CHROMA TRANSITION ORIGINAL SLOW CHROMA DEMODULATED CHROMA TRANSITION PRIOR CTI 5 SIGNAL SHARPENED CHROMA 5 TRANSITION AT THE OUTPUT OF CTI E Figure 18 CTI Luma Chroma Transition The chroma transient improvement block examines
122. is means if the settings of INSEL and the manual input muxing registers ADCO 1 2 sw contradict each other the ADCO ADCI ADCA2 sw settings apply and INSEL is ignored Manual input muxing controls only the analog input muxes INSEL 3 0 still has to be set so the follow on blocks process the video data in the correct format ADV7189B This means INSEL must be used to tell the ADV7189B whether the input signal is of component YC or CVBS format Restrictions in the channel routing are imposed by the analog signal routing inside the IC every input pin cannot be routed to each ADC Refer to Figure 6 for an overview on the routing capabilities inside the chip The three mux sections can be controlled by the reserved control signal buses ADC0 ADC1 ADC2 sw 3 0 Table 10 explains the control words used SETADC sw man en Manual Input Muxing Enable Address 4 7 ADCO sw 3 0 ADCO Mux Configuration Address 0xC3 3 0 ADCI sw 3 0 ADC1 Mux Configuration Address 0xC3 7 4 ADC2_sw 3 0 ADC2 Mux Configuration Address 0xC4 3 0 Table 10 Manual Mux Settings for All ADCs SETADC sw man en 1 ADCO sw 3 0 ADCO Connected To ADC1 sw 3 0 ADC1 Connected To ADC2 sw 3 0 ADC2 Connected To 0000 No Connection 0000 No Connection 0000 No Connection 0001 AIN1 0001 No Connection 0001 No Connection 0010 AIN2 0010 No Connection 0010 AIN2 0011 AIN3 0011 AIN3 0011 No Connection 0100 AIN4 0100 AIN4 0100 No Connection 0101 AIN5 0101 AIN5 01
123. izontal VS Timing Address 0x31 3 The HVSTIM bit allows the user to select where the VS signal is being asserted within a line of video Some interface circuitry can require VS to go low while HS is low When HVSTIM is 0 default the start of the line is relative to HSE When HVSTIM is 1 the start of the line is relative to HSB VSBHO VS Begin Horizontal Position Odd Address 0x32 7 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSBHO is 0 default the VS pin goes high at the middle of a line of video odd field When VSBHO is 1 the VS pin changes state at the start of a line odd field VSBHE VS Begin Horizontal Position Even Address 0x32 6 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSBHE is 0 default the VS pin goes high at the middle of a line of video even field When VSBHE is 1 the VS pin changes state at the start of a line even field VSEHO VS End Horizontal Position Odd Address 0x33 7 The VSEHO and VSEHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only w
124. le 69 Gemstar 1x Data Full Byte Mode ADV7189B Byte DI9 DI8 DI7 DI6 D 5 0 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 0 Line 3 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 Gemstar Word 1 7 0 0 0 User data words 7 Gemstar Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 5 0 Checksum Table 70 NTSC CCAP Data Half Byte Mode Byte DI9 DI8 DI7 DI6 DI5 D 4 DI3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 0 1 0 1 1 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 IEP EP 0 0 CCAP Word1 7 4 0 0 User data words 7 0 0 CCAP Word1 3 0 0 0 User data words 8 IEP EP 0 0 CCAP Word2 7 4 0 0 User data words 9 IEP EP 0 0 CCAP Word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 71 NTSC CCAP Data Full Byte Mode Byte DI9 DI8 DI7 DI6
125. lected the decoder selects the optimum Y filter depending on the CVBS video source quality good vs bad Auto wide notch for poor quality sources or wide band filter with Comb for good quality input Auto narrow notch for poor quality sources or wideband filter with comb for good quality input Decoder selects optimum Y shaping filter depending on CVBS quality SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 1 SVHS 1 SVHS 1 SVHS 1 SVHS 1 SVHS 1 SVHS 1 0 1 2 3 SVHS 14 5 6 7 8 SVHS 18 CCIR601 PAL NN1 PAL NN2 PAL NN3 lo olojojoj o o o 2 2j 2 2 2 2 2 2 o0 o0 o o o o PAL WN 1 PAL WN 2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 2 2 2 2 oioioioijioiolioliolioijoioioijioi io 2 2 2 2 o oloilo 2 2 3 3 oloilo oi2 3 3 3 ololioio 2 2 i iolo olo o 2joj2 o 23 o 23 o 2j o0 2 o 23 o 2 o 2 o0 23 o0j 23 o 2 o 23 o 3 o Reserved If one of these modes is selected the decoder does not change filter modes Depending on video quality a fixed filter response the one selected is used for good and bad quality video CSFM 2 0 C Shaping Filter mode allows the selection from a range of low pass chrominance filters SH1to SH5 a
126. lects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts The decisions of the control logic are shown in Figure 11 VIDEO QUALITY BAD GOOD 1 0 AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB SELECT WIDEBAND FILTER AS PER WYSFM 4 0 Figure 11 YSFM and WYSFM Control Flowchart SET YSFM YSFM IN AUTO MODE 00000 OR 00001 SELECT AUTOMATIC WIDEBAND FILTER ADV7189B YSFM 4 0 Y Shaping Filter Mode Address 0x17 4 0 The Y shaping filter mode bits allow the user to select from a wide range of low pass and notch filters When switched in automatic mode the filter is selected based on other register selections for example detected video standard as well as properties extracted from the incoming video itself for example quality time base stability The automatic selection always picks the widest possible bandwidth for the video input encountered e Ifthe YSFM settings specify a filter that is YSFM is set to values other than 00000 or 00001 the chosen filter is applied to all video regardless of its quality e In automatic selection mode the notch filters are only used for bad quality video signals For all other video signals wide band filters are used WYSFMOVR Wideband Y Shaping Filter Override Address 0x18 7 Setting the WYSFMOVR bit enables the use of the WYSFM 4 0 settings for good quality video signals For more i
127. ls 60 62 41 43 45 57 59 61 11 INTRQ Interrupt Request Output Interrupt occurs when certain signals are detected on the input video See the interrupt register map in Table 86 13 16 25 63 NC No Connect Pins 65 69 70 77 78 35 to32 24to PO P19 Video Pixel Output Port 17 8 to 5 76 to 73 2 HS Horizontal Synchronization Output Signal 1 VS Vertical Synchronization Output Signal 80 FIELD Field Synchronization Output Signal 67 SDA 1 0 Port Serial Data Input Output Pin 68 SCLK Port Serial Clock Input Max Clock Rate of 400 kHz 66 ALSB This pin selects the I C address for the ADV7189B ALSB set to a Logic 0 sets the address for a write as 0x40 for ALSB set to a logic high the address selected is 0x42 64 RESET System Reset Input Active Low A minimum low reset pulse width of 5 ms is required to reset the ADV7189B circuitry 27 LLC1 This is a line locked output clock for the pixel data output by the ADV7189B Nominally 27 MHz but varies up or down according to video line length 26 LLC2 This is divide by 2 version of the LLC1 output clock for the pixel data output by the ADV7189B Nominally 13 5 MHz but varies up or down according to video line length 29 XTAL This is the input for the 28 6363 MHz crystal can be overdriven by an external 3 3 V 27 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal 28 XTAL1 This pi
128. lue Enable Address OxOC O section 5 STD FLD LEN Field length is correct for currently selected video standard 6 INTERLACED Interlaced video detected field sequence found 7 PAL SW LOCK Reliable sequence of swinging bursts detected Rev B Page 19 of 104 ADV7189B STANDARD DEFINITION PROCESSOR SDP STANDARD DEFINITION PROCESSOR MACROVISION VBI DATA STANDARD DETECTION RECOVERY AUTODETECTION LUMA GAIN FILTER CONTROL DIGITIZED CVBS DIGITIZED Y YC SYNC CHROMA DIGITIZED CVBS CHROMA CHROMA GAIN DIGITIZED C YC DEMOD FILTER CONTROL Fsc RECOVERY LINE LENGTH PREDICTOR SLLC CONTROL LUMA 2D COMB LUMA RESAMPLE RESAMPLE gone VIDEO DATA CONTROL INSERTION OUTPUT CHROMA CHROMA MEASUREMENT B nca VIDEO DATA PROCESSING BLOCK 04983 0 008 Figure 8 Block Diagram of the Standard Definition Processor A block diagram of the ADV7189B s standard definition processor SDP is shown in Figure 8 The ADV7189B block can handle standard definition video in and YPrPb formats It can be divided into a lumi nance and chrominance path If the input video is of a composite type CVBS both processing paths are fed with the CVBS input SD LUMA PATH The input signal is processed by the following blocks e Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Luma Filter Block This block contains luma decimation filter YAA with
129. ming allows adjustment of the ol 1 Medium TC 1 sec LAGC 1 0 is set to luma AGC tracking speed auto gain 001 010 11 0 Fast TC 0 2 sec 011 or 100 1 1 Adaptive 0x30 Luma Gain LMG 7 0 Luma manual gain can be x x x x x LMG 11 0 1234dec gain Min value Control 2 used to program a desired manual is 1 in NTSC LMG 11 0 NTSC 1024 0 85 chroma gain or read back the 1266d gain is 1 in PAL PAL 0 81 actual used gain value Max value NTSC 2468 G 2 PAL 2532 G 2 0x31 VS and Reserved Set to default ee T HVSTIM Selects where within a line 0 Start of line relative to Hsync end oniro of video the VS signal is asserted 1 Start of line relative to HSB HSB Hsync begin NEWAVMODE Sets the EAV SAV 0 EAV SAV codes generated mode to suit ADI encoders 1 Manual VS Field position controlled by registers 0x32 0x33 and OxE5 OxEA Reserved Set to default 0x32 Vsync Field Reserved Set to default NEWAVMODE bit Control 2 VSBHE 0 VS goes high in the must be set high middle of the line even field 1 VS changes state at the start of the line even field VSBHO 0 VS goes high in the middle of the line odd field 1 VS changes state at the start of the line odd field 0x33 VsyncField Reserved Set to default Control 3 VSEHE 0 VS goes low in the middle NEWAVMODE bit of the line even field must be set high 1 VS changes state at the start of the line even field
130. n Do not make the power connection between the capacitor and the power pin Placing a via underneath the 100 nF capacitor pads down to the power plane is generally the best approach see Figure 41 VIA TO SUPPLY VIA TO GND 04983 0 038 1 Figure 41 Recommend Power Supply Decoupling It is particularly important to maintain low noise and good stability of PVDD Careful attention must be paid to regulation filtering and decoupling It is highly desirable to provide sepa rate regulated supplies for each of the analog circuitry groups AVDD DVDD DVDDIO and PVDD Some graphic controllers use substantially different levels of power when active during active picture time and when idle during horizontal and vertical sync periods This can result in a measurable change in the voltage supplied to the analog supply regulator which can in turn produce changes in the regulated analog supply voltage This is mitigated by regulating the analog supply or at least PVDD from a different cleaner power source for example from a 12 V supply ADV7189B It is recommended to use a single ground plane for the entire board This ground plane should have a space between the analog and digital sections of the PCB see Figure 42 ADV7189B ANALOG H DIGITAL SECTION SECTION Figure 42 PCB Ground Layout 04983 0 039 Experience has repeatedly shown that noise performance is the same or better with a single ground plane Using mul
131. n of automatic WYSFN filter best filter 1 Manual select filter using WYSFM A 0 0x19 Comb Filter PSFSEL 1 0 Controls the signal 0 0 Narrow Control bandwidth that is fed to the comb 0 11 Medium filters PAL 1 0 Wide 1 1 Widest NSFSEL 1 0 Controls the signal 0 0 Narrow bandwidth that is fed to the comb 0 1 Medium filters NTSC i lo Medi m 1 1 Wide Reserved 1 1 d Set as default Ox1D ADI Control Reserved 0 0 x x x Set to default 2 VS_JIT_COMP_EN 0 Enabled 1 Disabled EN28XTAL 0 Use 27 MHz crystal 1 Use 28 MHz crystal TRI_LLC 0 LLC pin active 1 LLC pin three stated Rev B Page 77 of 104 ADV7189B Bits Subaddress Register Bit Description 716 5 43 1 0 Comments Notes 0x27 Pixel Delay LTA 1 0 Luma timing adjust allows 0 0 No delay CVBS mode Control the user to specify a timing LTA 1 0 00b difference between chroma and 1 O Luma 1 clk 37ns delayed S Video mode luma samples 1 0 Luma 2 clk 74ns early LTA 1 0 01b PrPb mode LTA 1 0 01b 1 1 Luma 1 clk 37ns early Reserved Set to 0 CTA 2 0 Chroma timing adjust Not valid setting CVBS mode allows a specified timing difference olola Chroma 2 pixels early 2 0 011b between the luma and chroma ol1lo Chroma 1 pixel early samples Jel E y S Video mo
132. n section If the amplitude of the analog video signal is too high clipping can occur resulting in visual artifacts The analog input range of the ADC together with the clamp level determines the maximum supported amplitude of the video signal The minimum supported amplitude of the input video is determined by the ADV7189B s ability to retrieve horizontal and vertical timing and to lock to the colorburst if present There are separate gain control units for luma and chroma data Both can operate independently of each other The chroma unit however can also take its gain value from the luma path The possible AGC modes are summarized in Table 33 It is possible to freeze the automatic gain control loops This causes the loops to stop updating and the AGC determined gain at the time of the freeze to stay active until the loop is either unfrozen or the gain mode of operation is changed The currently active gain from any of the modes can be read back Refer to the description of the dual function manual gain registers LG 11 0 Luma Gain and CG 11 0 Chroma Gain in the Luma Gain and the Chroma Gain sections ANALOG VOLTAGE RANGE SUPPORTED BY ADC 1 6V RANGE FOR ADV7189B MAXIMUM VOLTAGE MINIMUM VOLTAGE SDP DATA GAIN SELECTION ONLY c Q9 RE PROCESSOR DPP GAIN CONTROL 04983 0 017 Figure 17 Gain Control Overview Rev B Page 30 of 104 Table 33 AGC Modes ADV7189B
133. n should be connected to the 28 6363 MHz crystal or left as connect if an external 3 3 V 27 MHz clock oscillator source is used to clock the ADV7189B In crystal mode the crystal must be a fundamental crystal 36 PWRDN A logic low on this pin places the ADV7189B in a power down mode Refer to Power Management Register in the I2C Register Maps section for more options on power down modes for the ADV7189B 79 OE When set to a logic low OE enables the pixel output bus P19 toPO of the ADV7189B A logic high on the OE pin places Pins P19 to PO HS VS SFL into a high impedance state 37 ELPF The recommended external loop filter must be connected to this ELPF pin as shown in Figure 46 12 SFL Subcarrier Frequency Lock This pin contains a serial output stream that be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices Inc digital video encoder 51 REFOUT Internal Voltage Reference Output Refer to Figure 46 for a recommended capacitor network for this pin 52 CML The CML pin is a common mode level for the internal ADCs Refer to Figure 46 for a recommended capacitor network for this pin 48 49 CAPY1 CAPY2 ADC s Capacitor Network Refer to Figure 46 for a recommended capacitor network for this pin 54 55 CAPC1 CAPC2 ADC s Capacitor Network Refer to Figure 46 for a recommended capacitor network for this pin Rev B Page 12 of 104 ANALOG FRONT END ANALOG I
134. n the logic level on the ALSB pin These four unique addresses are shown in Table 81 The ADV7189B s ALSB pin controls Bit 1 of the slave address By altering the ALSB it is possible to control two ADV7189Bs in an application without having a conflict with the same slave address The LSB Bit 0 sets either a read or write operation Logic 1 corresponds to a read operation Logic 0 corresponds to a write operation Table 81 C Address for ADV7189B ALSB R W Slave Address 0 0 0x40 0 1 0 41 1 0 0 42 1 1 0x43 To control the device on the bus a specific protocol must be followed First the master initiates a data transfer by establish ing a start condition which is defined by a high to low transition on SDA while SCLK remains high This indicates that an address data stream follows All peripherals respond to the start condition and shift the next eight bits 7 bit address R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse this is known as an acknowledge bit All other devices withdraw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the SDA and SCLK lines waiting for the start condition and the correct transmitted address SDATA SCLOCK 1 7 8V f 9 1 7 _ 8 START ADDR R W ACK SUBADDRESS ACK ipia lue 8 ADV7189B The R W
135. n transmission is inserted into the horizontal blanking period of the respective line of video A potential problem can arise if the retrieved data bytes have the value 0x00 or OxFF In an ITU R BT 656 compatible data stream these values are reserved and used only to form a fixed preamble The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways e Insert all data straight into the data stream even the reserved values of 0x00 and OxFE if they occur This can violate the output data format specification ITU R BT 1364 e Split all data into nibbles and insert the half bytes over double the number of cycles in a 4 bit format When GDECAD is 0 default the data is split into half bytes and inserted When GDECAD is 1 the data is output straight in 8 bit format ADV7189B Table 74 NTSC Line Enable Bits and Corresponding Line Numbering Line Number Line 3 0 ITU R BT 470 Enable Bit Comment 0 10 GDECOL O Gemstar 1 11 GDECOL 1 Gemstar 2 12 GDECOL 2 Gemstar 3 13 GDECOL 3 Gemstar 4 14 GDECOL 4 Gemstar 5 15 GDECOL 5 Gemstar 6 16 GDECOL 6 Gemstar 7 17 GDECOL 7 Gemstar 8 18 GDECOL 8 Gemstar 9 19 GDECOL 9 Gemstar 10 20 GDECOL 10 Gemstar 11 21 GDECOL 11 Gemstar or closed caption 12 22 GDECOL 12 Gemstar 13 23 GDECOL 13 Gemstar 14 24 GDECOL 14 Gemstar 15 25 GDECOL 15 Gemstar 0 273 10 GDECEL 0 Gemstar 1 274 11 GDECEL 1 Gemstar 2 275 12 GDECEL 2 Gemstar
136. nd wideband mode Auto selection 15 MHz Auto selection 2 17 MHz Automatically selects a C filter for the specified bandwidth SH1 SH2 SH3 SH4 SH5 2 2 oilo23i2 oj oj o Wideband mode Rev B Page 76 of 104 ADV7189B Bits Subaddress Register Bit Description 7 6 5 4 3 2 1 0 Comments Notes 0x18 Shaping WYSFM 4 0 Wideband Y Shaping 0 O O 0 0 Reserved Do not use Filter Filter mode allows the user to olo 1 Reserved Do not use ee m ofo sms B W input signals it is also used 1 0 14 1 SVHS2 when a good quality input CVBS 1 0 SVHS3 signal is detected For all other 1 1 1 svusa inputs the Y shaping filter chosen is controlled by YSFM 4 0 0 0 1 1 0 SVHS5 0 0 1 1 1 SVHS6 0 1 0 SVHS7 0 1 010 1 SVHS8 0 1 0110 SVHS9 011 0 1 1 SVHS10 011 1100 SVHS11 011 110 1 SVHS 12 011 1 1 0 SVHS 13 0 1 1 1 1 SVHS 14 1 0 0 0 0 SVHS15 1 0 0 07 1 SVHS 16 1 0 0 1 0 SVHS 17 1 0 0 1 SVHS 18 CCIR 601 1 0 1 0 Reserved Do not use Reserved Do not use 1 1 1 1 1 Reserved Do not use Reserved 0 0 Set to default WYSFMOVR Enables the use of 0 Auto selectio
137. nformation refer to the general discussion of the luma shaping filters in the Y Shaping Filter section and the flowchart shown in Figure 11 When WYSFMOVR is 0 the shaping filter for good quality video signals is selected automatically Setting WYSFMOVR to 1 default enables manual override via 4 0 NO USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO 04983 0 011 Rev B Page 27 of 104 ADV7189B Table 30 YSFM Function WYSFM 4 0 Wide Band Y Shaping Filter Mode YSFM 4 0 Description Address 0x18 4 0 0 0000 Automatic selection including a wide notch response PAL NTSC SECAM The WYSFM 4 0 bits allow the user to manually select a shaping 0 0001 Automatic selection including a narrow notch filter for good quality video signals for example CVBS with default response PAL NTSC SECAM stable time base luma component of YPrPb luma component 0 0010 SVHS 1 of YC The WYSFM bits are only active if the WYSFMOVR bit 0 0011 SVHS 2 is set to 1 See the general discussion of the shaping filter settings 0 0100 SVHS 3 in the Y Shaping Filter section 0 0101 SVHS 4 Table 31 WYSEM Function 0 0110 SVHS 5 WYSFM A 0 Description 0 0111 SVHS 6 0 0000 Do not use 0 1000 SVHS 7 0 0001 Do not use 0 1001 SVHS 8 0 0010 SVHS 1 0 1010 SVHS 9 0 0011 SVHS 2 0 1011 SVHS 10 0 0100 SVHS 3 0 1100 SVHS 11 0 0101 SVHS 4 0 1101 SVHS 12 0 0110 SVHS 5 0 1110 SVHS 13 0 0111 SVHS 6 0 1
138. nt lpvop 10 5 mA Analog Supply Current CVBS input 85 mA YPrPb input 180 mA Power Down Current IPwRDN 1 5 mA Power Up Time tewrup 20 ms 1 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7189BKSTZ 2 The min max specifications are guaranteed over this range 3 Pin 36 and Pin 79 Pin 1 Pin 2 Pin 5 to Pin 8 Pin 12 Pin 17 to Pin 24 Pin 32 to Pin 35 Pin 73 to Pin 76 and Pin 80 5 Guaranteed by characterization ADC1 powered on 7 All three ADCs powered on Rev B Page 6 of 104 ADV7189B VIDEO SPECIFICATIONS Guaranteed by characterization At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvpnio 3 0 V to 3 6 V Pvpp 1 65 V to 2 0 V operating temperature range unless otherwise specified Table 2 Parameter 2 Symbol Test Conditions Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS I P modulate 5 step 0 4 0 6 Degrees Differential Gain DG CVBS I P modulate 5 step 0 4 0 6 Luma Nonlinearity LNL CVBS P 5 step 0 4 0 7 96 NOISE SPECIFICATIONS SNR Unweighted Luma ramp 61 63 dB Luma flat field 63 65 dB Analog Front End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range 5 5 Vertical Lock Range 40 70 Hz Fsc Subcarrier Lock Range 1 3 2 Color Lock In Time 60 Lines Sync Depth Range 20 200 Color Burst Range 5 200 Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines CHROMA SPECIFICATIONS Hue Ac
139. o ioilojo Fixed luma comb 3 line Bottom lines of memory 2 0 chroma comb mode PAL 3 line adaptive for CTAPSN 01 4 line adaptive for CTAPSN 10 5 line adaptive for CTAPSN 11 Disable chroma comb Fixed 2 line for CTAPSN 01 Top lines of memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Fixed 3 line for CTAPSN 01 All lines of memory Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 Fixed 2 line for CTAPSN 01 Bottom lines of memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 2 11 CTAPSP 1 0 chroma comb taps PAL Not used Adapts 5 lines 3 lines 2 taps Adapts 5 lines 3 lines 3 taps Adapts 5 lines 4 lines 4 taps Ox3A Reserved Set as default PWRDN ADC 2 Enables power down of ADC2 ADC2 normal operation Power down ADC2 PWRDN_ADC_1 Enables power down of ADC1 ADC1 normal operation Power down ADC1 PWRDN_ADC_O Enables power down of ADCO ADCO normal operation Power down ADCO Reserved Set as default 0x3D Manual Window Control Reserved Set to default CKILLTHR 2 0 Kill at 0 5 Kill at 1 5 Kill at 2 5 Kill at 4 Kill at 8 5 Kill at 16 Kill at 32 2 2 oj o 2 2 o o 2 o 2 o o 2 o Reserved
140. oblems as follows First the PAL switch bit is only meaningful in PAL Some encoders including Analog Devices encoders also look at the state of this bit in NTSC Second there was a design change in Analog Devices encoders from ADV717x to ADV719x The older versions used the SFL GenLock Telegram bit directly while the later ones invert the bit prior to using it The reason for this is the inversion compensated for the 1 line delay of an SFL GenLock Telegram transmission As a result ADV717x encoders need the PAL switch bit in the SFL GenLock Telegram to be 1 for NTSC to work Also ADV7190 ADV7191 ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC If the state of the PAL switch bit is wrong a 180 phase shift occurs In a decoder encoder back to back system in which SFL is used this bit must be set up properly for the specific encoder used SFL_INV Address 0x41 6 Setting SFL_INV 6 to 0 makes the part SFL compatible with ADV7190 ADV7191 ADV7194 encoders Setting SFL_INV to 1 default makes the part SFL compatible with ADV717x ADV7173x encoders Lock Related Controls Lock information is presented to the user through Bits 1 0 of the Status 1 register See the STATUS 1 7 0 Address 0x10 7 0 section Figure 9 outlines the signal flow and the controls avail able to influence the way the lock status information is generated FILTER THE RAW LOCK SIGNAL CIL 2 0 COL 2 0 STATUS 1 0
141. occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to abso lute maximum rating conditions for extended periods may affect device reliability LP ESD SENSITIVE DEVICE Rev B Page 10 of 104 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 2 l zo 80 26 a a NC NO CONNECT e a o a a o XTAL1 X a a 2 a ADV7189B TOP VIEW Not to Scale 29 lt E x 30 a a gt Figure 5 80 Lead LQFP Pin Configuration Rev B Page 11 of 104 PVDD 8 AGND amp AGND 04983 0 002 ADV7189B ADV7189B Table 7 Pin Function Descriptions Pin No Mnemonic Type Function 3 9 14 31 71 DGND G Digital Ground 39 40 47 53 AGND G Analog Ground 56 4 15 DVDDIO Digital I O Supply Voltage 3 3 V 10 30 72 DVDD Digital Core Supply Voltage 1 8 V 50 AVDD P Analog Supply Voltage 3 3 V 38 PVDD PLL Supply Voltage 1 8 V 42 44 46 58 AINTtoAIN12 Analog Video Input Channe
142. omments Notes 0x38 NTSC Comb Control YCMN 2 0 luma comb mode NTSC Adaptive 3 line 3 tap luma Use low pass notch Fixed luma comb 2 line Top lines of memory Fixed luma comb 3 Line All lines of memory 1 Fixed luma comb 2 line Bottom lines of memory CCMN 2 0 chroma comb mode NTSC 3 line adaptive for CTAPSN 01 4 line adaptive for CTAPSN 10 5 line adaptive for CTAPSN 11 Disable chroma comb Fixed 2 line for CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Top lines of memory Fixed 3 line for CTAPSN 01 Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 All lines of memory Fixed 2 line for CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Bottom lines of memory CTAPSN 1 0 chroma comb taps NTSC Adapts 3 lines 2 lines Not used Adapts 5 lines 3 lines olo o o Adapts 5 lines 4 lines Rev B Page 81 of 104 ADV7189B Subaddress Register Bit Description Bits Comments Notes 0x39 PAL Comb Control YCMP 2 0 luma comb mode PAL Adaptive 5 line 3 tap luma comb Use low pass notch Fixed luma comb Top lines of memory Fixed luma comb 5 line All lines of memory 2 2 2
143. on Address 0x48 7 0 Address 0x49 7 0 section and the GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address Ox4B 7 0 section Table 72 PAL CCAP Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 DI3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 0 1 0 1 0 0 0 SDID 5 IEP EP 0 0 0 0 0 1 0 0 Data count 6 IEP EP 0 0 CCAP Word1 7 4 0 0 User data words 7 IEP EP 0 0 CCAP Word1 3 0 0 0 User data words 8 IEP EP 0 0 CCAP Word2 7 4 0 0 User data words 9 IEP EP 0 0 CCAP Word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 73 PAL CCAP Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 D 3 D 2 D 1 DIO Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 IEP EP EF 0 1 0 1 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 CCAP Word1 7 0 0 0 User data words 7 CCAP Word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Rev B Page 56 of 104
144. on Address 0x00 3 0 The INSEL bits allow the user to select an input channel as well as the input format Depending on the PCB connections only a subset of the INSEL modes are valid The INSEL 3 0 does not only switch the analog input muxing it also configures the standard definition processor core to process CVBS Comp S Video Y C or component YPbPr format Rev B Page 13 of 104 ADV7189B YES SET INSEL 3 0 FOR REQUIRED MUXING CONFIGURATION ADI RECOMMENDED INPUT MUXING SEE TABLE 9 ANALOG SIGNALS NO SET INSEL 3 0 CONFIGURE ADV7189B TO DECODE VIDEO FORMAT CVBS 0000 YC 0110 YPrPb 1001 USE MANUAL INPUT MUXING ADC SW MAN EN ADCO SW ADC1 SW ADC2 SW 04983 0 007 Figure 7 Input Muxing Overview Table 8 Input Channel Switching Using INSEL 3 0 Table 9 Input Channel Assignments Description INSEL 3 0 Analog Input Pins Video Format 0000 CVBS1 AINT default Composite 0001 CVBS2 AIN2 Composite 0010 CVBS3 AIN3 Composite 0011 CVBS4 AIN4 Composite 0100 CVBS5 AIN5 Composite 0101 CVBS6 AIN6 Composite 0110 Y1 AIN1 YC C1 AIN4 YC 0111 Y2 AIN2 YC C2 AIN5 YC 1000 Y3 AIN3 YC AIN6 YC 1001 Y1 AIN1 YPrPb PB1 AIN4 YPrPb PR1 AIN5 YPrPb 1010 Y2 AIN2 YPrPb PB2 AIN3 YPrPb PR2 AIN6 YPrPb 1011 CVBS7 AIN7 Composite 1100 CVBS8 AIN8 Composite 1101 CVBS9 AIN9 Composite 1110 CVBS10 AIN10 Composite 1111 CVBS11 AIN11 Comp
145. osite Input Pin ADI Recommended Input Muxing Control Channel No INSEL 3 0 AIN7 41 CVBS7 AIN1 42 CVBS1 YC1 Y YPrPb1 Y AIN8 43 CVBS8 AIN2 44 CVBS2 YC2 Y YPrPb2 Y AIN9 45 CVBS9 AIN3 46 CVBS3 YC3 Y YPrPb2 Pb AIN10 57 CVBS10 AINA 58 CVBS4 1 YPrPb1 Pb AIN11 59 CVBS11 AIN5 60 CVBS5 YC2 C YPrPb1 Pr AIN12 61 Not Available AIN6 62 CVBS6 YC3 C YPrPb2 Pr ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity Table 9 summarizes how the PCB lay out should connect analog video signals to the ADV7189B It is strongly recommended to connect any unused analog input pins to AGND to act as a shield Inputs AIN7 to AIN11 should be connected to AGND when only six input channels are used This improves the quality of the sampling due to better isolation between channels AIN12 is not under the control of INSEL 3 0 It can only be routed to ADC0 ADC1 ADC2 by manual muxing See Table 10 for further details Rev B Page 14 of 104 Manual Input Muxing By accessing a set of manual override muxing registers the analog input muxes of the ADV7189B can be controlled directly This is referred to as manual input muxing Manual input muxing overrides other input muxing control bits for example INSEL The manual muxing is activated by setting the ADC SW MAN EN bit It only affects the analog switches in front of the ADCs Th
146. p at any time It is intended for users who would like to do their own clamping Users should disable the current sources for analog clamping via the appropriate register bits wait until the digital clamp loop settles and then freeze it via the DCFE bit When DCFE is 0 default the digital clamp is operational When DCTE is 1 the digital clamp loop is frozen LUMA FILTER Data from the digital fine clamp block is processed by three sets of filters Note The data format at this point is CVBS for CVBS input or luma only for Y C and YPrPb input formats e Luma antialias filter YAA The ADV7189B receives video at a rate of 27 MHz In the case of 4x oversampled video the ADCs sample at 54 MHz and the first decimation is performed inside the DPP filters Therefore the data rate into the ADV7189B is always 27 MHz The ITU R BT 601 recommends a sampling frequency of 13 5 MHz The luma antialias filter decimates the oversampled video using a high quality linear phase low pass filter that pre serves the luma signal while at the same time attenuating out of band components The luma antialias filter YAA has a fixed response e Luma shaping filters YSH The shaping filter block is a programmable low pass filter with a wide variety of responses It can be used to selectively reduce the luma video signal bandwidth needed prior to scaling for example For some video sources that contain high frequency noise reducing the bandwid
147. p IFFILTSEL 2 0 IF filter selection 0 0 Bypass mode OdB Control for PAL and NTSC 2MHz 5 MHz NTSC filters 0 1 3dB 2 dB 0 0 6dB 43 5 dB 0 1 10dB 5 dB 1 0 Reserved 3 MHz 6 MHz PAL filters 1 1 2dB 2 dB 1 0 5 dB 3 dB 1 1 7dB 5 dB Reserved Rev Page 88 of 104 ADV7189B Subaddress Register Bit Description Bits Comments Notes OxF9 VS Mode Control EXTEND_VS_MAX_FREQ Limit maximum Vsync frequency to 66 25 Hz 475 lines frame Limit maximum Vsync frequency to 70 09 Hz 449 lines frame EXTEND_VS_MIN_FREQ Limit minimum Vsync frequency to 42 75 Hz 731 lines frame Limit minimum Vsync frequency to 39 51 Hz 791 lines frame VS_COAST_MODE 1 0 Auto Coast mode 50 Hz Coast mode 60 Hz Coast mode o E O 8 Reserved This value sets up the output coast frequency Reserved Rev B Page 89 of 104 ADV7189B 2 PROGRAMMING EXAMPLES EXAMPLES USING 28 MHz CLOCK Mode 1 CVBS Input Composite Video on AIN5 All standards are supported through autodetect 10 bit 4 2 2 ITU R BT 656 output on P19 to P10 Table 87 Mode 1 CVBS Input Register Address Register Value Notes 0x00 0x04 CVBS input on AIN5 0x03 0x00 Enable 10 bit output on P19 to P10 0x15 0x00 Slow down digital clamps 0x17 0x41 Set CSFM to SH1
148. r 4 layer PCB with solid ground plane 38 1 C W 1 Temperature range Tmn to Tmax 40 C to 85 C 0 C to 70 C for ADV7189BKSTZ 2 The min max specifications are guaranteed over this range TIMING DIAGRAMS t SDA SCLK g t4 ts gt lt i OUTPUT LLC 1 OUTPUT LLC 2 OUTPUTS P0 P19 VS HS FIELD SFL 04997 0 004 Figure 3 Pixel Port and Control Output Timing P0 P19 HS VS FIELD SFL 04983 0 005 Figure 4 OE Timing Rev B Page 9 of 104 ADV7189B ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating Avop to GND AV to AGND 4V Dvpp to 2 2V Pvop to AGND 22V to AV Dvopio to AVDD 0 3V to 0 3 V to Dvop 0 3 to 40 3 V Dvppio 0 3Vto 2V Dvovio Dvop 0 3 V to 2 V Avoo Pvop 0 3 V to 2 V Avov Dvop 0 3 V to 2 V Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature T Max Storage Temperature Range Infrared Reflow Soldering 20 sec 0 3 V to Dvpoo 0 3 V 0 3 V to Dvpoo 0 3 V AGND 0 3 V to Avoo 0 3 V 150 C 65 C to 150 C 260 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may
149. ration If set manual registers LTA 1 0 and CTA 2 0 are not used by the ADV7189B If the automatic mode is disabled via setting the AUTO_PDC_EN bit to 0 the values programmed into the LTA 1 0 and CTA 2 0 registers become active When AUTO_PDC_EN is 0 the ADV7189B uses the LTA 1 0 and CTA 2 0 values for delaying luma and chroma samples Refer to the LTA 1 0 Luma Timing Adjust Address 0x27 1 0 and the CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 sections When AUTO EN is 1 default the ADV7189B auto matically determines the LTA and CTA values to have luma and chroma aligned at the output CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 The Chroma timing adjust register allows the user to specify a timing difference between chroma and luma samples This can be used to compensate for external filter group delay differences in the luma vs chroma path and to allow a different number of pipeline delays while processing the video downstream Review this functionality together with the LTA 1 0 register The chroma can be delayed advanced only in chroma pixel steps One chroma pixel step is equal to two luma pixels The programmable delay occurs after demodulation where one can no longer delay by luma pixel steps For manual programming use the following defaults e input CTA 2 0 011 e YC input CTA 2 0 101 e YPrPb input CTA 2 0 110 Table 54 CTA Function CTA 2 0 Description 000
150. red This process is referred to as clamping the video This section explains the general process of clamping on the ADV7189B and shows the different ways in which a user can configure its behavior The ADV7189B uses a combination of current sources and a digital processing block for clamping as shown in Figure 10 The analog processing channel shown is replicated three times inside the IC While only one single channel and only one ADC is needed for a CVBS signal two independent channels are needed for YC S VHS type signals and three independent channels are needed to allow component signals YPrPb to be processed FINE COARSE CURRENT CURRENT SOURCES SOURCES ANALOG T 8 CLAMP CONTROL ADV7189B The clamping can be divided into two sections e Clamping before the ADC analog domain current sources e Clamping after the ADC digital domain digital processing block The ADCs can digitize an input signal only if it resides within the ADC s 1 6 V input voltage range An input signal with a dc level that is too large or too small is clipped at the top or bottom ofthe ADC range The primary task of the analog clamping circuits is to ensure the video signal stays within the valid ADC input window so the analog to digital conversion can take place It is not neces sary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits th
151. s 0 1 0 AGC Peak white algorithm Blank level to sync tip on 0 1 1 Reserved Reserved 1 0 1 Reserved 1 140 Reserved 1 1 1 Freeze gain Reserved 1 Set to 1 Rev B Page 78 of 104 ADV7189B Bits Subaddress Register Bit Description 716 5 43 Comments Notes Ox2D Chroma CMG 11 8 Chroma manual gain 0 CAGC 1 0 settings Gain can be used to program a desired decide in which Control 1 manual chroma gain Reading back mode CMG 11 0 from this register in AGC mode operates gives the current gain Reserved v 1 Setto 1 CAGT 1 0 Chroma automatic gain Slow TC 2 sec Has an effect only if timing allows adjustment of the ol 1 Medium TC 1 sec CAGC 1 0 is set to chroma AGC tracking speed ilo Fast TC 0 2 sec auto gain 10 1 1 Adaptive Ox2E Chroma CMG 7 0 Chroma manual gain 0 0 0 0 CMG 11 0 750d gain is Min value is 0 dec Gain lower 8 bits See CMG 11 8 for 1in NTSC 60 dB Control 2 description CMG 11 0 741d gain is Max value is 3750 1in PAL Gain 5 Ox2F Luma Gain LMG 11 8 Luma manual gain can x LAGC 1 0 settings decide Control 1 be used program a desired manual in which mode LMG 1 1 0 chroma gain or to read back the operates actual gain value used Reserved Set 1 LAGT 1 0 Luma automatic gain 0 0 Slow TC 2 sec Only has an effect if ti
152. s the manner in Split data into half byte To avoid 00 FF code Control 5 which decoded Gemstar data is inserted into the horizontal blanking period Output in straight 8 bit format Reserved zd pss xe Undefined 0 4 CTI CTI EN CTI enable Disable CTI Control 1 Enable CTI CTI AB EN Enables the mixing of Disable CTI alpha blender the transient improved chroma Enable CTI alpha blender with the original signal CTI AB 1 0 Controls the behavior Sharpest mixing of the alpha blend circuitry Sharp mixing 1 0 Smooth 1 1 Smoothest Reserved 0 Set to default DNR_EN Enable or bypass the DNR 0 Bypass the DNR block block 1 Enable the DNR block Reserved 1 Set to default Ox4E CTI DNR CTI_CTH 7 0 Specifies how bigthe 0 0 0 0 1 0 Set to 0x04 for A V input Control 2 amplitude step must be to be set to OxOA for tuner input steepened by the CTI block 0x50 CTI DNR DNR TH 7 0 Specifies the Control 4 maximum edge that is interpreted as noise and is therefore blanked Rev B Page 83 of 104 ADV7189B Bits Subaddress Register Bit Description 76 51413 2 1 0 Comments Notes 0x51 Lock Count CIL 2 0 Count into lock O O O 1 line of video determines the number of lines the ol o
153. se lines are detected Register LB LCT 7 0 reports back the number of black lines that were actually found By default the ADV7189B starts looking for those black lines in sync with the beginning of active video for example straight after the last VBI video line SL 3 0 allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis The detection window closes in the middle of the field Detection at the End of a Field The ADV7189B expects at least six continuous lines of black video at the bottom of a field before reporting back the number of lines actually found via the LB LCB 7 0 value The activity window for letterbox detection end of field starts in the middle of an active field Its end is programmable via LB EL 3 0 Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box If the ADV7189B finds at least two black lines followed by more nonblack video for example the subtitle and is then followed by the remainder of the bottom black block it reports back a midcount via LB LCM 7 0 If no subtitles are found LB LCM 7 0 reports the same number as LB LCB 7 0 There is a 2 field delay in the reporting of any line count parameters There is no letterbox detected bit The user is asked to read the LB LCT 7 0 and LB LCB 7 0 register values and to conclude whether or not the letterbox type video is present in soft
154. sion Interrupt Select 0 1 Pseudo sync only 1 0 Color stripe only 1 1 Pseudo sync or color stripe INTRQ_DUR_SEL 1 0 3 Xtal periods Interrupt Duration Select 0 1 15 Xtal periods 11 0 63 Xtal periods 1 1 Active until cleared 0x41 Reserved x x x x x x 0x42 Interrupt SD_LOCK_Q 0 No change These bits Status 1 1 SD input has caused the can be decoder to go from an unlocked Cleared or Read Only state to a locked state in egister SD_UNLOCK_Q 0 0x43 Register 1 SD input has caused the Register Access decoder to go from a locked 0x44 Page 2 state to an unlocked state respectively Reserved Reserved x Reserved X SD_FR_CHNG_Q 0 1 Denotes a change in the free run status MV_PS_CS_Q 0 1 Pseudo sync color striping detected See Reg 0x40 MV_INTRQ_SEL 1 0 for selection Reserved 0x43 Interrupt SD_LOCK_CLR 0 Do not clear Clear 1 1 Clears SD_LOCK_Q bit SD_UNLOCK_CLR 0 Do not clear Write Only 1 Clears SD_UNLOCK_Q bit Reserved Not used Register Reserved 0 Not used Access Page 2 Reserved 0 Not used SD_FR_CHNG_CLR 0 Do not clear 1 Clears SD_FR_CHNG_Q bit MV_PS_CS_CLR 0 Do not clear 1 Clears MV_PS_CS_Q bit Reserved X Not used Rev B Page 68 of 104 ADV7189B Bit Subaddress Register Bit Description 7
155. sync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified 04983 0 028 Figure 28 PAL Vsync Begin Rev B Page 46 of 104 ADV7189B ADVANCE END OF DELAY END OF VSYNC VSYNC BY PVENDJ A 0 BY PVEND 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 1 ADDITIONAL DELAY BY 1 LINE 0 0 1 ADVANCE BY 0 5 LINE ADVANCE BY 0 5 LINE 04983 0 029 VSYNC END Figure 29 PAL Vsync End PVENDDELO PAL Vsync End Delay on Odd Field Address OxE9 7 When PVENDDELO is 0 default there is no delay Setting PVENDDELO to 1 delays Vsync going low on an odd field by a line relative to PVEND PVENDDELE PAL Vsync End Delay on Even Field Address OxE9 6 When PVENDDELE is 0 default there is no delay Setting PVENDDELE to 1 delays Vsync going low on an even field by a line relative to PVEND PVENDSIGN PAL Vsync End Sign Address 0xE9 5 Setting PVENDSIGN to 0 default delays the end of Vsync Set for user manual programming Setting PVENDSIGN to 1 advances the end of Vsync Not recommended for user programming PVEND 4 0 PAL Vsync End Address OxE9 4 0 The default value of PVEND is 10100 indicating the PAL Vsync end position For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified PFTOGDELO PAL Field Toggle Delay on Odd Field Address OxEA 7 When PFTOGDELO is 0 def
156. th of the luma signal improves visual picture quality A follow on video compression stage can work more efficiently if the video is low pass filtered The ADV7189B has two responses for the shaping filter one that is used for good quality CVBS component and S VHS type sources and a second for nonstandard CVBS signals The YSH filter responses also include a set of notches for PAL and NTSC However it is recommended to use the comb filters for YC separation e Digital resampling filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system with no requirement for user intervention Figure 12 through Figure 15 show the overall response of all filters together Unless otherwise noted the filters are set into a typical wideband mode Y Shaping Filter For input signals in CVBS format the luma shaping filters play an essential role in removing the chroma component from a composite signal YC separation must aim for the best possible crosstalk reduction while still retaining as much bandwidth especially on the luma component as possible High quality YC separation can be achieved by using the internal comb filters ofthe ADV7189B Comb filtering however relies on the frequency relationship of the luma component multiples of the video line rate and the color
157. the input video data It detects transitions of chroma and can be pro grammed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth The CTI block however operates only on edges above a certain threshold to ensure that noise is not emphasized Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided Chroma transient improvements are needed primarily for sig nals that experienced severe chroma bandwidth limitation For those types of signals it is strongly recommended to enable the CTI block via CTI EN CTI EN Chroma Transient Improvement Enable Address 0 4 0 The CTI EN bit enables the CTI function If set to 0 the CTI block is inactive and the chroma transients are left untouched Setting CTI EN to 0 disables the CTI block Setting EN to 1 default enables the CTI block CTI AB EN Chroma Transient Improvement Alpha Blend Enable Address 0 4 1 The CTI AB EN bit enables an alpha blend function within the CTI block If set to 1 the alpha blender mixes the transient improved chroma with the original signal The sharpness of the alpha blending can be configured via the CTI AB 1 0 bits For the alpha blender to be active the CTI block must be enabled via the CTI EN bit Setting AB EN to 0 disables the CTI alpha blender Setting CTI AB EN to 1 default enables the CTI alpha blend mixing function CTI AB 1 0
158. the system picks the closest of the remaining enabled standards The results of the autodetection can be read back via the status registers See the Global Status Registers section for more information VID SEL 3 0 Address 0x00 7 4 Table 18 VID SEL Function VID SEL 3 0 Description 0000 default Autodetect PAL BGHID NTSC J no pedestal SECAM 0001 Autodetect PAL BGHID lt gt NTSC M pedestal SECAM 0010 Autodetect PAL N pedestal NTSC J no pedestal SECAM 0011 Autodetect PAL pedestal lt gt NTSC M pedestal SECAM 0100 NTSC J 1 0101 NTSC M 1 0110 PAL 60 0111 NTSC 4 43 1 1000 PAL BGHID 1001 PAL N PAL BGHID with pedestal 1010 PAL M without pedestal 1011 PAL M 1100 PAL Combination N 1101 PAL Combination N with pedestal 1110 SECAM 1111 SECAM with pedestal AD SEC525 EN Enable Autodetection of SECAM 525 Line Video Address 0x07 7 Setting AD SEC525 EN to 0 default disables the autodetection of a 525 line system with a SECAM style FM modulated color component Setting AD SEC525 EN to 1 enables the detection AD SECAM EN Enable Autodetection of SECAM Address 0x07 6 Setting AD SECAM EN to 0 disables the autodetection of SECAM Setting AD SECAM EN to 1 default enables the detection Rev B Page 21 of 104 ADV7189B AD_N443_EN Enable Autodetection of NTSC 443 Address 0x07 5 Setting AD_N443_EN to 0 disables th
159. ting NVENDDELE to 1 delays Vsync from going low on an even field by a line relative to NVEND NVENDSIGN NTSC Vsync End Sign Address 0xE6 5 For all NTSC PAL Vsync timing controls both the V bit in the AV code and the Vsync on the VS pin are modified NFTOGDELO NTSC Field Toggle Delay on Odd Field Address OxE7 7 When NFTOGDELO is 0 default there is no delay Setting NFTOGDELO to 1 delays the field toggle transition on an odd field by a line relative to NFTOG NFTOGDELE NTSC Field Toggle Delay on Even Field Address OxE7 6 When NFTOGDELE is 0 default there is no delay Setting NFTOGDELE to 1 delays the field toggle transition on an even field by a line relative to NFTOG ADVANCE TOGGLE OF FIELD BY NFTOG 4 0 NOT VALID FOR USER PROGRAMMING DELAY TOGGLE OF FIELD BY NFTOG 4 0 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE 04983 0 025 TOGGLE Figure 25 NTSC FIELD Toggle NFTOGSIGN NTSC Field Toggle Sign Address OxE7 5 Setting NFTOGSIGN to 0 delays the field transition Set for user manual programming Setting NFTOGSIGN to 1 default advances the field transition Not recommended for user programming Setting NVENDSIGN to 0 default delays the end of Vsync Set for user manual programming Setting NVENDSIGN to 1 advances the end of Vsync Not recommended for user programming NVEND NTSC 4 0 Vsync End Address 0 6 4 0 The default value of NVEND is 00100 indic
160. tion 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 COL 2 0 Count Out of Lock Address 0x51 5 3 COL 2 0 determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state and reports this via Status 0 1 0 It counts the value in lines of video Table 21 COL Function VS COAST 1 0 Description 00 default Auto coast mode follows VS frequency from last video input 01 Forces 50 Hz coast mode 10 Forces 60 Hz coast mode 11 Reserved CIL 2 0 Count Into Lock Address 0x51 2 0 CIL 2 0 determines the number of consecutive lines for which the into lock condition must be true before the system switches into the locked state and reports this via Status 0 1 0 It counts the value in lines of video COL 2 0 Description 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 SD COLOR CONTROLS These registers allow the user to control picture appearance including control of the active data in the event of video being lost These controls are independent of any other controls For instance brightness control is independent from picture clamp ing although both controls affect the signal s dc level CON 7 0 Contrast Adjust Address 0x08 7 0 This register allows the user to adjust the contrast of the picture Table 22 CON Function CON 7 0 Description
161. tion detected 1 CGMS sequence decoded Reserved x x x x 0x91 WSS1 WSS1 7 0 X X X X X X x x Read Only Wide screen signaling data 0x92 WSS2 WSS2 7 0 XIX X X X x x x WSS2 7 6 are Read Only Wide screen signaling data undetermined 0x93 WSS2 WSS2 7 0 X X X X X X X x Read Only Wide screen signaling data 0x94 EDTV2 EDTV2 7 0 X X X X X X x x Read Only EDTV data register 0x95 EDTV3 EDTV3 7 0 X X X X x x x x EDTV3 7 6 are EDTV3 5 is reserved Read Only EDTV data register undetermined for future use 0x96 CGMS1 CGMS1 7 0 Read Only CGMS data register 0x97 CGMS2 CGMS2 7 0 X X X X X X x x Read Only CGMS data register 0x98 CGMS3 CGMS3 7 0 X X X X x tx x CGMS3 7 4 are Read Only CGMS data register undetermined Rev B Page 84 of 104 ADV7189B Subaddress Register Bit Description Comments Notes 0x99 CCAP 1 Read Only CCAP1 7 0 Closed caption data register CCAP1 7 contains parity bit for Byte 0 Ox9A CCAP2 Read Only CCAP2 7 0 Closed caption data register CCAP2 7 contains parity bit for Byte 0 Ox9B Letterbox 1 Read Only LB LCT 7 0 Letterbox data register Reports the number of black lines detected at the top of active video Ox9C Letterbox 2 Read Only LB LCM 7 0 Letterbox data register Reports the number of black lines detected in the bottom half of active video if subtitl
162. tiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result In some cases using separate ground planes is unavoidable For these cases it is recommended to place a single ground plane under the ADV7189B The location of the split should be under the ADV7189B For this case it is even more important to place components wisely because the current loops are much longer current takes the path of least resistance Here is an example of a current loop power plane to ADV7189B to digital output trace to digital data receiver to digital ground plane to analog ground plane PLL Place the PLL loop filter components as close as possible to the ELPF pin Do not place any digital or other high frequency traces near these components Use the values suggested in the data sheet with tolerances of 10 or less DIGITAL OUTPUTS BOTH DATA AND CLOCKS Try to minimize the trace length that digital outputs have to drive Longer traces have higher capacitance which require more current which causes more internal digital noise Shorter traces reduce the possibility of reflections Adding a 30 to 50 series resistor can suppress reflections reduce EMI and reduce the current spikes inside the ADV7189B If series resistors are used place them as close as possible to the ADV7189B pins However try not to add vias or extra length to the output trace to make the resistors closer If possibl
163. tput on P19 to P10 Enable PAL autodetection only Slow down digital clamps Set CSFM to SH1 Stronger dot crawl reduction Enable 28 MHz crystal TRAQ Power down ADC 1 and ADC 2 MWE enable manual window BGB to 36 Set higher DNR threshold ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev B Page 93 of 104 ADV7189B EXAMPLES USING 27 MHz CLOCK Mode 1 CVBS Input Composite Video on AIN5 All standards are supported through autodetect 10 bit 4 2 2 ITU R BT 656 output on P19 to P10 Table 91 Mode 1 CVBS Input Register Address Register Value Notes 0x00 0x04 CVBS input on AIN5 0x03 0x00 Enable 10 bit output on P19 to P10 0x15 0x00 Slow down digital clamps 0x17 0x41 Set CSFM to SH1 0 16 Power down ADC 1 ADC 2 0x50 0x04 Set DNR threshold to 4 for flat response OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x
164. unctional Block Diagram eere 5 SpeGficationsu eden re ae e i reges tite ete 6 Electrical Characteristics ettet ritenere tine 6 Video Specifications 7 Timing Specifications seen 8 Analog Specifications essent 8 Thermal Specifications seen 9 Timing Diagrams ccce etae qe eT Re 9 Absolute Maximum Ratings essent 10 ESD rn rev mpi 10 Pin Configuration and Function Descriptions 11 Analog Frome End REEEERER REESE 13 Analog Input Muxing seen 13 Global Control Registers sse 16 Power Saye ettet eee 16 Reset Control eso ptem pt een 16 Global Pim Control eet 17 Global Status Registers seen 19 1 eto er DRM LLL 19 rica e ER 19 SD Autodetection Result sse 19 SUAS EESE ESTAT ERA 19 Mri M 19 Standard Definition Processor SDP sss 20 SD L rja Path eut Re E MERE 20 SD Chroma Paths ee eee nee eee dee ute 20 Sync PROCESSING seeianiueoieue ier I 21 VBI Data Recovery ene 21 General Setup ee Eh ER ERR UE 21 SD Color Controls eee eine NAA 23 Clamp Operation 25 L ma Filter eec 26 Chroma Filter cites tibt 29 Gain Operation screen pepe meriti ira 30 Chroma Transient Improvement CTI ss
165. ware LB 7 0 Letterbox Line Count Top Address 0x9B 7 0 LB LCM 7 0 Letterbox Line Count Mid Address 0x9C 7 0 LB LCB 7 0 Letterbox Line Count Bottom Address 0x9D 7 0 Table 62 LB LCx Access Information Signal Name Address Register Default Value LB LCT 7 0 Ox9B Readback only LB LCM 7 0 Ox9C Readback only LB_LCB 7 0 Ox9D Readback only LB TH 4 0 Letterbox Threshold Control Address 0xDC 4 0 Table 63 LB_TH Function LB TH 4 0 Description 01100 Default threshold for detection of black lines default 01101 to Increase threshold need larger active video 10000 content before identifying nonblack lines 00000 to Decrease threshold even small noise levels can 01011 cause the detection of nonblack lines LB SL 3 0 Letterbox Start Line Address 0xDD 7 4 The LB SL 3 0 bits are set at 0100b by default This means the letterbox detection window starts after the EDTV VBI data line For an NTSC signal this window is from Line 23 to Line 286 Changing the bits to 0101 the detection window starts on Line 24 and ends on Line 287 LB EL 3 0 Letterbox End Line Address 0xDD 3 0 The LB EL 3 0 bits are set at 1101b by default This means the letterbox detection window ends with the last active video line For an NTSC signal this window is from Line 262 to Line 525 Changing the bits to 1100 the detection window starts on Line 261 and ends on Line 254 Gemstar Data Recovery
166. x Drive Strength Selection Sync DR STR S 1 0 Address 0xF4 1 0 The DR STR S 1 0 bits allow the user to select the strength of the synchronization signals with which HS VS and F are driven For more information refer to the Drive Strength Selection Clock and the Drive Strength Selection Data sections Table 13 STR S Function DR STR S 1 0 Description 00 01 default 10 11 Low drive strength 1x Medium low drive strength 2x Medium high drive strength 3x High drive strength 4x Rev B Page 17 of 104 ADV7189B Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04 1 The EN_SFL_PIN bit enables the output of subcarrier lock information also known as GenLock from the ADV7189B core to an encoder in a decoder encoder back to back arrangement When EN_SFL_PIN is 0 default the subcarrier frequency lock output is disabled When EN_SFL_PIN is 1 the subcarrier frequency lock information is presented on the SFL pin Polarity LLC Pin PCLK Address 0 37 0 The polarity of the clock that leaves the ADV7189B via the LLCI and LLC2 pins can be inverted using the PCLK bit Changing the polarity of the LLC clock output can be necessary to meet the setup and hold time expectations of follow on chips Note This bit also inverts the polarity of the LLC2 clock When PCLK is 0 the LLC output polarity is inverted When PCLK is 1 default the LLC output polarity is
167. x34 first followed by 0x35 e No other taking place between the two or more writes for the sequence For example for HSB 10 0 write to Address 0x34 first immediately followed by 0x35 Rev B Page 62 of 104 26 REGISTER MAPS Table 82 Common and Normal Page 1 Register Map Details ADV7189B Subaddress Register Name Reset Value rw Dec Hex Input Control 0000 0000 rw 0 0x00 Video Selection 1100 1000 rw 1 0x01 Reserved 0000 0100 rw 2 0x02 Output Control 0000 1100 rw 3 0x03 Extended Output Control 01xx 0101 rw 4 0x04 Reserved 0000 0000 rw 5 0x05 Reserved 0000 0010 rw 6 0x06 Autodetect Enable 01111111 rw 7 0x07 Contrast 1000 0000 rw 8 0x08 Reserved 1000 0000 rw 9 0x09 Brightness 0000 0000 rw 10 Ox0A Hue 0000 0000 rw 11 0x0B Default Value Y 00110110 rw 12 0x0C Default Value C 0111 1100 rw 13 0x0D ADI Control 0000 0000 rw 14 OxOE Power Management 0000 0000 rw 15 Status 1 XXXX XXXX r 16 0x10 Ident XXXX XXXX r 17 0x11 Status 2 XXXX XXXX r 18 0x12 Status 3 XXXX XXXX r 19 0x13 Analog Clamp Control 0001 0010 rw 20 0x14 Digital Clamp Control 1 0100 xxxx rw 21 0x15 Reserved XXXX XXXX rw 22 0x16 Shaping Filter Control 0000 0001 rw 23 0x17 Shaping Filter Control 2 1001 0011 rw 24 0x18 Comb Filter Control 1111 0001 rw 25 0x19 Reserved XXXX XXXX rw 26 to 28 0x1A
168. xFF and 0x00 values These two values are reserved and are not to be used for active video Additionally the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma The RANGE bit allows the user to limit the range of values output by the ADV7189B to the recommended value range This bit ensures the reserved values of 255d OxFF and 00d 0x00 are not presented on the output pins unless they are part of an AV code header Table 52 RANGE Function LTA 1 0 Luma Timing Adjust Address 0x27 1 0 The Luma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples Note there is a certain functionality overlap with the CTA 2 0 register For manual programming use the following defaults e CVBS input LTA 1 0 00 e YC input LTA 1 0 01 e YPrPb input LTA 1 0 01 Table 53 LTA Function LTA 1 0 Description 00 default No delay 01 Luma 1 CLK 37 ns delayed 10 Luma 2 CLK 74 ns early 11 Luma 1 CLK 37 ns early RANGE Description 0 16 lt Y lt 235 16 lt lt 240 1 default 1 lt Y lt 254 1 lt C P lt 254 AUTO_PDC_EN Automatic Programmed Delay Control Address 0x27 6 Enabling the AUTO_PDC_EN function activates a function within the ADV7189B that automatically programs the LTA 1 0 and CTA 2 0 to have the chroma and luma data match delays for all modes of ope

ANALOG DEVICES ADV7189B handbook

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