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ST STM32F101x6 STM32F101x8 STM32F101xB handbook

1. Trace amp SWD gt Controller POWER 2 to 3 6V JNTRST VOLT REG v JTDI Cortex CPU ri ash i28 kB 18V Vss JTCK SWCLK 22 JTMS SWDIO KD N 25 64 bit VDD JTDO Fmax 36 MHz Kbs 2 as cc we 16KB vop 5 lt OSC IN GP DMA lt gt PCLK2 Lock S5 Qur 7 channels lt MANAGT 5 N RC 8 MHz e IWDG VDDA RC 32 kHz Standby VDDA SUPPLY 5 interface ys 4 NRST SUPERVISION VBAT VDDA POR PDR Rst VSSA p PTAL 32 kHz 21 PVD gt Int A AHB2 AHB2 Backup ANTI TAMP APB2 APB1 awu 9 Backup interface EXTI eee eee D waker K gt S C TIM2 KD 4 Channels 15 01 lt gt GPIOA KC KC 4 Channels 15 01 lt KK x lt 2 4 4 Channels 15 01 lt _ eroe 8 lt usare gt RGM CTS RTS PD 15 0 7 4 GPIOD SmartCard as AF N D lt den RX TX CTS RTS 023 eroe gt 2 USARIS SmartCard as AF e c MOSI MISO SCK NSS d lt gt SPI2 K lt I2C1 k 5 scL SDA SMBAL MOSI MISO gt C8 KA M gt as AF SCK NSS as AF RX TX CTS RTS KS 12 2 298 5 SmartCard as AF USART1 D V
2. 57 LQPF100 100 pin low profile quad flat package mechanical data 58 LQFP64 64 pin low profile quad flat package mechanical data 59 LQFP48 48 pin low profile quad flat package mechanical data 60 Thermal 61 Order codes sega E ea Race EORR kala 62 Document revision history 63 ky 0 f s www dzsc STM32F101xx List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 STM32F101xx access line block diagram 13 STM32F101xx access line LQFP100 pinout 14 STM32F101xx access line LQFP64 pinout 15 STM32F101xx access line LQFP48 pinout 15 Mapan dan BL ban nat wed pal benak ea SA ad dta 20 Pin loading conditions e km oa pa pn 22 Pin input voltage be ala 22 Power supply
3. 22 Current consumption measurement scheme 23 High speed external clock source AC timing diagram 33 Low speed external clock source AC timing 33 Typical application with 8 MHz 34 Typical application with a 32 768 kHz 35 Unused I O pin 43 AC characteristics definition 46 Recommended NRST pin protection 47 I2C bus AC waveforms and measurement Circuit 50 SPI timing diagram slave mode 0 52 SPI timing diagram slave mode and 11 52 SPI timing diagram master mode 53 ADC accuracy 55 Typical connection diagram using the ADC 55 Power supply and reference decoupling not connected to 56 Power supply and reference decoupling VREF connected to VDDA 56 LQPF100 100 pin low profile quad flat package outline
4. Typ Symbol Parameter Conditions Unit Vpp Vgar T 859 24V 33v Regulator in Run mode Low speed and high speed internal RC oscillators and high speed TBD 24 TBD oscillator OFF no independent Supply current in watchdog Stop mode Regulator in Low Power mode Ipp Low speed and high speed internal RC oscillators and high speed TBD 14 4 TBD oscillator OFF no independent watchdog Low speed internal RC oscillator and eid mode 9 independent watchdog OFF low TBD 24 TBD speed oscillator and RTC OFF _ Backup domain Low speed oscillator and RTC ON 19 1 40 TBD T supply current 1 TBD stands for to be determined 2 Typical values are measured at 25 3 3 V unless otherwise specified 3 Data based on characterization results tested in production at Vpp fici max and T4 4 Values expected for next silicon revision 5 To have the Standby consumption with RTC ON add Ipp Low speed oscillator and RTC ON to Ipp Standby when Vpp is present the Backup Domain is powered by Vpp supply ky 29 64 www dzsc Electrical characteristics STM32F101xx Typical current consumption The MCU is placed under the following conditions pins are in input mode with a static value at Vpp Vas no load All peripherals are disabled except if it is explicitly mentioned
5. 1 24 Current characteristics bo neuen mace RR 24 Thermal 25 General operating conditions 26 Operating conditions at power up power down 26 Embedded reset and power control block 27 Embedded internal reference 27 Maximum current consumption in Run and Sleep modes TA 85 28 Maximum current consumption in Stop and Standby 29 Typical current consumption in Run and Sleep modes 30 Typical current consumption in Stop and Standby modes 31 High speed user external HSE clock characteristics 32 Low speed user external clock 32 HSE 4 16 MHz oscillator 34 LSE oscillator characteristics fsg 32 768 2 35 HSI oscillator 36 LSI oscillator characteristics 36 Low power mode wakeup timingS
6. 37 PLL icharactensSuCs s seme cR RA BOR duet RC RR 37 Flash memory 38 Flash endurance and data 38 EMS Characteristics i oa lk nah Da AA ORA 39 EMI characteristics cR Ro ANE 40 ESD absolute maximum 05 40 Electrical sensitivities 41 VO static characteristics reu O DA a basa ema WA BR 42 Output voltage characteristics 44 AC 45 NRST characteristics 1 47 6 ee ba RAN Ba open kaka 48 IC characteristics a 49 SCL frequency fpc 42 36 MHz 3 3 50 SPI characteristics 51 5 itte SA BULAN MAN a o ART 4 E 54 ADC fpcLko 10 MHz fapc 10 MHz Rain lt 10 kQ VDDA 3 3 V 55 5
7. 58 LQFP64 64 pin low profile quad flat package outline 59 LQFP48 48 pin low profile quad flat package outline 60 5 64 www dzsc e Introduction STM32F101xx 6 64 Introduction This datasheet contains the description of the STM32F101xx access line family features pinout Electrical Characteristics Mechanical Data and Ordering information For information on programming erasing and protection of the internal Flash memory please refer to the STM32F10x Flash Programming Reference Manual For information the Cortex M M3 core please refer to the CortexTM M3 Technical Reference Manual Description The STM32F101xx access line family incorporates the high performance ARM Cortex M3 32 bit RISC core operating at a 36 MHz frequency high speed embedded memories Flash memory up to 128Kbytes and SRAM up to 16 Kbytes and an extensive range of enhanced peripherals and connected to two buses All devices offer standard communication interfaces two I Cs two SPIs and up to three USARTs one 12 bit ADC and three general purpose 16 bit timers The STM32F101 family operates in the 40 to 85 temperature range from a 2 0 to 3 6 V power supply A comprehensive set of power saving mode allows to design low power applications The complete STM32F101xx access line family includes devices in 3 different package types from
8. Table 21 Low power mode wakeup timings Symbol Parameter Conditions Typ Max Unit twus erp Wakeup from Sleep mode Wakeup on HSI RC clock 0 75 TBD us Wakeup from Stop mode HSI RC wakeup time 2 us 4 TBD regulator in run mode twustop ime us USTO Wakeup from Stop mode HSI RC wakeup time 2 us Regulator wakeup from LP 7 TBD regulator in low power mode mode time 5 us HSI RC wakeup time 2 us twusrpev 7 Wakeup from Standby mode Regulator wakeup from power 40 TBD us down time 38 us 1 TBD stands for to be determined 2 The wakeup time from Sleep and Stop mode are measured from the wakeup event to the point in which the user application code reads the first instruction The wakeup time from Standby mode is measured from the wakeup event to the point in which the device exits from reset PLL characteristics The parameters given in Table 22 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 22 PLL characteristics Value Symbol Parameter ee Unit Min Typ Max PLL input clock 8 0 MHz fPLL_IN PLL input clock duty cycle 40 60 Yo out PLL multiplier output clock 16 36 MHz tLock PLL lock time 200 US Cycle to cycle jitter 3 peak to Vpp is stable TBD TBD of peak 1 TBD stands for to be determined 2 Data based on device characterization not tested in produc
9. core with embedded Flash and SRAM The ARM Cortex M3 processor is the latest generation of ARM processors for embedded systems It has been developed to provide a low cost platform that meets the needs of MCU implementation with a reduced pin count and low power consumption while delivering outstanding computational performance and an advanced system response to interrupts The ARM Cortex M3 32 bit RISC processor features exceptional code efficiency delivering the high performance expected from an ARM core in the memory size usually associated with 8 and 16 bit devices The STM32F101xx access line family having an embedded ARM core is therefore compatible with all ARM tools and software Embedded Flash memory Up to 128 Kbytes of embedded Flash is available for storing programs and data Embedded SRAM Up to 16 Kbytes of embedded SRAM accessed read write at CPU clock speed with 0 wait states Nested vectored interrupt controller NVIC The STM32F101 xx access line embeds a nested vectored interrupt controller able to handle up to 43 maskable interrupt channels not including the 16 interrupt lines of Cortex M3 and 16 priority levels Closely coupled NVIC gives low latency interrupt processing Interrupt entry vector table address passed directly to the core Closely coupled NVIC core interface Allows early processing of interrupts Processing of ate arriving higher priority interrupts Support for tail cha
10. 16 MHz 1 Supply current in 8 MHz TBD Sleep mode Running on HSI clock code running from Flash all 4 MHz TBD peripheral disabled see RCC register description fpcLK1 pre scaler used to reduce the freguency 1 MHz TBD 500 kHz TBD 2 MHz TBD mA 1 TBD stands for to be determined 2 Typical values are measures at 25 3 3 V 4 30 64 HE www dzsc STM32F101xx Electrical characteristics Table 14 Typical current consumption in Stop and Standby modes Symbol Parameter Conditions Vpp Typ Unit Regulator in Run mode 3 3 V 24 Low speed and high speed internal RC oscillators OFF High speed oscillator OFF 24V TBD Supply current in Stop independent watchdog mode Regulator in Low Power mode 3 3V 149 Low speed and high speed internal RC oscillators OFF 8 High speed oscillator OFF no 2 4 V TBD independent watchdog 3 Low speed internal RC oscillator and 33V 2 independent watchdog OFF 24V TBD Supply current in Low speed internal RC oscillator and 3 3 V 3 18 A Standby mode independent watchdog ON 24V TBD H 3 Low speed internal RC oscillator ON 3 3 V 2 99 independent watchdog OFF 24V TBD 3 3V 1 49 Low speed oscillator and 8 Backup domain 24 V 1 A DD VBAT supply current 33V 0 59 H Low speed oscillator
11. Flash access time is adjusted to frequency 0 wait state from 0 to 24 MHz 1 wait state from 24 to 36 MHz The parameters given in Table 13 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 13 Typical current consumption Run and Sleep modes Symbol Parameter Conditions Typ Unit Oscillator running at 8 MHz with PLL code running 36 MHz TBD from Flash all peripheral disabled see RCC register 24 MHz 13 mA description 2 feci ko 16 MHz TBD 8 MHz 7 8 4 MHz 7 Running on HSI clock code running from Flash peripheral disabled see RCC register description 2 MHz 6 3 s fpcLK1 2 pre scaler used 1 MHz 6 2 in to reduce the frequenc Supply currentin y 500 kHz 61 Run mode 125 kHz 5 95 8 MHz 2 3 4 MHz 1 6 Running on HSI clock code running from RAM all IDD peripheral disabled see RCC register description 2 MHz 1 2 2 pre scaler used 1 MHz 1 to reduce the freguency 500 kH 0 88 2 125 kHz 0 82 Oscillator running at 8 MHz with PLL code running 36 MHz TBD from Flash all peripheral disabled see register 24 MHz TBD mA description feci 19 2 feci ke 122071
12. low profile guad flat package outline Di BARA KAMAR ARA ARAH 117 ES E1 ai14383 Table 41 LQFP64 64 low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 17 0 22 0 27 0 007 0 009 0 011 0 09 0 20 0 004 0 008 12 00 0 472 D1 10 00 0 394 E 12 00 0 472 E1 10 00 0 394 e 0 50 0 020 0 0 3 5 7 0 3 5 7 L 0 45 0 60 0 75 0 018 0 024 0 030 L1 1 00 0 039 Number of pins N 64 1574 59 64 Vx www dzsc Package characteristics STM32F101xx www dzsc 60 64 Figure 27 LQFP48 48 pin low profile quad flat package outline ai14384 Table 42 LQFP48 48 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 60 0 063 Al 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 17 0 22 0 27 0 007 0 009 0 011 0 09 0 20 0 004 0 008 D 9 00 0 354 D1 7 00 0 276 E 9 00 0 354 1 7 00 0 276 0 50 0 020 0 0 3 59 79 09 3 59 7 L 0 45 0 60 0 75 0 018 0 024 0 030 11 1 00 0 039 Number of pins N 48 1 Values in inches are converted from mm and rounded to 3 decimal digits 37 STM32F10
13. 212 7 PC13 ANTI PC13 TAMP 313 8 PC14 OSC32 lO 4 4 9 Pcteosca2 oUT vo Duri 10 Vss 5 Vss 5 5 5 5 5 12 OSC IN OSC IN 6 6 13 OSC OUT OSC OUT 7 7 14 NRST NRST 8 15 PCO ADC IN10 ADC IN10 9 16 PC1 ADC IN11 PC1 ADC IN11 10 17 PC2 ADC 1 12 2 ADC IN12 11 18 PC3 ADC IN13 ADC 1 13 8 12 19 5 20 VREF 5 VREF 21 VREF 5 VREF ia oo 4 a CTS Te 11 1151 24 GE T O 12 16 25 2 2 2 Te PA 13 17 26 Te PA3 18 27 Vss 4 Vss 4 19 28 Vpp 4 Vpp 4 16 64 y i www dzsc STM32F101xx Pin descriptions Table 3 Pin definitions continued Pins a 9 Main 239 Pin name function Default alternate functions after reset 321313 PA4 SPI1 NSS SPI1 NSS USART2 CK T4 20 729 USART2 CK ADC IN4 Ue PAg ADC IN4 15 21 30 5 5 SCK ADC IN5 5 SPI1_SCK ADC_IN5 PA6 SPI1_MISO ADC_IN6 SPI1_MISO ADC_IN6 TIM3 1 VO ds TIM3 10 PA7 SPI1 MOSI ADC IN7 SPI1 MOSI ADC IN7 dE TIM3 CH2 9 20 24 33 PC4 ADC 14 I O ADC IN14 25 34 PC5 ADC IN15 I O 5 ADC IN15 18 26 35
14. 1 _ HMM 0 1 Se am x 1 3 th SO p MISO 55 OUTPUT BIT6 OUT me gt gt MOSI INPUT MSB IN BITI IN LBN IN ai14135 4 52 64 STM32F101xx Electrical characteristics Figure 20 SPI timing diagram master mode High NSS input SCK Input 0 T 4 SCK Input 5 T tt T SCK INPUT MS BIN BIG IN i LSB IN MOS M OUT OUT OUT OUTUT tv MO th MO lt gt ai14136 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 57 53 64 Electrical characteristics STM32F101xx 5 3 16 12 bit ADC characteristics Unless otherwise specified the parameters given in Table 37 are derived from tests performed under ambient temperature fpc frequency and supply voltage conditions summarized in Table 7 Note It is recommended to perform a calibration after each power up Table 37 characteristics Symbol Parameter Conditions Min Typ Max Unit VppA power supply 24 3 6 V Positive reference voltage 2 0 VDDA V ADC clock frequency 0 6 14 MHz fs Sampling rate TBD 0 05 1 MHz 823 kHz External trigger frequ
15. STM 2F101x8 57 STM32F101x6 STM32F101x8 STM32F101xB Access line advanced ARM based 32 bit MCU with Flash memory six 16 bit timers ADC and seven communication interfaces Features m Core ARM 32 bit Cortex M3 CPU 36 MHz 45 DMIPS with 1 25 DMIPS MHz Single cycle multiplication and hardware division Nested interrupt controller with 43 maskable interrupt channels Interrupt processing down to 6 CPU cycles with tail chaining m Memories 32 to 128 Kbytes of Flash memory 6 to 16 Kbytes of SRAM m Clock reset and supply management 2 0 to 3 6 V application supply and l Os POR PDR and programmable voltage detector PVD 4 to 16 MHz high speed quartz oscillator Internal 8 MHz factory trimmed RC Internal 32 kHz RC PLL for CPU clock Dedicated 32 kHz oscillator for RTC with calibration m Low power LQFP48 7x7mm Preliminary Data 1 LQFP100 14 x 14 mm LQFP64 10 10 mm Temperature sensor m Up to 80 fast I O ports 32 49 80 5 V tolerant I Os All mappable on 16 external interrupt vectors Atomic read modify write operations m Up to 6 timers Up to three 16 bit timers each with up to 4 IC OC PWM or pulse counter 2 x 16 bit watchdog timers Independent and Window SysTick timer 24 bit downcounter m Upto 7 communication interfaces Up to 2 x 1 interfaces SMBus PMBus Up to 3 USARTs ISO 7816 interface LIN IrDA capability modem control
16. 14 64 STM32F101xx Pin descriptions Figure 3 STM32F101xx access line LAFP64 pinout VBAT PC13 ANTI PC14 OSC32 IN PC15 0SC32 OUT PDO OSC IN PD1 OSC OUT NRST 2 VSSA VDDA PAO WKUP 1 2 3 4 5 6 7 8 LQFP64 EA 50 UB WN ai14387 Figure 4 STM32F101xx access line LAFP48 pinout VBAT PC13 ANTI TAMP PC14 OSC32 IN PC15 0SC32 OUT OSC PD1 OSC OUT NRST VSSA VDDA PAO WKUP 1 2 00 Me 2 LT gt gt 48 47 46 45 44 43 42 41 40 39 38 37 LQFP48 DHLULILILTL IL VDD 2 VSS 2 PA13 PA12 11 10 PA9 PA8 PB15 PB14 13 12 ai14378 15 64 Pin descriptions STM32F101xx Table 3 Pin definitions Pins Main 2 3 S Pin name 8 function Default alternate functions LIE after reset 8148 1 2 2 TRACECK 2 PES TRACEDO TRACEDO 3 PE4 TRACED1 4 TRACED1 4 PE5 TRACED2 PE5 TRACED2 5 PE6 TRACED3 TRACED3 111 6 5
17. w STM32F101xx Electrical characteristics 5 3 3 5 3 4 Embedded reset and power control block characteristics The parameters given in Table 9 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 9 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit PLS 2 0 000 rising edge 2 1 2 18 2 26 V PLS 2 0 000 falling edge 2 2 08 2 16 V PLS 2 0 001 rising edge 2 19 2 28 2 37 V PLS 2 0 001 falling edge 2 09 2 18 2 27 V PLS 2 0 010 rising edge 2 28 2 38 2 48 V PLS 2 0 010 falling edge 2 18 2 28 2 38 V PLS 2 0 011 rising edge 2 38 2 48 2 58 V Programmable voltage PLS 2 0 011 falling edge 2 28 2 38 2 48 V Vpvo detector level selection PLS 2 0 100 rising edge 2 47 2 58 2 69 V PLS 2 0 100 falling edge 2 37 2 48 2 59 V PLS 2 0 101 rising edge 2 57 2 68 2 79 V PLS 2 0 101 falling edge 2 47 2 58 2 69 V PLS 2 0 110 rising edge 2 66 2 78 29 V PLS 2 0 110 falling edge 2 56 2 68 28 V PLS 2 0 111 rising edge 2 76 2 88 V PLS 2 0 111 falling edge 2 66 2 78 29 V Vpypnys PVD hysteresis 100 mV Power on power down reset Falling edge 1 8 1 88 1 96 threshold Rising edge
18. PBO ADC INS TIM3 CH3 I O ADC IN8 TIM3 CH3 19 27 36 PB1 ADC INS9 TIM3 CH4 10 PB1 ADC IN9 TIM3 CH4 20 28 37 2 1 lO FT 2 1 s 38 7 FT 7 39 PE8 FT PE8 40 PE9 FT PE9 41 PE10 PE10 42 PE11 VO FT PE11 208 12 VO FT PE12 44 PE13 VO FT PE13 45 PE14 VO FT PE14 ee 46 15 FT PE15 PB10 I2C2 SCL 5 5 7 21 29 47 USART3 TX FT PB10 1222 SCLS USART3 TX 1112 2 SDA 5 5 7 22 30 48 USART3 RX FT 11 1222 SDAS USART3 RX 23 31 49 Vss 4 Vss 4 24 32 50 Vpp 4 4 PB12 SPI2 NSS 5 2 NSS 94202 SMBAI 25 33 51 Dco smBayuSART3 ck O FT USART3 0 PB13 SPI2 SCK 517 517 26 34 52 USART3 CTS FT PB13 SPI2 SCK O USART3 CTS PB14 SPI2 MISO 5 7 5 7 27 35 53 USART3 RTS FT 14 SPI2_MISO 7 USART3_RTS 28 36 54 PB15 SPI2 MOSI O 15 5 2 MOSI 0 s PD8 FT PD8 ky 17 64 i www dzsc Pin descriptions STM32F101xx Table 3 Pin definitions continued Pins amp 3 function Default alternate functions cl O after reset lt 56 PD9 VO FT PD9 57 P
19. They can be served by DMA and they support SM Bus 2 0 PM Bus Universal synchronous asynchronous receiver transmitter USART The available USART interfaces communicate at up to 2 25 Mbit s They provide hardware management of the CTS and RTS signals support IIDA SIR ENDEC are ISO 7816 compliant and have LIN Master Slave capability The USART interfaces can be served by the DMA controller Serial peripheral interface SPI Up to two SPIs are able to communicate up to 18 Mbits s in slave and master modes in full duplex and simplex communication modes The 3 bit prescaler gives 8 master mode frequencies and the frame is configurable from 8 bit to 16 bit The hardware CRC generation verification supports basic SD Card MMC modes Both 5 5 can be served by the DMA controller GPIOs general purpose inputs outputs Each of the GPIO pins can be configured by software as output push pull or open drain as input with or without pull up or pull down or as Peripheral Alternate Function Most of the GPIO pins are shared with digital or analog alternate functions All GPIOs are high current capable The 1 alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I Os registers ADC analog to digital converter The 12 bit Analog to Digital Converter has up to 16 external channels and performs conversions in single shot or scan modes In scan mode automatic c
20. 40 to 85 TBD 33 Accuracy of HSI oscillator at TA 25 TBD H TBD 96 tsusi HSI oscillator startup time 1 2 us HSI oscillator power 8 consumption 80 HA 1 3 3 V 40 to 85 C unless otherwise specified 2 TBD stands for to be determined 3 Values based on device characterization not tested in production LSI Low Speed Internal RC Oscillator Table 20 LSI oscillator characteristics 1 Symbol Parameter Conditions Min Typ Max Unit Freguency 30 60 kHz LSI oscillator start up time 85 Us LSI oscillator power 0 65 1 2 consu mption IDD LSI 1 Vpp 40 to 85 C unless otherwise specified 2 Value based on device characterization not tested in production 36 64 www dzsc STM32F101xx Electrical characteristics 5 3 8 Wakeup time from low power mode The wakeup times given in Table 21 is measured on a wakeup phase with a 8 MHz HSI RC oscillator The clock source used to wake up the device depends from the current operating mode e Stop Standby mode the clock source is the RC oscillator Sleep mode the clock source is the clock that was set before entering Sleep mode All timings are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7
21. 55 89 PB3 JTDO TRACESWO I O FT JTDO PB3 TRACESWO 40 56 90 PB4 JNTRST VO FT JNTRST PB4 41 57 91 PB5 I2C1 SMBAI 5 2 1 SMBAI 42 58 92 PB6 I2C1 SCL TIM4 CH1 I O FT PB6 1221 5 1 7 0 43 59 93 PB7 I2C1 SDA TIM4 CH2 10 PB7 I2C1 5 4 cH2 9 0 44 60 94 BOOTO 45 61 95 PB8 TIM4 FT PB8 TIM4 0 0 46 62 96 PB9 TIM4 CH4 FT PB9 TIM4 49 7 97 PEO TIM4 ETR FT TIM4 ETR 98 PE1 VO FT PE1 47 63 99 Vss 3 S Vss 48 64 100 3 S Vpp 3 1 input output S supply HiZ high impedance 2 FT 5 V tolerant 3 Function availability depends on the chosen device Refer to Table 2 on page 7 4 PC13 PC14 and PC15 are supplied through the power switch and so their use in ouptut mode is limited they can be used only in output 2 MHz mode with a maximum load of 30 pF and only one pin can be put in output mode at a time 5 Available only on devices with a Flash memory density equal or higher than 64 Kbytes 6 For the 48 and LQFP64 packages the pins number 5 and 6 are configured as OSC IN OSC OUT after reset however the functionality of PDO and PD1 can be remapped by software on these pins 7 This alternate function can be remapped by software to some other port pins if available on the used package For more details refer to the Alternate function I O and debug configu
22. 48 pins to 100 pins Depending on the device chosen different sets of peripherals are included the description below gives an overview of the complete range of peripherals proposed in this family These features make the STM32F101xx access line microcontroller family suitable for a wide range of applications Application control and user interface Medical and handheld equipment PC peripherals gaming and GPS platforms Industrial applications PLC inverters printers and scanners Alarm systems Video intercom and HVAC Figure 1 shows the general block diagram of the device family Cortex Intelligent Processors by ARM lu e Bi 0 ww dzsc w STM32F101xx Description 2 1 Device overview Table 2 Device features and peripheral counts STM32F101xx access line Peripheral STM32F101Cx STM32F101Rx STM32F101Vx Flash Kbytes 32 64 32 64 128 64 128 SRAM Kbytes 6 10 6 10 16 10 16 General purpose 2 3 8 3 5 5 1 2 1 2 2 8 1 2 1 2 2 5 USART 2 3 2 3 3 12 bit synchronized ADC 1 1 number of channels 10 channels 16 channels GPIOs 32 49 80 CPU frequency 36 MHz Operating voltage 2 0to 3 6 V Operating temperature 40 to 85 Packages LQFP48 LQFP64 LQFP100 ky 7 64 www dzsc Description STM32F101xx 2 2 Overview 9
23. 5 Current characteristics This is implicitly insured if Vi maximum is respected If maximum cannot be respected the injection current must be limited externally to the value A positive injection is induced by Viy Vpp while a negative injection is induced by Viu amp Vas Table 5 Current characteristics Symbol Ratings Max Unit Total current into Vpp power lines 1 150 lyss Total current out of Vss ground lines sink 150 li Output current sunk by any I O and control pin 25 Output current source by any I Os and control pin 25 Injected current on NRST pin 5 mA sena 2 3 2 OSEE external OSC IN and Low 5 Injected current any other pin 9 t5 2 Total injected current sum of all I O and control pins 25 1 All 3 3 V power Vppa and ground Vas pins must always be connected to the external 3 3 V supply 2 must never be exceeded This is implicitly insured if Viy maximum is respected If maximum cannot be respected the injection current must be limited externally to the liy pi value A positive injection is induced by Viu Vpp while a negative injection is induced by lt 3 Negative injection disturbs the analog performance of the device See note in Section 5 3 16 12 bit ADC characteristics 4 When several inputs are submitted to a current injection the maximum Llinycpiny is the
24. OFF RTC ON 24 V 1 TBD stands for to determined 2 Typical values are measures at 25 3 3 V 3 Values expected for next silicon revision 4 To obtain Standby consumption with RTC ON add Low speed oscillator RTC ON to Ipp Standby ky 31 64 wwW dzsc Electrical characteristics STM32F101xx 5 3 6 External clock source characteristics High speed user external clock The characteristics given in Table 15 result from tests performed using an high speed external clock source and under ambient temperature and supply voltage conditions summarized in Table 7 Table 15 High speed user external HSE clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source fHSE_ext frequency 8 25 MHz OSC IN input pin high level voltage 0 7Vpp Vpp OSC IN input low level VHSEL voltage c Vss 0 3 IwHSE OSC IN high or low 16 tw HSE ns OSC_IN rise or fall time 5 OSC IN Input leakage IL current 9 Vss lt Vin lt Vpp t1 1 Value based on design simulation and or technology characteristics It is not tested in production Low speed user external clock The characteristics given in Table 16 result from tests performed using an low speed external clock source and under ambien
25. Typical values Unless otherwise specified typical data are based on T4 25 Vpp 3 3 V for the 2 V Npp lt 3 6 V voltage range They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 9596 of the devices have an error less than or equal to the value indicated meant22 Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7 21 64 0 www dzsc Electrical characteristics STM32F101xx Figure 6 Pin loading conditions Figure 7 Pin input voltage STM32F101 PIN C 50pF 2 ai14123 5 1 6 Power supply scheme Figure 8 Power supply scheme STM32F101 PIN ai14124 3 3V 1 8 3 6V GP I Os 1 2 3 4 5 Regulator 5 x 100 nF Vss 1 10 1 2 3 4 5 Backup Power switch OSC32K RTC Wake up logic Backup registers Kernel logic CPU Digital amp Memories 22 64 Analog RCs PLL ai14125 4 0
26. V ns Output low to high level rise time 25 2 7 V to 3 6 V 50 MHz Fmaxto out Maximum Frequency C 50 pF 2 7 3 6 V 30 MHz C 50 pF 2V to 2 7 V 20 MHz C 30 pF Vpp 2 7 V to 3 6 V 11 ines Outra high to low level fall CL 50pF Vpp 27Vto36V 8 50 pF Vpp 2 V to 2 7 V 12 ns C 30 pF 2 V to 3 6V low to high level rise 50 pF Vpp 27Vto36V 8 C 50 pF Vpp 2 V to 2 7 V 12 _ t Pulse width of external signals 10 T EXTlpw detected by the EXTI controller 1 Refer to the Reference user manual UM0306 for a description of GPIO Port configuration register 2 The maximum frequency is defined in Figure 15 3 Values based on design simulation and validated on silicon not tested in production 45 64 0 ww dzsc w Electrical characteristics STM32F101xx Figure 15 I O AC characteristics definition EXTERNAL ir IO out 4 OUTPUT i ON 50pF A T 4 Maximum frequency is achieved if ty t 2 3 and if the duty cycle is 45 55 when loaded by 50pF 14131 4 46 64 STM32F101xx Electrical characteristics 5 3 13 NRST pin characteristics The NRST pin input driver uses CMOS technology It is connected to a permanent pull up resistor Rpy see Table 29 Unless otherwise specified the parameters given in Table 32 are derived from tests p
27. after enable edge TBD X1 Data output valid time TBD TBD TBD th 2 Slave mode after enable edge TBD E 2 Data output hold time Master mode after enable edge TBD TBD to be determined Values based on design simulation and or characterization results and not tested in production Depends on fpc For example if fpc 8 MHz then 1 fpj 125 ns and tymo 255 ns gt Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 5 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z 57 51 64 0 www dzsc Electrical characteristics STM32F101xx Figure 18 SPI timing diagram slave mode and CPHA 0 NSS input SU NSS 99 gt 55 0 fT 8 CPOL 0 Ei x CPHA 0 8 Ai ER 1 1 1 d r SCK t 714 1 h SO LA dis SO MISO 1 tsu SI 97 14 ve MSB IN BITI IN Y IN INPUT Cl d ai14134 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp Figure 19 SPI timing diagram slave mode and 1 NSS input A ISU NSS He lt te SCk gt 66 4 39
28. change However it is recommended to take this point into account if the MCU is used in tough humidity conditions tsu Hse S the startup time measured from the moment it is enabled by software to a stabilized 8 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 12 Typical application with an 8 MHz crystal RESONATOR WITH INTEGRATED CAPACITORS T Bias sel Temat 4 ss Ci STM32F101xx ai14128 1 value depends on the crystal characteristics Typical value is in the range of 5 to 685 4 w 0 ww dzsc STM32F101xx Electrical characteristics Low speed external clock The low speed external LSE clock can be supplied with a 32 768 kHz crystal ceramic resonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 18 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 18 LSE oscillator characteristics sx 32 768 kHz Symbol P
29. parts to assess the latch up performance A supply overvoltage is applied to each power supply pin A current injection is applied to each input output and configurable I O pin These tests are compliant with EIA JESD 78 IC latch up standard Table 28 Electrical sensitivities Symbol Parameter LU Static latch up class 4105 Conditions Class level 41 64 wwW dzsc Electrical characteristics STM32F101xx 5 3 12 I O port characteristics General input output characteristics Unless otherwise specified the parameters given in Table 29 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 All unused pins must be held at a fixed voltage by using the I O output mode an external pull up or pull down resistor see Figure 14 Table 29 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level voltage 0 5 0 8 V IO TC mpar high level TTL ports 2 Vpp 0 5 voltage IO FT high level voltage 2 5 5V Input low level voltage 0 5 0 35 5 CMOS ports V Vg Input high level voltage 0 65 Vpp Vpp 0 5 10 TC trigger voltage 200 mV 7 hysteresis hys 1 10 TC Schmitt trigger voltage 4 hysteresis 9 5 VD Vss Vin lt 4 Standard I Os likg Input
30. www dzsc STM32F101xx Electrical characteristics 5 1 7 Current consumption measurement Figure 9 Current consumption measurement scheme IDD VBAT 9 3114126 23 64 0 ww dzsc Electrical characteristics STM32F101xx 5 2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 4 Voltage characteristics Table 5 Current characteristics and Table 6 Thermal characteristics may cause permanent damage to the device These are stress ratings only and functional operation of the device at these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 4 Voltage characteristics Symbol Ratings Min Max Unit External 3 3 V supply voltage including VppV 0 3 4 0 00788 Vppa and Vpp Input voltage on five volt tolerant pin Vss 0 3 45 5 Input voltage on any other pin Vss 0 3 Vppt0 3 IAVppxl Variations between different power pins 50 50 Variations between all the different ground mV IVssx Vssl 50 50 pins Electrostatic discharge voltage human ee TOU d VESD HBM maximum ratings electrical body model sensitivity 1 All 3 3 V power and ground Vss Vssa pins must always be connected to the external 3 3 V supply 2 Must never be exceeded see Table
31. 1 00 0x4001 1800 Port E 0x4001 1400 Port D 0x4001 1000 Port C 0 4001 0 00 Port B 0x4001 0800 PortA 0x4001 0400 EXTI 0x4001 0000 AFIO reserved 0x4000 7400 0 4000 7000 PWR 0x4000 6 00 BKR 0x4000 6800 reserved 0x4000 6400 15361080 0 4000 6000 reserved 4000 5 00 ___ served 0 4000 5800 1202 0 4000 5400 121 reserved 0 4000 4 00 0 4000 4800 USART3 0x4000 4400 USART2 reserved 0 4000 3 00 0 4000 3800 SES 0x4000 3400 reserved 0x4000 3000 0 4000 2 00 WWDG 0x4000 2800 RTC reserved 0x4000 0 00 0x4000 0800 4 0 4000 0400 TIM3 0 4000 0000 TIM2 1K www dzsc STM32F101xx Electrical characteristics 5 5 1 Electrical characteristics Test conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and freguencies by tests in production on 10096 of the devices with an ambient temperature at T4 25 and T4 given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation meant32
32. 1 84 1 92 20 V Vppnnys PDR hysteresis 40 Reset temporization 1 5 2 5 3 5 ms Embedded reference voltage The parameters given in Table 10 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 10 Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit Vperint Internal reference voltage 45 lt Ty lt 85 1 16 1 20 1 24 27 64 ww dzsc w Electrical characteristics STM32F101xx 5 3 5 Supply current characteristics The current consumption is measured as described in Figure 9 Current consumption measurement scheme Maximum current consumption The MCU is placed under the following conditions pins are in input mode with a static value at Vpp Vgg no load e All peripherals are disabled except if it is explicitly mentioned Flash access time is adjusted to frequency 0 wait state from 0 to 24 MHz 1 wait state from 24 to 36 MHz The parameters given in Table 11 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 11 Maximum current consumption in Run and Sleep modes T 85 1 Symbol Parameter Conditions Typ Max Unit External clock with PLL code running from 36 MHz 22 TBD Flash all peripherals enabled see RCC register description f
33. 1xx Electrical characteristics Table 38 ADC 10 2 10 MHz Rain 10 VppA z 3 3 0 Symbol Parameter Conditions Typ Max Unit Er Total unadjusted error 3 TBD Offset error 1 TBD Gain Error 2 TBD LSB Ep Differential linearity error 3 TBD EL Integral linearity error 2 TBD TBD to be determined 2 ADC Accuracy vs Negative Injection Current Injecting negative current on any of the standard non robust analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for Ii and in Section 5 3 12 does not affect the ADC accuracy Figure 21 ADC accuracy characteristics dodol eh ME ES 1 Example of an actual transfer curve 2 The ideal transfer curve 1022 T _ VssA 8 End point correlation line 1021 IDEAL 1024 Ze Ey Total Unadjusted Error maximum deviation between the actual and the ideal transfer curves 7 p Eg Offset Error deviation between the first actual 6 transition and the first ideal one Eg Gain Error dev
34. 1xx Package characteristics 6 1 Thermal characteristics The average chip junction temperature Ty in degrees Celsius may be calculated using the following equation Ty Ta Pp Oya 1 Where Tpis the ambient temperature in the package junction to ambient thermal resistance in C W Ppis the sum of Pint and Pp Pint Pro Pris the product of Ipp and Vpn expressed in Watts This is the chip internal power Po represents the power dissipation on input and output pins Most of the time for the application and can be neglected On the other hand may be significant if the device is configured to drive continuously external modules and or memories An approximate relationship between Pp and Tj if is neglected is given by Pp K Ty 273 C 2 Therefore solving equations 1 and 2 Pp x Ta 273 Pp 3 where K is a constant for the particular part which may be determined from equation 3 by measuring Pp at equilibrium for a known Ta Using this value of K the values of Pp and Tj may be obtained by solving equations 1 and 2 iteratively for any value of T4 Table 43 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient 100 14 x 14 mm 0 5 mm pitch Thermal resistance junction ambient 5 LQFP 64 10 x 10 mm 0 5 mm pitch 43 CAN Thermal resistance junction ambie
35. 3 3 V Ta 2 5 C 30 MHz to 130 MHz TBD Sem Peak level LQFP100 package compliant 5 with SAE J 1752 3 130 MHz to 1GHz TBD SAE EMI Level TBD 1 TBD stands for be determined Absolute maximum ratings electrical sensitivity Based on three different tests ESD LU using specific measurement methods the device is stressed in order to determine its performance in terms of electrical sensitivity Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size is either 3 parts cumulative mode or 3 parts x n 1 supply pins non cumulative mode The human body model HBM can be simulated The tests are compliant with JESD22 114 standard For more details refer to the application note AN1181 Table 27 ESD absolute maximum ratings Symbol Ratings Conditions Maximum value Unit Electrostatic discharge voltage human VESD HBM body model 2000 25 C V Electrostatic discharge voltage charge ESD CDM device model 1 TBD stands forto be determined 2 Values based on characterization results not tested in production ww dzsc w STM32F101xx Electrical characteristics Static latch up Two complementary static tests are reguired on 10
36. 314 timer characteristics 48 5 3 15 Communications interfaces 49 5 3 16 12 bit ADC characteristics 54 5 3 17 Temperature sensor characteristics 57 Package characteristics 58 6 1 Thermal characteristics 61 Order codes si facia we caw ee ca ea 62 7 1 Future family enhancements 62 Revision history 63 3 64 ww dzsc List of tables STM32F101xx List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 4 64 Device SUMMA ab ee PB wa sn ka Asa 1 Device features and peripheral counts STM32F101xx access 7 Pin definitiohs ues Ria Ra ba Ke RE alan 16 Voltage characteristics
37. D10 VO FT PD10 58 PD11 VO FT PD11 59 PD12 VO FT PD12 60 PD13 VO FT PD13 61 PD14 VO FT PD14 62 PD15 VO FT PD15 37 63 PC6 VO FT PC6 38 64 PC7 VO FT PC7 39 65 PC8 VO FT 40 66 9 VO FT 9 29 41 67 PAS USART1 CK MCO I O FT USART1 CK MCO 30 42 68 PA9 USART1 TX VO FT 9 USART1 TX 31 43 69 PA10 USART1 RX VO FT PA10 USART1 RX 32 44 70 PA11 USART1 CTS VO FT PA11 USART1 CTS 33 45 71 PA12 USART1 RTS VO FT PA12 USART1 RTS 34 46 72 PA13 JTMS SWDIO JTMS SWDIO PA13 73 Not connected 35 47 74 Vss 2 5 Vss 2 36 48 75 2 5 2 37 49 76 PA14 JTCK SWCLK JTCK SWCLK PA14 38 50 77 PA15 JTDI VO FT JTDI PA15 51 78 PC10 VO FT 10 52 79 11 FT 11 53 80 12 VO FT PC12 5 5 81 PDO OSC INO 6 6 82 PD1 FT OSC_OUT 54 83 PD2 TIM3 ETR FT PD2 TIM3 ETR 84 PD3 VO FT PD3 85 PD4 VO FT PD4 86 PD5 VO FT PD5 87 PD6 VO FT PD6 18 64 r Vx w ww dzsc STM32F101xx Pin descriptions Table 3 Pin definitions continued Pins amp 9 Main 239 Pin name 9 function Default alternate functions cl O after reset O 2 88 PD7 VO FT PD7 39
38. DDA 16AF VREF N 12bit E KN lt gt wwoe VREF Temp sensor ai14385 alternate function on I O port pin 2 TA 40 to 85 C junction temperature up to 125 13 64 www dzsc Pin descriptions STM32F101xx 3 Pin descriptions Figure 2 5 32 101 access line LQFP100 pinout E gt gt KR 9885993985989 905 9 9 t 6 f fo IR E 2 1 2 74 vss 2 40 3 73 NC 4 72 PA 13 5 71 12 VBATC 6 70 PA 11 7 69 10 PC14 OSC32 IND 8 68 PA9 PC15 OSC32_OUT 9 67 VSS 50 10 PC9 VDD 541 11 650 PC8 OSC 12 100 64 H OSC OuTd 13 63 PC6 14 62 PD15 15 61 PD14 16 60 PD13 2 17 59 h PD12 pc3d 18 58 PD11 55 19 57 PD10 158 20 56 H PD9 VREF q 21 55 h 8 22 54 PB15 PAO WKUP 23 53 5 PB14 PA1d 24 52 13 20 25 51 h 12 amp RN amp S8S9S 59935995999 zg9i199 7993 wb s st LO CO QI 00 O O sf 10 c amp oo amp amp amp amp ggaadaaaauiuuiuuunmnoo oo gt gt gt gt ai14386 4
39. NG OR LIFE SUSTAINING APPLICATIONS NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY DEATH OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ST PRODUCTS WHICH ARE NOT SPECIFIED AS AUTOMOTIVE GRADE MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER S OWN RISK Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2007 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom United States of America www st com 4 64 64
40. ST pin protection and Figure 17 bus AC waveforms and measurement circuit modified Sample size modified and machine model removed in Electrostatic discharge ESD Number of parts modified and standard reference updated in Static latch up 25 C and 85 C conditions removed and class name modified in Table 28 Electrical sensitivities tsU LSE changed to tsu LSE in Table 17 HSE 4 16 MHz oscillator characteristics In Table 24 Flash endurance and data retention typical endurance added data retention for T4 25 C removed and data retention for 85 C added Note removed below Table 7 General operating conditions changed to Vperinr in Table 10 Embedded internal reference voltage Ipp max values added to Table 11 Maximum current consumption in Run and Sleep modes T4 85 Ipp Hs max value added to Table 19 HSI oscillator characteristics Rpy and Rpp min and max values added to Table 29 I O static characteristics Rpy min and max values added to Table 32 NRST pin characteristics two notes removed Datasheet title corrected USB characteristics section removed Features on page 1 list optimized Small text changes 63 64 STM32F101xx Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and t
41. Up to 2 SPIs 18 Mbit s Table 1 Device summary Sleep Stop and Standby modes ael Vear supply for RTC and backup registers oot part STM32F101x6 STM32F101C6 STM32F101R6 STM32F101C8 STM32F101R8 Serial wire debug SWD and JTAG STM32F101x8 STM32F101V8 interfaces STM32F101xB STM32F101RB STM32F101VB m DMA T channel DMA controller Peripherals supported timers ADC SPIs I2Cs and USARTs m 12 bit 1 us A D converter 16 channel Conversion range 0 to 3 6 V July 2007 Rev 2 1 64 This is preliminary information on a new product now in development or undergoing evaluation Details are subject to www st com change without notice 0 www dzsc e Contents STM32F101xx Contents 1 Introduction Meg CEP 6 2 Description ics RR CR eae end ca do e e ed A err 6 2 1 Device overvieW 7 2 2 8 3 Pin descriptions 14 4 Memory mapping 20 5 Electrical characteristics 21 5 1 Test conditions 21 5 1 1 Minimum and maximum values 21 5 1 2 Typical Values e ern RR ORE Rr WR XR 21 5 1 3 Typical CUrVes sasic tanam ka EA on AN ban KAN E ga ae ea 21 5 1 4 Loading capaci
42. absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with Xi py maximum current injection on four I O port pins of the device 24 64 571 0 fg www dzsc STM32F101xx Electrical characteristics Table 6 Thermal characteristics Symbol Ratings Value Unit Storage temperature range 65 to 150 Maximum junction temperature see Thermal characteristics 25 64 0 ww dzsc Electrical characteristics STM32F101xx 5 3 5 5 3 1 3 2 26 64 Operating conditions General operating conditions Table 7 General operating conditions Symbol Parameter Conditions Min Max Unit Internal AHB clock freguency 0 36 Internal APB1 clock frequency 0 36 MHz Internal APB2 clock freguency 0 36 Standard operating voltage 2 3 6 V VBAT Backup operating voltage 1 8 3 6 V TA Ambient temperature range 40 85 Operating conditions at power up power down The parameters given in Table 8 are derived from tests performed under the ambient temperature condition summarized in Table 7 Table 8 Operating conditions at power up power down Symbol Parameter Conditions Min Unit V E t rise fall time p3 20 ms V ky ww dzsc
43. ame time 6 MA 7 v Output high level voltage for an 2 lt lt 27 Ves 04 OH when 4 pins are sourced at same time DDr 1 The ljo current sunk by the device must always respect the absolute maximum rating specified in Table 5 and the sum of lig I O ports and control pins must not exceed lyss Table 5 and the sum of lig ports and control pins must not exceed lypp The lig current sourced by the device must always respect the absolute maximum rating specified in 4 ww dzsc STM32F101xx Electrical characteristics Input output AC characteristics The definition and values of input output AC characteristics are given in Figure 15 and Table 31 respectively Unless otherwise specified the parameters given in Table 31 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 31 I O AC characteristics yo mode Symbol Parameter Conditions Max Unit fmax lo out Maximum frequency C 50 pF Vpp 2 V to 3 6 V 2 MHz Output high to low level fall 12 10 5 C 50 pF Vpp 2 V to 3 6 V ns Output low to high level rise 12 trtlo out time 3 5 fmaxtlO out Maximum frequency 2 C1 50pF Vpp 2Vto3 6V 10 MHz Output high to low level fall 2 01 5 C1 50 pF Vpp 2 V to 3 6
44. arameter Conditions Min Typ Max Unit Rr Feedback resistor 5 MO C Recommended load capacitance Ea versus equivalent serial Rs 30 15 pF L2 resistance of the crystal Vpp 33V LSE driving current 00 1 4 5 8 Vin Vss Oscillator transconductance 5 2 Startup time Vgs is stabilized 3 5 1 The oscillator selection can be optimized in terms of supply current using an high quality resonator with small Rg value for example MSIV TIN32 768 kHz Refer to crystal manufacturer for more details 2 tsu sp is the startup time measured from the moment it is enabled by software to a stabilized 33 768 kHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 13 Typical application with a 32 768 kHz crystal RESONATOR WITH INTEGRATED CAPACITORS 82 768 KHz resonator AH Cip STM32F101xx ai14129 57 35 64 www dzsc Electrical characteristics STM32F101xx 5 3 7 Internal Clock source characteristics The parameters given in Table 19 are derived from tests performed under ambient temperature and Vpp supply voitage conditions summarized in Table 7 High speed internal HSI RC oscillator Table 19 HSI oscillator characteristics 12 Symbol Parameter Conditions Min Max Unit fusi Freguency 8 MHz Ta
45. by mode allows to achieve the lowest power consumption The internal voltage regulator is switched off so that the entire 1 8 V domain is powered off The PLL the HSI and the HSE RC oscillators are also switched off After entering Standby mode SRAM and registers content are lost except for registers in the Backup domain and Standby circuitry The device exits Standby mode when an external reset NRST pin a IWDG reset a rising edge on the WKUP pin or an RTC alarm occurs Note The RTC the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode DMA The flexible 7 channel general purpose DMA is able to manage memory to memory peripheral to memory and memory to peripheral transfers The DMA controller supports circular buffer management avoiding the generation of interrupts when the controller reaches the end of the buffer Each channel is connected to dedicated hardware DMA requests with support for software trigger on each channel Configuration is made by software and transfer sizes between source and destination are independent The DMA can be used with the main peripherals SPI I2C USART general purpose timers TIMx and ADC 10 64 ky 0 f s www dzsc STM32F101xx Description RTC real time clock and backup registers The RTC and the backup registers are supplied through a switch that takes power either on Vpp supply when present or through the pin The backup
46. ck characteristics for the values of and 9 64 0 ww dzsc w Description STM32F101xx Voltage regulator The regulator has three operation modes main MR low power LPR and power down MRis used in the nominal regulation mode Run LPR is used in the Stop modes e Power down is used in Standby Mode the regulator output is in high impedance the kernel circuitry is powered down inducing zero consumption but the contents of the registers and SRAM are lost This regulator is always enabled after RESET It is disabled in Standby Mode providing high impedance output Low power modes The STM32F101xx access line supports three low power modes to achieve the best compromise between low power consumption short startup time and available wakeup Sources e Sleep mode In Sleep mode only the CPU is stopped All peripherals continue to operate and can wake up the CPU when an interrupt event occurs e Stop mode Stop mode allows to achieve the lowest power consumption while retaining the content of SRAM and registers All clocks in the 1 8 V domain are stopped the PLL the HSI and the HSE RC oscillators are disabled The voltage regulator can also be put either in normal or in low power mode The device can be woken up from Stop mode by any of the EXTI line The EXTI line source can be one of the 16 external lines the PVD output or the RTC alarm e Standby mode The Stand
47. dard protocol reguirement not tested in production 2 must be higher than 2 MHz to achieve the maximum standard mode frequency It must be higher than 4 MHz to achieve the maximum fast mode ISC frequency 3 The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL 49 64 0 ww dzsc w Electrical characteristics STM32F101xx Figure 17 bus waveforms and measurement circuit SDA 0114 50 gt 4 tsu SDA STM32F101 th STA gt lw SCKL 4 lh SDA tw SCKH 74 91 PH AK 1 4 50 5 0 ai14127b 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7 Table 35 SCL frequency fpc 36 MHz 3 3 9 faci 12 value kHz Rp 4 7 400 TBD 300 TBD 200 TBD 100 TBD 50 TBD 20 TBD 50 64 TBD to be determined External pull up resistance speed For speeds around 200 kHz the tolerance on the achieved speed is of 3596 For other speed ranges the tolerance on the achieved speed 3296 These variations depend on the accuracy of the external components used to design
48. device is stressed by two electromagnetic events until a failure occurs The failure is indicated by the LEDs e Electrostatic Discharge ESD positive and negative is applied to all device pins until a functional disturbance occurs This test is compliant with the IEC 1000 4 2 standard e FTB A Burst of Fast Transient voltage positive and negative is applied to Vpp and Vas through a 100 pF capacitor until a functional disturbance occurs This test is compliant with the IEC 1000 4 4 standard A device reset allows normal operations to be resumed The test results are given in Table 25 They are based on the EMS levels and classes defined in application note AN1709 Table 25 EMS characteristics Level Symbol Parameter Conditions Class Voltage limits to be applied on any I O pin to 3 3 V Ta 25 VrEsD 5 5 36 2 TBD induce a functional disturbance conforms to 1000 4 2 Fast transient voltage burst limits to be Vpp 3 3 25 Verte applied through 100pF on Vpp and Vas pins 36 MHz 4A to induce a functional disturbance conforms to IEC 1000 4 4 1 TBD stands for to be determined Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highly dependent on
49. eci 2 feci ko fucuk 24 MHz 21 TBD External clock PLL stopped code running from Flash all peripherals enabled see RCC register 8 MHz 10 TBD Supply current in description 2 Runmode External clock with PLL code running from RAM 36 MHz 13 18 all peripherals enabled see RCC register description fpci 2 feci ko fucuk 19 External clock PLL stopped code running from mA RAM all peripherals enabled see RCC register 8 MHz 45 TBD description 2 fPeLk2 fHcLK External clock with PLL code running from RAM 36 MHz 13 22 or Flash all peripherals enabled see register description fpc 2 24MHz 10 17 Supply current in 2 Sleep mode External clock PLL stopped code running from RAM or Flash all peripherals enabled see RCC register description 12 2 8 2 3 5 TBD 1 TBD stands for to be determined 2 Typical values are measured at T4 25 and 3 3 V 3 Data based on characterization results tested in production at max Tamax and code executed from RAM 4 28 64 0 fg E www dzsc STM32F101xx Electrical characteristics Table 12 Maximum current consumption in Stop and Standby modes
50. ed as a watchdog to reset the device when a problem occurs It is clocked from the main clock It has an early warning interrupt capability and the counter can be frozen in debug mode SysTick timer This timer is dedicated for OS but could also be used as a standard down counter It features e A24 bit down counter Autoreload capability e Maskable system interrupt generation when the counter reaches 0 e Programmable clock source General purpose timers TIMx There are up to 3 synchronizable standard timers embedded in the STM32F101xx access line devices These timers are based on a 16 bit auto reload up down counter a 16 bit prescaler and feature 4 independent channels each for input capture output compare PWM or one pulse mode output This gives up to 12 input captures output compares PWMs on the largest packages They can work together via the Timer Link feature for synchronization or event chaining The counter can be frozen in debug mode Any of the standard timers can be used to generate PWM outputs Each of the timers has independent DMA request generations 11 64 0 ww dzsc w Description STM32F101xx 12 64 bus Up to two bus interfaces can operate in multi master and slave modes They can support standard and fast modes They support dual slave addressing 7 bit only and both 7 10 bit addressing in master mode A hardware CRC generation verification is embedded
51. ed under ambient temperature fpc frequency and supply voltage conditions summarized in Table 7 Refer to Section 5 3 12 port characteristics for details on the input output alternate function characteristics output compare input capture external clock PWM output Table 33 TIMx characteristics Symbol Parameter TiMx Conditions Min Max Unit j j 1 t Timer resolution TIMxCLK tres TIM tim 2 3 4 36 MHz 27 8 ns Timer external clock 0 2 2 frequency on CH1 to x 22 3 4 CH4 36 MHz 0 18 MHz Resrim resolution 16 bit 16 bit counter clock 1 65536 trimeLk tcouNrER when internal x 2 3 4 clock is selected ftimxcLk 36 MHz 0 0278 1820 ttimxcLk Maximum possible x MAX_COUNT count 2 3 4 65536 36 MHz 119 2 s 1 x gives the TIM where 2 TIM2 is concerned etc 48 64 www dzsc STM32F101xx Electrical characteristics 5 3 15 Communications interfaces I2C interface characteristics Unless otherwise specified the parameters given in Table 34 are derived from tests performed under ambient temperature fpc frequency and Vpp supply voltage conditions summarized in Table 7 The STM32F101xx access line I2C interface meets the requirements of the standard 2 communication prot
52. ency fapc 14 MHz 17 1 fapc Vain Conversion voltage range 2 Vssa VDDA V External input impedance 2 3 C External capacitor on analog input Vin lt Vss lin I lt Iko Negative input leakage current on 400 on adjacent 5 6 uA analog pins analog Rapc Sampling switch resistance 1 Internal sample and hold ADC capacitor 9 pF 5 9 us tcaL Calibration time 14 MHz 83 1 0 214 us tat Injection conversion latency fapc 14 MHz 3 1 fapc ts Sampling time 14 MHz 0 107 17 1 us Power up time 0 0 1 US 1 18 US icon Total conversion time including fapc 14 MHz 14 1 5 for sampling sampling time 12 5 for successive 1 fapc approximation 1 TBD to be determined 2 Depending on the input signal variation fan Cain can be increased for stabilization time and reduced to allow the use of a larger serial resistor Rain It is valid for all fapc frequencies 14 MHz 3 During the sample time the input capacitance 5 max be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming 54 64 57 0 www dzsc STM32F10
53. erformed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 32 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit NRST Input low level voltage 0 5 0 8 NRST Input high level voltage 2 Vpp 0 5 NRST Schmitt trigger voltage Vhys NRST hysteresis 200 Weak pull up equivalent resistor Vin Vss 30 40 50 NRST Input filtered pulse 100 ns NRST Input not filtered pulse 300 TBD stands for to be determined 2 The pull up is designed with a true resistance in series with a switchable PMOS This PMOS contribution to the series resistance must be minimum 10 order 3 Values guaranteed by design not tested in production Figure 16 Recommended NRST pin protection External reset circuit p iN Internal Reset 5 FILTER STM32F101xx ai14132b 1 The reset network protects the device against parasitic resets 2 The user must ensure that the level on the NRST pin can go below the Vi rst max level specified in Table 32 Otherwise the reset will not be taken into account by the device 47 64 0 www dzsc Electrical characteristics STM32F101xx 5 3 14 TIM timer characteristics Unless otherwise specified the parameters given in Table 33 are derived from tests perform
54. he products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE ST PRODUCTS ARE NOT RECOMMENDED AUTHORIZED OR WARRANTED FOR USE IN MILITARY AIR CRAFT SPACE LIFE SAVI
55. iation between the last ideal 5 transition and the last actual one Eo EL Ep Differential Linearity Error maximum deviation 44 d 1 between actual steps and the ideal one 34 1 2 i E Integral Linearity Error maximum deviation 2 pa Epi between any actual transition and the end point 2 gt i correlation line 1 1 1 LSBipeat dub AAA 0 1 2 3 4 5 6 7 1021 1022 1023 1024 Vssa 14395 Figure 22 Typical connection diagram using the ADC STM32F101 ai14139 Refer to Table 37 for the values of RApc and 2 Cparasitic Must be added to Can It represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capacitance 3 pF A high Cpapasitic value will downgrade conversion accuracy To remedy this fapc should be reduced 57 55 64 0 www dzsc Electrical characteristics STM32F101xx General PCB design guidelines Power supply decoupling should be performed as shown in Figure 23 or Figure 24 depending on whether is connected to or not The 10 nF capacitors should be ceramic good quality They should be placed them as close as possible to the chip Figure 23 Power supply and reference decoupling not connected to VppA STM32F101xx 1 pF 10nF 1 10 ai14380 1 Veer and Veer inputs are available o
56. ining Processor state automatically saved Interrupt entry restored on interrupt exit with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency 8 64 www dzsc e STM32F101xx Description External interrupt event controller EXTI The external interrupt event controller consists of 19 edge detectors lines used to generate interrupt event requests Each line can be independently configured to select the trigger event rising edge falling edge both and can be masked independently A pending register maintains the status of the interrupt requests The EXTI can detect external line with pulse width lower than the Internal APB2 clock period Up to 80 GPIOs are connected to the 16 external interrupt lines Clocks and startup System clock selection is performed on startup however the internal RC 8 MHz oscillator is selected as default CPU clock on reset An external 4 16 MHz clock can be selected and is monitored for failure During such a scenario it is disabled and software interrupt management follows Similarly full interrupt management of the PLL clock entry is available when necessary for example with failure of an indirectly used external oscillator Several prescalers allow the configuration of the AHB frequency the High Speed APB APB2 and the low Speed APB APB1 domains The maximum frequency of the AHB and the APB domains is 36 MH
57. leakage current 4 Vin 5V 3 5 V tolerant I Os Weak pull up equivalent _ resistor Vin Vss 30 40 50 kQ Weak pull down equivalent 7 Rpp resistor 30 40 50 kQ pin capacitance 5 pF 1 Vpp 3 3 V 40 to 85 C unless otherwise specified 2 Values based on characterization results and not tested in production 3 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested 4 With a minimum of 100 mV 5 Leakage could be higher than max if negative current is injected on adjacent pins 6 Pull up and pull down resistors are designed with a true resistance in series with a switchable PMOS NMOS This PMOS NMOS contribution to the series resistance is minimum 10 order 42 64 ky 0 www dzsc STM32F101xx Electrical characteristics Figure 14 Unused I O pin connection 10 5 32 101 UNUSED VO PORT STM32F101 UNUSED VO PORT 7 ai14130 Output driving current The GPIOs general purpose input outputs can sink or source up to 8 mA and sink 20 mA with a relaxed In the user application the number of I O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5 2 The sum of the currents sourced by all the I Os on plus the maximum Run consumption of the MCU sourced on cannot exceed the absolute maxi
58. mum rating see Table 5 The sum of the currents sunk by all the I Os on Vss plus the maximum Run consumption of the MCU sunk on Vss cannot exceed the absolute maximum rating lyss see Table 5 43 64 www dzsc Electrical characteristics STM32F101xx 44 64 Output voltage levels Unless otherwise specified the parameters given in Table 30 are derived from tests performed under ambient temperature and Vpp supply voltage conditions summarized in Table 7 Table 30 Output voltage characteristics Symbol Parameter Conditions Min Max Unit Output Low level voltage for an I O pin 04 OL when 8 pins are sunk at same time TTL port lio B eu 8 mA V 2 utput High level voltage for an I O 27 Vc Vnn 3 6 when 4 pins are sourced at same time Output level voltage for an I O pin 1 VoU when 8 pins are sunk at same time CMOS port 1 Output high level voltage for an pi 2 utput high level voltage for pin 27V lt V 36V VoH when 4 pins are sourced at same time lt DD lt 24 Output low level voltage for an I O 13 when 8 pins are sunk at same time lio 20 mA Output high level voltage for an pin 2 7 V lt lt 3 6 V OH when 4 pins are sourced at same time BB vs NU Output low level voltage for an I O pin 04 OL when 8 pins are sunk at s
59. nly on 100 pin packages Figure 24 Power supply and reference decoupling connected to VppA STM32F101xx 1 10 nF Vrer Vssa ai14380 1 Veer and inputs are available only on 100 pin packages 4 56 64 www dzsc STM32F101xx Electrical characteristics 5 3 17 Temperature sensor characteristics Table 39 TS characteristics Symbol Parameter Conditions Min Typ Max Unit Vsense linearity with temperature H5 C Avg Slope Average slope 4 478 mV C Vos Voltage at 25 14 V 15 Startup time 4 10 US 57 64 wwW dzsc Package characteristics STM32F101xx Package characteristics Figure 25 LAPF100 100 pin low profile guad flat package outline ai14382 Table 40 100 100 pin low profile quad flat package mechanical data mm inches Dim Min Typ Max Min Typ Max A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A2 1 35 1 40 1 45 0 053 0 055 0 057 b 0 17 0 22 0 27 0 007 0 009 0 011 0 09 0 20 0 004 0 008 D 16 00 0 630 D1 14 00 0 551 E 16 00 0 630 E1 14 00 0 551 e 0 50 0 020 0 0 3 5 7 09 3 59 7 L 0 45 0 60 0 75 0 018 0 024 0 030 11 1 00 0 039 Number of pins N 100 STM32F101xx Package characteristics Figure 26 LAFP64 64
60. nt 55 LQFP 48 7 x 7 mm 0 5 mm pitch 61 64 0 ww dzsc w Order codes STM32F101xx 7 7 1 62 64 Order codes Table 44 Order codes Flash program SRAM Partnumber memory memory Package Kbytes Kbytes STM32F101C6T6 32 6 LQFP48 STM32F101C8T6 64 10 STM32F101R6T6 32 6 STM32F101R8T6 64 10 LQFP64 STM32F101RBT6 128 16 STM32F101V8T6 64 10 LQFP100 STM32F101VBT6 128 16 Future family enhancements Further developments of the STM32F101xx access line will see an expansion of the current options Larger packages will soon be available with up to 512KB Flash 48 SRAM and with extended features such as EMI support DAC and additional timers and USARTS 0 ww dzsc w 5 32 101 Revision history 8 Revision history Table 45 Document revision history Date 06 Jun 2007 Revision 4 Changes First draft 20 Jul 07 values modified in Table 11 Maximum current consumption in Run and Sleep modes Tp 85 Vpar range modified in Power supply schemes VREF min value liat and added to Table 37 ADC Characteristics Table 33 characteristics modified Note 5 modified and Note 7 Note 4 and Note 6 added below Table 3 Pin definitions Figure 11 Low speed external clock source AC timing diagram Figure 8 Power supply scheme Figure 16 Recommended NR
61. ocol with the following restrictions the I O pins SDA and SCL mapped to are not true open drain When configured as open drain the PMOS connected between the I O pin and Vpp is disabled but is still present In addition there is a protection diode between the I O pin and Vpp As a consequence when multiple master devices are connected to the I2C bus it is not possible to power off the STM32F101xx while another Fc master node remains powered on Otherwise the ST device would be powered by the protection diode The I2C characteristics are described in Table 34 Refer also to Section 5 3 12 I O port characteristics for more details on the input output alternate function characteristics SDA and SCL Table 34 characteristics Standard mode 1220 Fast mode 12 7 0 Symbol Parameter Unit Min Max Min Max tw SCLL SCL clock low time 4 7 1 3 us twiScLH SCL clock high time 4 0 0 6 lsuspA SDA setup time 250 100 SDA data hold time 00 0 9000 SDA SDA and SCL rise time 1000 20 0 1 300 ns SDA and SCL fall time 300 20 0 1C 300 Start condition hold time 4 0 0 6 Repeated Start condition setu HS tus time 4 7 0 6 Stop condition setup time 4 0 0 6 US Stop to Start condition time bus tw STO STA fee 4 7 1 3 us Capacitive load for each bus line 400 400 pF 1 Values based on stan
62. onversion is performed on a selected group of analog inputs The ADC can be served by the DMA controller An analog watchdog feature allows very precise monitoring of the converted voltage of one some or all selected channels An interrupt is generated when the converted voltage is outside the programmed thresholds Temperature sensor The temperature sensor has to generate a linear voltage with any variation in temperature The conversion range is between 2V Vppa 3 6V The temperature sensor is internally connected to the ADC IN16 input channel which is used to convert the sensor output voltage into a digital value 0 ww dzsc w STM32F101xx Description Serial wire JTAG debug port SWJ DP The ARM SWJ DP Interface is embedded and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific seguence on the TMS pin is used to switch between JTAG DP and SW DP Figure 1 5 32 101 access line block diagram
63. output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details on the resonator characteristics frequency package accuracy Table 17 HSE 4 16 MHz oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fosc Oscillator frequency 4 8 16 MHz Rr Feedback resistor 200 Recommended load capacitance versus eguivalent serial Rs 30 Q 30 pF 2 resistance of the crystal 9 Vpp 3 3 V 12 HSE driving current ViN Vss with 30 pF 1 mA load Oscillator transconductance Startup 25 mA V ISU HSE Startup time Vss is stabilized 2 ms Resonator characteristics given by the crystal ceramic resonator manufacturer For C 4 and it is recommended to use high quality ceramic capacitors in the 5 pF to 25 pF range typ designed for high frequency applications and selected to match the requirements of the crystal or resonator C and are usually the same size The crystal manufacturer typically specifies a load capacitance which is the series combination of C and C and MCU pin capacitance must be included when sizing C and 10 pF can be used as a rough estimate of the combined pin and board capacitance The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment due to the induced leakage and the bias condition
64. ration section the STM32F10xxx reference manual UMO306 available from the STMicroelectronics website www st com 19 64 0 www dzsc Memory mapping STM32F101xx 4 Memory mapping The memory map is shown in Figure 5 Figure 5 Memory map OxFFFF FFFF OxFFFF F000 7 0xE010 0000 0 000 0000 0 000 0000 Cortex M3 internal peripherals 5 0xA000 0000 4 0x8000 0000 0x6000 0000 0x4000 0000 Peripherals SRAM 0x2000 0000 0x0000 0000 Code ai14379 20 64 Ox1 FFF Ox1 FFF F9FF 0x1 FFF F800 0x1 FFF F000 0x0801 FFFF oT 00800 0000 Reserved reserved Option bytes System memory reserved Flash memory APB memory space OxFFFF FFFR 4K 1K 3K 1K 3K 1 1K 1K 1 1K 1K 1K 1K 1K 2K 1 1 1 1 1 1K 1K 35K 1K 1K 1K 1K 1K 1K 1K 1K 2K 1K 1K 2K 1K 1K 1K 1K 1K 7K 1K 1K OxEo100000 f Served 0 6000 0000 resorved x4002 3400 oon 0x4002 3000 Tesorved ox4oo2 2400 reserved 0x4002 20001 Flash interface 0x4002 1400 reserved 0x4002 1000 RCC 0x4002 0400 reserved 0x4002 0000 DMA reserved 0 4001 3 00 0 4001 3800 USAI ox4001 3400 eserved 0 4001 3000 Ox40012coo eServed 4001 28001 eserved 0x4001 2400 ADG reserved 0x4001
65. registers ten 16 bit registers can be used to store data when Vpp power is not present The Real Time Clock provides a set of continuously running counters which can be used with suitable software to provide a clock calendar function and provides an alarm interrupt and a periodic interrupt It is clocked by an external 32 768 kHz oscillator the internal low power RC oscillator or the high speed external clock divided by 128 The internal low power RC has a typical frequency of 32 kHz The RTC can be calibrated using an external 512Hz output to compensate for any natural quartz deviation The RTC features a 32 bit programmable counter for long term measurement using the Compare register to generate an alarm A 20 bit prescaler is used for the time base clock and is by default configured to generate a time base of 1 second from a clock at 32 768 kHz Independent watchdog The independent watchdog is based on a 12 bit downcounter and 8 bit prescaler It is clocked from an independent 32 kHz internal RC and as it operates independently from the main clock it can operate in Stop and Standby modes It can be used as a watchdog to reset the device when a problem occurs or as a free running timer for application time out management It is hardware or software configurable through the option bytes The counter can be frozen in debug mode Window watchdog The window watchdog is based on a 7 bit downcounter that can be set as free running It can be us
66. t temperature and supply voltage conditions summarized in Table 7 Table 16 Low speed user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source ex frequency 32 768 1000 kHz OSC32 IN input pin high level VisEH voltage 0 7Vpp Vpp OSC32 IN input pin low level VLSEL voltage Vss 0 3Vpp W LSE OSC32 IN high or low time 450 tw LSE ns 188 OSC32 IN rise or fall time 5 t sE OSC32 IN Input leakage IL current 9 Vss s Vin s 1 1 Value based on design simulation and or technology characteristics It is not tested in production 32 64 ky 0 www dzsc STM32F101xx Electrical characteristics Figure 10 High speed external clock source AC timing diagram EXTERNAL CLOCK SOURCE JUUL ai14127 Figure 11 Low speed external clock source AC timing diagram EXTERNAL CLOCK SOURCE JUUL ai14140b 33 64 Electrical characteristics STM32F101xx 34 64 High speed external clock The high speed external HSE clock can be supplied with a 4 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 17 In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize
67. the application 4 0 www dzsc STM32F101xx Electrical characteristics SPI interface characteristics Unless otherwise specified the parameters given in Table 36 are derived from tests performed under ambient temperature fpc frequency and supply voltage conditions summarized in Table 7 Refer to Section 5 3 12 port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 36 characteristics Symbol Parameter Conditions Min Max Unit Master mode TBD TBD SCK SPI clock frequency MHz 1 te Sck Slave mode 0 TBD SPI clock rise and fall time Capacitive load 50 pF TBD f SCK tsunss NSS setup time Slave mode 0 35 NSS hold time Slave mode 0 2 WSCKH SCK high and low time Master mode Team TBD tw SCKL presc TBD t 2 Master mode TBD su MI gt Data input setup time 154 5 Slave mode TBD Master mode TBD 2 Slave mode TBD gt Data input hold time Master mode TBD TBD Slave mode pg TBD TBD 9 Slave mode TBD TBD taso 2O Data output access time Slave mode fpc TBD TBD TBD 80 Data output disable time Slave mode TBD TBD Slave mode after enable edge TBD tvso 21 Data output valid time TBD TBD ae Master mode
68. the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical Data corruption control registers 39 64 www dzsc Electrical characteristics STM32F101xx 5 43 11 40 64 Pregualification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Electromagnetic Interference EMI The electromagnetic field emitted by the device is monitored while a simple application is executed toggling 2 LEDs through the I O ports This emission test is compliant with SAE J 1752 3 standard which specifies the test board and the pin loading Table 26 characteristics Max vs Symbol Parameter Conditions monitored Unit freguency band 8 36 MHz 0 1 MHz to 30 MHz TBD
69. tion 37 64 0 ww dzsc w Electrical characteristics STM32F101xx 5 3 9 Memory characteristics Flash memory The characteristics are given at 40 to 85 C unless otherwise specified Table 23 Flash memory characteristics Symbol Parameter Conditions Min Typ Max Unit tprog Word programming time TA 40 to 85 C 20 40 us tERASE Page 1kB erase time Ta 40 to 85 20 40 ms Mass erase time Ta 40 to 85 20 40 ms Read mode 36MHz with 2 wait states 20 ma 3 3 V Suppl 7 Write Erase modes DD id da fucik 36 MHz 5 mA Vpp 3 3 V Power down mode HALT 50 Vpp 3 0 to 3 6 V 1 TBD stands for to be determined 2 Values based on characterization and not tested in production Table 24 Flash endurance and data retention Value Symbol Parameter Conditions Unit Min Typ Max Endurance 1 10 kcycles Data retention 85 30 Years 1 Values based on characterization not tested in production 38 64 fg E www dzsc STM32F101xx Electrical characteristics 5 3 10 characteristics Susceptibility tests are performed on sample basis during device characterization Functional EMS Electromagnetic susceptibility While simple application is executed on the device toggling 2 LEDs through I O ports the
70. tor 21 5 1 5 PIN inp t voltage oo tesa sie es RE 21 5 1 6 Power supply scheme 22 5 1 7 Current consumption measurement 23 5 2 Absolute maximum 24 5 3 Operating conditions 26 5 3 1 General operating conditions 26 5 3 2 Operating conditions at power up power down 26 5 3 3 Embedded reset and power control block characteristics 27 5 3 4 Embedded reference voltage 27 5 3 5 Supply current characteristics 28 5 3 6 External clock source 32 5 3 7 Internal Clock source characteristics 36 5 3 8 PLL characteristics 37 5 3 9 Memory characteristics 38 5 3 10 characteristics 39 5 3 11 Absolute maximum ratings electrical sensitivity 40 5 3 12 42 5 313 NRST pin characteristics 47 2 64 ky ww dzsc w STM32F101xx Contents 5
71. z Boot modes At startup boot pins are used to select one of five boot options e Boot from User Flash e Boot from System Memory e Bootfrom SRAM The boot loader is located in System Memory It is used to reprogram the Flash memory by using the USART Power supply schemes Vpp 2 0to 3 6 V External power supply for I Os and the internal regulator Provided externally through Vpp pins Vasa VppA 2 0 to 3 6 V External analog power supplies for ADC Reset blocks RCs and PLL In Vpp range ADC is limited at 2 4 V Vpar 1 8 to 3 6 V Power supply for RTC external clock 32 kHz oscillator and backup registers through power switch when Vpp is not present Power supply supervisor The device has an integrated power on reset POR power down reset PDR circuitry It is always active and ensures proper operation starting from down to 2 V The device remains in reset mode when is below a specified threshold without the need for an external reset circuit The device features an embedded Programmable voltage detector PVD that monitors the Vpp power supply and compares it to the Vpyp threshold An interrupt can be generated when Vpp drops below the Vpyp and or when Vpp is higher than the Vpyp threshold interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software Refer to Table 9 Embedded reset and power control blo

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