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ANALOG DEVICES UG-293 handbook

1. Figure 29 Top Side Rev 0 Page 20 of 28 L Figure 30 Ground Plane Layer 2 000000 000000 000000 000099 000000 000000 000000 000000 990099 9990908 999099 909009 009000 90000 9009000 0090000 200000 0090900 000000 9 9 9 9 9 9 9 9 9 9 o o Figure 31 Power Plane Layer 3 Rev 0 Page 21 of 28 09940 030 09940 031 000 000 900000 600000 C 600 000000 600000 z 000 o 9 o s 900000 o o0 9 o o 9 5 oe 5 D D D 9 Figure 32 Power Plane Layer 4 Do 54 c o0000on BT 6 66 6 O O ME j T SE G 200000 O s Q 600006 600000 000006 600006 000000 S 9 g Figure 33 Ground Plane Layer 5 Rev 0 Page 22 of 28 09940 032 09940 033 0 660 Figure 34 Bottom Side Rev 0 Page 23 of 28 ORDERING INFORMATION BILL OF MATERIALS Table 1 AD9643 AD9613 AD6649 AD6643 Bill of Materials Item Reference Designator Manufacturer Part No C101 C102 C103 C105 C109 C110 C111 C112 C113 C114 C115 C514 C515 C516 C520 C521 C107 C117 C118 C121 C122 C212 C123 C231 C233 C235 C237 C239 C301 C305 C306 C307 C311 C312 C401 C402 C403 C
2. 6 Configuring the Board o oe o ordinis 6 Using the Software for Testing eere 6 Evaluation Board Schematics and Artwork 14 Orderino Inform tor RUN 24 Bill Ob Materials ccce aga aja ARRIERE DIA 24 Related TAK seach coc M 27 Rev 0 Page 2 of 28 EVALUATION BOARD HARDWARE The AD9643 AD9613 AD6649 or AD6643 evaluation board provides all of the support circuitry required to operate these parts in their various modes and configurations Figure 2 shows the typical bench characterization setup used to evaluate the ac performance of the AD9643 AD9613 AD6649 or AD6643 It is critical that the signal sources used for the analog input and the clock have very low phase noise lt 1 ps rms jitter to realize the optimum performance of the signal chain Proper filtering of the analog input signal to remove harmonics and lower the inte grated or broadband noise at the input is necessary to achieve the specified noise performance See the Evaluation Board Software Quick Start Procedures section to get started and see Figure 23 to Figure 34 for the complete schematics and layout diagrams These diagrams demonstrate the routing and grounding techniques that should be applied at the system level when designing application boards using these converters POWER SUPPLIES This evaluation board comes with a wall mountable switching power supply that provid
3. za d 9 ET im UCAS LE cT J 270 TI TO U 5 BT OTA dUd NIAOVSOLYHS 7m 8 ed o ING 5 Na amar Lv orca anou ANT a Fo 9 NC a roe pum E 557170 OV E NAS ua 9 9 3nr Seto Lp c mills TITY se m 6074 m me gr 38 8 T TD 5 S e V to S Di B x eo D o BID A av a 5 6 c UNDO BT 9 TY S EK 5858 EE J D D g 3 5 w b BTA JNT oa KO D D m 9 D D 1 S IS S 5812 15 e6v9oadU vaedu 404 GOJ3Cg33N LON ALI JIHILUdWHOO 8560 NOS AYLINDYID UMHIX3 TOTaL SNIMBYC JHL LSNIHDU Q3XO3GHO MH OL SAJAN GDISOS SIHL 04 LNTYdLOOS JHL LAG Gd Nie Figure 23 DUT and Related Circuits Rev 0 Page 14 of 28 Vc0 0v660 Jnec 1 nee vezo EZZ ING gecu ZHW T Hna a A CNS T A 1123 S 5 ST 5158 2 A nee 0553 ZHW OT TU009d 110412 2NAS oW cc cc aanwga naan 9406 amp 6 665 am 24 8 7 Z041982 TIUL GONG ANY AAAY 30 SNIeHOHS SLENTWNS OL ZHW T A lddfis ONIHOLIMS JUNOI LdO 9024 ING AQT 20958 s 359 anez 1129 0159 aong di vzZS di ues UN A LAN a Tazdr 3024 0245 SOTWNY NE dE A ed ONY SZvE TES SZ 5 alo 1 9 gt a CJ S o gt o KI N I L 8 a 8 Lo ethw jth ZHW T STS DNO CON TES a c as e ps 1MOdd is7ns Sl co gd WLIOTO NEdE
4. T ING GOT 812 0 aco 210 Trou all alla r INI 001 ING T c c c c 5 yy m MN o 6 r94 21 TTG or9u TTG I I I i 5 ING ING m m m m 001 997 2 2 D D sti gr9y 017 6a 6E9Y 60 m m m m 5 D D D D INI T ING 3817 3 OO NWN 1NG 3HL MUIN SHOLSISSY WO 80 2794 80 2a 20 i ING GGT ING 901 coSd easd TOSd TOSd 3 OL NMUd ONY NIO ONAS DNIDNIAH __ _wu or 90 3794 90 2 TS ING 001 ING QOT oe NNNM u k D u Sv9H a 9 94 a r E 8 ING ING gga Na o S 72 a zHS2 dAD TY eus2usn 20 ra sE94 10 All a allg M ING ING 3 at gaT 2 B B 52841 INT A Ev9el 20 SING vesy LING D D D D ING INI 0071 ING 997 cv9u ada ood 020 109d toad TYLISITTNEGE SOT a SON Gia ODAL JHL OL S12991 1719 100A94 21001 T LADNI NANIO NMULYU SI 10EWAS SIHL 3LON NOU anro A mov T A 2032 T LNG YVAN S022 SOU 1d 1 10AU toa 74 e ING 8 a Aju OIGG c oas OIUS UJ T 9 i aT 4 Tesy a 1L as AT w alu MTT ew ZME VELOMY o Ow 5234 ZNA ve LDOY Egan mr Qa g A S E N3 IdS 159094 Figure 28 SPI Configuration Circuit and FIFO Board Connector Circuit Rev 0 Page 19 of 28 660 0 660 Moa O an 9 r e E RE 15 i
5. kN PR PTT 0 10 20 30 40 50 60 70 80 90 100 110 120 FREQUENCY MHz Figure 16 Typical FFT AD9643 the performance plot data as a csv formatted file See Figure 16 for an example gt gt Graph AD9643 Average FFT 11 18 2010 11 43 08 AM pcs alls File a ale ela ejr E E Hr SNR 69 811 dB SNRFS 70 835 dB SINAD 69 632 dBc DC Power 48 101 dBFS Fund Frequency 105 758 MHz 1 Fund Power 1 024 dBFS Harm 2 Power 85 388 dBc Harm 3 Power 91 062 dBc Harm 4 Power 95 841 dBc Harm 5 Power 93 685 dBc Harm 6 Power 103 515 dBc Worst Other Power 91 579 dBFS Noise VHz 151 73 dBFS VHz Average Bin Noise 115 99 dBFS 1 THD 83 557 dBc i SFDR 85 387 dBc 09940 016 Figure 17 Graph Window of VisualAnalog AD9643 Rev 0 Page 11 of 28 09940 017 4 If operating the AD6649 in the mode using the 95 MHz FIR filter and fixed frequency NCO the amplitude displayed is 2 5 dBFS for a 1 0 dBFS input signal see Figure 18 to the desired settings If operating the AD6649 in the mode utilizing the 100 MHz FIR filter and tunable frequency NCO the amplitude displayed is 1 3 dBFS for a 1 0 dBFS input signal see Figure 19 a 09940 019 Figure 19 Visual Graph Window of VisualAnalog AD6649 100 MHz FIR Filter and Tunable Frequency NCO Mode 5 Repeat Step 3 to save the graph in a csv f
6. vert Lr Hi Faget FA Soe yan Figure 9 SPI Controller New DUT Button 1 20 4 f Garam r 3 Inthe ADCBase 0 tab of the SPIController window find the lea TET divider use the drop down box to select the correct clock divide ratio if necessary See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information eae 4 Inthe ADCBase 0 tab of the SPIController window find the KUNG TO AE ONONE Kap GAE A A FLEX OUTPUT DELAY 17 box Select the DCO Clk Delay Enable checkbox to enable this feature In the drop down box select 600 ps additional delay on DCO pin These settings align the output timing with the input timing on the capture FPGA CLK DIV B section see Figure 11 If using the clock 09940 011 gt SPIController 1 0 69 3 USB Ezusb 0 CS 1 AD9643spiR03 cfg AD9643spiR03 cal File Config Help Sa 0 aE Li PATT2 1C 1B o ple m USERTEST 67 E te USER TEST PATT4 20 1F OVP Port DCO Clk Invert Channel Multiplexed Mode En Vref Adjust 1 75V pk pk M DCO Clk Delay Enable DCO Clk Delay 100 ps additional delay on DCO pin 11 18 2010 11 38 11 AM 09940 010 Figure 11 SPI Controller CLK DIV B Section Rev 0 Page 8 of 28 Evaluation Board User Guide 6 Ifusing the AD6649 the device can be
7. LYOddNS NS ING b TIPY PEN Tis 14 140ddnsTns ING e QTvH E33 LYOddNS NS ck GN 4 A H sotva chbasd ovausTovY SOTWNE NEE Z XT GNSV gave 50 EdE AT AT MT 2 2 12v A ONY T 62ry NIdESOBBOOTMSLIZLKYS z T gard T S079 mum MES HS DOWNY ANT o NT o NTO 6779 vTVO 141 0 Figure 26 Optional Active Input Circuits Rev 0 Page 17 of 28 o ce Oo X gt o M J ET PTLNOTNE E Ant WLISTO NEdDE ceso DON NEE S S H HlUd X90070 2 HLIM SdqUd 3HUHS 1 0AU1 e YSLN3S9 OL YSLNSO SAIW OVS H S UWS LNOAYT i Sa trees MOO ID 4NLSSUa lt 8 1 5 3 P ING T 0 1n07n8 T 9 8 gasu 5 s gasy 320 824 5 S e 3 E 8 2 4054 A ET PTLNOTNE ON9U ON94 JNT KT 5 5 EN L S E 5 l i E 08 09 EP 6 Gr z 3 sasa iR io 1 P E gf ant o 6 ses2 paso TTid NE MILI TOKIN AT 0 _ 2oso NITI 2 u S NT a 631 1NITND vo koi Ant R EITIO AYMLINDYID X19 SANTA NO INO 5 S 05853 Us 5 GESYING obl E BAN gt Figure 27 Default and Optional Clock Input Circuits Rev 0 Page 18 of 28 o co A gt S WAXIU3H 2 Id N Em A coSd casd TOSd Tosd ING
8. SPI Controller Example ADC A Tab NSR Settings for the AD6643 7 fusing the Noise Shaping Reguantizer NSR feature of the the NOISE SHAPED REQUANTIZER TUNING 3E AD6643 the settings in the ADC A and or ADC B pages section must be changed see Figure 14 The NSR Enable 8 Click the Run button in the VisualAnalog toolbar see checkbox must be selected under the NOISE SHAPED Figure 15 REQUANTIZER 1 3C section This enables the circuitry in the AD6643 To select the bandwidth mode select 0 for 22 and 1 for 33 under the NSR Mode drop down menu MN mu Wedon Hep in the NOISE SHAPED REQUANTIZER 1 3C section Upon selecting the bandwidth mode select the desired 2 p Canvas AD9643 Average ican 09940 015 tuning word in the NSR Tuning drop down menu under Figure 15 Run Button Encircled in Red in VisualAnalog Toolbar Collapsed Display Rev 0 Page 10 of 28 Adjusting the Amplitude of the Input Signal 0 50MSPS 90 1MHz 1dBFS The next step is to adjust the amplitude of the input signal for _20 SNR 70 6dB 71 6dBFS SFDR 88dBc THIRD HARMONIC Ls each channel as follows 1 Adjust the amplitude of the input signal so that the fundamental is at the desired level Examine the Fund Power reading in the left panel of the VisualAnalog Graph window See Figure 17 2 Repeat this procedure for Channel B if desired 3 Click the Save disk icon within the Graph window to save AMPLITUDE dBFS
9. T401 1402 U401 U501 U603 Y501 0 001 UF capacitor ceramic monolithic 12 pF capacitor ceramic COG 0402 100 MHZ inductor ferrite bead Connector PCB SMA ST edge mount 2 2 uH inductor SM 120 nH inductor SM 3 9 nH inductor SM 2 0 kO resistor film SMD 0402 10 kQ resistor PREC thick film chip RO402 49 9 resistor PREC thick film chip RO402 0 O resistor film SMD 0402 TBD 3 130 O resistor PREC thick film chip RO402 150 resistor ultra PREC ultrareliability MF chip 1 resistor ultra PREC ultrareliability MEF chip TBD R0402 100 O resistor PREC thick film chip R0201 100 resistor film SMD 0402 XFMR RF XFMR RF IC Analog Devices ADL5202 IC Analog Devices AD9523 1 IC Analog Devices CMOS quad SPDT switches 60 MHz to 800 MHZ IC oscillator voltage controlled oscillator Rev 0 Page 26 of 28 Murata GRM155R71H122KA01D Samsung CLO5C2R7CBNC Phycomp YAGEO 0402CG220J9B200 Murata GRM155R71H102KA01D Murata GRM1555C1H120JZ01D Panasonic EXC ML20A390U Samtec SMA J P X ST EM1 Toko FDV0630 2R2M Panasonic ELJ RER12JF3 Toko LL1005 FN3N9K Multicomp CR10B202JT Panasonic ERJ 2RKF 1002X Panasonic ERJ 2RKF49R9X Panasonic ERJ 2GEOROOX Panasonic ERJ 2RKF 1 300X Susumu RG1005P 151 B T5 Susumu RG1005P 102 B T5 Panasonic ERJ 1GEF1000C Venkel CRO402 16W 1000FPT Mini Circuits ADT1 1WT Mini Circuits TC3 1T Analog Devices ADL5202 Analog Devices AD9523 1BCPZ Analog Devices
10. 100 resistor PREC thick film chip R0402 27 kQ resistor CHIP SMD 0402 4 64 resistor PREC thick film chip R0402 15 resistor chip SMD 0402 13 kO resistor film SMD 0402 10 5 resistor PREC thick film chip R0402 33 resistor film SMD 0402 36 0 resistor film SMD 0402 15 0 resistor film SMD 0402 49 9 Q resistor PREC thick film chip R0402 100 O resistor PREC thick film chip R0201 200 O resistor PREC thick film chip R0402 XFMR RF 1 1 SKT 64 pin LFCSP IC Analog Devices low dropout CMOS linear regulator IC 150 mA ultralow noise CMOS linear regulator IC Analog Devices low dropout CMOS linear regulator IC Analog Devices dual configurable synchronous PWM step down regulator IC 150 mA ultralow noise CMOS linear regulator IC tiny logic UHS dual buffer IC tiny logic UHS dual buffer 1 uF capacitor monolithic ceramic 0402 0 1 uF capacitor ceramic X7R 0402 0 01 uF capacitor ceramic X7R 0402 Rev 0 Page 25 of 28 CUI Inc PJ 202A Wieland Z5 531 3625 0 Wieland Z5 531 3425 0 Samtec TSW 103 08 G S Tyco 6469169 1 Panasonic ERJ 2GEOROOX NIC Components Corp NRCO6F2610TRF Panasonic ERJ 2RKF1002X Panasonic ERJ 2RKF1911X Panasonic ERJ 2RKF1001X Panasonic ERJ 2RKF10ROX Panasonic ERJ 2RKF1003X Panasonic ERJ 2RKF2702X Panasonic ERJ 2RKF4641X Panasonic ERJ 2RKF 1502X Yageo 9C04021A1302FLHF3 Panasonic ERJ 2RKF 1052X Panasonic ERJ 2GEJ330X Panasonic ERJ 2GEJ360X Panasoni
11. 7 T gen sa Ll 1L4 ZrrasTdag 1123 ano9 24 8 T ZINYASTAaAY soen ge Na 90 RNYTNEGE g 179 Mon Lal T di ues ZHWOOT m c n ca QT Td aano a SZ9E TES SZ LH E E ZONvAST dau 3 m G6 A 89 U Zed ZHW T D 140ddnsTns 7 T S 1023 NIN WLISTA AEE G6 LH ZU NUSO T dI Teen TEN d IIO C N33H 9 189 Figure 24 Board Power Input and Supply Rev 0 Page 15 of 28 LNOTAWY Sc0 0v660 I7 YSLNS9 OL YSALNSD 5 IIW 3H fJY0HS 595 IN IMT TLOY see t TTEO S Ud 34045 EON GE xl esee SS li SASNAL UNE 55 FALON cak p YSLNS9 OL YSALNSD 5 11 3H fJY0HS S ING 1 10AU 1 U 1f dWU MT o 192 id DJ S Ud 3905 TOEL as PG Apis ES AES NAJA LE a INO INAM 1 INGLIS Sie LIIGaNL DO UNE Figure 25 Passive Analog Input Circuits Rev 0 Page 16 of 28 920 0660 07 LNOT did U71no ddg 7 TSA4N3NOOWOO 17 SITI 1238800 SHXIOH 301d 380 SIRI 393Hl ING 442961 SIN3NOdHOD 5 SIMWAN 15384059 341d 333 3 3OU d 344 SOR 363H1 a AJ ING d p mos usaa STba a 5 a USITTEZSTTY Gey ING 2 A anov ING N1 134d 2025704 E ny 38 r30 LYOddNS NS FE
12. WARRANTY OF MERCHANTABILITY TITLE FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL SPECIAL INDIRECT OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER S POSSESSION OR USE OF THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO LOST PROFITS DELAY COSTS LABOR COSTS OR LOSS OF GOODWILL ADI S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS 100 00 EXPORT Customer agrees that it will not directly or indirectly export the Evaluation Board to another country and that it will comply with all applicable United States federal laws and regulations relating to exports GOVERNING LAW This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts excluding conflict of law rules Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County Massachusetts and Customer hereby submits to the personal jurisdiction and venue of such courts The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed ANALOG DEVICES Rev 0 Page 28 of 28 2011 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners UG09940 0 11 11 0 www analog com
13. configured into two must be clicked under the MISC EXTRA 5A section The different modes The default mode utilizes a 95 MHz FIR second mode uses a 100 MHz FIR filter and a tunable filter and fixed frequency NCO The SPI controller settings frequency NCO see Figure 13 In this mode the High for this mode are shown in Figure 12 Under the MAIN 50 Latency NCO option under MISC EXTRA 5A must be section the Fir Low Latency Mode En checkbox must be clicked and the Fir Low Latency Mode En checkbox must selected and the Low Latency NCO Fs 4 Only option be cleared under the MAIN 50 section SPIController 10 72 3 USB Ezusb 0 CS 1 AD6649spi File Config Help E Global ADCBase 0 ADC A ADC B m m Sync on high level of sync pin v Bypass All Blocks and Output 9 Bit Data Datapath Gain oe 09940 012 4 21 2011 4 54 57 PM Figure 12 SPI Controller AD6649 ADC A Tab 95 MHz FIR Filter and Fixed Freguency NCO Mode Rev 0 Page 9 of 28 A sPiController 1 0 72 3 USB Ezusb 0 CS 1 AD6649spiR03 c File Config Help IBITTRESTEEESES Global ADCBase 0 ADC A Apc SUT PUT WO DET Reduce Output Gain by 50 Bypass All Blocks and Output 9 Bit Data 09940 013 4 21 2011 4 55 48 PM Figure 13 SPI Controller AD6649 ADC A Tab 95 MHz FIR Filter and Fixed Frequency NCO Mode E UR RUPEE cu CU agi 23 018 babe C3 1 kDa cq Abe AE ca S 09940 014 Figure 14
14. 404 C405 C406 C407 C408 C409 C411 C413 C414 C419 C501 C502 C504 C505 C506 C507 C517 C518 C519 C535 C536 C537 C538 C539 C540 C541 C542 C543 C544 C545 C546 C547 C548 C601 C604 C201 C232 C234 C236 C238 C240 C202 C203 C204 C206 C207 C209 C225 C227 C228 C230 C241 C243 C210 C211 C220 C221 C223 C224 C213 C214 C216 C215 C217 C218 C226 C229 C302 C308 C303 C304 C309 C310 C410 C412 C524 C525 C526 C527 C530 C534 C503 C508 C510 C511 C512 C513 C523 C532 C533 CR201 CR202 CR203 CR501 CR502 CR204 CR205 CR206 CR503 E201 E202 E204 E205 E207 E208 E209 E210 E211 E212 E213 E214 E215 E216 E217 E501 E502 F201 FL201 J101 J301 J303 J506 JP201 JP203 L401 L402 L407 L408 L501 L502 L503 L504 L505 L506 P101 P102 P103 P104 P105 P106 P107 P108 P109 P110 Printed circuit board AD9643 engineering board 0 1 uF capacitor ceramic X5R 0201 1 uF capacitor monolithic ceramic 0402 0 1 uF capacitor ceramic X7R 0402 10 pF capacitor tantalum 4 7 uF capacitor monolithic ceramic X5R 22 uF capacitor ceramic chip 2200 pF capacitor ceramic X7R 0402 100 pF capacitor chip mono ceramic COG 0402 1500 pF capacitor ceramic X7R 0402 0 01 pF capacitor ceramic X7R 0402 3 9 pF capacitor ceramic NPO 0402 8 2 pF capacitor ceramic NPO 0402 10 pF capacitor ceramic monolithic 0 33 uF capacitor ceramic X5R 0 001 UF capacit
15. 9 40 41 42 43 44 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 P201 P202 P203 P400 P601 P602 C528 R101 R217 R219 R401 R402 R439 R440 R441 R442 R506 R522 R523 R537 R606 R613 R616 R628 R201 R202 R409 R413 R416 R417 R418 R419 R420 R421 R422 R423 R424 R425 R509 R515 R516 R518 R519 R601 R609 R610 R615 R103 R203 R205 R222 R427 R428 R429 R430 R431 R432 R434 R445 R502 R603 R605 R626 R206 R319 R320 R339 R340 R207 R208 R602 R611 R612 R209 R210 R211 R212 R213 R214 R302 R303 R539 R540 R313 R314 R333 R334 R315 R316 R335 R336 R317 R318 R337 R338 R501 R503 R505 R604 R510 R511 R524 R525 R526 R527 R531 R532 R535 R536 R544 R545 R546 R513 R514 T302 1303 1306 1307 1501 T503 U1010 U201 U202 U203 U204 U205 U206 U207 U300 U602 U601 C125 C126 C313 C314 C441 C442 C522 C529 C602 C603 C205 C208 C242 Connector PCB DC power jack SM Connector PCB header 6 position Connector PCB pluggable header Connector PCB BERG header ST male 3 pin Connector PCB 60 pin RA connector 0 O resistor film SMD 0402 261 resistor film chip thick 10 kO resistor PREC thick film chip RO402 1 91 resistor PREC thick film chip R0402 1 00 kQ resistor PREC thick film chip R0402 10 Q resistor PREC thick film chip R0402
16. 9 and AD6643 evaluation board which provides all of the support circuitry required to operate the AD9643 AD9613 AD6649 and AD6643 in their various modes and configurations The application software used to interface with the devices is also described The AD9643 AD9613 AD6649 and AD6643 data sheets provide additional information and should be consulted when using the evaluation board All documents and software tools are available at http www analog com fifo For additional information or questions send an email to highspeed converters analog com TYPICAL MEASUREMENT SETUP 09940 001 Figure 1 AD9643 AD9613 AD6649 or AD6643 Family Evaluation Board and HSC ADC EVALCZ Data Capture Board PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS Rev 0 Page 1 of 28 TABLE OF CONTENTS AA Pduiptient Needed a ag aaa QU Software Needed ata ena General DescrIDUOD akasa aaa ANE ro Typical Measurement Setup quse p A UNE RevisioD EHSEOEY extis gada aa ase a a ga vua paka aga Evaluation Board Hardware agagah Pa agi aa akak a Power Supplies a Gana ka Input Sietiales Go oot stp e ana gan is inang a nia da ng aga ANA REVISION HISTORY 11 11 Revision 0 Initial Version OWE sio al Ss 4 Default Operation and Jumper Selection Settings 4 Evaluation Board Software Quick Start Procedures
17. ADC power source is more efficient than using the default LDOs Rev 0 Page 5 of 28 EVALUATION BOARD SOFTWARE QUICK START PROCEDURES This section provides quick start procedures for using the AD9643 AD9613 AD6649 AD6643 evaluation board Both the default and optional settings are described CONFIGURING THE BOARD Before using the software for testing configure the evaluation board as follows 1 Connect the evaluation board to the data capture board as shown in Figure 1 and Figure 2 Connect one 6 V 2 5 A switching power supply such as the CUI Inc EPS060250UH PHP SZ that is supplied to the AD9643 AD9613 AD6649 AD6643 board Connect another 6 V 2 5 A switching power supply such as the CUI EPS060250UH PHP SZ that is supplied to the HSC ADC EVALCZ board Connect the HSC ADC EVALCZ board J6 to the PC with a USB cable On the ADC evaluation board confirm that jumpers are installed on the P105 P108 P104 P107 P110 and P103 headers Connect a low jitter sample clock to Connector J506 Use a clean signal generator with low phase noise to provide an input signal to the desired channel s at Connector J301 Channel A and or Connector J303 Channel B Use a 1 m shielded RG 58 50 Q coaxial cable to connect the signal generator For best results use a narrow band band pass filter with 50 O terminations and an appropriate center frequency Analog Devices uses TTE Allen Avionics and K amp L band pass filter
18. ADG734BRUZ Epson Toyocom TCO 2111 RELATED LINKS Resource AD6643 AD6649 AD9613 AD9643 ADP2114 AD9523 ADG734 AN 878 AN 877 AN 835 AN 905 Description Product Page 14 Bit 170 210 250 MSPS 1 8 V Dual Analog to Digital Converter ADC Product Page IF Diversity Receiver Product Page 12 bit 170 210 250 MSPS 1 8 V Dual Analog to Digital Converter ADC Product Page 14 Bit 170 210 250 MSPS 1 8 V Dual Analog to Digital Converter ADC Product Page Configurable Dual 2 A Single 4 A Synchronous Step Down DC to DC Regulator Product Page 14 Output Low Jitter Clock generator Product Page CMOS 2 5 O Low Voltage Quad SPDT Switch Application Note High Speed ADC SPI Control Software Application Note Interfacing to High Speed ADCs via SPI Application Note Understanding ADC Testing and Evaluation Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual Rev 0 Page 27 of 28 NOTES A ESD Caution ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Legal Terms and Conditions By using the evaluation board discussed herein together with any tools components documentation or support mater
19. ANALOG DEVICES Evaluation Board User Guide UG 293 One Technology Way P O Box 9106 e Norwood MA 02062 9106 U S A Tel 781 329 4700 Fax 781 461 3113 e www analog com Evaluating the AD9643 AD9613 AD6649 AD6643 Analog to Digital Converters FEATURES Full featured evaluation board for the AD9643 AD9613 AD6649 AD6643 SPI interface for setup and control External or AD9523 clocking option Balun transformer or amplifier input drive options LDO regulator power supply VisualAnalog and SPI controller software interfaces EQUIPMENT NEEDED Analog signal source and antialiasing filter Sample clock source if not using the on board oscillator 2 switching power supplies 6 0 V 2 5 A CUI EPS060250UH PHP SZ provided PC running Windows 98 2nd ed Windows 2000 Windows ME or Windows XP USB 2 0 port recommended USB 1 1 compatible AD9643 AD9613 AD6649 or AD6643 evaluation board HSC ADC EVALCZ FPGA based data capture kit SOFTWARE NEEDED VisualAnalog SPI controller DOCUMENTS NEEDED AD9643 AD9613 AD6649 or AD6643 data sheet HSC ADC EVALCZ data sheet AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual AN 878 Application Note High Speed ADC SPI Control Software AN 877 Application Note Interfacing to High Speed ADCs via SPI AN 835 Application Note Understanding ADC Testing and Evaluation GENERAL DESCRIPTION This user guide describes the AD9643 AD9613 AD664
20. D9523 must be configured through the SPI controller software to set up the PLL and other operation modes Consult the AD9523 data sheet for more information about these and other options PDWN To enable the power down feature add a shorting jumper across P101 at Pin 1 and Pin 2 to connect the PDWN pin to AVDD OEB To disable the digital output pins and place them in a high imped ance state add a shorting jumper across P102 at Pin 1 and Pin 2 to connect the OEB pin to AVDD 8 2pF W AD9643 AD9613 AD6649 AD6643 8 2pF 09940 003 Y Figure 3 Default Analog Input Configuration of the AD9643 AD9613 AD6649 AD6643 Rev 0 Page 4 of 28 Switching Power Supply Optionally the ADC on the board can be configured to use the ADP2114 dual switching power supply to provide power to the DRVDD and AVDD rails of the ADC To configure the board to operate from the ADP2114 the following changes must be incorporated see the Evaluation Board Schematics and Artwork and the Bill of Materials sections for specific recommendations for part values 1 Install R204 and R221 to enable the ADP2114 2 Install R216 and R218 3 Install L201 and L202 Remove JP201 and JP203 5 Remove jumpers from across Pin 1 and Pin 2 on P107 and P108 respectively 6 Place jumpers across Pin 1 and Pin 2 of P106 and P109 respectively Making these changes enables the switching converter to power the ADC Using the switching converter as the
21. DC EVALCZ for data capture The output signals from Channel A and Channel B for the AD9643 AD9613 AD6649 and AD6643 are routed through P601 and P602 respectively to the FPGA on the data capture board DEFAULT OPERATION AND JUMPER SELECTION SETTINGS This section explains the default and optional settings or modes allowed on the AD9643 AD9613 AD6649 AD6643 evaluation board Power Circuitry Connect the switching power supply that is supplied in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P201 Analog Input The A and B channel inputs on the evaluation board are set up for a double balun coupled analog input with a 50 O impedance This input network is optimized to support a wide frequency band See the AD9643 AD9613 AD6649 and AD6643 data sheets for addi tional information on the recommended networks for different input frequency ranges The nominal input drive level is 10 dBm to achieve 2 V p p full scale into 50 O At higher input frequencies slightly higher input drive levels are required due to losses in the front end network Optionally Channel A and Channel B inputs on the board can be configured to use the ADL5202 digitally controlled variable gain wide bandwidth amplifier The ADL5202 component is included on the evaluation board at U401 However the path into 0 1 2V p p and out of the ADL5202 can be configured in many different ways depending on the applicatio
22. VALCZ board e Make sure the FPGA has been programmed by verifying that the DONE LED is illuminated on the HSC ADC EVALCZ board If this LED is not illuminated make sure the U4 switch on the board is in the correct position for USB CONFIG e Make sure the correct FPGA program was installed by clicking the Settings button in the ADC Data Capture block in VisualAnalog Then select the FPGA tab and verify that the proper FPGA bin file is selected for the part ATL HAT Huit eg 1 fx eral a uw ma mar mg pum ren 177 09940 022 If VisualAnalog indicates that the data capture timed out do the Figure 22 Graph Window of VisualAnalog NSR Enabled AD6643 following 9 The amplitude shows approximately 0 6 dB lower than e Make sure that all power and USB connections are secure WBed ek ee e Probe the DCO signal at the ADC on the evaluation board this loss An amplitude of 1 6 dBFS with NSR enabled and confirm that a clock signal is present at the ADC is analogous to an amplitude of 1 0 dBFS with NSR disabled 10 Repeat Step 3 to save the graph in a csv file format sampling rate Rev 0 Page 13 of 28 EVALUATION BOARD SCHEMATICS AND ARTWORK 20 07660 NT STI2 ANT TETI TW3 1S X d f UWS D U C 800 U 59 14 95 Vle Sbb X OL S D O0 NI Ta EE J d ve ST i TTO SE
23. c ERJ 2RFK15ROX Panasonic ERJ 2RKF49R9X Panasonic ERJ 1GEF1000C Panasonic ERJ 2RKF2000X M A COM ETC1 1 13 Analog Devices AD6649BCPZ or AD9643BCPZ Analog Devices ADP1708ARDZ R7 Analog Devices ADP150AUJZ 3 3 R7 Analog Devices ADP1706ARDZ 1 8 R7 Analog Devices ADP2114ACPZ Analog Devices ADP150AUJZ 1 8 R7 Fairchild NC7WZ16P6X Fairchild NC7WZ07P6X Murata GRM155R60J105KE19D Murata GRM155R71C104KA88D Murata GRM155R71H103KA01D Item Reference Designator Manufacturer Part No TBD C0603 1200 pF capacitor ceramic X7R 0402 2 7 pF capacitor ceramic 22 pF capacitor ceramic 68 69 70 ZI 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 1 Do not install C219 C222 C415 C416 C421 C422 C417 C423 C418 C424 C509 C531 E203 E206 1403 1404 J502 1503 1505 L201 L202 L403 L404 L405 L406 L409 L410 L411 L412 L507 R102 R104 R107 R108 R517 R627 R629 R105 R301 D55R321 R437 R438 R520 R521 R529 R530 R106 R109 R110 R111 R112 R204 R216 R218 R221 R311 R312 R331 R332 R403 R404 R406 R407 R410 R411 R414 R415 R508 R533 R534 R538 R541 R542 R608 R630 R631 R632 R215 R220 R405 R408 R412 R426 R443 R444 R433 R446 R507 R512 R633 R634 R635 R636 R637 R638 R639 R640 R641 R642 R643 R644 R645 R646 R647 R648 R649 R650 R543 T301 1305 502
24. cted to the computer Also make sure the dipswitch U4 on the HSC ADC EVALC is set to the following configuration MO ON M1 OFF M2 OFF If the configuration is successful you will see the DONE light Do not show this message again 09940 005 Figure 5 VisualAnalog Default Configuration Message To change features to settings other than the default settings click the Expand Display button located on the bottom right corner of the window to see what is shown in Figure 7 Detailed instructions for changing the features and capture settings can be found in the AN 905 Application Note VisualAnalog Converter Evaluation Tool Version 1 0 User Manual After the changes are made to the capture settings click the Collapse Display button see Figure 6 gt VisualAnalog Canvas AD9643 Average FFT Ele Edit View Ex alb amp 20908 avras FT Rev 0 Page 6 of 28 Canvas Tool Window Help 09940 006 Figure 6 VisualAnalog Window Toolbar Collapsed Display D vang me EE ek File Edit View Canvas Tools Window Help la Hp lt ADI Average FFT o S ADC Data Formatter Window Routine Board Interfaces 0 eB ADC Data Capture z ate Window Blackman Hanis NL EB FIFO4x Interface kai DEBUG ONLY Window Routine Setting Up the SPI Controller Software After the ADC data capture board setup is complete set up the SPI cont
25. es a 6 V 2 A maximum output Connect the supply to a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz The output from the supply is provided through a 2 1 mm inner diameter jack that connects to the printed circuit board PCB at P201 The 6 V supply is fused and conditioned on the PCB before connecting to the low dropout linear regulators default configuration that supply the proper bias to each of the various sections on the board WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz SWITCHING POWER SUPPLY SWITCHING POWER SUPPLY SIGNAL SYNTHESIZER SIGNAL SYNTHESIZER ANALOG INPUT NE im m OPTIONAL CLOCK SOURCE The evaluation board can be powered in a nondefault condition using external bench power supplies To do this remove the jumpers on the P103 P104 P107 P108 and P105 header pins to disconnect the outputs from the on board LDOs This enables the user to bias each section of the board individually Use P202 and P203 to connect a different supply for each section A 1 8 V supply is needed with a 1 A current capability for DUT_AVDD and DRVDD however it is recommended that separate supplies be used for both analog and digital domains An additional supply is also required to supply 1 8 V for digital support circuitry on the board DVDD This should also have a 1 A current capability and can be combined with DRVDD with little or no degradation in performance To operate the evaluatio
26. ials the Evaluation Board you are agreeing to be bound by the terms and conditions set forth below Agreement unless you have purchased the Evaluation Board in which case the Analog Devices Standard Terms and Conditions of Sale shall govern Do not use the Evaluation Board until you have read and agreed to the Agreement Your use of the Evaluation Board shall signify your acceptance of the Agreement This Agreement is made by and between you Customer and Analog Devices Inc ADI with its principal place of business at One Technology Way Norwood MA 02062 USA Subject to the terms and conditions of the Agreement ADI hereby grants to Customer a free limited personal temporary non exclusive non sublicensable non transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above and agrees not to use the Evaluation Board for any other purpose Furthermore the license granted is expressly made subject to the following additional limitations Customer shall not i rent lease display sell transfer assign sublicense or distribute the Evaluation Board and ii permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Custome
27. ile format 6 If operating the AD6643 with NSR enabled certain options in VisualAnalog must be enabled Click the button circled in the FFT Analysis box see Figure 20 in VisualAnalog to bring up the options for setting the NSR 09940 018 Figure 18 Visual Graph Window of VisualAnalog AD6649 95 MHz FIR Filter and Fixed Frequency NCO Mode lola X gt VisualAnalog Canvas AD6643 Average FF File Edit View Canvas Tools Window Help d Board Interfaces A bwal ADC Data Capture fer Data Router Window Routine FFT Average FFT Analysis TES Zo 0 4l FIFO4 x Interface Ej m DEBUG ONLY Window Blackman Hanis ES 1of5 FFT Analysis Window Routine Window Blackman Haris Average ES 1of5 m kudhi Complex Waveform Merger 41 Complex Waveform Splitter E Data Router fj DNL INL Analysis NE poula 35M 19M 285M 38M 475M 57M 665M 76M 855M 35M al Histogram Analysis inf Ivs Q b Inverse FFT Logic Analysis j ka 9 Mixer BY Power Phase o4 Resampler _ vx Resolution Formatter lf Scalar Math ay ff Waveform Analysis e TL Window Routine Pattem Saver E Sources 3643 Average FFT 4 22 2011 1 59 34 PM HE tW Gaussian Noise m Pattem Loader 4 m H Ready 09940 020 Figure 20 VisualAnalog Main Window Sh
28. n therefore the parts in the input and output path are left unpopulated Users should see the ADL5202 data sheet for additional information on this part and for configuring the inputs and outputs The ADL5202 by default is held in power down mode but can be enabled by adding 1 resistors at R427 and R428 to enable Channel A and Channel B respectively Clock Circuitry The default clock input circuit that is populated on the AD9643 AD9613 AD6649 AD6643 evaluation board uses a simple transformer coupled circuit with a high bandwidth 1 1 impedance ratio transformer T503 that adds a very low amount of jitter to the clock path The clock input is 50 terminated and ac coupled to handle single ended sine wave types of inputs The transformer converts the single ended input to a differential signal that is clipped by CR503 before entering the ADC clock inputs The board is set by default to use an external clock generator An external clock source capable of driving a 50 O terminated input should be connected to J506 A differential LVPECL clock driver output can also be used to clock the ADC input using the AD9523 U501 To place the AD9523 into the clock path populate R541 and R542 with 0 Q resistors and remove C532 and C533 to disconnect the default clock path inputs In addition populate R533 and R534 with 0 resistors remove R522 and R523 to disconnect the default clock path outputs and insert AD9523 LVPECL Output 2 The A
29. n board using the SPI and alternate clock options a separate 3 3 V analog supply is needed in addition to the other supplies This 3 3 V supply or 3P3V_ANALOG should have a 1 A current capability This 3 3 V supply is also used to support the optional input path amplifier ADL5202 on Channel A and Channel B INPUT SIGNALS When connecting the clock and analog source use clean signal generators with low phase noise such as the Rohde amp Schwarz SMA or HP 8644B signal generators or an equivalent Use a 1 m shielded RG 58 50 O coaxial cable for connecting to the evalua tion board Enter the desired frequency and amplitude see the Specifications section in the data sheet of the respective part RUNNING ADC ANALYZER OR VISUAL ANALOG USER SOFTWARE 09940 002 Figure 2 Evaluation Board Connection Rev 0 Page 3 of 28 When connecting the analog input source use ofa multipole narrow band band pass filter with 50 0 terminations is recom mended Analog Devices Inc uses TTE and K amp L Microwave Inc band pass filters The filters should be connected directly to the evaluation board If an external clock source is used it should also be supplied with a clean signal generator as previously specified Typically most Analog Devices evaluation boards can accept 2 8 V p p or 13 dBm sine wave input for the clock OUTPUT SIGNALS The default setup uses the Analog Devices high speed converter evaluation platform HSC A
30. or ceramic monolithic 0 47 uF capacitor chip ceramic X7R 0603 390 pF capacitor chip monolithic ceramic COG 0402 Diode rectifier GPP SMD Diode Schottky 3 amp rectifier LED green surface mount Diode recovery rectifier Diode Schottky dual series 100 MHZ inductor ferrite bead 45 chip bead core 1 1 A fuse poly switch PTC device 1812 Filter noise suppression LC combined type Connector PCB SMA ST edge mount 0 resistor jumper SMD 0805 SHRT 1 uH inductor SM 1 uH inductor SMT power Connector PCB header 2 position Rev 0 Page 24 of 28 9643EE01 Murata GRM033R60J104KE19D Murata GRM155R60J105KE19D Murata GRM155R71C104KA88D AVX TAJA106KO10RNJ Murata GRM188R60J475KE19 Murata GRM21BR60J226ME39L Phycomp Yageo CC0402KRX7R9BB222 Murata GRM1555C1H101JDO1D Murata GRM155R71H152KA01D Murata GRM155R71H103KA01D Murata GRM1555C1H3R9CZ01D YAGEO 0402CG829D9B200 Murata GRM21BR61C106KE15L Murata GRM155R61A334KE15D Murata GRM155R71H102KA01D Murata GCM188R71C474KA55D Murata GRM1555C1H391JA01D Diode Inc S1AB 13 MCC SK33A TP Panasonic LNJ314G8TRA Micro Commercial Components CORP S2A TP Avago HSMS 2812BLK Panasonic EXC ML20A390U Panasonic EXCCL3225U1 Tyco Electronics NANOSMDC110F 2 Murata BNX016 01 Samtec SMA J P X ST EM1 Panasonic ERJ 6GEYJO O Coilcraft 0603LS 102XGLB Coilcraft ME3220 102MLB Samtec TSW 102 08 G S Item Reference Designator Manufacturer Part No 33 34 35 36 3 38 3
31. owing FFT Analysis for AD6643 Rev 0 Page 12 of 28 7 Configure the settings in the FFT analysis to match the Troubleshooting Tips settings selected for the NSR in the SPI controller see If the FFT plot appears abnormal do the following PD A e Ifyou see a normal noise floor when you disconnect the B m ee EN ES signal generator from the analog input be sure you are not Tm karanan aa overdriving the ADC Reduce the input level if necessary TT izo ladne 7 SFOR e In VisualAnalog click the Settings button in the Input ae eee Formatter block see Figure 7 Check that Number Format in the settings of the Input Formatter block is set to the correct encoding offset binary by default Repeat 106643 NSR Sein for the other channel RE If the FFT appears normal but the performance is poor check the following e Make sure an appropriate filter is used on the analog input e Make sure the signal generators for the clock and the analog input are clean low phase noise 09940 021 lt e Change the analog input frequency slightly if noncoherent Figure 21 VisualAnalog FFT Analysis Settings for AD6643 sampling is being used 8 The result should show an FFT plot that looks similar to e Make sure the SPI configuration file matches the product Figure 22 being evaluated If the FFT window remains blank after Run is clicked do the following e Make sure the evaluation board is securely connected to the HSC ADC E
32. r all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material content of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agrees to return to ADI the Evaluation Board at that time LIMITATION OF LIABILITY THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED AS IS AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS ENDORSEMENTS GUARANTEES OR WARRANTIES EXPRESS OR IMPLIED RELATED TO THE EVALUATION BOARD INCLUDING BUT NOT LIMITED TO THE IMPLIED
33. roller software using the following procedure 1 Open the SPI controller software by going to the Start menu or by double clicking the SPIController software desktop icon If prompted for a configuration file select the appropriate one If not check the title bar of the window to determine which configuration is loaded If necessary choose Cfg Open from the File menu and select the appropriate file based on your part type Note that the CHIP ID 1 field should be filled to indicate whether the correct SPI controller configuration file is loaded see Figure 8 JA ee 11 MM Figure 8 SPI Controller CHIP ID 1 Section Rev 0 Page 7 of 28 09940 007 09940 008 2 Click the New DUT button in the SPIController window 5 Note that other settings can be changed on the ADCBase 0 tab see Figure 11 and the ADC A and ADC B tabs see Figure 10 to set up the part in the desired mode The settings on the ADCBase 0 tab affect the entire part whereas the settings on the ADC A and ADC pages affect the selected channel only See the appropriate part data sheet the AN 878 Application Note High Speed ADC SPI Control Software and the AN 877 Application Note Interfacing to High Speed ADCs via SPI for additional information on the available settings LA imm 3 3681 USA n CE Lane capo x Fic 77 RH 0 DUAE ee I a RC A 1 09940 009 moo Em coco One T a ieu ADC Dig Chigi Fase Long m
34. s USING THE SOFTWARE FOR TESTING Setting Up the ADC Data Capture After configuring the board set up the ADC data capture using the following steps 1 Open VisualAnalog on the connected PC The appro priate part type should be listed in the status bar of the VisualAnalog New Canvas window Select the template that corresponds to the type of testing to be performed see Figure 4 where the AD9643 is shown as an example The AD9643 is given as an example in this user guide Similar settings are used for the AD9613 For the AD6649 and AD6643 the differences are noted where necessary in the steps that follow VisualAnalog New Canvas Categories New Existing Recent Templates 2 LO AD9238 C AD9248 AD9251 C AD9258 CJ AD9258 12 CJ AD9262 DL C AD9267 E Logic CJ AD9268 DL D L D L by 5 Two Tone Average Two Tone 09940 004 Figure 4 VisualAnalog New Canvas Window After the template is selected a message appears asking if the default configuration can be used to program the FPGA see Figure 5 Click Yes and the window closes VisualAnalog JJ Visual4nalog will now attempt to program the on board FPGA with a default file for the AD9643 Please click Yes to program the FPGA If you prefer to use the current FPGA configuration click No Before clicking Yes please make sure the HSC ADC EVALC is powered with the correct supply and that the board is conne

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