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ANALOG DEVICES AD8546/AD8548 handbook

1. 10 10 E Vey 27V E Vsy 18V a E 1 E 1 gt z amp o amp E 5 100m p 40 C 5 100m E 40 C a 25 C a 25 C e 85 C e 85 C B 125 C ad 125 C o 10m 5 10m Lu Lu z E H Im 5 1m o o gt gt 5 E a 0 1m 2 0 1m E E 2 2 o o 0 01m 2 0 01m 2 0 001 0 01 0 1 1 10 100 3 0 001 0 01 0 1 1 10 100 3 LOAD CURRENT mA 8 LOAD CURRENT mA 8 Figure 15 Output Voltage Von to Supply Rail vs Load Current Figure 18 Output Voltage Vo to Supply Rail vs Load Current 10 10 E Vsy 27V E Vsy 18V 1 go a a E 5 10om 40 C 5 100m E 40C o 25 C a 25 C e 85 C e 485 C A 125 C 3 125 C o 10m o 10m U U z q 5 1m 5 1m o o gt gt E E 2 0 1m 2 0 1m E E 2 2 o o 0 01m 0 01m 2 0 001 0 01 0 1 1 10 100 3 0 001 0 01 0 1 1 10 100 amp LOAD CURRENT mA 8 LOAD CURRENT mA 8 Figure 16 Output Voltage Va to Supply Rail vs Load Current Figure 19 Output
2. 1000 1000 Vsy 2 7V Vsy 18V lt x t Z gt gt gt 100 gt 100 E E o o z z U U a a UU U o o o o z z u 10 w 10 q q S 5 o o gt gt 1 5 1 i 10 100 1k 10k 100k IMs 10 100 1k 10k 100k IMs FREQUENCY Hz FREQUENCY Hz 8 Figure 51 Voltage Noise Density vs Frequency Figure 54 Voltage Noise Density vs Frequency Vsy 18V SL gt a a gt gt LL a af a uu Lu G o lt lt E E 1 E l o o gt gt TIME 2s DIV E TIME 2s DIV 8 Figure 52 0 1 Hz to 10 Hz Noise Figure 55 0 1 Hz to 10 Hz Noise 3 0 20 Vsy 2 7V Vsy 18V Vin 2 6V 18 Vin 17 9V 2 5 RL 1MO RL 1MO Ay 1 16 Ay z 41 20 EM g S 12 A 1 5 E 10 2 a a g E E 10 E ee 6 4 0 5 2 0 m 0 2 10 100 1k 10k 100k 1M 10 100 1k 10k 100k im Z FREQUENCY Hz FREQUENCY Hz 8 Figure 53 Output Swing vs Frequency Figure 56 Output Swing vs Frequency Rev B Page 15 of 24 AD8546 AD8548
3. 100 100 Vsy 2 7V Vgy 18V Vin 0 2V rms Vin 0 5V rms RL 1MQ RL IMQ Ay 1 Ay 1 10 10 z z 1 1 Q Q rI x H 0 1 0 1 0 01 5 0 01 2 10 100 1k 10k 100k 10 100 1k 10k 100k FREQUENCY Hz 8 FREQUENCY Hz 8 Figure 57 THD N vs Frequency Figure 59 THD N vs Frequency 0 b Vin 1V p p Vin 5V p p Vin 10V p p Vin 15V p p Vin 17V p p CHANNEL SEPARATION dB CHANNEL SEPARATION dB 10k 100k FREQUENCY Hz 09585 058 09585 061 FREQUENCY Hz Figure 58 Channel Separation vs Frequency Figure 60 Channel Separation vs Frequency Rev B Page 16 of 24 AD8546 AD8548 APPLICATIONS INFORMATION The AD8546 AD8548 are low input bias current micropower CMOS amplifiers that operate over a wide supply voltage range of 2 7 V to 18 V The AD8546 AD8548 also employ unique input and output stages to achieve rail to rail input and output ranges with very low supply current INPUT STAGE Figure 61 shows the simplified schematic of the AD8546 AD8548 The input stage comprises two differential transistor pairs
4. 0 03 06 09 12 15 18 21 24 27 2 0 3 6 9 12 15 18 2 Vem V E Vem V E Figure 9 Input Offset Voltage vs Common Mode Voltage Figure 12 Input Offset Voltage vs Common Mode Voltage 10000 Vey 27V 1000 100 lt lt amp a 2 o 10 1 let lle 0 1 o 25 50 75 100 125 5 25 50 75 100 125 TEMPERATURE C 8 TEMPERATURE C 8 Figure 10 Input Bias Current vs Temperature Figure 13 Input Bias Current vs Temperature 4 Vsy 18V 3 2 1 T T 0 m m E B 125 C 1 85 C 25 C 2 3 4 0 2 4 6 8 10 12 14 16 18 Vem V 0 03 06 09 12 15 18 21 24 27 Vem V Figure 11 Input Bias Current vs Common Mode Voltage Figure 14 Input Bias Current vs Common Mode Voltage 09585 014 09585 017 Rev B Page 8of 24 AD8546 AD8548
5. 50 25 0 25 50 75 100 125 TEMPERATURE C Figure 26 Supply Current per Amplifier vs Temperature 09585 029 AD8546 AD8548 60 135 60 135 Vsy 2 7V Vsy 18V PHASE RL 1MQ PHASE RL 1MO 40 an 90 40 90 a a Z 20 45 3 3 20 45 gt E o gt C S a GAIN a a a o0 o a a o o 2 9 D 9 GAIN E gt I z r H 20 45 wW 20 45 2 o o C 10pF C 10pF CL 100pF C 100pF 0 60 135 60 135 o 1k 10k 100k 1M 1k 10k 100k 1M 8 FREQUENCY Hz 8 FREQUENCY Hz 8 Figure 27 Open Loop Gain and Phase vs Frequency Figure 30 Open Loop Gain and Phase vs Frequency ao a J B z z lt q lt 5 o a n fe fe s s 7 q a a U U o o fe le d d o o FREQUENCY Hz 3 FREQUENCY Hz 8 Figure 28
6. Package Type 9 9 Unit 8 Lead MSOP RM 8 142 45 C W 14 Lead SOIC_N R 14 115 36 C W ESD CAUTION 1 The input pins have clamp diodes to the power supply pins Limit the input current to 10 mA or less whenever input signals exceed the power supply rail by 0 3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability A AT ESD electrostatic discharge sensitive device Charged devices and circuit boards can discharge without detection Although this product features patented or proprietary protection circuitry damage may occur on devices subjected to high energy ESD Therefore proper ESD precautions should be taken to avoid performance degradation or loss of functionality Rev B Page 6 of 24 AD8546 AD8548 TYPICAL PERFORMANCE CHARACTERISTICS T 25 C unless otherwise noted 40 35 30 25 20 15 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 10 0 No vogo Ra III I 1 2
7. 09585 070 Rev B Page 19 of 24 AD8546 AD8548 Note that 100 kO resistors are used in series with the input of the op amp If smaller resistor values are used the supply current of the system increases much more For more information about using op amps as comparators see the AN 849 Application Note Using Op Amps as Comparators 4 mA TO 20 mA PROCESS CONTROL CURRENT LOOP TRANSMITTER A 2 wire current transmitter is often used in distributed control systems and process control applications to transmit analog signals between sensors and process controllers Figure 70 shows a 4 mA to 20 mA current loop transmitter ADR125 NOTES 1 R1 R2 R 09585 072 Figure 70 4 mA to 20 mA Current Loop Transmitter The transmitter is powered directly from the control loop power supply and the current in the loop carries signal from 4 mA to 20 mA Thus 4 mA establishes the baseline current budget within which the circuit must operate The AD8546 is an excellent choice due to its low supply current of 33 uA per amplifier over temperature and supply voltage The current transmitter controls the current flowing in the loop where a zero scale input signal is represented by 4 mA of current and a full scale input signal is represented by 20 mA The transmitter also floats from the control loop power supply V pp whereas signal ground is in the receiver The loop current is measured at the load resistor R at the receiver side With
8. Figure 45 Negative Overload Recovery a gt E e e 2 Lu G lt E ET o gt TIME 10ps DIV Figure 46 Positive Settling Time to 0 1 a gt E e e 19 uu o lt E a o gt TIME 10ps DIV Figure 47 Negative Settling Time to 0 1 S 5 w 2 d E E o E gt 2 E E P 5 Z o E E 8 E a a gt E e e L W o lt E o gt 09585 046 VOLTAGE 500mV DIV 09585 050 Rev B Page 14 of 24 I Vey 29V 2 Ay 10 RL 1MQ 1 INPUT 0 OUTPUT 0 5 10 TIME 40ps DIV Figure 48 Negative Overload Recovery INPUT Vsy 18V RL 100kQ C 10pF I ROY NE E dr nnne nnnm 5m V 0 ERROR BAND OUTPUT rM Q 5mV TIME 10ps DIV Figure 49 Positive Settling Time to 0 1 TIME 10ps DIV Figure 50 Negative Settling Time to 0 196 OUTPUT VOLTAGE V 09585 049 09585 053 09585 048 AD8546 AD8548
9. an NMOS pair M1 M2 and a PMOS pair M3 M4 The input common mode voltage determines which differential pair turns on and is more active than the other The PMOS differential pair is active when the input voltage approaches and reaches the lower supply rail The NMOS differ ential pair is needed for input voltages up to and including the upper supply rail This topology allows the amplifier to maintain a wide dynamic input voltage range and maximize signal swing to both supply rails For the greater part of the input common mode voltage range the PMOS differential pair is active Differential pairs commonly exhibit different offset voltages The handoff from one pair to the other creates a step like char acteristic that is visible in the Vos vs Vy graphs see Figure 5 and Figure 8 This characteristic is inherent in all rail to rail amplifiers that use the dual differential pair topology Therefore always choose a common mode voltage that does not include the region of handoff from one input differential pair to the other Additional steps in the Vos vs Vem graphs are also visible as the input common mode voltage approaches the power supply rails These changes are a result of the load transistors M8 M9 M14 and M15 running out of headroom As the load transistors are forced into the triode region of operation the mismatch of their drain impedances contributes to the offset voltage of the ampli fier This problem is exace
10. Closed Loop Gain vs Frequency Figure 31 Closed Loop Gain vs Frequency 1000 1000 Ay 100 Ay 100 Ay 10 Ay 10 100 100 L Ay 1 m Ay 1 a a 5 5 o o N N 10 10 Vsy 27V Vsy 18V 1 a 1 100 1k 10k 100k 3 100 1k 10k 100k 3 FREQUENCY Hz 3 FREQUENCY Hz 8 Figure 29 Output Impedance vs Frequency Figure 32 Output Impedance vs Frequency Rev B Page 11 of 24 AD8546 AD8548 14 Vsy 2 7V P Vem Vsy 2 Vsy 18V 120 120 Vom Vsy 2 100 100 2 80 9 80 tc tc E z 8 8 60 40 40 20 20 0 x 0 9 100 1k 10k 100k IM 100 1k 10k 100k 1M FREQUENCY Hz 8 FREQUENCY Hz E Figure 33 CMRR vs Frequency Figure 36 CMRR vs Frequency 100 100 Vey 2 7V 80 80 a 60 a 60 B 2 tc tc E PSRR t 40 PSRR oe odo 20 20 0 x 0 5 100 1k 10k 100k 1M 100 1k 10k 100k 1M 3 FREQUENCY Hz 3 FREQUENCY Hz 8 Figure 34 PSRR vs Frequency Figure 37 PSRR vs Frequency E g E o o o o I rI
11. Configuration Figure 64 shows the AD8546 AD8548 in a noninverting config uration with a resistive load R at the output The actual load seen by the amplifier is the parallel combination of R1 R2 and R Vsy RL err RL R1 R2 09585 065 Figure 64 Noninverting Op Amp Configuration Rev B Page 18 of 24 AD8546 AD8548 COMPARATOR OPERATION An op amp is designed to operate in a closed loop configuration with feedback from its output to its inverting input Figure 65 shows the AD8546 configured as a voltage follower with an input voltage that is always kept at the midpoint of the power supplies The same configuration is applied to the unused channel A1 and A2 indicate the placement of ammeters to measure supply current Isy refers to the current flowing from the upper supply rail to the op amp and Isy refers to the current flowing from the op amp to the lower supply rail Vsy 100kO 100kO 09585 066 Vsv Figure 65 Voltage Follower Configuration As expected Figure 66 shows that in normal operating condition the total current flowing into the op amp is equivalent to the total current flowing out of the op amp where Isy Isy 36 HA for the AD8546 at Vsy 18 V Isy PER DUAL AMPLIFIER uA 0 2 4 6 8 10 12 14 16 18 Vsy V Figure 66 Supply Current vs Supply Voltage Voltage Follower 09585 067 In contrast to op amps comparators ar
12. Dimensions shown in millimeters 8 75 0 3445 L 8 55 0 3366 4 14 8 4 00 0 1575 6 20 0 2441 3 80 0 1496 7 5 80 0 2283 L gt le ee 0 50 0 0197 po 1 75 0 0689 e 25 0 0098 0 25 0 0098 1 85 0 0531 8 0 10 0 0039 y A C COPLANARITY SEATING a 0 10 T PLANE 0 25 0 0098 1 27 0 0500 0 31 0 0122 0 17 0 0067 0 40 0 0157 COMPLIANT TO JEDEC STANDARDS MS 012 AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS INCH DIMENSIONS IN PARENTHESES ARE ROUNDED OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 72 14 Lead Standard Small Outline Package SOIC N Narrow Body R 14 Dimensions shown in millimeters and inches 060606 A ORDERING GUIDE Model Temperature Range Package Description Package Option Branding AD8546ARMZ 40 C to 125 C 8 Lead Mini Small Outline Package MSOP RM 8 A2V AD8546ARMZ RL 40 C to 125 C 8 Lead Mini Small Outline Package MSOP RM 8 A2V AD8546ARMZ R7 40 C to 125 C 8 Lead Mini Small Outline Package MSOP RM 8 A2V AD8548ARZ 40 C to 125 C 14 Lead Standard Small Outline Package SOIC_N R 14 AD8548ARZ RL 40 C to 125 C 14 Lead Standard Small Outline Package SOIC_N R 14 AD8548ARZ R7 40 C to 125 C 14 Lead Standard Small Outline Package SOIC_N R 14 Z RoHS Compliant Part Rev B Page 21 of 24 AD8546 AD8548 NOTES Rev B Page 22 of 24 AD
13. 14 The input devices are also protected from large differential input voltages by clamp diodes D1 and D2 These diodes are buffered from the inputs with two 10 kO resistors R1 and R2 The differential diodes turn on when the differential input voltage exceeds approximately 600 mV in this condition the differential input resistance drops to 20 kQ 09585 062 Figure 61 Simplified Schematic Rev B Page 17 of 24 AD8546 AD8548 OUTPUT STAGE The AD8546 AD8548 feature a complementary output stage consisting of the M16 and M17 transistors see Figure 61 These transistors are configured in a Class AB topology and are biased by the voltage source VB2 This topology allows the output voltage to go within millivolts of the supply rails achieving a rail to rail output swing The output voltage is limited by the output imped ance of the transistors which are low Roy MOS devices The output voltage swing is a function of the load current and can be estimated using the output voltage to supply rail vs load current graphs see Figure 15 Figure 16 Figure 18 and Figure 19 RAIL TO RAIL INPUT AND OUTPUT The AD8546 AD8548 feature rail to rail input and output with a supply voltage from 2 7 V to 18 V Figure 62 shows the input and output waveforms of the AD8546 AD8548 configured as a unity gain buffer with a supply voltage of 9 V and a resistive load of 1 MQ With an input voltage of 9 V the AD8546 AD8548 allow the output to
14. 48 TABLE OF CONTENTS Features futon 1 Applications ee d Ro eR 1 Pin Configurations eite tei oed 1 General Description 1 Revision History zsent a 2 Specifications sini 3 Electrical Characteristics 18 V Operation u n 3 Electrical Characteristics 10 V Operation nn 4 Electrical Characteristics 2 7 V Operation n 5 Absolute Maximum Ratings senes 6 Thermal Resistance rosiers ir ea a E RE 6 ESD Caution esseere ene tetetentnntet 6 REVISION HISTORY 4 12 Rev A to Rev B Added AD8548 and 14 Lead SOIC ss Universal Changes to Product Title Features Section General Description Section and Table 1 sss 1 Added Figure 2 Renumbered Figures Sequentially 1 Moved Electrical Characteristics 18 V Operation Section 3 Changes to Table 2 eratis veias erupit ek puo 3 Changes to Table 3 sss 4 Moved Electrical Characteristics 2 7 V Operation Section 5 Changes to Table 4 mariani 5 Charges to Table G tero tre eite ect 6 Changes to Figure 4 Figure 5 Figure 7 and Figure 8 7 Deleted Figure 8 and Figure LL 8 Typical Performance Characteristics sees 7 Applications Information eeeeeeeneneeteeenteennnnns 17 InputStage i enemies tees 17 Output Stage T 18 Rail to Rail Input and Output sse 18 Resistive Lo
15. 8546 AD8548 NOTES Rev B Page 23 of 24 AD8546 AD8548 NOTES 2011 2012 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners D09505 04 13B DEVICES www analog com Rev B Page 24 of 24
16. ANALOG DEVICES 22 uA RRIO CMOS 18 V Operational Amplifier AD8546 AD8548 FEATURES Micropower at high voltage 22 pA maximum Low input bias current 20 pA maximum Gain bandwidth product 240 kHz Slew rate 80 V ms Large signal voltage gain 110 dB minimum Single supply operation 2 7 V to 18V Dual supply operation 1 35 V to 9 V Unity gain stable APPLICATIONS Portable medical equipment Remote sensors Transimpedance amplifiers Current monitors 4 mA to 20 mA loop drivers Buffer level shifting GENERAL DESCRIPTION The AD8546 and AD8548 are dual and quad micropower high input impedance amplifiers optimized for low power and wide operating supply voltage range applications The AD8546 AD8548 rail to rail input output RRIO feature provides increased dynamic range to drive low frequency data converters making these amplifiers ideal for dc gain and buffering of sensor front ends or high impedance input sources used in wireless or remote sensors or transmitters The low supply current specification 22 uA of the AD8546 AD8548 over a wide operating voltage range of 2 7 V to 18 V or dual supplies 1 35 V to 9 V makes these amplifiers useful for a variety of battery powered portable applications such as ECGs pulse monitors glucose meters smoke and fire detectors vibration monitors and backup battery sensors The AD8546 AD8548 are specified over the extended industrial temperature range of 40 C to 125
17. C 10 pF Ay 1 60 Degrees Channel Separation cs f 10 kHz R 1 MQ 105 dB NOISE PERFORMANCE Voltage Noise e p p f 0 1 Hz to 10 Hz 5 uV p p Voltage Noise Density e f 1kHz 50 nV 4Hz f 10kHz 45 nV 4Hz Current Noise Density i f 1 kHz 0 1 pA VHZ Rev B Page 4 of 24 AD8546 AD8548 ELECTRICAL CHARACTERISTICS 2 7 V OPERATION Voy 2 7 V Vem Vyy 2 T 25 C unless otherwise noted Table 4 Parameter Symbol Test Conditions Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage Vos Vem OV to 2 7 V 3 mV Vey 0 3 V to 24 V 40 C lt T lt 4125 C 4 mV Vem OV to 2 7 V 40 C lt T lt 125 C 12 mV Offset Voltage Drift AVog AT 3 uV C Input Bias Current lg 1 10 pA 40 C lt T lt 125 C 2 6 nA Input Offset Current los 20 pA 40 C lt T lt 125 C 5 2 nA Input Voltage Range IVR 0 2 7 V Common Mode Rejection Ratio CMRR Vem OV to 2 7 V 60 75 dB Vey 0 3 V to 2 4 V 40 C lt T lt 125 C 58 dB Vem OV to 2 7 V 40 C lt T lt 125 C 49 dB Large Signal Voltage Gain Avo R 100 kO Vo 0 5 V to 2 2 V 97 115 dB 40 C lt T lt 125 C 90 dB Input Resistance Rn 10 GO Input Capacitance Differential Mode Com 3 5 pF Common Mode Cinci 3 5 pF OUTPUT CHARACTERISTICS Output Voltage High Vou R 100 KO to Vey 40 C lt T lt 125 C 2 69 V Output Voltage Low Vor R 100 KO to Vey 40 C lt T lt 125 C 10 mV Short Circuit Cu
18. C The AD8546 is available in an 8 lead MSOP package the AD8548 is available in a 14 lead SOIC N package Rev B Information fumished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights ofthird parties that may result fromits use Specifications subjectto change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners PIN CONFIGURATIONS TOP VIEW INA 3 Not to Scale H T t z w 09585 001 OUT A 1 14 OUT D INA 2 IND INA LS AD8548 v L3 top view 1 V IN B 5 Not to Scale JN C NB 6 INC OUT B s ouT C 3 Figure 2 AD8548 14 Lead SOIC N Table 1 Micropower Op Amps Supply Voltage Amplifier 5V 12V to 18V 36V Single AD8500 AD8663 AD8505 AD8541 AD8603 ADA4505 1 Dual AD8502 AD8546 OP295 AD8506 AD8657 ADA4062 2 AD8542 AD8667 AD8607 OP281 ADA4505 2 Quad AD8504 AD8548 OP495 AD8508 AD8669 ADA4062 4 AD8544 OP481 AD8609 ADA4505 4 1 See www analog com for the latest selection of micropower op amps One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 461 3113 2011 2012 Analog Devices Inc All rights reserved AD8546 AD85
19. ORE XD od eee CCC C Vos mV 333 e q I 2 2 x a I 09585 002 09585 105 Vos mV Figure 3 Input Offset Voltage Distribution Figure 6 Input Offset Voltage Distribution N e Vey 27V 40 C STA S 125 C Vey 18V 40 C lt T4 S 125 C eo e e eo D eo e NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS N eo o 0 0 05 10 15 20 25 30 35 40 45 50 55 60 TCVos 4V C 0 0 05 10 15 20 25 30 35 40 45 50 55 60 TCVos uV C 09585 004 09585 007 Figure 4 Input Offset Voltage Drift Distribution Figure 7 Input Offset Voltage Drift Distribution Vey 27V Vos mV o Vos mV 0 03 06 09 12 15 18 21 24 27 Vem V Figure 5 Input Offset Voltage vs Common Mode Voltage Figure 8 Input Offset Voltage vs Common Mode Voltage 09585 005 09585 008 Vem V Rev B Page 7 of 24 AD8546 AD8548 Vey 18V Vey 2 7V 40 C ST S 125 C 40 C S TA S 125 C Vos mV
20. Voltage Vo to Supply Rail vs Load Current 2 700 18 000 RL 1MO 2 699 _ 17 995 S I 5 Z uj 2 698 ul 17 990 g E S S o o gt 2697 17 985 2 R 100k0 A Ry 100k0 5 2 o o 2 696 17 980 Vsy 18V 2 695 E 17 975 50 25 0 25 50 75 100 1252 50 25 0 25 50 75 100 1255 TEMPERATURE C 8 TEMPERATURE C Figure 17 Output Voltage Von vs Temperature Figure 20 Output Voltage Vo vs Temperature Rev B Page 9 of 24 AD8546 AD8548 OUTPUT VOLTAGE Vo mV Isy PER AMP pA E 0 je pe do 50 25 0 25 50 75 100 125 TEMPERATURE C 09585 021 Figure 21 Output Voltage Vo vs Temperature 35 Vey 27V 30 25 20 15 10 5 40 C 25 C 85 C 0 125 C 0 0 3 0 6 0 9 1 2 1 5 1 8 2 1 24 2 7 Vem V 09585 123 Figure 22 Supply Current per Amplifier vs Common Mode Voltage Isy PER AMP uA 0 3 6 9 12 15 18 Vsy V Figure 23 Supply Current per Amplifier vs Supply Voltage 09585 026 OUTPUT VOLTAGE Vo mV Isy PER AMP pA 50 25 0 25 50 75 100 125 TEMPERATURE C Figure 24 Output Voltage Vo vs Temperature 0 3 6 9 12 15 18 Vem V 09585 024 09585 126 Figure 25 Supply Current per Amplifier vs Common Mode Voltage Isy PER AMP uA Rev B Page 10 of 24
21. a zero scale input a current of V per Ryun flows through R This creates a current Li that flows through the sense resistor as determined by the following equation Isense min Vuge X R Rui X Rsense With a full scale input voltage current flowing through R is increased by the full scale change in V y Rspyy This creates an increase in the current flowing through the sense resistor Tsense perra Full Scale Change in Vy x R Rspan X Rsense Therefore Isense MAX Isense MIN Tense DELTA When R gt gt Rs the current through the load resistor at the receiver side is almost equivalent to I Figure 70 shows a design for a full scale input voltage of 5 V At 0 V of input the loop current is 3 5 mA and at a full scale input of 5 V the loop current is 21 mA This allows software calibration to fine tune the current loop to the 4 mA to 20 mA range Together the AD8546 and the ADR125 consume quiescent current of only 160 uA making 3 34 mA current available to power additional signal conditioning circuitry or to power a bridge circuit Rev B Page 20 of 24 AD8546 AD8548 OUTLINE DIMENSIONS a 0 65 BSC 0 95 15 MAX 0 85 1 10 MAX LET ce Ot t wt 0 80 qs d 040 eT d on Loss 0 05 o 09 0 40 m a 0 40 COPLANARITY T 025 0 1 10 07 2009 B COMPLIANT TO JEDEC STANDARDS MO 187 AA Figure 71 8 Lead Mini Small Outline Package MSOP RM 8
22. ad eret eee mee 18 Comparator Operation iii 19 4 mA to 20 mA Process Control Current Loop Transmitter 20 Outline Dimensions eene 21 Ordering G id es i aN EEO au 21 Changes to Figure 9 Figure 10 Figure 12 and Figure 13 8 Changes to Figure 22 and Figure 25 Changes to Figure 33 Changes to Figure 63 and Figure 64 Updated Outline Dimensions essen Added Figure 72 o etin ette Changes to Ordering Guide sse 4 11 Rev 0 to Rev A Changes to Product Title Features Section Applications Section General Description Section and Table 1 1 1 11 Revision 0 Initial Version Rev B Page 2 of 24 AD8546 AD8548 SPECIFICATIONS ELECTRICAL CHARACTERISTICS 18 V OPERATION Vey 18 V Va Vsy 2 T 25 C unless otherwise noted Table 2 Parameter Symbol Test Conditions Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage Vos Vem 0V to 18V 3 mV Vem 0 3 V to 17 7 V 40 C lt T lt 125 C 7 mV Vem OV to 18V 40 C lt T lt 125 C 12 mV Offset Voltage Drift AVos AT 3 uV C Input Bias Current lg 5 20 pA 40 C lt T lt 125 C 2 6 nA Input Offset Current los 40 pA 40 C lt T lt 125 C 5 2 nA Input Voltage Range IVR 0 18 V Common Mode Rejection Ratio CMRR Vem 2 0Vto 18V 74 95 dB Vem 0 3 V to 17 7 V 40 C
23. e designed to work in an open loop configuration and to drive logic circuits Although op amps are different from comparators occasionally an unused section of a dual or quad op amp is used as a comparator to save board space and cost however this is not recommended Figure 67 and Figure 68 show the AD8546 configured as a com parator with 100 kQ resistors in series with the input pins The unused channel is configured as a buffer with the input voltage kept at the midpoint of the power supplies 09585 068 Vay Figure 67 Comparator Configuration A Vsy 100kQ 09585 069 Figure 68 Comparator Configuration B The AD8546 AD8548 have input devices that are protected from large differential input voltages by Diode D1 and Diode D2 see Figure 61 These diodes consist of substrate PNP bipolar transistors and turn on when the differential input voltage exceeds approximately 600 mV however these diodes also allow a current path from the input to the lower supply rail resulting in an increase in the total supply current of the system As shown in Figure 69 both configurations yield the same result At 18 V of power supply Isy remains at 36 pA per dual amplifier but Isy increases to 140 uA in magnitude per dual amplifier 160 140 120 100 Y 80 Isy PER DUAL AMPLIFIER uA 0 2 4 6 8 10 12 14 16 18 Vsy V Figure 69 Supply Current vs Supply Voltage AD8546 as a Comparator
24. lt T lt 125 C 68 dB Vey OV to 18V 40 C lt T lt 4125 C 65 dB Large Signal Voltage Gain Avo R 100 KQ V9 0 5 V to 17 5V 110 125 dB 40 C lt T lt 125 C 105 dB Input Resistance Rn 10 GO Input Capacitance Differential Mode Copy 3 5 pF Common Mode Cincm 10 5 pF OUTPUT CHARACTERISTICS Output Voltage High Vou R 100 KO to Vey 40 C lt T 125 C 17 97 V Output Voltage Low Vor R 100 KO to Vey 40 C lt T lt 125 C 30 mV Short Circuit Current lsc 12 mA Closed Loop Output Impedance Zour f 1 kHz A 1 15 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Vy 2 7 V to 18V 95 115 dB 40 C lt T lt 125 C 90 dB Supply Current per Amplifier lsy lo 0 mA 18 22 uA 40 C lt T lt 125 C 33 uA DYNAMIC PERFORMANCE Slew Rate SR R 1 MQ C 10 pF Ay 2 41 80 V ms Settling Time to 0 196 ts Vn 1 V step R 100 kQ C 10 pF 15 US Gain Bandwidth Product GBP R 1MQ C 10 pF Ay 1 240 kHz Phase Margin Oy R 1 MQ C 10 pF Ay 1 60 Degrees Channel Separation cs f 10 kHz R 1 MO 105 dB NOISE PERFORMANCE Voltage Noise e p p f 0 1 Hz to 10 Hz 5 uV p p Voltage Noise Density en f 1 kHz 50 nV VHz f 10 kHz 45 nV VHz Current Noise Density i f 1kHz 0 1 pA VHZ Rev B Page 3 of 24 AD8546 AD8548 ELECTRICAL CHARACTERISTICS 10 V OPERATION Voy 10 V Vem Vsy 2 T 25 C unless otherwise noted Table 3 Parameter Symbol Test Condi
25. o o tc tc ul ul 2 gt o o 0 o 0 x 10 100 1000 10 100 1000 Z CAPACITANCE pF 8 CAPACITANCE pF 8 Figure 35 Small Signal Overshoot vs Load Capacitance Figure 38 Small Signal Overshoot vs Load Capacitance Rev B Page 12 of 24 AD8546 AD8548 s a E 3 6 E 5 lt lt t a o o gt gt TIME 100ps DIV 8 TIME 1001s DIV E Figure 39 Large Signal Transient Response Figure 42 Large Signal Transient Response S L r r Vsy 1 35V Ay 1 RL 1MO C 100pF a a gt gt E E 2 2 Lu Lu o o lt lt E E al E o o gt gt 3 3 TIME 100ps DIV 8 TIME 1001s DIV E Figure 40 Small Signal Transient Response Figure 43 Small Signal Transient Response INPUT VOLTAGE V OUTPUT VOLTAGE V INPUT VOLTAGE V OUTPUT VOLTAGE V 09585 044 09585 047 TIME 40ps DIV TIME 40ps DIV Figure 41 Positive Overload Recovery Figure 44 Positive Overload Recovery Rev B Page 13 of 24 AD8546 AD8548 INPUT VOLTAGE V Vey 1 35V 0 4 Ay 10 BL IMQ 0 2 L INPUT 0 L OUTPUT 0 1 2 TIME 40ps DIV
26. rbated at high temperatures due to the decrease in the threshold voltage of the input transistors See Figure 9 and Figure 12 for typical performance data Current Source I1 drives the PMOS transistor pair As the input common mode voltage approaches the upper rail I1 is steered away from the PMOS differential pair through the M5 transistor The bias voltage VB1 controls the point where this transfer occurs M5 diverts the tail current into a current mirror consisting of the M6 and M7 transistors The output of the current mirror then drives the NMOS transistor pair Note that the activation of this current mirror causes a slight increase in supply current at high common mode voltages see Figure 22 and Figure 25 The AD8546 AD8548 achieve their high performance by using low voltage MOS devices for their differential inputs These low voltage MOS devices offer excellent noise and bandwidth per unit of current Each differential input pair is protected by proprietary regulation circuitry not shown in Figure 61 The regulation circuitry consists of a combination of active devices which main tain the proper voltages across the input pairs during normal operation and passive clamping devices which protect the amplifier during fast transients However these passive clamping devices begin to forward bias as the common mode voltage approaches either power supply rail This causes an increase in the input bias current see Figure 11 and Figure
27. rrent lsc 4 mA Closed Loop Output Impedance Zout f 1 kHz Ay 1 20 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Voy 2 7 V to 18V 95 115 dB 40 C lt T lt 125 C 90 dB Supply Current per Amplifier ley l 2 0mA 18 22 yA 40 C lt T lt 125 C 33 uA DYNAMIC PERFORMANCE Slew Rate SR R 1 MQ C 10 pF Ay 41 50 V ms Settling Time to 0 1 ts Vn 1V step R 100 kO C 10 pF 20 US Gain Bandwidth Product GBP R 1 MQ C 10 pF Ay 1 190 kHz Phase Margin Om R 1 MQ C 10 pF Ay 1 60 Degrees Channel Separation cs f 10 kHz R 1 MQ 105 dB NOISE PERFORMANCE Voltage Noise e p p f 0 1 Hz to 10 Hz 6 uV p p Voltage Noise Density e f 1kHz 60 nV 4Hz f 10kHz 56 nV VHz Current Noise Density i f 1 kHz 0 1 pA VHz Rev B Page 5 of 24 AD8546 AD8548 ABSOLUTE MAXIMUM RATINGS Table 5 Parameter Rating Supply Voltage 20 5V Input Voltage Input Current Differential Input Voltage Output Short Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature Soldering 60 sec V 300 mV to V 300 mV 10 mA TVs Indefinite 65 C to 150 C 40 C to 125 C 65 C to 150 C 300 C THERMAL RESISTANCE 0 is specified for the worst case conditions that is a device soldered in a circuit board for surface mount packages using a standard 4 layer board Table 6 Thermal Resistance
28. swing very close to both rails Additionally the AD8546 AD8548 do not exhibit phase reversal INPUT Ix OUTPUT T PS AMO VOLTAGE 5V DIV 09585 063 TIME 2001s DIV Figure 62 Rail to Rail Input and Output RESISTIVE LOAD The feedback resistor alters the load resistance that an amplifier sees Therefore it is important to carefully select the value of the feedback resistors used with the AD8546 AD8548 The amplifiers are capable of driving resistive loads down to 100 kQ The Inverting Op Amp Configuration section and the Noninverting Op Amp Configuration section show how the feedback resistor changes the actual load resistance seen at the output of the amplifier Inverting Op Amp Configuration Figure 63 shows the AD8546 AD8548 in an inverting config uration with a resistive load R at the output The actual load seen by the amplifier is the parallel combination of the feedback resistor R2 and the load R For example the combination of a feedback resistor of 1 KQ and a load of 1 MQ results in an equivalent load resistance of 999 Q at the output Because the AD8546 AD8548 are incapable of driving such a heavy load performance degrades greatly To avoid loading the output use a larger feedback resistor but consider the effect of resistor thermal noise on the overall circuit 09585 064 RL err RL R2 Figure 63 Inverting Op Amp Configuration Noninverting Op Amp
29. tions Comments Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage Vos Vom 2 0Vto 10V 3 mV Vey 0 3 V to 9 7 V 40 C lt T lt 4125 C 8 mV Vey OV to 10 V 40 C lt T lt 4125 C 12 mV Offset Voltage Drift AVog AT 3 uV C Input Bias Current lg 2 15 pA 40 C lt T lt 4125 C 2 6 nA Input Offset Current los 30 pA 40 C lt T lt 125 C 5 2 nA Input Voltage Range IVR 0 10 V Common Mode Rejection Ratio CMRR Vem 0Vto 10V 70 88 dB Vey 0 3V to 9 7 V 40 C T lt 125 C 62 dB Vem OV to 10 V 40 C lt T lt 125 C 60 dB Large Signal Voltage Gain Avo R 100 kQ Vo 0 5 V to 9 5 V 105 120 dB 40 C lt T lt 125 C 100 dB Input Resistance Rn 10 GO Input Capacitance Differential Mode Com 3 5 pF Common Mode Cinci 3 5 pF OUTPUT CHARACTERISTICS Output Voltage High Vou R 100 KO to Vey 40 C lt T lt 125 C 9 98 V Output Voltage Low Vor R 100 KO to Vey 40 C lt T lt 125 C 20 mV Short Circuit Current lsc 11 mA Closed Loop Output Impedance Zout f 1 kHz Ay 1 15 Q POWER SUPPLY Power Supply Rejection Ratio PSRR Voy 2 7 V to 18V 95 115 dB 40 C lt T lt 125 C 90 dB Supply Current per Amplifier ley l 2 0mA 18 22 yA 40 C lt T lt 125 C 33 uA DYNAMIC PERFORMANCE Slew Rate SR R 1 MQ C 10 pF A 2 41 75 V ms Settling Time to 0 1 ts Vn 1V step R 100 kO C 10 pF 15 us Gain Bandwidth Product GBP R 1 MQ C 10 pF Ay 2 1 235 kHz Phase Margin Om R 1 MQ

ANALOG DEVICES AD8546/AD8548 handbook

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