FAIRCHILD Design Guideline for Primary Side Regulated (PSR) Flyback Converter Using FAN103 FSEZ13X7 handbook
Contents
1. fs 50kHz fs 33kHz 0 75A lo Figure 6 Output Voltage and Current Operating Area STEP 1 Estimate the Efficiencies A charger application has output voltage and current that change over wide range as shown in Figure 6 To optimize the power stage design the efficiencies and input powers should be specified for operating point A nominal output voltage and current B 70 of nominal output voltage and C minimum output voltage respectively Estimated overall efficiency n for operating points A B and C The overall power conversion efficiency should be estimated to calculate the input power If no reference data is available use the typical efficiency in Table 1 m Estimated primary side efficiency np and secondary side efficiency ns for operating points A B and C Figure 7 shows the definition of primary side and secondary side efficiencies where the primary side efficiency is for the power transfer from AC line input to the transformer primary side while the secondary side efficiency is for the power transfer from the transformer primary side to the power supply output The typical values for the primary side and secondary side efficiencies are given as l 2 Np N Ns Zy output voltage lt 10V 2 2 1 Np 9 Us Z output voltage gt 10V 3 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 Table 1 Typical Efficiency of Flyback Converter Output Typical Eff2. 2 5 By setting Rs1 34 8KQ Rs is obtained as 82kQ It is recommended to place a bypass capacitor of 22 68pF closely between the Vs pin and the GND pin to bypass the switching noise and keep the accuracy of the sampled voltage for CV regulation The value of the capacitor affects the load regulation and constant current regulation Figure 13 illustrates the measured waveform on the Vs pin with a different Vs capacitor If a higher value Vs capacitor is used the charging time becomes longer and the sampled voltage is higher than the actual value Lisa eassr n al higher Vs Cap lower Vs Cap Vs pin waveform sampling voltage p a sampling voltage Figure 13 Effect on Sampling Voltage with Different Vs Capacitor www fairchildsemi com AN 8033 STEP 7 Determine the Output Filter Stage The peak to peak ripple of capacitor current is given as N Al cap ls 39 S The voltage ripple on the output is given by AIT Alo I9 AV a FAI Re 40 ZG Al Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor Then additional LC filter stages post filter can be used When using the post filters be careful not to place the corner frequency too low Too low a corner frequency may make the system unstable or limit the control bandwidth It is typical to set the corner frequency of the post filter at around 1 10 1 5 of the
3. 70 nominal output voltage operating point B are given as O7 V an PN B et een O 8 1 B OTV sl Pin r B ig 9 S B The overall efficiency at the minimum output voltage operating point C can be approximated as Veo OV AY Vo eve ne min where Vo is the minimum output voltage Nac 10 The secondary side efficiency at minimum output voltage operating point C can be approximated as Vo Vo Vp min l N 1 1 Vo Vpr Vo Then the power supply input power and transformer input power at the minimum output voltage operating point C are given as Ns c Z s yae a Bwac 12 lac V min T N PNr c see 13 15 C i Design Example i _ Assuming the overall efficiency is 70 at operating point A nominal output voltage and current the i secondary side efficiency is obtained as i 2 2 Ny n 0 77 0 788 i Then the input powers of the power supply and transformer are obtained as N N Yolo _ 3 75 _ 5 s6y n 0 7 Be aa ATN IN T Ns 7 0 723 The efficiencies at 70 of nominal output voltage are 0 7 V Vy V Nos 21 gt 0 67 pee OV ave Va i N N i ron us 0 7 Vo mess 0 756 0 7 V V vV i Then the input powers of the power supply and transformer at 70 of nominal output voltage are i obtained as i i es ale ead _ 0 3 91W Nas IN B 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 The efficiencies at th
4. regulation since it allows better output regulation The key of primary side regulation is how to obtain output voltage and current information without directly sensing them Once these values are obtained the control can be accomplished by the conventional feedback compensation method The operation principles of DCM flyback converter are as follows During the MOSFET ON time ton input voltage Vpz is applied across the primary side inductor Lin Then MOSFET current las increases linearly from zero to the peak value I During this time the energy is drawn from the input and stored in the inductor When the MOSFET is turned off the energy stored in the inductor forces the rectifier diode D to be turned on During the diode conduction time tp the output voltage V together with diode forward voltage drop Vf are applied across the secondary side inductor L xN N a and the diode current Ip decreases linearly from the peak value I x N N to zero At the end of tp all the energy stored in the inductor has been delivered to the output um When the diode current reaches zero the transformer auxiliary winding voltage Vw begins to oscillate by the resonance between the primary side inductor Lm and the MOSFET output capacitor During the diode conduction time the sum of output voltage and diode forward voltage drop is reflected to the auxiliary winding side as V Vr x N N Since the diode forwar
5. resistor with proper rated wattage should be chosen based on the power loss The maximum ripple of the snubber capacitor voltage is obtained as AV a eae ae 43 Coy Roy In general 5 20 ripple of the selected capacitor voltage is reasonable In the snubber design in this section neither the lossy discharge of the inductor nor stray capacitance is considered In the actual converter the loss in the snubber network is less than the designed value due to this effect 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 11 Design Example Since the voltage overshoot of drain i voltage has been determined same as the reflected output voltage The snubber voltage is Voy Vro Vos 144V The leakage inductance is measured as 48H Then the i loss in snubber network is given as i i l V i Poy Beier ie Rae 0 20W SN RO 2 Roy 99kO SN To allow 20 ripple on the snubber voltage 29V c o Vw CL 142 _ N AV Raf 28 99x10 50x10 www fairchildsemi com AN 8033 5 Print Circuit Board Layout Print circuit board layout and design are very important for switching power supply where the voltage and current change with high dv dt and di dt Good PCB layout minimizes excessive EMI and prevents the power supply from being disrupted during surge ESD tests Guidelines The numbers in the following guidelines refer to Figure 15 and Figure 16 To improve EMI perform
6. transformer turns ratio the voltage overshoot on drain voltage should be also considered The maximum voltage stress of MOSFET is given as Vag SV eV el Vs 21 For reasonable snubber design voltage overshoot Vos 1s typically 1 1 5 times of the reflected output voltage It is also typical to have a margin of 15 20 of breakdown voltage for maximum MOSFET voltage stress Figure 9 Transformer Turns Ratio and Voltage Stress on MOSFET and Diode The transformer turns ratio between the auxiliary winding and secondary winding N N should be determined by considering the permissible IC supply voltage Vpp range and minimum output voltage in CC mode When the power supply operates in constant current CC mode Vpp changes together with the output voltage as seen in Figure 10 The overshoot of auxiliary winding voltage caused by the leakage inductance also affects the Vpp Vpp voltage at light load condition where the overshoot of auxiliary winding voltage is negligible is given as www fairchildsSemi com 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 AN 8033 min N Vop N V V Vra 22 S The actual Vpp voltage at heavy load is higher than Equation 8 due to the overshoot by the leakage inductance which is proportional to the voltage overshoot of MOSFET drain to source voltage shown in Figure 10 Considering the effect of voltage overshoot the Vpp voltages for nominal output voltage
7. 11 16 A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness www fairchildsSemi com
8. Figure 23 Measured Output Voltage and Output Current Curve www fairchildsSemi com AN 8033 8 Related Resources FSEZ1317 Primary Side Regulation PWM with Power MOSFET Integrated Datasheet FAN103 Primary Side Regulation PWM Controller Datasheet AN 6067 Design and Application of Primary Side Regulation PSR PWM Controller Fairchild Power Supply WebDesigner Flyback Design amp Simulation In Minutes at No Expense DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life or c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16
9. R FSEZ13X7 significantly simplify the challenge of meeting tighter efficiency requirements while eliminating external components FAN103 and FSEZ13x7 also have an integrated output cable voltage drop compensation and external component temperature variation compensation circuit which allows high accuracy even at the end of the output cable for charger applications This application note presents practical design considerations for battery chargers employing Fairchild Semiconductor PWM PSR controller FAN103 and Power Switch MOSFET Controller EZ PSR FSEZ13X7 It includes designing the transformer and output filter selecting the components and implementing constant current constant voltage control The step by step design procedure described helps engineers design a power supply more easily The design procedure is verified through an experimental prototype converter using FSEZ1317 Figure 1 shows the typical application circuit of primary side controlled flyback converter using FSEZ1317 Csn2 saw Figure 1 Typical Application Circuit of FSEZ1317 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 www fairchildsemi com AN 8033 2 Operation Principle of Primary Side Regulation Figure 2 shows the simplified circuit diagram of a primary side regulated flyback converter and its typical waveforms are shown in Figure 3 Generally discontinuous conduction mode DCM operation is preferred for primary side
10. ance and reduce line frequency ripples the output of the bridge rectifier should be connected to capacitors Cor and Cpr first then to the primary switching circuits The primary high frequency current loop is in Cora Transformer MOSFET Rcs Cpy 1 The area enclosed by this current loop should be kept as short as possible Place Rsrarr for protect the inrush spike 100kQ is recommended Rcs should be connected Cp s ground directly Keep it short and wide Trace 4 1 and place it close the CS pin for reducing switching noise High voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference If a heat sink is used for the MOSFET connect this heat sink to ground As indicated by 2 the area enclosed by the transformer aux winding Dpp and Cpp should also be kept short path Place Cpp Cs Rs2 and Ccown close to each pin of PSR controller for good decoupling and to reduce the switching noise As indicated by 3 the ground of the control circuits should be connected first then to other circuitry GND 3 2 4 1 May make it possible to avoid common impedance interference for the sense signal Regarding the ESD discharge path put in the shortcut pad between AC line and DC output which is the best way The other method is to discharge the ESD energy to AC line through the primary main ground 1 Because ESD energy is del
11. and minimum output voltage are given as max amp N N Vp N Vo V N os V 23 min N min N Vop N Vo Vr i N Vos 7 Vra 24 where Vy is the diode forward voltage drop of auxiliary winding diode Vo yo C Figure 10 Vbo and Winding Voltage Design Example Assuming that drain voltage overshoot is same as the reflected output voltage the maximum drain voltage is given as Vos E Vp T Vko t Vos Vz Vireo For 700V MOSFET with 25 margin the reflected output voltage is obtained as Vos 9 75 x 700 gt 373 2Vzo 2 Veg lt 710V Setting Vro 72 and V 0 55 the turns ratio Np Ns is obtained as Np Vergo _ 72 R0 lt 3 N V V 5 55 The allowable Vpp range is from 5 5 to 24V considering the tolerance Considering voltage ripple on Vpp caused by burst operation at no load condition 3V margin is added for Vpp voltage calculation at no load condition as OL 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 Vpp 5 9 55 0 7 gt 5 543 S n Na gt 1 66 N S N I Vp 5 0 55 72 0 7 lt 24 DD N 13 S MM No lt 2 23 S y m2 Sc 125 0 55 57 0 7 gt 5 5 S S Na gt 0 84 S To minimize the power consumption of PWM IC it is required to keep Vpp as low as possible Therefore STEP 4 Design the Transformer Figure 11 shows the definition of MOSFET conduction time ton diode conducti
12. btained as i T a Violon i 5 4us i ON B N R i Ny 07 Vo tV The transformer primary side inductance is calculated i as min 2 Vmes Tower f 2 24mH INT B Then the peak drain current at maximum output power condition is given as i 2P Tyg 292mA m JS The MOSFET conduction time at the nominal output i condition is obtained as i 3 px a 0 292 7 03us DL i EE16 core is selected for the transformer and the i i minimum number of turns for the transformer primary i side to avoid the core saturation is given by PK Lolas B A sat e _ 2 24x10 0 292 0 3 19x10 min P 114 Then determine the proper integer for Ns so that the i resulting N is larger than N Np 13xN 13x9 117 gt N www fairchildsemi com AN 8033 The auxiliary winding turns N 1s given as N 1 65x9 15 a 5 The MOSFET conduction time at minimum output voltage is obtained as l 2Py rece LN sal 7 3 9 us Vrac sr The non conduction time at minimum output voltage 1 N Vege orrac ae lonec 1 mai a Ei sr Np Vo V 6 82 us gt 3 us ISTEP 5 Calculate the Voltage and Current of the Switching Devices Primary Side MOSFET The voltage stress of the MOSFET was discussed when determining the transformer turns ratio in STEP 3 Assuming that drain voltage overshoot is the same as the reflected output voltage the maximu
13. d voltage drop decreases as current decreases the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero By sampling the winding voltage at the end of the diode conduction time the output voltage information can be obtained The internal error amplifier for output voltage regulation EA_V compares the sampled voltage with internal precise reference to generate an error voltage Vcomv which determines the duty cycle of the MOSFET as shown in Figure 2 Meanwhile the output current can be estimated through calculation Assuming that output current is same as the average of the diode current in steady state the output current can be estimated as Io px 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the diode conduction time tp and switching period t These output information is compared with internal precise reference to generate error voltage Vcom which determines the duty cycle of the MOSFET as shown in the block diagram of Figure 2 Among the two error voltages Vcomy and Vcom the smaller one actually determines the duty cycle Therefore during constant voltage regulation mode Vcomy determines the duty cycle while Vcom is saturated to HIGH During constant current regula
14. dominant to the decrease of toy in determining the sum of toy and tp the converter tends to enter CCM as output voltage decreases FANI03 and FSEZ13X7 have a frequency reduction function to prevent CCM operation by extending the switching period which is activated when the output voltage drops below 70 of its nominal value as depicted in Figure 5 Therefore 70 of output voltage and minimum output voltage are the two worst cases for the transformer design 70 of Vo The transformer should be designed for DCM both at 70 of nominal output voltage and minimum output voltage Once the converter is designed to operate in DCM at 70 of nominal output voltage and minimum output voltage DCM operation is guaranteed for entire load range Figure 4 ton and tp Change as Output Voltage Decreases fs 50kHz fs 33kHz lo max 14 Figure 5 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 lo max Operation Range of Charger with CC CV www fairchildsemi com AN 8033 4 Design Procedure In this section a design procedure is presented using the schematic of Figure 6 as a reference An offline charger with 3 75W S5V output has been selected as a design example The design specifications are as follows ine voltage range 90 264V ac and 60Hz um Nominal output voltage and current 5V 0 75A um Output voltage ripple less than 150mV um Minimum output voltage in CC mode 25 of nominal output 1 25V
15. e it is necessary to use an additional network to clamp the voltage The RCD snubber circuit and MOSFET drain voltage waveform are shown in Figure 14 The RCD snubber network absorbs the current in the leakage inductance by turning on the snubber diode D n once the MOSFET drain voltage exceeds the voltage of node X as depicted in Figure 14 In the analysis of snubber network it is assumed that the snubber capacitor is large enough that its voltage does not change significantly during one switching cycle The snubber capacitor should be ceramic or a material that offers low ESR Electrolytic or tantalum capacitors are unacceptable due to these reasons Compensation 15 20 of BVdss N w vot Vpr ds 2009 Fairchild Semiconductor Corporation www fairchildsemi com Rev 1 0 1 11 16 11 AN 8033 T Figure 14 Snubber Circuit and its Waveforms The snubber capacitor voltage at full load condition Vsn is given as Vss Vro Vos 41 The power dissipated in the snubber network is obtained as V l PK s2 P ffLel SN Ro 5 As melding Voy 42 SN Vko where Ips is peak drain current at full load Lyx is the leakage inductance Vsw is the snubber capacitor voltage at full load and Ray is the snubber resistor The leakage inductance is measured at the switching frequency on the primary winding with all other windings shorted Then the snubber
16. e minimum output voltage are Vo OU V _0 _ 9 F 0 540 Nac 1 y V Ve min N V Nsac s She 0 608 Vom V Va The input powers of the power supply and transformer at the minimum output voltage are obtained as V miny N ge 2 2 1 74W Nac V miT N ene 2 0 54W Ns c STEP 2 Determine the DC Link Capacitor CoL and the DC Link Voltage Range It is typical to select the DC link capacitor as 2 3uF per watt of input power for universal input range 90 265Vems and 1uF per watt of input power for European input range 195V 265Vpms With the DC link capacitor chosen the minimum DC link voltage is obtained as Py Da Ci Ja where Viwg is the minimum line voltage Cpr is the DC link capacitor fr is the line frequency and Den is the DC link capacitor charging duty ratio defined as shown in Figure 8 which is typically about 0 2 Veo 2 Va T 14 The maximum DC link voltage is given as Vien v2 i Vie 15 where Vine is the maximum line voltage The minimum input DC link voltage at 70 nominal output voltage are given as Cor Sr The minimum input DC link voltage at minimum output voltage are given as ae iy XS B 5 N Vine 16 P 1 D min 2 Va T mec 17 yV ai Cor fi www fairchildsemi com AN 8033 Minimum DC link voltage DC link voltage Figure 8 DC Link Voltage Waveforms Design Example By choosing two 4 7uF capaci
17. eee ee FAIRCHILD Se eee SEMICONDUCTOR www fairchildsemi com Application Note AN 8033 Design Guideline for Primary Side Regulated PSR Flyback Converter Using FAN103 and FSEZ13X7 1 Introduction More than half of the external power supplies are used for portable electronics such as laptops cellular phones and MP3 players and therefore have output voltage and output current regulation capabilities for battery charging In applications where precise output current regulation is required current sensing in the secondary side is always necessary which results in additional sensing loss For power supply designers struggling in an environment of increasing regulatory pressures the output current sensing is a daunting design challenge Primary side regulation PSR for power supplies can be an optimal solution for alleviating the burden of achieving international energy efficiency regulations California Energy Commission CEC and Energy Star in charger designs The primary side regulation controls the output voltage and current precisely with the information in the primary side of the power supply only not only removing the output current sensing loss but also eliminating all secondary feedback circuitry This facilitates a higher efficiency power supply design without incurring AC line tremendous costs Fairchild Semiconductor PWM PSR controller FAN103 and Fairchild Power Switch FPS MOSFET Controller EZ PS
18. iciency Typical Efficiency Voltage for Universal Input for European Input 3 3 6V 65 70 67 72 6 12V 70 77 12 19 12 24V 11 82 19 84 Figure 7 Definition of Primary and Secondary Side Efficiency With the estimated overall efficiency the input power at nominal output is given as Ny N Vo Lo aa ama 4 77 where Vo and Io are the nominal output voltage and current respectively Then the input power of transformer at nominal output is given as aan 5 1s As mentioned in previous section when the output voltage drops below 70 of its nominal value the frequency is reduced to 33kHz to prevent CCM operation Thus the transformer should be designed for DCM both at 70 of nominal output voltage and minimum output voltage As output voltage reduces in CC mode the efficiency also drops To optimize the transformer design it is required to estimate the efficiencies properly at 70 of nominal output voltage and minimum output voltage conditions The overall efficiency at 70 of nominal output voltage operating point B can be approximated as 0 7 V gt Vo Vp Nog Oa eo 6 where Vrp is diode forward voltage drop The secondary side efficiency at 70 of nominal output voltage operating point B can be approximated as 0 7 V gt Vo Vp a 1 0 7 Vo Ve V Ns B Z s www fairchildsSemi com AN 8033 Then the power supply input power and transformer input power at
19. ivered from secondary to primary though the transformer stray capacitor the controller circuit should not be placed on the discharge path 5 shows places where the point discharge route can be placed to bypass the static electricity energy it is suggested to map out this discharge route in Figure 15 and Figure 16 For the surge path select fusible resistor type with wire wound type to reduce inrush current and surge energy use m input filter two bulk capacitor and one inductance to share the surge energy Csn2 Rsn2 5 Line Figure 15 EZ PSR FSEZ13X7 Layout Consideration 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 12 www fairchildsemi com AN 8033 5 5 Csn2 R SN2 VoL Coi2 Cor 7 Rruse 0000 AC line me QuosFE T Figure 16 PSR PWM FAN103 Layout Consideration 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 13 www fairchildsemi com AN 8033 6 Final Schematic of Design Example Figure 17 shows the final schematic of the 3 75W charger design example EE16core is used for the transformer Figure 18 shows the transformer information 1nF 750 Csn2 Rsn2z 1mH 0000 1N4007 1N4007 V 00 00 1kO Coe Coti 4 7uF 4 7HF 1N4007 1N4007 Rruse 0000 10Q 4 7pH 1N4007 0 AC line Figure 17 Final Schematic of the EZ PSR FSEZ1317 3 75W Design Example Core EE16 PC40 Bobbin EE16 10 pins Horizontal type Secondary g Windi
20. m drain voltage is given as Seeeennenneeeneeneanenneeeeeseneeseoenneseeseneneeeeneees Ve Va Veet Vos 33 The rms current though the MOSFET is given as ne IT I ps I m a 34 Secondary Side diode The maximum reverse voltage and the rms current of the rectifier diode are obtained respectively as N max VV FR 35 amp La pa i Design Example Assuming voltage overshoot of _ drain to source is same as reflected output voltage the i maximum voltage across the MOSFET is calculated as iv my RA 2V 5 517V S The rms current though the MOSFET is Tov fe les mhac at lt 0 1A The diode voltage and current are obtained as aA Vo s ps 54 B 3380 ae o 93 1321 474 Veo 72 9 i Scokttky diode SB240 ate is selected 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 STEP 6 Output Voltage and Current Setting The nominal output current is determined by the sensing resistor value and transformer turns ratio as N Reese 6 37 SENSE NI x8 5 37 The voltage divider Rs and Re should be determined so that Vs is 2 5V at the end of diode current conduction time as shown in Figure 9 Ra N Vo iie yey OL R W T 38 Select 1 tolerance resistor for better output regulation Design Example The sensing resistor is obtained as e oa ms NI x8 5 9 0 75x8 5 SENSE p o divider network is determined as Fit 8 N 2 233 R N 25 9
21. nd 230Vac condition are higher than 68 Figure 22 shows the measured no load power consumption at different line voltage As can be seen in the figures even in the 264V ac AC line the no load standby power consumption is still less than 30mW meeting the five star level of new power consumption regulation for charger Figure 23 shows the measured output voltage and output current curve CV regulation achieves 1 38 for entire line and load condition The CC regulation can achieve 3 6 with a fold back voltage of 1 5V a Vds 100Vidiv EL Ea iii Ip 200mA div i a time 5us div Figure 19 Operation Waveforms at 70 of Nominal Output Voltage and Minimum Line Voltage Condition Vds 100V div Ip 200mA div I 4 time Sus div Figure 20 Operation Waveforms at Minimum Output Voltage and Minimum Line Voltage Condition 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 74 115Vac 60Hz 71 61 avg 72 70 230Vac 50Hz 70 01 avg 68 66 649 65 5 Energy Star V 2009 o 62 58 25 50 75 50 40 30 Input power mW 20 10 0 Load 100 Figure 21 Measured Efficiency 90 120 150 180 210 Input voltage V 240 27 0 Figure 22 Measured No Load Power Consumption Output voltage V 0 90Vac 115Vac 230Vac 264Vac O 100 200 300 400 500 600 700 800 900 Output current mA
22. ng i 4 1st Shield 4 Primary Winding 3 2 Auxiliary Winding BOBBIN Figure 18 Transformer Structure Notes 1 When W4R s winding is reversed winding it must wind one layer 2 When W2 is winding it must wind three layers and put one layer of tape after winding the first layer me 2UEW 0 23 1 Ez W2 3 1 2UEW 0 18 1 sm aa a y owm 7 9 TExE055 9 f o 3 o NEE CORE ROUNDING TAPE 3 a Primary Side Inductance 2 25mH 5 100kHz 1V Primary Side Leakage Inductance 80uH Maximum Short One of the Secondary Windings 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 14 www fairchildsSemi com AN 8033 7 Test Result of Design Example To show the validity of the design procedure presented in this application note the converter of the design example has been built and tested All the circuit components are used as designed in the design example Figure 19 shows the operation waveforms at 70 of nominal output voltage and minimum line voltage condition As designed in STEP 4 the non conduction time is 4us before frequency reduction occurs which guarantees DCM operation Figure 20 shows the operation waveforms at minimum output voltage and minimum line voltage condition As designed in STEP 4 the non conduction time is about 6 8us which guarantees DCM operation Figure 21 shows the measured efficiency for different load conditions The average efficiencies at 115V ac a
23. on time tp and non conduction time torr The sum of MOSFET conduction time and diode conduction time at 70 of nominal output voltage is obtained as N Vao Let l yl s 25 ON DPO O ONS Np 0 7 Vo V a The first step to design the transformer is to determine how much non conduction time torr is allowed in DCM operation Once the torr is determined by considering the frequency variation caused by frequency hopping and its own tolerance the MOSFET conduction time is obtained as T Lfs Tore 7 N l Vores N 0 7 V V 26 ton i tb torr ts Figure 11 Definition of toy tp and torr The transformer primary side inductance can be calculated as V min Y 2 L _ DL B on s f 27 2PNras www fairchildsSemi com AN 8033 The maximum peak drain current can be obtained at the nominal output condition as 2P PK _ IN T 28 Lp S The MOSFET conduction time at the nominal output condition is obtained as L PK m Ton Lps y_ min 29 DL The minimum number of turns for the transformer primary side to avoid the core saturation is given by PK min L I DS Ne eeo 30 DS where A is the cross sectional area of the core in m and Bear 1s the saturation flux density in Tesla Figure 12 shows the typical characteristics of ferrite core from TDK PC40 Since the saturation flux density Bsa decreases as the temperature rises the high temperature characteristics should be considered when i
24. switching frequency seeeccenseceeeneeacccnsccesseeesscseseeenseeascenseeense ga egg ee enn ee eneneenerennereneneneeeeserenenensscensesesseenssessecssssesees Design Example Assuming 470uF electrolytic capacitor with 30mQ ESR for output capacitor the _ voltage ripple on the output is Al Ty Ale AV Ale lo ATR 137mV STEP 8 Cable Voltage Drop Compensation When it comes to cellular phone charger application the actual battery is located at the end of cable which causes typically several percentage of voltage drop on the actual battery voltage FAN103 and FSEZ13X7 have cable voltage drop compensation that can be programmed by a resistor on the COMR pin as shown in Table 3 The resistances of the standard 1 8m cable for different AWG are summarized in Table 4 Table 3 Cable Compensation Design Example Assuming 26AWG 1 8m cable is used the voltage drop at maximum output current is AV Reap Lo 0 48 0 75 0 36V AV 5020 555 V 5 The default setting can be used without any resistor on COMR pin To improve the noise immunity of COMR pin it is typical to connect a 1uF bypass capacitor on the COMR pin STEP 9 Design RCD Snubber in Primary Side When the power MOSFET is turned off there is a high voltage spike on the drain due to the transformer leakage inductance This excessive voltage on the MOSFET may lead to an avalanche breakdown and eventually failure of the device Therefor
25. t comes to charger in enclosed case If there is no reference data use Ba 0 25 0 3 T Table 2 shows the commonly used cores for battery chargers with output power under 10W The cores recommended in Table 2 are typical for the universal input range and 50kHz switching frequency Once the turns ratio is obtained determine the proper integer for Ns so that the resulting N is larger than N obtained from Equation 30 Magnetization Curves typical Material PC 40 400 300 200 E 100 Jae esses 0 800 1600 Magnetic field H A m Figure 12 Typical B H Curves of Ferrite Core TDK PC40 DCM operation at minimum output voltage should be also checked The MOSFET conduction time at minimum output voltage is given as 1 2P L o INT CHn C i min VoLec I where fsg is the reduced switching frequency to prevent CCM operation Toy 31 2009 Fairchild Semiconductor Corporation Rev 1 0 1 11 16 11 Then the non conduction time at minimum output voltage IS given as I N Vorec T T 1 33 OFF C For al N vm re V 33 The non conduction time should be larger than 3us 10 of switching period considering the tolerance of switching frequency Table 2 Typical Cores for Battery Charger Application for Universal Input Range DCM Operation and fs 50kHz Design Example Setting the non conduction time at i 70 of nominal output voltage as 4us the MOSFET i conduction time is o
26. tion mode Vcom determines the duty cycle while Vcomy is saturated to HIGH lo Estimator Tp Estimator PWM Control Primary side regulation Controller Vo Estimator Figure 2 Primary Side Regulated Flyback Converter las MOSFET Drain to Source Current Figure 3 Key Waveforms of Primary Side Regulated Flyback Converter www fairchildsSemi com AN 8033 3 Design Consideration Converters with Constant Current CC output reguire more design consideration than the conventional power supply design with a fixed output voltage In CC operation the voltage for control IC Vpp which is usually obtained with an auxiliary winding of the transformer changes with the output voltage Thus the Vpp operation range determines the constant current control range FAN103 and FSEZ13X7 have a wide supply voltage Vpp operation range from 5V up to 24V which allows stable CC regulation even with output voltage lower than a quarter of its nominal value Another important design consideration for CC operation is that the transformer should be designed to guarantee DCM operation in all operation range since the output information is properly obtained only in DCM operation as described in Section 2 As seen in Figure 4 the MOSFET conduction time ton decreases as output voltage decreases in CC mode Meanwhile the diode conduction time tp increases as the output voltage decreases Since the increase of tox is
27. tors in parallel for the DC link capacitor the minimum and maximum DC link voltage for each condition are obtained as i 2 V may2 _ wU Din LINE Cor Ji 2 90 Seal 93V 2 4 7x10 60 V 2 264 373V min Vor I P 1 D Vise 7 _ iN B nd Cor i f 000 103V 2 4 7x10 5 60 i P 1 D i Virec NV T E act 7 a DL JL Oi SItSsshiSgi 117V 2 4 7x10 60 lt S dS B 5 NO STEP 3 Determine the Transformer Turns Ratio Figure 9 shows the MOSFET drain to source voltage waveforms When the MOSFET is turned off the sum of the input voltage Vp and the output voltage reflected to the primary is imposed across the MOSFET as Vos AA ae Vro 18 where Vpro is reflected output voltage defined as IN Vro Vo tV 19 N where Vp is the diode forward voltage drop and Np and Ns are number of turns for primary side and secondary side respectively When the MOSFET is turned on the output voltage together with input voltage reflected to the secondary are imposed across the diode as Va SEOL Ve a Vo 20 As observed in Equations 6 and 7 increasing the transformer turns ratio N N results in increased voltage of MOSFET while it leads to reduced voltage stress of rectifier diode Therefore the transformer turns ratio N N should be determined by the compromise between MOSFET and diode voltage stresses When determining the
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FAIRCHILD Design Guideline for Primary Side Regulated (PSR) Flyback Converter Using FAN103 FSEZ13X7